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/nrf_hw_models-latest/src/nrfx/hal/
Dnrf_cracen_cm.c17 nrf_cracen_cm_config_indirect_mask_t mask) in nrf_cracen_cm_config_indirect_set() argument
19 p_reg->CRYPTMSTRDMA.CONFIG = (uint32_t)mask; in nrf_cracen_cm_config_indirect_set()
38 void nrf_cracen_cm_int_enable(NRF_CRACENCORE_Type * p_reg, uint32_t mask) in nrf_cracen_cm_int_enable() argument
40 p_reg->CRYPTMSTRDMA.INTENSET = mask; in nrf_cracen_cm_int_enable()
44 void nrf_cracen_cm_int_disable(NRF_CRACENCORE_Type * p_reg, uint32_t mask) in nrf_cracen_cm_int_disable() argument
46 p_reg->CRYPTMSTRDMA.INTENCLR = mask; in nrf_cracen_cm_int_disable()
50 void nrf_cracen_cm_int_clear(NRF_CRACENCORE_Type * p_reg, uint32_t mask) in nrf_cracen_cm_int_clear() argument
52 p_reg->CRYPTMSTRDMA.INTSTATCLR = mask; in nrf_cracen_cm_int_clear()
Dnrf_gpiote.c102 void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask) in nrf_gpiote_int_enable() argument
105 p_reg->NRFX_CONCAT_2(INTENSET, NRF_GPIOTE_IRQ_GROUP) = mask; in nrf_gpiote_int_enable()
110 void nrf_gpiote_int_disable(NRF_GPIOTE_Type * p_reg, uint32_t mask) in nrf_gpiote_int_disable() argument
113 p_reg->NRFX_CONCAT_2(INTENCLR, NRF_GPIOTE_IRQ_GROUP) = mask; in nrf_gpiote_int_disable()
134 uint32_t mask) in nrf_gpiote_int_group_enable() argument
139 p_reg->INTENSET0 = mask; in nrf_gpiote_int_group_enable()
142 p_reg->INTENSET1 = mask; in nrf_gpiote_int_group_enable()
146 p_reg->INTENSET2 = mask; in nrf_gpiote_int_group_enable()
151 p_reg->INTENSET3 = mask; in nrf_gpiote_int_group_enable()
156 p_reg->INTENSET4 = mask; in nrf_gpiote_int_group_enable()
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Dnrf_cracen.c14 void nrf_cracen_int_enable(NRF_CRACEN_Type * p_reg, uint32_t mask) in nrf_cracen_int_enable() argument
16 p_reg->INTENSET = mask; in nrf_cracen_int_enable()
20 void nrf_cracen_int_disable(NRF_CRACEN_Type * p_reg, uint32_t mask) in nrf_cracen_int_disable() argument
22 p_reg->INTENCLR = mask; in nrf_cracen_int_disable()
Dnrf_temp.c25 void nrf_temp_int_enable(NRF_TEMP_Type * p_reg, uint32_t mask) in nrf_temp_int_enable() argument
28 NRF_TEMP_regs.INTENSET = mask; in nrf_temp_int_enable()
32 void nrf_temp_int_disable(NRF_TEMP_Type * p_reg, uint32_t mask) in nrf_temp_int_disable() argument
35 NRF_TEMP_regs.INTENCLR = mask; in nrf_temp_int_disable()
Dnrf_ecb.c25 void nrf_ecb_int_enable(NRF_ECB_Type * p_reg, uint32_t mask) in nrf_ecb_int_enable() argument
27 p_reg->INTENSET = mask; in nrf_ecb_int_enable()
31 void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask) in nrf_ecb_int_disable() argument
33 p_reg->INTENCLR = mask; in nrf_ecb_int_disable()
Dnrf_aar.c13 void nrf_aar_int_enable(NRF_AAR_Type * p_reg, uint32_t mask) in nrf_aar_int_enable() argument
15 p_reg->INTENSET = mask; in nrf_aar_int_enable()
19 void nrf_aar_int_disable(NRF_AAR_Type * p_reg, uint32_t mask) in nrf_aar_int_disable() argument
21 p_reg->INTENCLR = mask; in nrf_aar_int_disable()
Dnrf_radio.c49 void nrf_radio_int_enable(NRF_RADIO_Type * p_reg, uint32_t mask) in nrf_radio_int_enable() argument
52 p_reg->INTENSET = mask; in nrf_radio_int_enable()
54 p_reg->INTENSET00 = mask; in nrf_radio_int_enable()
59 void nrf_radio_int_disable(NRF_RADIO_Type * p_reg, uint32_t mask) in nrf_radio_int_disable() argument
62 p_reg->INTENCLR = mask; in nrf_radio_int_disable()
64 p_reg->INTENCLR00 = mask; in nrf_radio_int_disable()
Dnrf_rng.c27 void nrf_rng_int_enable(NRF_RNG_Type * p_reg, uint32_t mask) in nrf_rng_int_enable() argument
30 NRF_RNG_regs.INTENSET = mask; in nrf_rng_int_enable()
34 void nrf_rng_int_disable(NRF_RNG_Type * p_reg, uint32_t mask) in nrf_rng_int_disable() argument
37 NRF_RNG_regs.INTENCLR = mask; in nrf_rng_int_disable()
Dnrf_rtc.c25 void nrf_rtc_int_enable(NRF_RTC_Type * p_reg, uint32_t mask) in nrf_rtc_int_enable() argument
28 p_reg->INTENSET = mask; in nrf_rtc_int_enable()
32 void nrf_rtc_int_disable(NRF_RTC_Type * p_reg, uint32_t mask) in nrf_rtc_int_disable() argument
35 p_reg->INTENCLR = mask; in nrf_rtc_int_disable()
78 void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask) in nrf_rtc_event_enable() argument
81 p_reg->EVTENSET = mask; in nrf_rtc_event_enable()
Dnrf_ccm.c28 void nrf_ccm_int_enable(NRF_CCM_Type * p_reg, uint32_t mask) in nrf_ccm_int_enable() argument
30 p_reg->INTENSET = mask; in nrf_ccm_int_enable()
34 void nrf_ccm_int_disable(NRF_CCM_Type * p_reg, uint32_t mask) in nrf_ccm_int_disable() argument
36 p_reg->INTENCLR = mask; in nrf_ccm_int_disable()
Dnrf_grtc.c49 void nrf_grtc_int_enable(NRF_GRTC_Type * p_reg, uint32_t mask) in nrf_grtc_int_enable() argument
51 p_reg->GRTC_INTENSET = mask; in nrf_grtc_int_enable()
55 void nrf_grtc_int_disable(NRF_GRTC_Type * p_reg, uint32_t mask) in nrf_grtc_int_disable() argument
57 p_reg->GRTC_INTENCLR = mask; in nrf_grtc_int_disable()
65 uint32_t mask) in nrf_grtc_int_group_enable() argument
67 *(uint32_t*)((char*)p_reg->INTENSET0 + INTENGRPOFFSET*group_idx) = mask; in nrf_grtc_int_group_enable()
73 uint32_t mask) in nrf_grtc_int_group_disable() argument
75 *(uint32_t*)((char*)p_reg->INTENCLR0 + INTENGRPOFFSET*group_idx) = mask; in nrf_grtc_int_group_disable()
Dnrf_ipc.c34 void nrf_ipc_int_enable(NRF_IPC_Type * p_reg, uint32_t mask) in nrf_ipc_int_enable() argument
36 p_reg->INTENSET = mask; in nrf_ipc_int_enable()
42 void nrf_ipc_int_disable(NRF_IPC_Type * p_reg, uint32_t mask) in nrf_ipc_int_disable() argument
44 p_reg->INTENCLR = mask; in nrf_ipc_int_disable()
Dnrf_egu.c37 void nrf_egu_int_enable(NRF_EGU_Type * p_reg, uint32_t mask) in nrf_egu_int_enable() argument
39 p_reg->INTENSET = mask; in nrf_egu_int_enable()
45 void nrf_egu_int_disable(NRF_EGU_Type * p_reg, uint32_t mask) in nrf_egu_int_disable() argument
47 p_reg->INTENCLR = mask; in nrf_egu_int_disable()
Dnrf_54_ecb.c33 void nrf_ecb_int_enable(NRF_ECB_Type * p_reg, uint32_t mask) in nrf_ecb_int_enable() argument
36 p_reg->INTENSET = mask; in nrf_ecb_int_enable()
40 void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask) in nrf_ecb_int_disable() argument
43 p_reg->INTENCLR = mask; in nrf_ecb_int_disable()
Dnrf_ppi.c24 void nrf_ppi_channels_enable(NRF_PPI_Type * p_reg, uint32_t mask) in nrf_ppi_channels_enable() argument
26 p_reg->CHENSET = mask; in nrf_ppi_channels_enable()
30 void nrf_ppi_channels_disable(NRF_PPI_Type * p_reg, uint32_t mask) in nrf_ppi_channels_disable() argument
32 p_reg->CHENCLR = mask; in nrf_ppi_channels_disable()
Dnrf_54_aar.c21 void nrf_aar_int_enable(NRF_AAR_Type * p_reg, uint32_t mask) in nrf_aar_int_enable() argument
24 p_reg->INTENSET = mask; in nrf_aar_int_enable()
28 void nrf_aar_int_disable(NRF_AAR_Type * p_reg, uint32_t mask) in nrf_aar_int_disable() argument
31 p_reg->INTENCLR = mask; in nrf_aar_int_disable()
Dnrf_54_ccm.c36 void nrf_ccm_int_enable(NRF_CCM_Type * p_reg, uint32_t mask) in nrf_ccm_int_enable() argument
39 p_reg->INTENSET = mask; in nrf_ccm_int_enable()
43 void nrf_ccm_int_disable(NRF_CCM_Type * p_reg, uint32_t mask) in nrf_ccm_int_disable() argument
46 p_reg->INTENCLR = mask; in nrf_ccm_int_disable()
Dnrf_timer.c66 uint32_t mask) in nrf_timer_int_enable() argument
69 p_reg->INTENSET = mask; in nrf_timer_int_enable()
74 uint32_t mask) in nrf_timer_int_disable() argument
77 p_reg->INTENCLR = mask; in nrf_timer_int_disable()
Dnrf_clock.c25 void nrf_clock_int_enable(NRF_CLOCK_Type * p_reg, uint32_t mask) in nrf_clock_int_enable() argument
27 p_reg->INTENSET = mask; in nrf_clock_int_enable()
33 void nrf_clock_int_disable(NRF_CLOCK_Type * p_reg, uint32_t mask) in nrf_clock_int_disable() argument
35 p_reg->INTENCLR = mask; in nrf_clock_int_disable()
Dnrf_uart.c41 void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t mask) in nrf_uart_int_enable() argument
44 p_reg->INTENSET = mask; in nrf_uart_int_enable()
48 void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t mask) in nrf_uart_int_disable() argument
51 p_reg->INTENCLR = mask; in nrf_uart_int_disable()
Dnrf_dppi.c45 void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask) in nrf_dppi_channels_enable() argument
47 p_reg->CHENSET = mask; in nrf_dppi_channels_enable()
53 void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask) in nrf_dppi_channels_disable() argument
55 p_reg->CHENCLR = mask; in nrf_dppi_channels_disable()
Dnrf_uarte.c51 void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask) in nrf_uarte_int_enable() argument
54 p_reg->INTENSET = mask; in nrf_uarte_int_enable()
58 void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask) in nrf_uarte_int_disable() argument
61 p_reg->INTENCLR = mask; in nrf_uarte_int_disable()
/nrf_hw_models-latest/src/HW_models/
DNRF_GPIOTE.c164 int mask; in nrf_gpiote_eval_interrupt() local
170 mask = (st->GPIOTE_ITEN[line] >> i) & 0x1; in nrf_gpiote_eval_interrupt()
171 if (NRF_GPIOTE_regs[inst].EVENTS_IN[i] && mask) { in nrf_gpiote_eval_interrupt()
178 mask = (st->GPIOTE_ITEN[line] & GPIOTE_INTENCLR_PORT_Msk) >> GPIOTE_INTENCLR_PORT_Pos; in nrf_gpiote_eval_interrupt()
179 if (NRF_GPIOTE_regs[inst].EVENTS_PORT && mask) { in nrf_gpiote_eval_interrupt()
183 …mask = (st->GPIOTE_ITEN[line] & GPIOTE_INTENCLR0_PORT0NONSECURE_Msk) >> GPIOTE_INTENCLR0_PORT0NONS… in nrf_gpiote_eval_interrupt()
184 if (NRF_GPIOTE_regs[inst].EVENTS_PORT[0].NONSECURE && mask) { in nrf_gpiote_eval_interrupt()
187 …mask = (st->GPIOTE_ITEN[line] & GPIOTE_INTENCLR0_PORT0SECURE_Msk) >> GPIOTE_INTENCLR0_PORT0SECURE_… in nrf_gpiote_eval_interrupt()
188 if (NRF_GPIOTE_regs[inst].EVENTS_PORT[0].SECURE && mask) { in nrf_gpiote_eval_interrupt()
DNHW_CRACEN_RNG.c360 void nhw_CRACEN_RNG_fake_test_error(uint32_t mask) { in nhw_CRACEN_RNG_fake_test_error() argument
361 if (mask & CRACEN_RNG_FAKE_STARTUP_ERROR) { in nhw_CRACEN_RNG_fake_test_error()
364 if (mask & CRACEN_RNG_FAKE_REP_TEST_ERROR) { in nhw_CRACEN_RNG_fake_test_error()
367 if (mask & CRACEN_RNG_FAKE_PROP_TEST_ERROR) { in nhw_CRACEN_RNG_fake_test_error()
370 if (mask & CRACEN_RNG_FAKE_AIS31_PRENOISE_ERROR) { in nhw_CRACEN_RNG_fake_test_error()
373 if (mask & CRACEN_RNG_FAKE_AIS31_NOISE_ERROR) { in nhw_CRACEN_RNG_fake_test_error()
DNHW_CRACEN_RNG.h34 void nhw_CRACEN_RNG_fake_test_error(uint32_t mask);

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