1 /*
2  * Copyright (c) 2023 Nordic Semiconductor ASA
3  *
4  * Note: Most of these file content is taken directly or with minor
5  * modifications from the Nordic nrfx MDK files, which are
6  *
7  * SPDX-License-Identifier: BSD-3-Clause
8  *
9  * Therefore this file overall has that same license.
10  *
11  * HW peripherals SW regiters interface definitions
12  * For an nRF5340 SOC
13  *
14  */
15 
16 #ifndef _NRF5340_PERI_TYPES_H
17 #define _NRF5340_PERI_TYPES_H
18 
19 #include <stdint.h>
20 
21 #ifndef __IM
22   #define __IM
23 #endif
24 #ifndef __OM
25   #define __OM
26 #endif
27 #ifndef __IOM
28   #define __IOM
29 #endif
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 /**
36   * @brief FICR_INFO [INFO] (Device info)
37   */
38 typedef struct {
39   __IM  uint32_t  CONFIGID;                     /*!< (@ 0x00000000) Configuration identifier                                   */
40   __IM  uint32_t  DEVICEID[2];                  /*!< (@ 0x00000004) Description collection: Device identifier                  */
41   __IM  uint32_t  PART;                         /*!< (@ 0x0000000C) Part code                                                  */
42   __IM  uint32_t  VARIANT;                      /*!< (@ 0x00000010) Part Variant, Hardware version and Production
43                                                                     configuration                                              */
44   __IM  uint32_t  PACKAGE;                      /*!< (@ 0x00000014) Package option                                             */
45   __IM  uint32_t  RAM;                          /*!< (@ 0x00000018) RAM variant                                                */
46   __IM  uint32_t  FLASH;                        /*!< (@ 0x0000001C) Flash variant                                              */
47   __IM  uint32_t  CODEPAGESIZE;                 /*!< (@ 0x00000020) Code memory page size in bytes                             */
48   __IM  uint32_t  CODESIZE;                     /*!< (@ 0x00000024) Code memory size                                           */
49   __IM  uint32_t  DEVICETYPE;                   /*!< (@ 0x00000028) Device type                                                */
50 } FICR_INFO_Type;                               /*!< Size = 44 (0x2c)                                                          */
51 
52 
53 /**
54   * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified)
55   */
56 typedef struct {
57   __IM  uint32_t  ADDR;                         /*!< (@ 0x00000000) Description cluster: Address                               */
58   __IM  uint32_t  DATA;                         /*!< (@ 0x00000004) Description cluster: Data                                  */
59 } FICR_TRIMCNF_Type;                            /*!< Size = 8 (0x8)                                                            */
60 
61 
62 /**
63   * @brief FICR_NFC [NFC] (Unspecified)
64   */
65 typedef struct {
66   __IM  uint32_t  TAGHEADER0;                   /*!< (@ 0x00000000) Default header for NFC Tag. Software can read
67                                                                     these values to populate NFCID1_3RD_LAST,
68                                                                     NFCID1_2ND_LAST and NFCID1_LAST.                           */
69   __IM  uint32_t  TAGHEADER1;                   /*!< (@ 0x00000004) Default header for NFC Tag. Software can read
70                                                                     these values to populate NFCID1_3RD_LAST,
71                                                                     NFCID1_2ND_LAST and NFCID1_LAST.                           */
72   __IM  uint32_t  TAGHEADER2;                   /*!< (@ 0x00000008) Default header for NFC Tag. Software can read
73                                                                     these values to populate NFCID1_3RD_LAST,
74                                                                     NFCID1_2ND_LAST and NFCID1_LAST.                           */
75   __IM  uint32_t  TAGHEADER3;                   /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read
76                                                                     these values to populate NFCID1_3RD_LAST,
77                                                                     NFCID1_2ND_LAST and NFCID1_LAST.                           */
78 } FICR_NFC_Type;                                /*!< Size = 16 (0x10)                                                          */
79 
80 
81 /**
82   * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data)
83   */
84 typedef struct {
85   __IM  uint32_t  BYTES;                        /*!< (@ 0x00000000) Amount of bytes for the required entropy bits              */
86   __IM  uint32_t  RCCUTOFF;                     /*!< (@ 0x00000004) Repetition counter cutoff                                  */
87   __IM  uint32_t  APCUTOFF;                     /*!< (@ 0x00000008) Adaptive proportion cutoff                                 */
88   __IM  uint32_t  STARTUP;                      /*!< (@ 0x0000000C) Amount of bytes for the startup tests                      */
89   __IM  uint32_t  ROSC1;                        /*!< (@ 0x00000010) Sample count for ring oscillator 1                         */
90   __IM  uint32_t  ROSC2;                        /*!< (@ 0x00000014) Sample count for ring oscillator 2                         */
91   __IM  uint32_t  ROSC3;                        /*!< (@ 0x00000018) Sample count for ring oscillator 3                         */
92   __IM  uint32_t  ROSC4;                        /*!< (@ 0x0000001C) Sample count for ring oscillator 4                         */
93 } FICR_TRNG90B_Type;                            /*!< Size = 32 (0x20)                                                          */
94 
95 
96 /**
97   * @brief RADIO_PSEL [PSEL] (Unspecified)
98   */
99 typedef struct {
100   __IOM uint32_t  DFEGPIO[8];                   /*!< (@ 0x00000000) Description collection: Pin select for DFE pin
101                                                                     n                                                          */
102 } RADIO_PSEL_Type;                              /*!< Size = 32 (0x20)                                                          */
103 
104 
105 /**
106   * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel)
107   */
108 typedef struct {
109   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Data pointer                                               */
110   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of buffer words to transfer                 */
111   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of samples transferred in the last transaction      */
112 } RADIO_DFEPACKET_Type;                         /*!< Size = 12 (0xc)                                                           */
113 
114 
115 /**
116   * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified)
117   */
118 typedef struct {
119   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: Access for bus access generated
120                                                                     from the external domain n List capabilities
121                                                                     of the external domain n                                   */
122 } SPU_EXTDOMAIN_Type;                           /*!< Size = 4 (0x4)                                                            */
123 
124 
125 /**
126   * @brief SPU_DPPI [DPPI] (Unspecified)
127   */
128 typedef struct {
129   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: Select between secure and
130                                                                     non-secure attribute for the DPPI channels                 */
131   __IOM uint32_t  LOCK;                         /*!< (@ 0x00000004) Description cluster: Prevent further modification
132                                                                     of the corresponding PERM register                         */
133 } SPU_DPPI_Type;                                /*!< Size = 8 (0x8)                                                            */
134 
135 
136 /**
137   * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified)
138   */
139 typedef struct {
140   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: Select between secure and
141                                                                     non-secure attribute for pins 0 to 31 of
142                                                                     port n                                                     */
143   __IOM uint32_t  LOCK;                         /*!< (@ 0x00000004) Description cluster: Prevent further modification
144                                                                     of the corresponding PERM register                         */
145 } SPU_GPIOPORT_Type;                            /*!< Size = 8 (0x8)                                                            */
146 
147 
148 /**
149   * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified)
150   */
151 typedef struct {
152   __IOM uint32_t  REGION;                       /*!< (@ 0x00000000) Description cluster: Define which flash region
153                                                                     can contain the non-secure callable (NSC)
154                                                                     region n                                                   */
155   __IOM uint32_t  SIZE;                         /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure
156                                                                     callable (NSC) region n                                    */
157 } SPU_FLASHNSC_Type;                            /*!< Size = 8 (0x8)                                                            */
158 
159 
160 /**
161   * @brief SPU_RAMNSC [RAMNSC] (Unspecified)
162   */
163 typedef struct {
164   __IOM uint32_t  REGION;                       /*!< (@ 0x00000000) Description cluster: Define which RAM region
165                                                                     can contain the non-secure callable (NSC)
166                                                                     region n                                                   */
167   __IOM uint32_t  SIZE;                         /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure
168                                                                     callable (NSC) region n                                    */
169 } SPU_RAMNSC_Type;                              /*!< Size = 8 (0x8)                                                            */
170 
171 
172 /**
173   * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified)
174   */
175 typedef struct {
176   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: Access permissions for flash
177                                                                     region n                                                   */
178 } SPU_FLASHREGION_Type;                         /*!< Size = 4 (0x4)                                                            */
179 
180 
181 /**
182   * @brief SPU_RAMREGION [RAMREGION] (Unspecified)
183   */
184 typedef struct {
185   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: Access permissions for RAM
186                                                                     region n                                                   */
187 } SPU_RAMREGION_Type;                           /*!< Size = 4 (0x4)                                                            */
188 
189 
190 /**
191   * @brief SPU_PERIPHID [PERIPHID] (Unspecified)
192   */
193 typedef struct {
194   __IOM uint32_t  PERM;                         /*!< (@ 0x00000000) Description cluster: List capabilities and access
195                                                                     permissions for the peripheral with ID n                   */
196 } SPU_PERIPHID_Type;                            /*!< Size = 4 (0x4)                                                            */
197 
198 
199 /**
200   * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks)
201   */
202 typedef struct {
203   __OM  uint32_t  EN;                           /*!< (@ 0x00000000) Description cluster: Enable channel group n                */
204   __OM  uint32_t  DIS;                          /*!< (@ 0x00000004) Description cluster: Disable channel group n               */
205 } NRF_DPPIC_TASKS_CHG_Type;                         /*!< Size = 8 (0x8)                                                            */
206 
207 
208 /**
209   * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks)
210   */
211 typedef struct {
212   __IOM uint32_t  EN;                           /*!< (@ 0x00000000) Description cluster: Subscribe configuration
213                                                                     for task CHG[n].EN                                         */
214   __IOM uint32_t  DIS;                          /*!< (@ 0x00000004) Description cluster: Subscribe configuration
215                                                                     for task CHG[n].DIS                                        */
216 } DPPIC_SUBSCRIBE_CHG_Type;                     /*!< Size = 8 (0x8)                                                            */
217 
218 
219 /**
220   * @brief CLOCK_HFCLKAUDIO [HFCLKAUDIO] (Unspecified)
221   */
222 typedef struct {
223   __IOM uint32_t  FREQUENCY;                    /*!< (@ 0x00000000) Audio PLL frequency in 11.176 MHz - 11.402 MHz
224                                                                     or 12.165 MHz - 12.411 MHz frequency bands                 */
225 } CLOCK_HFCLKAUDIO_Type;                        /*!< Size = 4 (0x4)                                                            */
226 
227 
228 /**
229   * @brief RESET_NETWORK [NETWORK] (ULP network core control)
230   */
231 typedef struct {
232   __IM  uint32_t  RESERVED;
233   __IOM uint32_t  FORCEOFF;                     /*!< (@ 0x00000004) Force network core off                                     */
234 } RESET_NETWORK_Type;                           /*!< Size = 8 (0x8)                                                            */
235 
236 
237 /**
238   * @brief UART_PSEL [PSEL] (Unspecified)
239   */
240 typedef struct {
241   __IOM uint32_t  RTS;                          /*!< (@ 0x00000000) Pin select for RTS                                         */
242   __IOM uint32_t  TXD;                          /*!< (@ 0x00000004) Pin select for TXD                                         */
243   __IOM uint32_t  CTS;                          /*!< (@ 0x00000008) Pin select for CTS                                         */
244   __IOM uint32_t  RXD;                          /*!< (@ 0x0000000C) Pin select for RXD                                         */
245 } UART_PSEL_Type;                               /*!< Size = 16 (0x10)                                                          */
246 
247 
248 /**
249   * @brief UARTE_PSEL [PSEL] (Unspecified)
250   */
251 typedef struct {
252   __IOM uint32_t  RTS;                          /*!< (@ 0x00000000) Pin select for RTS signal                                  */
253   __IOM uint32_t  TXD;                          /*!< (@ 0x00000004) Pin select for TXD signal                                  */
254   __IOM uint32_t  CTS;                          /*!< (@ 0x00000008) Pin select for CTS signal                                  */
255   __IOM uint32_t  RXD;                          /*!< (@ 0x0000000C) Pin select for RXD signal                                  */
256 } UARTE_PSEL_Type;                              /*!< Size = 16 (0x10)                                                          */
257 
258 
259 /**
260   * @brief UARTE_RXD [RXD] (RXD EasyDMA channel)
261   */
262 typedef struct {
263   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Data pointer                                               */
264   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in receive buffer                  */
265   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes transferred in the last transaction        */
266 } UARTE_RXD_Type;                               /*!< Size = 12 (0xc)                                                           */
267 
268 
269 /**
270   * @brief UARTE_TXD [TXD] (TXD EasyDMA channel)
271   */
272 typedef struct {
273   __IOM uint32_t  PTR;                          /*!< (@ 0x00000000) Data pointer                                               */
274   __IOM uint32_t  MAXCNT;                       /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer                 */
275   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000008) Number of bytes transferred in the last transaction        */
276 } UARTE_TXD_Type;                               /*!< Size = 12 (0xc)                                                           */
277 
278 
279 /**
280   * @brief VREQCTRL_VREGRADIO [VREGRADIO] (Unspecified)
281   */
282 typedef struct {
283   __IOM uint32_t  VREQH;                        /*!< (@ 0x00000000) Request high voltage on RADIO After requesting
284                                                                     high voltage, the user must wait until VREQHREADY
285                                                                     is set to Ready                                            */
286   __IM  uint32_t  RESERVED;
287   __IM  uint32_t  VREQHREADY;                   /*!< (@ 0x00000008) High voltage on RADIO is ready                             */
288 } VREQCTRL_VREGRADIO_Type;                      /*!< Size = 12 (0xc)                                                           */
289 
290 /**
291   * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified)
292   */
293 typedef struct {
294   __IOM uint32_t  RX;                           /*!< (@ 0x00000000) Result of last incoming frame                              */
295 } NFCT_FRAMESTATUS_Type;                        /*!< Size = 4 (0x4)                                                            */
296 
297 
298 /**
299   * @brief NFCT_TXD [TXD] (Unspecified)
300   */
301 typedef struct {
302   __IOM uint32_t  FRAMECONFIG;                  /*!< (@ 0x00000000) Configuration of outgoing frames                           */
303   __IOM uint32_t  AMOUNT;                       /*!< (@ 0x00000004) Size of outgoing frame                                     */
304 } NFCT_TXD_Type;                                /*!< Size = 8 (0x8)                                                            */
305 
306 
307 /**
308   * @brief NFCT_RXD [RXD] (Unspecified)
309   */
310 typedef struct {
311   __IOM uint32_t  FRAMECONFIG;                  /*!< (@ 0x00000000) Configuration of incoming frames                           */
312   __IM  uint32_t  AMOUNT;                       /*!< (@ 0x00000004) Size of last incoming frame                                */
313 } NFCT_RXD_Type;                                /*!< Size = 8 (0x8)                                                            */
314 
315 
316 /* =========================================================================================================================== */
317 /* ================                                          AAR                                              ================ */
318 /* =========================================================================================================================== */
319 
320 
321 /**
322   * @brief Accelerated Address Resolver (AAR)
323   */
324 
325 typedef struct {                                /*!< (@ 0x4100E000) AAR_NS Structure                                           */
326   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified
327                                                                     in the IRK data structure                                  */
328   __IM  uint32_t  RESERVED;
329   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000008) Stop resolving addresses                                   */
330   __IM  uint32_t  RESERVED1[29];
331   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000080) Subscribe configuration for task START                     */
332   __IM  uint32_t  RESERVED2;
333   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000088) Subscribe configuration for task STOP                      */
334   __IM  uint32_t  RESERVED3[29];
335   __IOM uint32_t  EVENTS_END;                   /*!< (@ 0x00000100) Address resolution procedure complete                      */
336   __IOM uint32_t  EVENTS_RESOLVED;              /*!< (@ 0x00000104) Address resolved                                           */
337   __IOM uint32_t  EVENTS_NOTRESOLVED;           /*!< (@ 0x00000108) Address not resolved                                       */
338   __IM  uint32_t  RESERVED4[29];
339   __IOM uint32_t  PUBLISH_END;                  /*!< (@ 0x00000180) Publish configuration for event END                        */
340   __IOM uint32_t  PUBLISH_RESOLVED;             /*!< (@ 0x00000184) Publish configuration for event RESOLVED                   */
341   __IOM uint32_t  PUBLISH_NOTRESOLVED;          /*!< (@ 0x00000188) Publish configuration for event NOTRESOLVED                */
342   __IM  uint32_t  RESERVED5[94];
343   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
344   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
345   __IM  uint32_t  RESERVED6[61];
346   __IM  uint32_t  STATUS;                       /*!< (@ 0x00000400) Resolution status                                          */
347   __IM  uint32_t  RESERVED7[63];
348   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable AAR                                                 */
349   __IOM uint32_t  NIRK;                         /*!< (@ 0x00000504) Number of IRKs                                             */
350   __IOM uint32_t  IRKPTR;                       /*!< (@ 0x00000508) Pointer to IRK data structure                              */
351   __IM  uint32_t  RESERVED8;
352   __IOM uint32_t  ADDRPTR;                      /*!< (@ 0x00000510) Pointer to the resolvable address                          */
353   __IOM uint32_t  SCRATCHPTR;                   /*!< (@ 0x00000514) Pointer to data area used for temporary storage            */
354 } NRF_AAR_Type;                                 /*!< Size = 1304 (0x518)                                                       */
355 
356 /* Peripheral: AAR */
357 /* Description: Accelerated Address Resolver */
358 
359 /* Register: AAR_TASKS_START */
360 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */
361 
362 /* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */
363 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
364 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
365 #define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
366 
367 /* Register: AAR_TASKS_STOP */
368 /* Description: Stop resolving addresses */
369 
370 /* Bit 0 : Stop resolving addresses */
371 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
372 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
373 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
374 
375 /* Register: AAR_SUBSCRIBE_START */
376 /* Description: Subscribe configuration for task START */
377 
378 /* Bit 31 :   */
379 #define AAR_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
380 #define AAR_SUBSCRIBE_START_EN_Msk (0x1UL << AAR_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
381 #define AAR_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
382 #define AAR_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
383 
384 /* Bits 7..0 : DPPI channel that task START will subscribe to */
385 #define AAR_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
386 #define AAR_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
387 
388 /* Register: AAR_SUBSCRIBE_STOP */
389 /* Description: Subscribe configuration for task STOP */
390 
391 /* Bit 31 :   */
392 #define AAR_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
393 #define AAR_SUBSCRIBE_STOP_EN_Msk (0x1UL << AAR_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
394 #define AAR_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
395 #define AAR_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
396 
397 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
398 #define AAR_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
399 #define AAR_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
400 
401 /* Register: AAR_EVENTS_END */
402 /* Description: Address resolution procedure complete */
403 
404 /* Bit 0 : Address resolution procedure complete */
405 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
406 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
407 #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
408 #define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
409 
410 /* Register: AAR_EVENTS_RESOLVED */
411 /* Description: Address resolved */
412 
413 /* Bit 0 : Address resolved */
414 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */
415 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */
416 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */
417 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */
418 
419 /* Register: AAR_EVENTS_NOTRESOLVED */
420 /* Description: Address not resolved */
421 
422 /* Bit 0 : Address not resolved */
423 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */
424 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */
425 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */
426 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */
427 
428 /* Register: AAR_PUBLISH_END */
429 /* Description: Publish configuration for event END */
430 
431 /* Bit 31 :   */
432 #define AAR_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
433 #define AAR_PUBLISH_END_EN_Msk (0x1UL << AAR_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
434 #define AAR_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
435 #define AAR_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
436 
437 /* Bits 7..0 : DPPI channel that event END will publish to. */
438 #define AAR_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
439 #define AAR_PUBLISH_END_CHIDX_Msk (0xFFUL << AAR_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
440 
441 /* Register: AAR_PUBLISH_RESOLVED */
442 /* Description: Publish configuration for event RESOLVED */
443 
444 /* Bit 31 :   */
445 #define AAR_PUBLISH_RESOLVED_EN_Pos (31UL) /*!< Position of EN field. */
446 #define AAR_PUBLISH_RESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_RESOLVED_EN_Pos) /*!< Bit mask of EN field. */
447 #define AAR_PUBLISH_RESOLVED_EN_Disabled (0UL) /*!< Disable publishing */
448 #define AAR_PUBLISH_RESOLVED_EN_Enabled (1UL) /*!< Enable publishing */
449 
450 /* Bits 7..0 : DPPI channel that event RESOLVED will publish to. */
451 #define AAR_PUBLISH_RESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
452 #define AAR_PUBLISH_RESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_RESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
453 
454 /* Register: AAR_PUBLISH_NOTRESOLVED */
455 /* Description: Publish configuration for event NOTRESOLVED */
456 
457 /* Bit 31 :   */
458 #define AAR_PUBLISH_NOTRESOLVED_EN_Pos (31UL) /*!< Position of EN field. */
459 #define AAR_PUBLISH_NOTRESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_NOTRESOLVED_EN_Pos) /*!< Bit mask of EN field. */
460 #define AAR_PUBLISH_NOTRESOLVED_EN_Disabled (0UL) /*!< Disable publishing */
461 #define AAR_PUBLISH_NOTRESOLVED_EN_Enabled (1UL) /*!< Enable publishing */
462 
463 /* Bits 7..0 : DPPI channel that event NOTRESOLVED will publish to. */
464 #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
465 #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
466 
467 /* Register: AAR_INTENSET */
468 /* Description: Enable interrupt */
469 
470 /* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */
471 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
472 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
473 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
474 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
475 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
476 
477 /* Bit 1 : Write '1' to enable interrupt for event RESOLVED */
478 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
479 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
480 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
481 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
482 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
483 
484 /* Bit 0 : Write '1' to enable interrupt for event END */
485 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
486 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
487 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
488 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
489 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
490 
491 /* Register: AAR_INTENCLR */
492 /* Description: Disable interrupt */
493 
494 /* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */
495 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
496 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
497 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
498 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
499 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
500 
501 /* Bit 1 : Write '1' to disable interrupt for event RESOLVED */
502 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
503 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
504 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
505 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
506 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
507 
508 /* Bit 0 : Write '1' to disable interrupt for event END */
509 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
510 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
511 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
512 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
513 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
514 
515 /* Register: AAR_STATUS */
516 /* Description: Resolution status */
517 
518 /* Bits 3..0 : The IRK that was used last time an address was resolved */
519 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
520 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
521 
522 /* Register: AAR_ENABLE */
523 /* Description: Enable AAR */
524 
525 /* Bits 1..0 : Enable or disable AAR */
526 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
527 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
528 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
529 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
530 
531 /* Register: AAR_NIRK */
532 /* Description: Number of IRKs */
533 
534 /* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */
535 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
536 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
537 
538 /* Register: AAR_IRKPTR */
539 /* Description: Pointer to IRK data structure */
540 
541 /* Bits 31..0 : Pointer to the IRK data structure */
542 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
543 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
544 
545 /* Register: AAR_ADDRPTR */
546 /* Description: Pointer to the resolvable address */
547 
548 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
549 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
550 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
551 
552 /* Register: AAR_SCRATCHPTR */
553 /* Description: Pointer to data area used for temporary storage */
554 
555 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */
556 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
557 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
558 
559 
560 
561 /* =========================================================================================================================== */
562 /* ================                                          CCM                                              ================ */
563 /* =========================================================================================================================== */
564 
565 
566 /**
567   * @brief AES CCM mode encryption (CCM)
568   */
569 
570 typedef struct {                                /*!< (@ 0x4100E000) CCM_NS Structure                                           */
571   __OM  uint32_t  TASKS_KSGEN;                  /*!< (@ 0x00000000) Start generation of keystream. This operation
572                                                                     will stop by itself when completed.                        */
573   __OM  uint32_t  TASKS_CRYPT;                  /*!< (@ 0x00000004) Start encryption/decryption. This operation will
574                                                                     stop by itself when completed.                             */
575   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000008) Stop encryption/decryption                                 */
576   __OM  uint32_t  TASKS_RATEOVERRIDE;           /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with
577                                                                     the contents of the RATEOVERRIDE register
578                                                                     for any ongoing encryption/decryption                      */
579   __IM  uint32_t  RESERVED[28];
580   __IOM uint32_t  SUBSCRIBE_KSGEN;              /*!< (@ 0x00000080) Subscribe configuration for task KSGEN                     */
581   __IOM uint32_t  SUBSCRIBE_CRYPT;              /*!< (@ 0x00000084) Subscribe configuration for task CRYPT                     */
582   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000088) Subscribe configuration for task STOP                      */
583   __IOM uint32_t  SUBSCRIBE_RATEOVERRIDE;       /*!< (@ 0x0000008C) Subscribe configuration for task RATEOVERRIDE              */
584   __IM  uint32_t  RESERVED1[28];
585   __IOM uint32_t  EVENTS_ENDKSGEN;              /*!< (@ 0x00000100) Keystream generation complete                              */
586   __IOM uint32_t  EVENTS_ENDCRYPT;              /*!< (@ 0x00000104) Encrypt/decrypt complete                                   */
587   __IOM uint32_t  EVENTS_ERROR;                 /*!< (@ 0x00000108) Deprecated register - CCM error event                      */
588   __IM  uint32_t  RESERVED2[29];
589   __IOM uint32_t  PUBLISH_ENDKSGEN;             /*!< (@ 0x00000180) Publish configuration for event ENDKSGEN                   */
590   __IOM uint32_t  PUBLISH_ENDCRYPT;             /*!< (@ 0x00000184) Publish configuration for event ENDCRYPT                   */
591   __IOM uint32_t  PUBLISH_ERROR;                /*!< (@ 0x00000188) Deprecated register - Publish configuration for
592                                                                     event ERROR                                                */
593   __IM  uint32_t  RESERVED3[29];
594   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
595   __IM  uint32_t  RESERVED4[64];
596   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
597   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
598   __IM  uint32_t  RESERVED5[61];
599   __IM  uint32_t  MICSTATUS;                    /*!< (@ 0x00000400) MIC check result                                           */
600   __IM  uint32_t  RESERVED6[63];
601   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable                                                     */
602   __IOM uint32_t  MODE;                         /*!< (@ 0x00000504) Operation mode                                             */
603   __IOM uint32_t  CNFPTR;                       /*!< (@ 0x00000508) Pointer to data structure holding the AES key
604                                                                     and the NONCE vector                                       */
605   __IOM uint32_t  INPTR;                        /*!< (@ 0x0000050C) Input pointer                                              */
606   __IOM uint32_t  OUTPTR;                       /*!< (@ 0x00000510) Output pointer                                             */
607   __IOM uint32_t  SCRATCHPTR;                   /*!< (@ 0x00000514) Pointer to data area used for temporary storage            */
608   __IOM uint32_t  MAXPACKETSIZE;                /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH
609                                                                     = Extended                                                 */
610   __IOM uint32_t  RATEOVERRIDE;                 /*!< (@ 0x0000051C) Data rate override setting.                                */
611   __IOM uint32_t  HEADERMASK;                   /*!< (@ 0x00000520) Header (S0) mask.                                          */
612 } NRF_CCM_Type;                                 /*!< Size = 1316 (0x524)                                                       */
613 
614 
615 /* Peripheral: CCM */
616 /* Description: AES CCM mode encryption */
617 
618 /* Register: CCM_TASKS_KSGEN */
619 /* Description: Start generation of keystream. This operation will stop by itself when completed. */
620 
621 /* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */
622 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */
623 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */
624 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */
625 
626 /* Register: CCM_TASKS_CRYPT */
627 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */
628 
629 /* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */
630 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */
631 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */
632 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */
633 
634 /* Register: CCM_TASKS_STOP */
635 /* Description: Stop encryption/decryption */
636 
637 /* Bit 0 : Stop encryption/decryption */
638 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
639 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
640 #define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
641 
642 /* Register: CCM_TASKS_RATEOVERRIDE */
643 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
644 
645 /* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */
646 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */
647 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */
648 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */
649 
650 /* Register: CCM_SUBSCRIBE_KSGEN */
651 /* Description: Subscribe configuration for task KSGEN */
652 
653 /* Bit 31 :   */
654 #define CCM_SUBSCRIBE_KSGEN_EN_Pos (31UL) /*!< Position of EN field. */
655 #define CCM_SUBSCRIBE_KSGEN_EN_Msk (0x1UL << CCM_SUBSCRIBE_KSGEN_EN_Pos) /*!< Bit mask of EN field. */
656 #define CCM_SUBSCRIBE_KSGEN_EN_Disabled (0UL) /*!< Disable subscription */
657 #define CCM_SUBSCRIBE_KSGEN_EN_Enabled (1UL) /*!< Enable subscription */
658 
659 /* Bits 7..0 : DPPI channel that task KSGEN will subscribe to */
660 #define CCM_SUBSCRIBE_KSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
661 #define CCM_SUBSCRIBE_KSGEN_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_KSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
662 
663 /* Register: CCM_SUBSCRIBE_CRYPT */
664 /* Description: Subscribe configuration for task CRYPT */
665 
666 /* Bit 31 :   */
667 #define CCM_SUBSCRIBE_CRYPT_EN_Pos (31UL) /*!< Position of EN field. */
668 #define CCM_SUBSCRIBE_CRYPT_EN_Msk (0x1UL << CCM_SUBSCRIBE_CRYPT_EN_Pos) /*!< Bit mask of EN field. */
669 #define CCM_SUBSCRIBE_CRYPT_EN_Disabled (0UL) /*!< Disable subscription */
670 #define CCM_SUBSCRIBE_CRYPT_EN_Enabled (1UL) /*!< Enable subscription */
671 
672 /* Bits 7..0 : DPPI channel that task CRYPT will subscribe to */
673 #define CCM_SUBSCRIBE_CRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
674 #define CCM_SUBSCRIBE_CRYPT_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_CRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
675 
676 /* Register: CCM_SUBSCRIBE_STOP */
677 /* Description: Subscribe configuration for task STOP */
678 
679 /* Bit 31 :   */
680 #define CCM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
681 #define CCM_SUBSCRIBE_STOP_EN_Msk (0x1UL << CCM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
682 #define CCM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
683 #define CCM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
684 
685 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
686 #define CCM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
687 #define CCM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
688 
689 /* Register: CCM_SUBSCRIBE_RATEOVERRIDE */
690 /* Description: Subscribe configuration for task RATEOVERRIDE */
691 
692 /* Bit 31 :   */
693 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos (31UL) /*!< Position of EN field. */
694 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Msk (0x1UL << CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos) /*!< Bit mask of EN field. */
695 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Disabled (0UL) /*!< Disable subscription */
696 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (1UL) /*!< Enable subscription */
697 
698 /* Bits 7..0 : DPPI channel that task RATEOVERRIDE will subscribe to */
699 #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
700 #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
701 
702 /* Register: CCM_EVENTS_ENDKSGEN */
703 /* Description: Keystream generation complete */
704 
705 /* Bit 0 : Keystream generation complete */
706 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */
707 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */
708 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */
709 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */
710 
711 /* Register: CCM_EVENTS_ENDCRYPT */
712 /* Description: Encrypt/decrypt complete */
713 
714 /* Bit 0 : Encrypt/decrypt complete */
715 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */
716 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */
717 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */
718 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */
719 
720 /* Register: CCM_EVENTS_ERROR */
721 /* Description: Deprecated register - CCM error event */
722 
723 /* Bit 0 : Deprecated field -  CCM error event */
724 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */
725 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */
726 #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */
727 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */
728 
729 /* Register: CCM_PUBLISH_ENDKSGEN */
730 /* Description: Publish configuration for event ENDKSGEN */
731 
732 /* Bit 31 :   */
733 #define CCM_PUBLISH_ENDKSGEN_EN_Pos (31UL) /*!< Position of EN field. */
734 #define CCM_PUBLISH_ENDKSGEN_EN_Msk (0x1UL << CCM_PUBLISH_ENDKSGEN_EN_Pos) /*!< Bit mask of EN field. */
735 #define CCM_PUBLISH_ENDKSGEN_EN_Disabled (0UL) /*!< Disable publishing */
736 #define CCM_PUBLISH_ENDKSGEN_EN_Enabled (1UL) /*!< Enable publishing */
737 
738 /* Bits 7..0 : DPPI channel that event ENDKSGEN will publish to. */
739 #define CCM_PUBLISH_ENDKSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
740 #define CCM_PUBLISH_ENDKSGEN_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDKSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
741 
742 /* Register: CCM_PUBLISH_ENDCRYPT */
743 /* Description: Publish configuration for event ENDCRYPT */
744 
745 /* Bit 31 :   */
746 #define CCM_PUBLISH_ENDCRYPT_EN_Pos (31UL) /*!< Position of EN field. */
747 #define CCM_PUBLISH_ENDCRYPT_EN_Msk (0x1UL << CCM_PUBLISH_ENDCRYPT_EN_Pos) /*!< Bit mask of EN field. */
748 #define CCM_PUBLISH_ENDCRYPT_EN_Disabled (0UL) /*!< Disable publishing */
749 #define CCM_PUBLISH_ENDCRYPT_EN_Enabled (1UL) /*!< Enable publishing */
750 
751 /* Bits 7..0 : DPPI channel that event ENDCRYPT will publish to. */
752 #define CCM_PUBLISH_ENDCRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
753 #define CCM_PUBLISH_ENDCRYPT_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDCRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
754 
755 /* Register: CCM_PUBLISH_ERROR */
756 /* Description: Deprecated register - Publish configuration for event ERROR */
757 
758 /* Bit 31 :   */
759 #define CCM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */
760 #define CCM_PUBLISH_ERROR_EN_Msk (0x1UL << CCM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */
761 #define CCM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */
762 #define CCM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */
763 
764 /* Bits 7..0 : DPPI channel that event ERROR will publish to. */
765 #define CCM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
766 #define CCM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
767 
768 /* Register: CCM_SHORTS */
769 /* Description: Shortcuts between local events and tasks */
770 
771 /* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */
772 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
773 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
774 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
775 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
776 
777 /* Register: CCM_INTENSET */
778 /* Description: Enable interrupt */
779 
780 /* Bit 2 : Deprecated intsetfield -  Write '1' to enable interrupt for event ERROR */
781 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
782 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
783 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
784 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
785 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
786 
787 /* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */
788 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
789 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
790 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
791 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
792 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
793 
794 /* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */
795 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
796 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
797 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
798 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
799 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
800 
801 /* Register: CCM_INTENCLR */
802 /* Description: Disable interrupt */
803 
804 /* Bit 2 : Deprecated intclrfield -  Write '1' to disable interrupt for event ERROR */
805 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
806 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
807 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
808 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
809 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
810 
811 /* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */
812 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
813 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
814 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
815 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
816 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
817 
818 /* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */
819 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
820 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
821 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
822 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
823 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
824 
825 /* Register: CCM_MICSTATUS */
826 /* Description: MIC check result */
827 
828 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
829 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
830 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
831 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
832 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
833 
834 /* Register: CCM_ENABLE */
835 /* Description: Enable */
836 
837 /* Bits 1..0 : Enable or disable CCM */
838 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
839 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
840 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
841 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
842 
843 /* Register: CCM_MODE */
844 /* Description: Operation mode */
845 
846 /* Bit 24 : Packet length configuration */
847 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
848 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
849 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */
850 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */
851 
852 /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
853 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
854 #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
855 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
856 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
857 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */
858 #define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */
859 
860 /* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */
861 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
862 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
863 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
864 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
865 
866 /* Register: CCM_CNFPTR */
867 /* Description: Pointer to data structure holding the AES key and the NONCE vector */
868 
869 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */
870 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
871 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
872 
873 /* Register: CCM_INPTR */
874 /* Description: Input pointer */
875 
876 /* Bits 31..0 : Input pointer */
877 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
878 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
879 
880 /* Register: CCM_OUTPTR */
881 /* Description: Output pointer */
882 
883 /* Bits 31..0 : Output pointer */
884 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
885 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
886 
887 /* Register: CCM_SCRATCHPTR */
888 /* Description: Pointer to data area used for temporary storage */
889 
890 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation,
891         MIC generation and encryption/decryption. */
892 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
893 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
894 
895 /* Register: CCM_MAXPACKETSIZE */
896 /* Description: Length of keystream generated when MODE.LENGTH = Extended */
897 
898 /* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */
899 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
900 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
901 
902 /* Register: CCM_RATEOVERRIDE */
903 /* Description: Data rate override setting. */
904 
905 /* Bits 1..0 : Data rate override setting */
906 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
907 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
908 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
909 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
910 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */
911 #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */
912 
913 /* Register: CCM_HEADERMASK */
914 /* Description: Header (S0) mask. */
915 
916 /* Bits 7..0 : Header (S0) mask */
917 #define CCM_HEADERMASK_HEADERMASK_Pos (0UL) /*!< Position of HEADERMASK field. */
918 #define CCM_HEADERMASK_HEADERMASK_Msk (0xFFUL << CCM_HEADERMASK_HEADERMASK_Pos) /*!< Bit mask of HEADERMASK field. */
919 
920 
921 
922 /* =========================================================================================================================== */
923 /* ================                                         CLOCK                                          ================ */
924 /* =========================================================================================================================== */
925 
926 
927 /**
928   * @brief Clock management (CLOCK)
929   */
930 
931 typedef struct {                                /*!< (@ 0x40005000) CLOCK_NS Structure                                         */
932   __OM  uint32_t  TASKS_HFCLKSTART;             /*!< (@ 0x00000000) Start HFCLK128M/HFCLK64M source as selected in
933                                                                     HFCLKSRC                                                   */
934   __OM  uint32_t  TASKS_HFCLKSTOP;              /*!< (@ 0x00000004) Stop HFCLK128M/HFCLK64M source                             */
935   __OM  uint32_t  TASKS_LFCLKSTART;             /*!< (@ 0x00000008) Start LFCLK source as selected in LFCLKSRC                 */
936   __OM  uint32_t  TASKS_LFCLKSTOP;              /*!< (@ 0x0000000C) Stop LFCLK source                                          */
937   __OM  uint32_t  TASKS_CAL;                    /*!< (@ 0x00000010) Start calibration of LFRC oscillator                       */
938   __IM  uint32_t  RESERVED;
939   __OM  uint32_t  TASKS_HFCLKAUDIOSTART;        /*!< (@ 0x00000018) Start HFCLKAUDIO source                                    */
940   __OM  uint32_t  TASKS_HFCLKAUDIOSTOP;         /*!< (@ 0x0000001C) Stop HFCLKAUDIO source                                     */
941   __OM  uint32_t  TASKS_HFCLK192MSTART;         /*!< (@ 0x00000020) Start HFCLK192M source as selected in HFCLK192MSRC         */
942   __OM  uint32_t  TASKS_HFCLK192MSTOP;          /*!< (@ 0x00000024) Stop HFCLK192M source                                      */
943   __IM  uint32_t  RESERVED1[22];
944   __IOM uint32_t  SUBSCRIBE_HFCLKSTART;         /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART                */
945   __IOM uint32_t  SUBSCRIBE_HFCLKSTOP;          /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP                 */
946   __IOM uint32_t  SUBSCRIBE_LFCLKSTART;         /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART                */
947   __IOM uint32_t  SUBSCRIBE_LFCLKSTOP;          /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP                 */
948   __IOM uint32_t  SUBSCRIBE_CAL;                /*!< (@ 0x00000090) Subscribe configuration for task CAL                       */
949   __IM  uint32_t  RESERVED2;
950   __IOM uint32_t  SUBSCRIBE_HFCLKAUDIOSTART;    /*!< (@ 0x00000098) Subscribe configuration for task HFCLKAUDIOSTART           */
951   __IOM uint32_t  SUBSCRIBE_HFCLKAUDIOSTOP;     /*!< (@ 0x0000009C) Subscribe configuration for task HFCLKAUDIOSTOP            */
952   __IOM uint32_t  SUBSCRIBE_HFCLK192MSTART;     /*!< (@ 0x000000A0) Subscribe configuration for task HFCLK192MSTART            */
953   __IOM uint32_t  SUBSCRIBE_HFCLK192MSTOP;      /*!< (@ 0x000000A4) Subscribe configuration for task HFCLK192MSTOP             */
954   __IM  uint32_t  RESERVED3[22];
955   __IOM uint32_t  EVENTS_HFCLKSTARTED;          /*!< (@ 0x00000100) HFCLK128M/HFCLK64M source started                          */
956   __IOM uint32_t  EVENTS_LFCLKSTARTED;          /*!< (@ 0x00000104) LFCLK source started                                       */
957   __IM  uint32_t  RESERVED4[5];
958   __IOM uint32_t  EVENTS_DONE;                  /*!< (@ 0x0000011C) Calibration of LFRC oscillator complete event              */
959   __IOM uint32_t  EVENTS_HFCLKAUDIOSTARTED;     /*!< (@ 0x00000120) HFCLKAUDIO source started                                  */
960   __IOM uint32_t  EVENTS_HFCLK192MSTARTED;      /*!< (@ 0x00000124) HFCLK192M source started                                   */
961   __IM  uint32_t  RESERVED5[22];
962   __IOM uint32_t  PUBLISH_HFCLKSTARTED;         /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED               */
963   __IOM uint32_t  PUBLISH_LFCLKSTARTED;         /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED               */
964   __IM  uint32_t  RESERVED6[5];
965   __IOM uint32_t  PUBLISH_DONE;                 /*!< (@ 0x0000019C) Publish configuration for event DONE                       */
966   __IOM uint32_t  PUBLISH_HFCLKAUDIOSTARTED;    /*!< (@ 0x000001A0) Publish configuration for event HFCLKAUDIOSTARTED          */
967   __IOM uint32_t  PUBLISH_HFCLK192MSTARTED;     /*!< (@ 0x000001A4) Publish configuration for event HFCLK192MSTARTED           */
968   __IM  uint32_t  RESERVED7[86];
969   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
970   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
971   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
972   __IM  uint32_t  INTPEND;                      /*!< (@ 0x0000030C) Pending interrupts                                         */
973   __IM  uint32_t  RESERVED8[62];
974   __IM  uint32_t  HFCLKRUN;                     /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been
975                                                                     triggered                                                  */
976   __IM  uint32_t  HFCLKSTAT;                    /*!< (@ 0x0000040C) Status indicating which HFCLK128M/HFCLK64M source
977                                                                     is running This register value in any CLOCK
978                                                                     instance reflects status only due to configurations/action
979                                                                     in that CLOCK instance.                                    */
980   __IM  uint32_t  RESERVED9;
981   __IM  uint32_t  LFCLKRUN;                     /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been
982                                                                     triggered                                                  */
983   __IM  uint32_t  LFCLKSTAT;                    /*!< (@ 0x00000418) Status indicating which LFCLK source is running
984                                                                     This register value in any CLOCK instance
985                                                                     reflects status only due to configurations/actions
986                                                                     in that CLOCK instance.                                    */
987   __IM  uint32_t  LFCLKSRCCOPY;                 /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART
988                                                                     task was triggered                                         */
989   __IM  uint32_t  RESERVED10[12];
990   __IM  uint32_t  HFCLKAUDIORUN;                /*!< (@ 0x00000450) Status indicating that HFCLKAUDIOSTART task has
991                                                                     been triggered                                             */
992   __IM  uint32_t  HFCLKAUDIOSTAT;               /*!< (@ 0x00000454) Status indicating which HFCLKAUDIO source is
993                                                                     running                                                    */
994   __IM  uint32_t  HFCLK192MRUN;                 /*!< (@ 0x00000458) Status indicating that HFCLK192MSTART task has
995                                                                     been triggered                                             */
996   __IM  uint32_t  HFCLK192MSTAT;                /*!< (@ 0x0000045C) Status indicating which HFCLK192M source is running        */
997   __IM  uint32_t  RESERVED11[45];
998   __IOM uint32_t  HFCLKSRC;                     /*!< (@ 0x00000514) Clock source for HFCLK128M/HFCLK64M                        */
999   __IOM uint32_t  LFCLKSRC;                     /*!< (@ 0x00000518) Clock source for LFCLK                                     */
1000   __IM  uint32_t  RESERVED12[15];
1001   __IOM uint32_t  HFCLKCTRL;                    /*!< (@ 0x00000558) HFCLK128M frequency configuration                          */
1002   __IOM CLOCK_HFCLKAUDIO_Type HFCLKAUDIO;       /*!< (@ 0x0000055C) Unspecified                                                */
1003   __IM  uint32_t  RESERVED13[4];
1004   __IOM uint32_t  HFCLKALWAYSRUN;               /*!< (@ 0x00000570) Automatic or manual control of HFCLK128M/HFCLK64M          */
1005   __IOM uint32_t  LFCLKALWAYSRUN;               /*!< (@ 0x00000574) Automatic or manual control of LFCLK                       */
1006   __IM  uint32_t  RESERVED14;
1007   __IOM uint32_t  HFCLKAUDIOALWAYSRUN;          /*!< (@ 0x0000057C) Automatic or manual control of HFCLKAUDIO                  */
1008   __IOM uint32_t  HFCLK192MSRC;                 /*!< (@ 0x00000580) Clock source for HFCLK192M                                 */
1009   __IOM uint32_t  HFCLK192MALWAYSRUN;           /*!< (@ 0x00000584) Automatic or manual control of HFCLK192M                   */
1010   __IM  uint32_t  RESERVED15[12];
1011   __IOM uint32_t  HFCLK192MCTRL;                /*!< (@ 0x000005B8) HFCLK192M frequency configuration                          */
1012 } NRF_CLOCK_Type;                               /*!< Size = 1468 (0x5bc)                                                       */
1013 
1014 
1015 /* Peripheral: CLOCK */
1016 /* Description: Clock management 0 */
1017 
1018 /* Register: CLOCK_TASKS_HFCLKSTART */
1019 /* Description: Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */
1020 
1021 /* Bit 0 : Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */
1022 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */
1023 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */
1024 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */
1025 
1026 /* Register: CLOCK_TASKS_HFCLKSTOP */
1027 /* Description: Stop HFCLK128M/HFCLK64M source */
1028 
1029 /* Bit 0 : Stop HFCLK128M/HFCLK64M source */
1030 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */
1031 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */
1032 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */
1033 
1034 /* Register: CLOCK_TASKS_LFCLKSTART */
1035 /* Description: Start LFCLK source as selected in LFCLKSRC */
1036 
1037 /* Bit 0 : Start LFCLK source as selected in LFCLKSRC */
1038 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */
1039 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */
1040 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */
1041 
1042 /* Register: CLOCK_TASKS_LFCLKSTOP */
1043 /* Description: Stop LFCLK source */
1044 
1045 /* Bit 0 : Stop LFCLK source */
1046 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */
1047 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */
1048 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */
1049 
1050 /* Register: CLOCK_TASKS_CAL */
1051 /* Description: Start calibration of LFRC oscillator */
1052 
1053 /* Bit 0 : Start calibration of LFRC oscillator */
1054 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */
1055 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */
1056 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */
1057 
1058 /* Register: CLOCK_TASKS_HFCLKAUDIOSTART */
1059 /* Description: Start HFCLKAUDIO source */
1060 
1061 /* Bit 0 : Start HFCLKAUDIO source */
1062 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTART field. */
1063 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTART field. */
1064 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Trigger (1UL) /*!< Trigger task */
1065 
1066 /* Register: CLOCK_TASKS_HFCLKAUDIOSTOP */
1067 /* Description: Stop HFCLKAUDIO source */
1068 
1069 /* Bit 0 : Stop HFCLKAUDIO source */
1070 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTOP field. */
1071 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTOP field. */
1072 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Trigger (1UL) /*!< Trigger task */
1073 
1074 /* Register: CLOCK_TASKS_HFCLK192MSTART */
1075 /* Description: Start HFCLK192M source as selected in HFCLK192MSRC */
1076 
1077 /* Bit 0 : Start HFCLK192M source as selected in HFCLK192MSRC */
1078 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTART field. */
1079 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos) /*!< Bit mask of TASKS_HFCLK192MSTART field. */
1080 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Trigger (1UL) /*!< Trigger task */
1081 
1082 /* Register: CLOCK_TASKS_HFCLK192MSTOP */
1083 /* Description: Stop HFCLK192M source */
1084 
1085 /* Bit 0 : Stop HFCLK192M source */
1086 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTOP field. */
1087 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos) /*!< Bit mask of TASKS_HFCLK192MSTOP field. */
1088 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Trigger (1UL) /*!< Trigger task */
1089 
1090 /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */
1091 /* Description: Subscribe configuration for task HFCLKSTART */
1092 
1093 /* Bit 31 :   */
1094 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
1095 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
1096 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
1097 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
1098 
1099 /* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */
1100 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1101 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1102 
1103 /* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */
1104 /* Description: Subscribe configuration for task HFCLKSTOP */
1105 
1106 /* Bit 31 :   */
1107 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
1108 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
1109 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
1110 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
1111 
1112 /* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */
1113 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1114 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1115 
1116 /* Register: CLOCK_SUBSCRIBE_LFCLKSTART */
1117 /* Description: Subscribe configuration for task LFCLKSTART */
1118 
1119 /* Bit 31 :   */
1120 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */
1121 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */
1122 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */
1123 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */
1124 
1125 /* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */
1126 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1127 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1128 
1129 /* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */
1130 /* Description: Subscribe configuration for task LFCLKSTOP */
1131 
1132 /* Bit 31 :   */
1133 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */
1134 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */
1135 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */
1136 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */
1137 
1138 /* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */
1139 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1140 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1141 
1142 /* Register: CLOCK_SUBSCRIBE_CAL */
1143 /* Description: Subscribe configuration for task CAL */
1144 
1145 /* Bit 31 :   */
1146 #define CLOCK_SUBSCRIBE_CAL_EN_Pos (31UL) /*!< Position of EN field. */
1147 #define CLOCK_SUBSCRIBE_CAL_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_CAL_EN_Pos) /*!< Bit mask of EN field. */
1148 #define CLOCK_SUBSCRIBE_CAL_EN_Disabled (0UL) /*!< Disable subscription */
1149 #define CLOCK_SUBSCRIBE_CAL_EN_Enabled (1UL) /*!< Enable subscription */
1150 
1151 /* Bits 7..0 : DPPI channel that task CAL will subscribe to */
1152 #define CLOCK_SUBSCRIBE_CAL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1153 #define CLOCK_SUBSCRIBE_CAL_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_CAL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1154 
1155 /* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTART */
1156 /* Description: Subscribe configuration for task HFCLKAUDIOSTART */
1157 
1158 /* Bit 31 :   */
1159 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos (31UL) /*!< Position of EN field. */
1160 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos) /*!< Bit mask of EN field. */
1161 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Disabled (0UL) /*!< Disable subscription */
1162 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Enabled (1UL) /*!< Enable subscription */
1163 
1164 /* Bits 7..0 : DPPI channel that task HFCLKAUDIOSTART will subscribe to */
1165 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1166 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1167 
1168 /* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP */
1169 /* Description: Subscribe configuration for task HFCLKAUDIOSTOP */
1170 
1171 /* Bit 31 :   */
1172 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos (31UL) /*!< Position of EN field. */
1173 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos) /*!< Bit mask of EN field. */
1174 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Disabled (0UL) /*!< Disable subscription */
1175 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Enabled (1UL) /*!< Enable subscription */
1176 
1177 /* Bits 7..0 : DPPI channel that task HFCLKAUDIOSTOP will subscribe to */
1178 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1179 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1180 
1181 /* Register: CLOCK_SUBSCRIBE_HFCLK192MSTART */
1182 /* Description: Subscribe configuration for task HFCLK192MSTART */
1183 
1184 /* Bit 31 :   */
1185 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos (31UL) /*!< Position of EN field. */
1186 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos) /*!< Bit mask of EN field. */
1187 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Disabled (0UL) /*!< Disable subscription */
1188 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Enabled (1UL) /*!< Enable subscription */
1189 
1190 /* Bits 7..0 : DPPI channel that task HFCLK192MSTART will subscribe to */
1191 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1192 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1193 
1194 /* Register: CLOCK_SUBSCRIBE_HFCLK192MSTOP */
1195 /* Description: Subscribe configuration for task HFCLK192MSTOP */
1196 
1197 /* Bit 31 :   */
1198 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos (31UL) /*!< Position of EN field. */
1199 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos) /*!< Bit mask of EN field. */
1200 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Disabled (0UL) /*!< Disable subscription */
1201 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Enabled (1UL) /*!< Enable subscription */
1202 
1203 /* Bits 7..0 : DPPI channel that task HFCLK192MSTOP will subscribe to */
1204 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1205 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1206 
1207 /* Register: CLOCK_EVENTS_HFCLKSTARTED */
1208 /* Description: HFCLK128M/HFCLK64M source started */
1209 
1210 /* Bit 0 : HFCLK128M/HFCLK64M source started */
1211 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */
1212 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */
1213 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
1214 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */
1215 
1216 /* Register: CLOCK_EVENTS_LFCLKSTARTED */
1217 /* Description: LFCLK source started */
1218 
1219 /* Bit 0 : LFCLK source started */
1220 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */
1221 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */
1222 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */
1223 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */
1224 
1225 /* Register: CLOCK_EVENTS_DONE */
1226 /* Description: Calibration of LFRC oscillator complete event */
1227 
1228 /* Bit 0 : Calibration of LFRC oscillator complete event */
1229 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */
1230 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */
1231 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */
1232 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */
1233 
1234 /* Register: CLOCK_EVENTS_HFCLKAUDIOSTARTED */
1235 /* Description: HFCLKAUDIO source started */
1236 
1237 /* Bit 0 : HFCLKAUDIO source started */
1238 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKAUDIOSTARTED field. */
1239 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKAUDIOSTARTED field. */
1240 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_NotGenerated (0UL) /*!< Event not generated */
1241 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Generated (1UL) /*!< Event generated */
1242 
1243 /* Register: CLOCK_EVENTS_HFCLK192MSTARTED */
1244 /* Description: HFCLK192M source started */
1245 
1246 /* Bit 0 : HFCLK192M source started */
1247 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLK192MSTARTED field. */
1248 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLK192MSTARTED field. */
1249 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_NotGenerated (0UL) /*!< Event not generated */
1250 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Generated (1UL) /*!< Event generated */
1251 
1252 /* Register: CLOCK_PUBLISH_HFCLKSTARTED */
1253 /* Description: Publish configuration for event HFCLKSTARTED */
1254 
1255 /* Bit 31 :   */
1256 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
1257 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
1258 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
1259 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
1260 
1261 /* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to. */
1262 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1263 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1264 
1265 /* Register: CLOCK_PUBLISH_LFCLKSTARTED */
1266 /* Description: Publish configuration for event LFCLKSTARTED */
1267 
1268 /* Bit 31 :   */
1269 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
1270 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */
1271 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
1272 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
1273 
1274 /* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to. */
1275 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1276 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1277 
1278 /* Register: CLOCK_PUBLISH_DONE */
1279 /* Description: Publish configuration for event DONE */
1280 
1281 /* Bit 31 :   */
1282 #define CLOCK_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */
1283 #define CLOCK_PUBLISH_DONE_EN_Msk (0x1UL << CLOCK_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */
1284 #define CLOCK_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */
1285 #define CLOCK_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */
1286 
1287 /* Bits 7..0 : DPPI channel that event DONE will publish to. */
1288 #define CLOCK_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1289 #define CLOCK_PUBLISH_DONE_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1290 
1291 /* Register: CLOCK_PUBLISH_HFCLKAUDIOSTARTED */
1292 /* Description: Publish configuration for event HFCLKAUDIOSTARTED */
1293 
1294 /* Bit 31 :   */
1295 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
1296 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos) /*!< Bit mask of EN field. */
1297 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
1298 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
1299 
1300 /* Bits 7..0 : DPPI channel that event HFCLKAUDIOSTARTED will publish to. */
1301 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1302 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1303 
1304 /* Register: CLOCK_PUBLISH_HFCLK192MSTARTED */
1305 /* Description: Publish configuration for event HFCLK192MSTARTED */
1306 
1307 /* Bit 31 :   */
1308 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos (31UL) /*!< Position of EN field. */
1309 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos) /*!< Bit mask of EN field. */
1310 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Disabled (0UL) /*!< Disable publishing */
1311 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Enabled (1UL) /*!< Enable publishing */
1312 
1313 /* Bits 7..0 : DPPI channel that event HFCLK192MSTARTED will publish to. */
1314 #define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1315 #define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1316 
1317 /* Register: CLOCK_INTEN */
1318 /* Description: Enable or disable interrupt */
1319 
1320 /* Bit 9 : Enable or disable interrupt for event HFCLK192MSTARTED */
1321 #define CLOCK_INTEN_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
1322 #define CLOCK_INTEN_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
1323 #define CLOCK_INTEN_HFCLK192MSTARTED_Disabled (0UL) /*!< Disable */
1324 #define CLOCK_INTEN_HFCLK192MSTARTED_Enabled (1UL) /*!< Enable */
1325 
1326 /* Bit 8 : Enable or disable interrupt for event HFCLKAUDIOSTARTED */
1327 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
1328 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
1329 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Disable */
1330 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Enable */
1331 
1332 /* Bit 7 : Enable or disable interrupt for event DONE */
1333 #define CLOCK_INTEN_DONE_Pos (7UL) /*!< Position of DONE field. */
1334 #define CLOCK_INTEN_DONE_Msk (0x1UL << CLOCK_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
1335 #define CLOCK_INTEN_DONE_Disabled (0UL) /*!< Disable */
1336 #define CLOCK_INTEN_DONE_Enabled (1UL) /*!< Enable */
1337 
1338 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */
1339 #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1340 #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1341 #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */
1342 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */
1343 
1344 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */
1345 #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1346 #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1347 #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */
1348 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */
1349 
1350 /* Register: CLOCK_INTENSET */
1351 /* Description: Enable interrupt */
1352 
1353 /* Bit 9 : Write '1' to enable interrupt for event HFCLK192MSTARTED */
1354 #define CLOCK_INTENSET_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
1355 #define CLOCK_INTENSET_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
1356 #define CLOCK_INTENSET_HFCLK192MSTARTED_Disabled (0UL) /*!< Read: Disabled */
1357 #define CLOCK_INTENSET_HFCLK192MSTARTED_Enabled (1UL) /*!< Read: Enabled */
1358 #define CLOCK_INTENSET_HFCLK192MSTARTED_Set (1UL) /*!< Enable */
1359 
1360 /* Bit 8 : Write '1' to enable interrupt for event HFCLKAUDIOSTARTED */
1361 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
1362 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
1363 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Read: Disabled */
1364 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Read: Enabled */
1365 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Set (1UL) /*!< Enable */
1366 
1367 /* Bit 7 : Write '1' to enable interrupt for event DONE */
1368 #define CLOCK_INTENSET_DONE_Pos (7UL) /*!< Position of DONE field. */
1369 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
1370 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
1371 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
1372 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
1373 
1374 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */
1375 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1376 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1377 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1378 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1379 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
1380 
1381 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */
1382 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1383 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1384 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1385 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1386 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
1387 
1388 /* Register: CLOCK_INTENCLR */
1389 /* Description: Disable interrupt */
1390 
1391 /* Bit 9 : Write '1' to disable interrupt for event HFCLK192MSTARTED */
1392 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
1393 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
1394 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Disabled (0UL) /*!< Read: Disabled */
1395 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Enabled (1UL) /*!< Read: Enabled */
1396 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Clear (1UL) /*!< Disable */
1397 
1398 /* Bit 8 : Write '1' to disable interrupt for event HFCLKAUDIOSTARTED */
1399 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
1400 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
1401 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Read: Disabled */
1402 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Read: Enabled */
1403 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Clear (1UL) /*!< Disable */
1404 
1405 /* Bit 7 : Write '1' to disable interrupt for event DONE */
1406 #define CLOCK_INTENCLR_DONE_Pos (7UL) /*!< Position of DONE field. */
1407 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
1408 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
1409 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
1410 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
1411 
1412 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */
1413 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1414 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1415 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1416 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1417 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
1418 
1419 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */
1420 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1421 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1422 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1423 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1424 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
1425 
1426 /* Register: CLOCK_INTPEND */
1427 /* Description: Pending interrupts */
1428 
1429 /* Bit 9 : Read pending status of interrupt for event HFCLK192MSTARTED */
1430 #define CLOCK_INTPEND_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */
1431 #define CLOCK_INTPEND_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */
1432 #define CLOCK_INTPEND_HFCLK192MSTARTED_NotPending (0UL) /*!< Read: Not pending */
1433 #define CLOCK_INTPEND_HFCLK192MSTARTED_Pending (1UL) /*!< Read: Pending */
1434 
1435 /* Bit 8 : Read pending status of interrupt for event HFCLKAUDIOSTARTED */
1436 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */
1437 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */
1438 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_NotPending (0UL) /*!< Read: Not pending */
1439 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pending (1UL) /*!< Read: Pending */
1440 
1441 /* Bit 7 : Read pending status of interrupt for event DONE */
1442 #define CLOCK_INTPEND_DONE_Pos (7UL) /*!< Position of DONE field. */
1443 #define CLOCK_INTPEND_DONE_Msk (0x1UL << CLOCK_INTPEND_DONE_Pos) /*!< Bit mask of DONE field. */
1444 #define CLOCK_INTPEND_DONE_NotPending (0UL) /*!< Read: Not pending */
1445 #define CLOCK_INTPEND_DONE_Pending (1UL) /*!< Read: Pending */
1446 
1447 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */
1448 #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1449 #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1450 #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
1451 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
1452 
1453 /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */
1454 #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1455 #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1456 #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */
1457 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */
1458 
1459 /* Register: CLOCK_HFCLKRUN */
1460 /* Description: Status indicating that HFCLKSTART task has been triggered */
1461 
1462 /* Bit 0 : HFCLKSTART task triggered or not */
1463 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1464 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1465 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1466 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1467 
1468 /* Register: CLOCK_HFCLKSTAT */
1469 /* Description: Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */
1470 
1471 /* Bit 16 : HFCLK state */
1472 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1473 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1474 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
1475 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
1476 
1477 /* Bit 4 : ALWAYSRUN activated */
1478 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
1479 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
1480 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */
1481 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */
1482 
1483 /* Bit 0 : Active clock source */
1484 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
1485 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
1486 #define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< Clock source: HFINT - 128 MHz on-chip oscillator */
1487 #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator */
1488 
1489 /* Register: CLOCK_LFCLKRUN */
1490 /* Description: Status indicating that LFCLKSTART task has been triggered */
1491 
1492 /* Bit 0 : LFCLKSTART task triggered or not */
1493 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1494 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1495 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1496 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1497 
1498 /* Register: CLOCK_LFCLKSTAT */
1499 /* Description: Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */
1500 
1501 /* Bit 16 : LFCLK state */
1502 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1503 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1504 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
1505 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
1506 
1507 /* Bit 4 : ALWAYSRUN activated */
1508 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
1509 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
1510 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */
1511 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */
1512 
1513 /* Bits 1..0 : Active clock source */
1514 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
1515 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
1516 #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
1517 #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
1518 #define CLOCK_LFCLKSTAT_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */
1519 
1520 /* Register: CLOCK_LFCLKSRCCOPY */
1521 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
1522 
1523 /* Bits 1..0 : Clock source */
1524 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
1525 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
1526 #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
1527 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
1528 #define CLOCK_LFCLKSRCCOPY_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */
1529 
1530 /* Register: CLOCK_HFCLKAUDIORUN */
1531 /* Description: Status indicating that HFCLKAUDIOSTART task has been triggered */
1532 
1533 /* Bit 0 : HFCLKAUDIOSTART task triggered or not */
1534 #define CLOCK_HFCLKAUDIORUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1535 #define CLOCK_HFCLKAUDIORUN_STATUS_Msk (0x1UL << CLOCK_HFCLKAUDIORUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1536 #define CLOCK_HFCLKAUDIORUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1537 #define CLOCK_HFCLKAUDIORUN_STATUS_Triggered (1UL) /*!< Task triggered */
1538 
1539 /* Register: CLOCK_HFCLKAUDIOSTAT */
1540 /* Description: Status indicating which HFCLKAUDIO source is running */
1541 
1542 /* Bit 16 : HFCLKAUDIO state */
1543 #define CLOCK_HFCLKAUDIOSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1544 #define CLOCK_HFCLKAUDIOSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1545 #define CLOCK_HFCLKAUDIOSTAT_STATE_NotRunning (0UL) /*!< HFCLKAUDIO not running */
1546 #define CLOCK_HFCLKAUDIOSTAT_STATE_Running (1UL) /*!< HFCLKAUDIO running */
1547 
1548 /* Bit 4 : ALWAYSRUN activated */
1549 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
1550 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
1551 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */
1552 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */
1553 
1554 /* Register: CLOCK_HFCLK192MRUN */
1555 /* Description: Status indicating that HFCLK192MSTART task has been triggered */
1556 
1557 /* Bit 0 : HFCLK192MSTART task triggered or not */
1558 #define CLOCK_HFCLK192MRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1559 #define CLOCK_HFCLK192MRUN_STATUS_Msk (0x1UL << CLOCK_HFCLK192MRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1560 #define CLOCK_HFCLK192MRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1561 #define CLOCK_HFCLK192MRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1562 
1563 /* Register: CLOCK_HFCLK192MSTAT */
1564 /* Description: Status indicating which HFCLK192M source is running */
1565 
1566 /* Bit 16 : HFCLK192M state */
1567 #define CLOCK_HFCLK192MSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1568 #define CLOCK_HFCLK192MSTAT_STATE_Msk (0x1UL << CLOCK_HFCLK192MSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1569 #define CLOCK_HFCLK192MSTAT_STATE_NotRunning (0UL) /*!< HFCLK192M not running */
1570 #define CLOCK_HFCLK192MSTAT_STATE_Running (1UL) /*!< HFCLK192M running */
1571 
1572 /* Bit 4 : ALWAYSRUN activated */
1573 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */
1574 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */
1575 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */
1576 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */
1577 
1578 /* Bit 0 : Active clock source */
1579 #define CLOCK_HFCLK192MSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
1580 #define CLOCK_HFCLK192MSTAT_SRC_Msk (0x1UL << CLOCK_HFCLK192MSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
1581 #define CLOCK_HFCLK192MSTAT_SRC_HFINT (0UL) /*!< Clock source: HFINT - on-chip oscillator */
1582 #define CLOCK_HFCLK192MSTAT_SRC_HFXO (1UL) /*!< Clock source: HFXO - derived from external 32 MHz crystal oscillator */
1583 
1584 /* Register: CLOCK_HFCLKSRC */
1585 /* Description: Clock source for HFCLK128M/HFCLK64M */
1586 
1587 /* Bit 0 : Select which HFCLK source is started by the HFCLKSTART task */
1588 #define CLOCK_HFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
1589 #define CLOCK_HFCLKSRC_SRC_Msk (0x1UL << CLOCK_HFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
1590 #define CLOCK_HFCLKSRC_SRC_HFINT (0UL) /*!< HFCLKSTART task starts HFINT oscillator */
1591 #define CLOCK_HFCLKSRC_SRC_HFXO (1UL) /*!< HFCLKSTART task starts HFXO oscillator */
1592 
1593 /* Register: CLOCK_LFCLKSRC */
1594 /* Description: Clock source for LFCLK */
1595 
1596 /* Bits 1..0 : Select which LFCLK source is started by the LFCLKSTART task */
1597 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
1598 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
1599 #define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */
1600 #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */
1601 #define CLOCK_LFCLKSRC_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */
1602 
1603 /* Register: CLOCK_HFCLKCTRL */
1604 /* Description: HFCLK128M frequency configuration */
1605 
1606 /* Bits 1..0 : High frequency clock HCLK */
1607 #define CLOCK_HFCLKCTRL_HCLK_Pos (0UL) /*!< Position of HCLK field. */
1608 #define CLOCK_HFCLKCTRL_HCLK_Msk (0x3UL << CLOCK_HFCLKCTRL_HCLK_Pos) /*!< Bit mask of HCLK field. */
1609 #define CLOCK_HFCLKCTRL_HCLK_Div1 (0UL) /*!< Divide HFCLK by 1 */
1610 #define CLOCK_HFCLKCTRL_HCLK_Div2 (1UL) /*!< Divide HFCLK by 2 */
1611 
1612 /* Register: CLOCK_HFCLKAUDIO_FREQUENCY */
1613 /* Description: Audio PLL frequency in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands */
1614 
1615 /* Bits 15..0 : Frequency 0: 10.666 MHz 65535: 13.333 MHz */
1616 #define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
1617 #define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Msk (0xFFFFUL << CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
1618 
1619 /* Register: CLOCK_HFCLKALWAYSRUN */
1620 /* Description: Automatic or manual control of HFCLK128M/HFCLK64M */
1621 
1622 /* Bit 0 : Ensure clock is always running */
1623 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
1624 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
1625 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */
1626 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */
1627 
1628 /* Register: CLOCK_LFCLKALWAYSRUN */
1629 /* Description: Automatic or manual control of LFCLK */
1630 
1631 /* Bit 0 : Ensure clock is always running */
1632 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
1633 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
1634 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */
1635 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */
1636 
1637 /* Register: CLOCK_HFCLKAUDIOALWAYSRUN */
1638 /* Description: Automatic or manual control of HFCLKAUDIO */
1639 
1640 /* Bit 0 : Ensure clock is always running */
1641 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
1642 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
1643 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */
1644 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */
1645 
1646 /* Register: CLOCK_HFCLK192MSRC */
1647 /* Description: Clock source for HFCLK192M */
1648 
1649 /* Bit 0 : Select which HFCLK192M source is started by the HFCLK192MSTART task */
1650 #define CLOCK_HFCLK192MSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
1651 #define CLOCK_HFCLK192MSRC_SRC_Msk (0x1UL << CLOCK_HFCLK192MSRC_SRC_Pos) /*!< Bit mask of SRC field. */
1652 #define CLOCK_HFCLK192MSRC_SRC_HFINT (0UL) /*!< HFCLK192MSTART task starts HFINT oscillator */
1653 #define CLOCK_HFCLK192MSRC_SRC_HFXO (1UL) /*!< HFCLK192MSTART task starts HFXO oscillator */
1654 
1655 /* Register: CLOCK_HFCLK192MALWAYSRUN */
1656 /* Description: Automatic or manual control of HFCLK192M */
1657 
1658 /* Bit 0 : Ensure clock is always running */
1659 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */
1660 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */
1661 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */
1662 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */
1663 
1664 /* Register: CLOCK_HFCLK192MCTRL */
1665 /* Description: HFCLK192M frequency configuration */
1666 
1667 /* Bits 1..0 : High frequency clock HCLK192M */
1668 #define CLOCK_HFCLK192MCTRL_HCLK192M_Pos (0UL) /*!< Position of HCLK192M field. */
1669 #define CLOCK_HFCLK192MCTRL_HCLK192M_Msk (0x3UL << CLOCK_HFCLK192MCTRL_HCLK192M_Pos) /*!< Bit mask of HCLK192M field. */
1670 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div1 (0UL) /*!< Divide HFCLK192M by 1 */
1671 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div2 (1UL) /*!< Divide HFCLK192M by 2 */
1672 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div4 (2UL) /*!< Divide HFCLK192M by 4 */
1673 
1674 /* =========================================================================================================================== */
1675 /* ================                                          ECB_NS                                           ================ */
1676 /* =========================================================================================================================== */
1677 
1678 
1679 /**
1680   * @brief AES ECB Mode Encryption (ECB_NS)
1681   */
1682 
1683 typedef struct {                                /*!< (@ 0x4100D000) ECB_NS Structure                                           */
1684   __OM  uint32_t  TASKS_STARTECB;               /*!< (@ 0x00000000) Start ECB block encrypt                                    */
1685   __OM  uint32_t  TASKS_STOPECB;                /*!< (@ 0x00000004) Abort a possible executing ECB operation                   */
1686   __IM  uint32_t  RESERVED[30];
1687   __IOM uint32_t  SUBSCRIBE_STARTECB;           /*!< (@ 0x00000080) Subscribe configuration for task STARTECB                  */
1688   __IOM uint32_t  SUBSCRIBE_STOPECB;            /*!< (@ 0x00000084) Subscribe configuration for task STOPECB                   */
1689   __IM  uint32_t  RESERVED1[30];
1690   __IOM uint32_t  EVENTS_ENDECB;                /*!< (@ 0x00000100) ECB block encrypt complete                                 */
1691   __IOM uint32_t  EVENTS_ERRORECB;              /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB
1692                                                                     task or due to an error                                    */
1693   __IM  uint32_t  RESERVED2[30];
1694   __IOM uint32_t  PUBLISH_ENDECB;               /*!< (@ 0x00000180) Publish configuration for event ENDECB                     */
1695   __IOM uint32_t  PUBLISH_ERRORECB;             /*!< (@ 0x00000184) Publish configuration for event ERRORECB                   */
1696   __IM  uint32_t  RESERVED3[95];
1697   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1698   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1699   __IM  uint32_t  RESERVED4[126];
1700   __IOM uint32_t  ECBDATAPTR;                   /*!< (@ 0x00000504) ECB block encrypt memory pointers                          */
1701 } NRF_ECB_Type;                                 /*!< Size = 1288 (0x508)                                                       */
1702 
1703 
1704 /* Peripheral: ECB */
1705 /* Description: AES ECB Mode Encryption */
1706 
1707 /* Register: ECB_TASKS_STARTECB */
1708 /* Description: Start ECB block encrypt */
1709 
1710 /* Bit 0 : Start ECB block encrypt */
1711 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */
1712 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */
1713 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */
1714 
1715 /* Register: ECB_TASKS_STOPECB */
1716 /* Description: Abort a possible executing ECB operation */
1717 
1718 /* Bit 0 : Abort a possible executing ECB operation */
1719 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */
1720 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */
1721 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */
1722 
1723 /* Register: ECB_SUBSCRIBE_STARTECB */
1724 /* Description: Subscribe configuration for task STARTECB */
1725 
1726 /* Bit 31 :   */
1727 #define ECB_SUBSCRIBE_STARTECB_EN_Pos (31UL) /*!< Position of EN field. */
1728 #define ECB_SUBSCRIBE_STARTECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STARTECB_EN_Pos) /*!< Bit mask of EN field. */
1729 #define ECB_SUBSCRIBE_STARTECB_EN_Disabled (0UL) /*!< Disable subscription */
1730 #define ECB_SUBSCRIBE_STARTECB_EN_Enabled (1UL) /*!< Enable subscription */
1731 
1732 /* Bits 7..0 : DPPI channel that task STARTECB will subscribe to */
1733 #define ECB_SUBSCRIBE_STARTECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1734 #define ECB_SUBSCRIBE_STARTECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STARTECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1735 
1736 /* Register: ECB_SUBSCRIBE_STOPECB */
1737 /* Description: Subscribe configuration for task STOPECB */
1738 
1739 /* Bit 31 :   */
1740 #define ECB_SUBSCRIBE_STOPECB_EN_Pos (31UL) /*!< Position of EN field. */
1741 #define ECB_SUBSCRIBE_STOPECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STOPECB_EN_Pos) /*!< Bit mask of EN field. */
1742 #define ECB_SUBSCRIBE_STOPECB_EN_Disabled (0UL) /*!< Disable subscription */
1743 #define ECB_SUBSCRIBE_STOPECB_EN_Enabled (1UL) /*!< Enable subscription */
1744 
1745 /* Bits 7..0 : DPPI channel that task STOPECB will subscribe to */
1746 #define ECB_SUBSCRIBE_STOPECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1747 #define ECB_SUBSCRIBE_STOPECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STOPECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1748 
1749 /* Register: ECB_EVENTS_ENDECB */
1750 /* Description: ECB block encrypt complete */
1751 
1752 /* Bit 0 : ECB block encrypt complete */
1753 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */
1754 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */
1755 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */
1756 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */
1757 
1758 /* Register: ECB_EVENTS_ERRORECB */
1759 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */
1760 
1761 /* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */
1762 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */
1763 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */
1764 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */
1765 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */
1766 
1767 /* Register: ECB_PUBLISH_ENDECB */
1768 /* Description: Publish configuration for event ENDECB */
1769 
1770 /* Bit 31 :   */
1771 #define ECB_PUBLISH_ENDECB_EN_Pos (31UL) /*!< Position of EN field. */
1772 #define ECB_PUBLISH_ENDECB_EN_Msk (0x1UL << ECB_PUBLISH_ENDECB_EN_Pos) /*!< Bit mask of EN field. */
1773 #define ECB_PUBLISH_ENDECB_EN_Disabled (0UL) /*!< Disable publishing */
1774 #define ECB_PUBLISH_ENDECB_EN_Enabled (1UL) /*!< Enable publishing */
1775 
1776 /* Bits 7..0 : DPPI channel that event ENDECB will publish to. */
1777 #define ECB_PUBLISH_ENDECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1778 #define ECB_PUBLISH_ENDECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ENDECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1779 
1780 /* Register: ECB_PUBLISH_ERRORECB */
1781 /* Description: Publish configuration for event ERRORECB */
1782 
1783 /* Bit 31 :   */
1784 #define ECB_PUBLISH_ERRORECB_EN_Pos (31UL) /*!< Position of EN field. */
1785 #define ECB_PUBLISH_ERRORECB_EN_Msk (0x1UL << ECB_PUBLISH_ERRORECB_EN_Pos) /*!< Bit mask of EN field. */
1786 #define ECB_PUBLISH_ERRORECB_EN_Disabled (0UL) /*!< Disable publishing */
1787 #define ECB_PUBLISH_ERRORECB_EN_Enabled (1UL) /*!< Enable publishing */
1788 
1789 /* Bits 7..0 : DPPI channel that event ERRORECB will publish to. */
1790 #define ECB_PUBLISH_ERRORECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1791 #define ECB_PUBLISH_ERRORECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ERRORECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1792 
1793 /* Register: ECB_INTENSET */
1794 /* Description: Enable interrupt */
1795 
1796 /* Bit 1 : Write '1' to enable interrupt for event ERRORECB */
1797 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1798 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1799 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1800 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1801 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1802 
1803 /* Bit 0 : Write '1' to enable interrupt for event ENDECB */
1804 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1805 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1806 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1807 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1808 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1809 
1810 /* Register: ECB_INTENCLR */
1811 /* Description: Disable interrupt */
1812 
1813 /* Bit 1 : Write '1' to disable interrupt for event ERRORECB */
1814 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1815 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1816 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1817 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1818 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1819 
1820 /* Bit 0 : Write '1' to disable interrupt for event ENDECB */
1821 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1822 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1823 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1824 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1825 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1826 
1827 /* Register: ECB_ECBDATAPTR */
1828 /* Description: ECB block encrypt memory pointers */
1829 
1830 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
1831 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
1832 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
1833 
1834 
1835 /* =========================================================================================================================== */
1836 /* ================                                          EGU                                              ================ */
1837 /* =========================================================================================================================== */
1838 
1839 
1840 /**
1841   * @brief Event generator unit 0 (EGU0_NS)
1842   */
1843 
1844 typedef struct {                                /*!< (@ 0x4001B000) EGU0_NS Structure                                          */
1845   __OM  uint32_t  TASKS_TRIGGER[16];            /*!< (@ 0x00000000) Description collection: Trigger n for triggering
1846                                                                     the corresponding TRIGGERED[n] event                       */
1847   __IM  uint32_t  RESERVED[16];
1848   __IOM uint32_t  SUBSCRIBE_TRIGGER[16];        /*!< (@ 0x00000080) Description collection: Subscribe configuration
1849                                                                     for task TRIGGER[n]                                        */
1850   __IM  uint32_t  RESERVED1[16];
1851   __IOM uint32_t  EVENTS_TRIGGERED[16];         /*!< (@ 0x00000100) Description collection: Event number n generated
1852                                                                     by triggering the corresponding TRIGGER[n]
1853                                                                     task                                                       */
1854   __IM  uint32_t  RESERVED2[16];
1855   __IOM uint32_t  PUBLISH_TRIGGERED[16];        /*!< (@ 0x00000180) Description collection: Publish configuration
1856                                                                     for event TRIGGERED[n]                                     */
1857   __IM  uint32_t  RESERVED3[80];
1858   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
1859   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
1860   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
1861 } NRF_EGU_Type;                                 /*!< Size = 780 (0x30c)                                                        */
1862 
1863 /* Peripheral: EGU */
1864 /* Description: Event generator unit */
1865 
1866 /* Register: EGU_TASKS_TRIGGER */
1867 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */
1868 
1869 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */
1870 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */
1871 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */
1872 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */
1873 
1874 /* Register: EGU_SUBSCRIBE_TRIGGER */
1875 /* Description: Description collection: Subscribe configuration for task TRIGGER[n] */
1876 
1877 /* Bit 31 :   */
1878 #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */
1879 #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */
1880 #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */
1881 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */
1882 
1883 /* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */
1884 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1885 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1886 
1887 /* Register: EGU_EVENTS_TRIGGERED */
1888 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */
1889 
1890 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */
1891 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */
1892 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */
1893 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */
1894 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */
1895 
1896 /* Register: EGU_PUBLISH_TRIGGERED */
1897 /* Description: Description collection: Publish configuration for event TRIGGERED[n] */
1898 
1899 /* Bit 31 :   */
1900 #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */
1901 #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */
1902 #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */
1903 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */
1904 
1905 /* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to. */
1906 #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
1907 #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
1908 
1909 /* Register: EGU_INTEN */
1910 /* Description: Enable or disable interrupt */
1911 
1912 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */
1913 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1914 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1915 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1916 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1917 
1918 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */
1919 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1920 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1921 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1922 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1923 
1924 /* Register: EGU_INTENSET */
1925 /* Description: Enable interrupt */
1926 
1927 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */
1928 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1929 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1930 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1931 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1932 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1933 
1934 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */
1935 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1936 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1937 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1938 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1939 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1940 
1941 /* Register: EGU_INTENCLR */
1942 /* Description: Disable interrupt */
1943 
1944 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */
1945 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1946 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1947 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1948 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1949 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1950 
1951 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */
1952 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1953 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1954 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1955 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1956 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1957 
1958 
1959 
1960 
1961 /* =========================================================================================================================== */
1962 /* ================                                         DPPIC_NS                                          ================ */
1963 /* =========================================================================================================================== */
1964 
1965 
1966 /**
1967   * @brief Distributed programmable peripheral interconnect controller (DPPIC_NS)
1968   */
1969 
1970 typedef struct {                                /*!< (@ 0x4100F000) DPPIC_NS Structure                                         */
1971   __OM  NRF_DPPIC_TASKS_CHG_Type TASKS_CHG[6];      /*!< (@ 0x00000000) Channel group tasks                                        */
1972   __IM  uint32_t  RESERVED[20];
1973   __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks                        */
1974   __IM  uint32_t  RESERVED1[276];
1975   __IOM uint32_t  CHEN;                         /*!< (@ 0x00000500) Channel enable register                                    */
1976   __IOM uint32_t  CHENSET;                      /*!< (@ 0x00000504) Channel enable set register                                */
1977   __IOM uint32_t  CHENCLR;                      /*!< (@ 0x00000508) Channel enable clear register                              */
1978   __IM  uint32_t  RESERVED2[189];
1979   __IOM uint32_t  CHG[6];                       /*!< (@ 0x00000800) Description collection: Channel group n Note:
1980                                                                     Writes to this register are ignored if either
1981                                                                     SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS
1982                                                                     is enabled                                                 */
1983 } NRF_DPPIC_Type;                               /*!< Size = 2072 (0x818)                                                       */
1984 
1985 
1986 
1987 /* Peripheral: DPPIC */
1988 /* Description: Distributed programmable peripheral interconnect controller */
1989 
1990 /* Register: DPPIC_TASKS_CHG_EN */
1991 /* Description: Description cluster: Enable channel group n */
1992 
1993 /* Bit 0 : Enable channel group n */
1994 #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */
1995 #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
1996 #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */
1997 
1998 /* Register: DPPIC_TASKS_CHG_DIS */
1999 /* Description: Description cluster: Disable channel group n */
2000 
2001 /* Bit 0 : Disable channel group n */
2002 #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */
2003 #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */
2004 #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */
2005 
2006 /* Register: DPPIC_SUBSCRIBE_CHG_EN */
2007 /* Description: Description cluster: Subscribe configuration for task CHG[n].EN */
2008 
2009 /* Bit 31 :   */
2010 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */
2011 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */
2012 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */
2013 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */
2014 
2015 /* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */
2016 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2017 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2018 
2019 /* Register: DPPIC_SUBSCRIBE_CHG_DIS */
2020 /* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */
2021 
2022 /* Bit 31 :   */
2023 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */
2024 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */
2025 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */
2026 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */
2027 
2028 /* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */
2029 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2030 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2031 
2032 /* Register: DPPIC_CHEN */
2033 /* Description: Channel enable register */
2034 
2035 /* Bit 31 : Enable or disable channel 31 */
2036 #define DPPIC_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
2037 #define DPPIC_CHEN_CH31_Msk (0x1UL << DPPIC_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
2038 #define DPPIC_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
2039 #define DPPIC_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
2040 
2041 /* Bit 0 : Enable or disable channel 0 */
2042 #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
2043 #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
2044 #define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
2045 #define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
2046 
2047 /* Register: DPPIC_CHENSET */
2048 /* Description: Channel enable set register */
2049 
2050 /* Bit 31 : Channel 31 enable set register. Writing 0 has no effect. */
2051 #define DPPIC_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
2052 #define DPPIC_CHENSET_CH31_Msk (0x1UL << DPPIC_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
2053 #define DPPIC_CHENSET_CH31_Disabled (0UL) /*!< Read: Channel disabled */
2054 #define DPPIC_CHENSET_CH31_Enabled (1UL) /*!< Read: Channel enabled */
2055 #define DPPIC_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
2056 
2057 /* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */
2058 #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
2059 #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
2060 #define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */
2061 #define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */
2062 #define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
2063 
2064 /* Register: DPPIC_CHENCLR */
2065 /* Description: Channel enable clear register */
2066 
2067 /* Bit 31 : Channel 31 enable clear register.  Writing 0 has no effect. */
2068 #define DPPIC_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
2069 #define DPPIC_CHENCLR_CH31_Msk (0x1UL << DPPIC_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
2070 #define DPPIC_CHENCLR_CH31_Disabled (0UL) /*!< Read: Channel disabled */
2071 #define DPPIC_CHENCLR_CH31_Enabled (1UL) /*!< Read: Channel enabled */
2072 #define DPPIC_CHENCLR_CH31_Clear (1UL) /*!< Write: Disable channel */
2073 
2074 /* Bit 0 : Channel 0 enable clear register.  Writing 0 has no effect. */
2075 #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
2076 #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
2077 #define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */
2078 #define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */
2079 #define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */
2080 
2081 /* Register: DPPIC_CHG */
2082 /* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */
2083 
2084 /* Bit 31 : Include or exclude channel 31 */
2085 #define DPPIC_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
2086 #define DPPIC_CHG_CH31_Msk (0x1UL << DPPIC_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
2087 #define DPPIC_CHG_CH31_Excluded (0UL) /*!< Exclude */
2088 #define DPPIC_CHG_CH31_Included (1UL) /*!< Include */
2089 
2090 /* Bit 0 : Include or exclude channel 0 */
2091 #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
2092 #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
2093 #define DPPIC_CHG_CH0_Excluded (0UL) /*!< Exclude */
2094 #define DPPIC_CHG_CH0_Included (1UL) /*!< Include */
2095 
2096 /* =========================================================================================================================== */
2097 /* ================                                          FICR                                             ================ */
2098 /* =========================================================================================================================== */
2099 
2100 
2101 /**
2102   * @brief Factory Information Configuration Registers (FICR)
2103   */
2104 
2105 typedef struct {                                /*!< (@ 0x00FF0000) FICR_S Structure                                           */
2106   __IM  uint32_t  RESERVED[128];
2107   __IOM FICR_INFO_Type INFO;                    /*!< (@ 0x00000200) Device info                                                */
2108   __IM  uint32_t  RESERVED1[53];
2109   __IOM FICR_TRIMCNF_Type TRIMCNF[32];          /*!< (@ 0x00000300) Unspecified                                                */
2110   __IM  uint32_t  RESERVED2[20];
2111   __IOM FICR_NFC_Type NFC;                      /*!< (@ 0x00000450) Unspecified                                                */
2112   __IM  uint32_t  RESERVED3[488];
2113   __IOM FICR_TRNG90B_Type TRNG90B;              /*!< (@ 0x00000C00) NIST800-90B RNG calibration data                           */
2114   __IM  uint32_t  XOSC32MTRIM;                  /*!< (@ 0x00000C20) XOSC32M capacitor selection trim values                    */
2115 } NRF_FICR_APP_Type;                            /*!< Size = 3108 (0xc24)                                                       */
2116 
2117 typedef struct {                                /*!< (@ 0x01FF0000) FICR_NS Structure                                          */
2118   __IM  uint32_t  RESERVED[128];
2119   __IOM FICR_INFO_Type INFO;                    /*!< (@ 0x00000200) Device info                                                */
2120   __IM  uint32_t  RESERVED1[21];
2121   __IM  uint32_t  ER[4];                        /*!< (@ 0x00000280) Description collection: Encryption Root, word
2122                                                                     n                                                          */
2123   __IM  uint32_t  IR[4];                        /*!< (@ 0x00000290) Description collection: Identity Root, word n              */
2124   __IM  uint32_t  DEVICEADDRTYPE;               /*!< (@ 0x000002A0) Device address type                                        */
2125   __IM  uint32_t  DEVICEADDR[2];                /*!< (@ 0x000002A4) Description collection: Device address n                   */
2126   __IM  uint32_t  RESERVED2[21];
2127   __IOM FICR_TRIMCNF_Type TRIMCNF[32];          /*!< (@ 0x00000300) Unspecified                                                */
2128 } NRF_FICR_NET_Type;                            /*!< Size = 1024 (0x400)                                                       */
2129 
2130 
2131 /* =========================================================================================================================== */
2132 /* ================                                           P0_NS                                           ================ */
2133 /* =========================================================================================================================== */
2134 
2135 
2136 /**
2137   * @brief GPIO Port 0 (P0_NS)
2138   */
2139 
2140 typedef struct {                                /*!< (@ 0x418C0500) P0_NS Structure                                            */
2141   __IM  uint32_t  RESERVED;
2142   __IOM uint32_t  OUT;                          /*!< (@ 0x00000004) Write GPIO port                                            */
2143   __IOM uint32_t  OUTSET;                       /*!< (@ 0x00000008) Set individual bits in GPIO port                           */
2144   __IOM uint32_t  OUTCLR;                       /*!< (@ 0x0000000C) Clear individual bits in GPIO port                         */
2145   __IM  uint32_t  IN;                           /*!< (@ 0x00000010) Read GPIO port                                             */
2146   __IOM uint32_t  DIR;                          /*!< (@ 0x00000014) Direction of GPIO pins                                     */
2147   __IOM uint32_t  DIRSET;                       /*!< (@ 0x00000018) DIR set register                                           */
2148   __IOM uint32_t  DIRCLR;                       /*!< (@ 0x0000001C) DIR clear register                                         */
2149   __IOM uint32_t  LATCH;                        /*!< (@ 0x00000020) Latch register indicating what GPIO pins that
2150                                                                     have met the criteria set in the PIN_CNF[n].SENSE
2151                                                                     registers                                                  */
2152   __IOM uint32_t  DETECTMODE;                   /*!< (@ 0x00000024) Select between default DETECT signal behavior
2153                                                                     and LDETECT mode (For non-secure pin only)                 */
2154   __IOM uint32_t  DETECTMODE_SEC;               /*!< (@ 0x00000028) Select between default DETECT signal behavior
2155                                                                     and LDETECT mode (For secure pin only)                     */
2156   __IM  uint32_t  RESERVED1[117];
2157   __IOM uint32_t  PIN_CNF[32];                  /*!< (@ 0x00000200) Description collection: Configuration of GPIO
2158                                                                     pins                                                       */
2159 } NRF_GPIO_Type;                                /*!< Size = 640 (0x280)                                                        */
2160 
2161 
2162 /* =========================================================================================================================== */
2163 /* ================                                         GPIOTE_NS                                         ================ */
2164 /* =========================================================================================================================== */
2165 
2166 
2167 /**
2168   * @brief GPIO Tasks and Events (GPIOTE_NS)
2169   */
2170 
2171 typedef struct {                                /*!< (@ 0x4100A000) GPIOTE_NS Structure                                        */
2172   __OM  uint32_t  TASKS_OUT[8];                 /*!< (@ 0x00000000) Description collection: Task for writing to pin
2173                                                                     specified in CONFIG[n].PSEL. Action on pin
2174                                                                     is configured in CONFIG[n].POLARITY.                       */
2175   __IM  uint32_t  RESERVED[4];
2176   __OM  uint32_t  TASKS_SET[8];                 /*!< (@ 0x00000030) Description collection: Task for writing to pin
2177                                                                     specified in CONFIG[n].PSEL. Action on pin
2178                                                                     is to set it high.                                         */
2179   __IM  uint32_t  RESERVED1[4];
2180   __OM  uint32_t  TASKS_CLR[8];                 /*!< (@ 0x00000060) Description collection: Task for writing to pin
2181                                                                     specified in CONFIG[n].PSEL. Action on pin
2182                                                                     is to set it low.                                          */
2183   __IOM uint32_t  SUBSCRIBE_OUT[8];             /*!< (@ 0x00000080) Description collection: Subscribe configuration
2184                                                                     for task OUT[n]                                            */
2185   __IM  uint32_t  RESERVED2[4];
2186   __IOM uint32_t  SUBSCRIBE_SET[8];             /*!< (@ 0x000000B0) Description collection: Subscribe configuration
2187                                                                     for task SET[n]                                            */
2188   __IM  uint32_t  RESERVED3[4];
2189   __IOM uint32_t  SUBSCRIBE_CLR[8];             /*!< (@ 0x000000E0) Description collection: Subscribe configuration
2190                                                                     for task CLR[n]                                            */
2191   __IOM uint32_t  EVENTS_IN[8];                 /*!< (@ 0x00000100) Description collection: Event generated from
2192                                                                     pin specified in CONFIG[n].PSEL                            */
2193   __IM  uint32_t  RESERVED4[23];
2194   __IOM uint32_t  EVENTS_PORT;                  /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins
2195                                                                     with SENSE mechanism enabled                               */
2196   __IOM uint32_t  PUBLISH_IN[8];                /*!< (@ 0x00000180) Description collection: Publish configuration
2197                                                                     for event IN[n]                                            */
2198   __IM  uint32_t  RESERVED5[23];
2199   __IOM uint32_t  PUBLISH_PORT;                 /*!< (@ 0x000001FC) Publish configuration for event PORT                       */
2200   __IM  uint32_t  RESERVED6[65];
2201   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
2202   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
2203   __IM  uint32_t  RESERVED7[126];
2204   __IOM uint32_t  LATENCY;                      /*!< (@ 0x00000504) Latency selection for Event mode (MODE=Event)
2205                                                                     with rising or falling edge detection on
2206                                                                     the pin.                                                   */
2207   __IM  uint32_t  RESERVED8[2];
2208   __IOM uint32_t  CONFIG[8];                    /*!< (@ 0x00000510) Description collection: Configuration for OUT[n],
2209                                                                     SET[n], and CLR[n] tasks and IN[n] event                   */
2210 } NRF_GPIOTE_Type;                              /*!< Size = 1328 (0x530)                                                       */
2211 
2212 
2213 /* Bit 31 : Write '1' to disable interrupt for event PORT */
2214 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
2215 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
2216 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
2217 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
2218 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
2219 
2220 /* Register: GPIOTE_CONFIG */
2221 /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */
2222 
2223 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
2224 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
2225 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
2226 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
2227 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
2228 
2229 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
2230 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
2231 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
2232 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
2233 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
2234 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
2235 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
2236 
2237 /* Bit 13 : Port number */
2238 #define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */
2239 #define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */
2240 
2241 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */
2242 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
2243 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
2244 
2245 /* Bits 1..0 : Mode */
2246 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
2247 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
2248 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
2249 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
2250 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
2251 
2252 /* Register: GPIO_PIN_CNF */
2253 /* Description: Description collection: Configuration of GPIO pins */
2254 
2255 /* Bits 30..28 : Select which MCU/Subsystem controls this pin Note: this field is only accessible from secure code. */
2256 #define GPIO_PIN_CNF_MCUSEL_Pos (28UL) /*!< Position of MCUSEL field. */
2257 #define GPIO_PIN_CNF_MCUSEL_Msk (0x7UL << GPIO_PIN_CNF_MCUSEL_Pos) /*!< Bit mask of MCUSEL field. */
2258 #define GPIO_PIN_CNF_MCUSEL_AppMCU (0x0UL) /*!< Application MCU */
2259 #define GPIO_PIN_CNF_MCUSEL_NetworkMCU (0x1UL) /*!< Network MCU */
2260 #define GPIO_PIN_CNF_MCUSEL_Peripheral (0x3UL) /*!< Peripheral with dedicated pins */
2261 #define GPIO_PIN_CNF_MCUSEL_TND (0x7UL) /*!< Trace and Debug Subsystem */
2262 
2263 /* Bits 17..16 : Pin sensing mechanism */
2264 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
2265 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
2266 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
2267 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
2268 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
2269 
2270 /* Bits 11..8 : Drive configuration */
2271 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
2272 #define GPIO_PIN_CNF_DRIVE_Msk (0xFUL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
2273 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
2274 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
2275 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
2276 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
2277 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */
2278 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
2279 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */
2280 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
2281 #define GPIO_PIN_CNF_DRIVE_E0E1 (11UL) /*!< Extra high drive '0', extra high drive '1' */
2282 
2283 /* Bits 3..2 : Pull configuration */
2284 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
2285 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
2286 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
2287 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
2288 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
2289 
2290 /* Bit 1 : Connect or disconnect input buffer */
2291 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
2292 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
2293 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
2294 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
2295 
2296 /* Bit 0 : Pin direction. Same physical register as DIR register */
2297 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
2298 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
2299 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
2300 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
2301 
2302 
2303 /* =========================================================================================================================== */
2304 /* ================                                          IPC_NS                                           ================ */
2305 /* =========================================================================================================================== */
2306 
2307 
2308 /**
2309   * @brief Interprocessor communication (IPC_NS)
2310   */
2311 
2312 typedef struct {                                /*!< (@ 0x41012000) IPC_NS Structure                                           */
2313   __OM  uint32_t  TASKS_SEND[16];               /*!< (@ 0x00000000) Description collection: Trigger events on IPC
2314                                                                     channel enabled in SEND_CNF[n]                             */
2315   __IM  uint32_t  RESERVED[16];
2316   __IOM uint32_t  SUBSCRIBE_SEND[16];           /*!< (@ 0x00000080) Description collection: Subscribe configuration
2317                                                                     for task SEND[n]                                           */
2318   __IM  uint32_t  RESERVED1[16];
2319   __IOM uint32_t  EVENTS_RECEIVE[16];           /*!< (@ 0x00000100) Description collection: Event received on one
2320                                                                     or more of the enabled IPC channels in RECEIVE_CNF[n]      */
2321   __IM  uint32_t  RESERVED2[16];
2322   __IOM uint32_t  PUBLISH_RECEIVE[16];          /*!< (@ 0x00000180) Description collection: Publish configuration
2323                                                                     for event RECEIVE[n]                                       */
2324   __IM  uint32_t  RESERVED3[80];
2325   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
2326   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
2327   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
2328   __IM  uint32_t  INTPEND;                      /*!< (@ 0x0000030C) Pending interrupts                                         */
2329   __IM  uint32_t  RESERVED4[128];
2330   __IOM uint32_t  SEND_CNF[16];                 /*!< (@ 0x00000510) Description collection: Send event configuration
2331                                                                     for TASKS_SEND[n]                                          */
2332   __IM  uint32_t  RESERVED5[16];
2333   __IOM uint32_t  RECEIVE_CNF[16];              /*!< (@ 0x00000590) Description collection: Receive event configuration
2334                                                                     for EVENTS_RECEIVE[n]                                      */
2335   __IM  uint32_t  RESERVED6[16];
2336   __IOM uint32_t  GPMEM[2];                     /*!< (@ 0x00000610) Description collection: General purpose memory             */
2337 } NRF_IPC_Type;                                 /*!< Size = 1560 (0x618)                                                       */
2338 
2339 
2340 /* =========================================================================================================================== */
2341 /* ================                                          NFCT_NS                                          ================ */
2342 /* =========================================================================================================================== */
2343 
2344 
2345 /**
2346   * @brief NFC-A compatible radio 0 (NFCT_NS)
2347   */
2348 
2349 typedef struct {                                /*!< (@ 0x4002D000) NFCT_NS Structure                                          */
2350   __OM  uint32_t  TASKS_ACTIVATE;               /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing
2351                                                                     frames, change state to activated                          */
2352   __OM  uint32_t  TASKS_DISABLE;                /*!< (@ 0x00000004) Disable NFCT peripheral                                    */
2353   __OM  uint32_t  TASKS_SENSE;                  /*!< (@ 0x00000008) Enable NFC sense field mode, change state to
2354                                                                     sense mode                                                 */
2355   __OM  uint32_t  TASKS_STARTTX;                /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change
2356                                                                     state to transmit                                          */
2357   __IM  uint32_t  RESERVED[3];
2358   __OM  uint32_t  TASKS_ENABLERXDATA;           /*!< (@ 0x0000001C) Initializes the EasyDMA for receive.                       */
2359   __IM  uint32_t  RESERVED1;
2360   __OM  uint32_t  TASKS_GOIDLE;                 /*!< (@ 0x00000024) Force state machine to IDLE state                          */
2361   __OM  uint32_t  TASKS_GOSLEEP;                /*!< (@ 0x00000028) Force state machine to SLEEP_A state                       */
2362   __IM  uint32_t  RESERVED2[21];
2363   __IOM uint32_t  SUBSCRIBE_ACTIVATE;           /*!< (@ 0x00000080) Subscribe configuration for task ACTIVATE                  */
2364   __IOM uint32_t  SUBSCRIBE_DISABLE;            /*!< (@ 0x00000084) Subscribe configuration for task DISABLE                   */
2365   __IOM uint32_t  SUBSCRIBE_SENSE;              /*!< (@ 0x00000088) Subscribe configuration for task SENSE                     */
2366   __IOM uint32_t  SUBSCRIBE_STARTTX;            /*!< (@ 0x0000008C) Subscribe configuration for task STARTTX                   */
2367   __IM  uint32_t  RESERVED3[3];
2368   __IOM uint32_t  SUBSCRIBE_ENABLERXDATA;       /*!< (@ 0x0000009C) Subscribe configuration for task ENABLERXDATA              */
2369   __IM  uint32_t  RESERVED4;
2370   __IOM uint32_t  SUBSCRIBE_GOIDLE;             /*!< (@ 0x000000A4) Subscribe configuration for task GOIDLE                    */
2371   __IOM uint32_t  SUBSCRIBE_GOSLEEP;            /*!< (@ 0x000000A8) Subscribe configuration for task GOSLEEP                   */
2372   __IM  uint32_t  RESERVED5[21];
2373   __IOM uint32_t  EVENTS_READY;                 /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send
2374                                                                     frames                                                     */
2375   __IOM uint32_t  EVENTS_FIELDDETECTED;         /*!< (@ 0x00000104) Remote NFC field detected                                  */
2376   __IOM uint32_t  EVENTS_FIELDLOST;             /*!< (@ 0x00000108) Remote NFC field lost                                      */
2377   __IOM uint32_t  EVENTS_TXFRAMESTART;          /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted
2378                                                                     frame                                                      */
2379   __IOM uint32_t  EVENTS_TXFRAMEEND;            /*!< (@ 0x00000110) Marks the end of the last transmitted on-air
2380                                                                     symbol of a frame                                          */
2381   __IOM uint32_t  EVENTS_RXFRAMESTART;          /*!< (@ 0x00000114) Marks the end of the first symbol of a received
2382                                                                     frame                                                      */
2383   __IOM uint32_t  EVENTS_RXFRAMEEND;            /*!< (@ 0x00000118) Received data has been checked (CRC, parity)
2384                                                                     and transferred to RAM, and EasyDMA has
2385                                                                     ended accessing the RX buffer                              */
2386   __IOM uint32_t  EVENTS_ERROR;                 /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register
2387                                                                     contains details on the source of the error.               */
2388   __IM  uint32_t  RESERVED6[2];
2389   __IOM uint32_t  EVENTS_RXERROR;               /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX
2390                                                                     register contains details on the source
2391                                                                     of the error.                                              */
2392   __IOM uint32_t  EVENTS_ENDRX;                 /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN)
2393                                                                     in Data RAM full.                                          */
2394   __IOM uint32_t  EVENTS_ENDTX;                 /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA
2395                                                                     has ended accessing the TX buffer                          */
2396   __IM  uint32_t  RESERVED7;
2397   __IOM uint32_t  EVENTS_AUTOCOLRESSTARTED;     /*!< (@ 0x00000138) Auto collision resolution process has started              */
2398   __IM  uint32_t  RESERVED8[3];
2399   __IOM uint32_t  EVENTS_COLLISION;             /*!< (@ 0x00000148) NFC auto collision resolution error reported.              */
2400   __IOM uint32_t  EVENTS_SELECTED;              /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed       */
2401   __IOM uint32_t  EVENTS_STARTED;               /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames.                */
2402   __IM  uint32_t  RESERVED9[11];
2403   __IOM uint32_t  PUBLISH_READY;                /*!< (@ 0x00000180) Publish configuration for event READY                      */
2404   __IOM uint32_t  PUBLISH_FIELDDETECTED;        /*!< (@ 0x00000184) Publish configuration for event FIELDDETECTED              */
2405   __IOM uint32_t  PUBLISH_FIELDLOST;            /*!< (@ 0x00000188) Publish configuration for event FIELDLOST                  */
2406   __IOM uint32_t  PUBLISH_TXFRAMESTART;         /*!< (@ 0x0000018C) Publish configuration for event TXFRAMESTART               */
2407   __IOM uint32_t  PUBLISH_TXFRAMEEND;           /*!< (@ 0x00000190) Publish configuration for event TXFRAMEEND                 */
2408   __IOM uint32_t  PUBLISH_RXFRAMESTART;         /*!< (@ 0x00000194) Publish configuration for event RXFRAMESTART               */
2409   __IOM uint32_t  PUBLISH_RXFRAMEEND;           /*!< (@ 0x00000198) Publish configuration for event RXFRAMEEND                 */
2410   __IOM uint32_t  PUBLISH_ERROR;                /*!< (@ 0x0000019C) Publish configuration for event ERROR                      */
2411   __IM  uint32_t  RESERVED10[2];
2412   __IOM uint32_t  PUBLISH_RXERROR;              /*!< (@ 0x000001A8) Publish configuration for event RXERROR                    */
2413   __IOM uint32_t  PUBLISH_ENDRX;                /*!< (@ 0x000001AC) Publish configuration for event ENDRX                      */
2414   __IOM uint32_t  PUBLISH_ENDTX;                /*!< (@ 0x000001B0) Publish configuration for event ENDTX                      */
2415   __IM  uint32_t  RESERVED11;
2416   __IOM uint32_t  PUBLISH_AUTOCOLRESSTARTED;    /*!< (@ 0x000001B8) Publish configuration for event AUTOCOLRESSTARTED          */
2417   __IM  uint32_t  RESERVED12[3];
2418   __IOM uint32_t  PUBLISH_COLLISION;            /*!< (@ 0x000001C8) Publish configuration for event COLLISION                  */
2419   __IOM uint32_t  PUBLISH_SELECTED;             /*!< (@ 0x000001CC) Publish configuration for event SELECTED                   */
2420   __IOM uint32_t  PUBLISH_STARTED;              /*!< (@ 0x000001D0) Publish configuration for event STARTED                    */
2421   __IM  uint32_t  RESERVED13[11];
2422   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
2423   __IM  uint32_t  RESERVED14[63];
2424   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
2425   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
2426   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
2427   __IM  uint32_t  RESERVED15[62];
2428   __IOM uint32_t  ERRORSTATUS;                  /*!< (@ 0x00000404) NFC Error Status register                                  */
2429   __IM  uint32_t  RESERVED16;
2430   __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS;      /*!< (@ 0x0000040C) Unspecified                                                */
2431   __IM  uint32_t  NFCTAGSTATE;                  /*!< (@ 0x00000410) Current operating state of NFC tag                         */
2432   __IM  uint32_t  RESERVED17[3];
2433   __IM  uint32_t  SLEEPSTATE;                   /*!< (@ 0x00000420) Sleep state during automatic collision resolution          */
2434   __IM  uint32_t  RESERVED18[6];
2435   __IM  uint32_t  FIELDPRESENT;                 /*!< (@ 0x0000043C) Indicates the presence or not of a valid field             */
2436   __IM  uint32_t  RESERVED19[49];
2437   __IOM uint32_t  FRAMEDELAYMIN;                /*!< (@ 0x00000504) Minimum frame delay                                        */
2438   __IOM uint32_t  FRAMEDELAYMAX;                /*!< (@ 0x00000508) Maximum frame delay                                        */
2439   __IOM uint32_t  FRAMEDELAYMODE;               /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer           */
2440   __IOM uint32_t  PACKETPTR;                    /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in
2441                                                                     Data RAM                                                   */
2442   __IOM uint32_t  MAXLEN;                       /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD
2443                                                                     data storage each                                          */
2444   __IOM NFCT_TXD_Type TXD;                      /*!< (@ 0x00000518) Unspecified                                                */
2445   __IOM NFCT_RXD_Type RXD;                      /*!< (@ 0x00000520) Unspecified                                                */
2446   __IM  uint32_t  RESERVED20;
2447   __IOM uint32_t  MODULATIONCTRL;               /*!< (@ 0x0000052C) Enables the modulation output to a GPIO pin which
2448                                                                     can be connected to a second external antenna.             */
2449   __IM  uint32_t  RESERVED21[2];
2450   __IOM uint32_t  MODULATIONPSEL;               /*!< (@ 0x00000538) Pin select for Modulation control                          */
2451   __IM  uint32_t  RESERVED22[21];
2452   __IOM uint32_t  NFCID1_LAST;                  /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID)                     */
2453   __IOM uint32_t  NFCID1_2ND_LAST;              /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID)                 */
2454   __IOM uint32_t  NFCID1_3RD_LAST;              /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID)                       */
2455   __IOM uint32_t  AUTOCOLRESCONFIG;             /*!< (@ 0x0000059C) Controls the auto collision resolution function.
2456                                                                     This setting must be done before the NFCT
2457                                                                     peripheral is activated.                                   */
2458   __IOM uint32_t  SENSRES;                      /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings                      */
2459   __IOM uint32_t  SELRES;                       /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings                       */
2460 } NRF_NFCT_Type;                                /*!< Size = 1448 (0x5a8)                                                       */
2461 
2462 
2463 /* =========================================================================================================================== */
2464 /* ================                                        APPMUTEX_NS                                        ================ */
2465 /* =========================================================================================================================== */
2466 
2467 
2468 /**
2469   * @brief MUTEX 0 (APPMUTEX_NS)
2470   */
2471 
2472 typedef struct {                                /*!< (@ 0x40030000) APPMUTEX_NS Structure                                      */
2473   __IM  uint32_t  RESERVED[256];
2474   __IOM uint32_t  MUTEX[16];                    /*!< (@ 0x00000400) Description collection: Mutex register                     */
2475 } NRF_MUTEX_Type;                               /*!< Size = 1088 (0x440)                                                       */
2476 
2477 
2478 
2479 /* =========================================================================================================================== */
2480 /* ================                                          NVMC                                             ================ */
2481 /* =========================================================================================================================== */
2482 
2483 
2484 /**
2485   * @brief Non-volatile memory controller (NVMC)
2486   *
2487   * Note: This is the app core register layouts
2488   * as by now the icache registers are just ignored
2489   */
2490 
2491 typedef struct {                                /*!< (@ 0x40039000) NVMC_NS Structure                                          */
2492   __IM  uint32_t  RESERVED[256];
2493   __IM  uint32_t  READY;                        /*!< (@ 0x00000400) Ready flag                                                 */
2494   __IM  uint32_t  RESERVED1;
2495   __IM  uint32_t  READYNEXT;                    /*!< (@ 0x00000408) Ready flag                                                 */
2496   __IM  uint32_t  RESERVED2[62];
2497   __IOM uint32_t  CONFIG;                       /*!< (@ 0x00000504) Configuration register                                     */
2498   __IM  uint32_t  RESERVED3;
2499   __OM  uint32_t  ERASEALL;                     /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory          */
2500   __IM  uint32_t  RESERVED4[3];
2501   __IOM uint32_t  ERASEPAGEPARTIALCFG;          /*!< (@ 0x0000051C) Register for partial erase configuration                   */
2502   __IM  uint32_t  RESERVED5[25];
2503   __IOM uint32_t  CONFIGNS;                     /*!< (@ 0x00000584) Non-secure configuration register                          */
2504   __OM  uint32_t  WRITEUICRNS;                  /*!< (@ 0x00000588) Non-secure APPROTECT enable register                       */
2505 } NRF_NVMC_Type;                                /*!< Size = 1420 (0x58c)                                                       */
2506 
2507 
2508 /* Peripheral: NVMC */
2509 /* Description: Non-volatile memory controller */
2510 
2511 /* Register: NVMC_READY */
2512 /* Description: Ready flag */
2513 
2514 /* Bit 0 : NVMC is ready or busy */
2515 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
2516 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
2517 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */
2518 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
2519 
2520 /* Register: NVMC_READYNEXT */
2521 /* Description: Ready flag */
2522 
2523 /* Bit 0 : NVMC can accept a new write operation */
2524 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
2525 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
2526 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
2527 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
2528 
2529 /* Register: NVMC_CONFIG */
2530 /* Description: Configuration register */
2531 
2532 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
2533 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
2534 #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
2535 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
2536 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
2537 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
2538 #define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */
2539 
2540 /* Register: NVMC_ERASEALL */
2541 /* Description: Register for erasing all non-volatile user memory */
2542 
2543 /* Bit 0 : Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. */
2544 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
2545 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
2546 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
2547 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
2548 
2549 /* Register: NVMC_ERASEPAGEPARTIALCFG */
2550 /* Description: Register for partial erase configuration */
2551 
2552 /* Bits 6..0 : Duration of the partial erase in milliseconds */
2553 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */
2554 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */
2555 
2556 
2557 /* =========================================================================================================================== */
2558 /* ================                                         POWER_NS                                          ================ */
2559 /* =========================================================================================================================== */
2560 
2561 
2562 /**
2563   * @brief Power control 0 (POWER_NS)
2564   */
2565 
2566 typedef struct {                                /*!< (@ 0x40005000) POWER_NS Structure                                         */
2567   __IM  uint32_t  RESERVED[30];
2568   __OM  uint32_t  TASKS_CONSTLAT;               /*!< (@ 0x00000078) Enable Constant Latency mode                               */
2569   __OM  uint32_t  TASKS_LOWPWR;                 /*!< (@ 0x0000007C) Enable Low-Power mode (variable latency)                   */
2570   __IM  uint32_t  RESERVED1[30];
2571   __IOM uint32_t  SUBSCRIBE_CONSTLAT;           /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT                  */
2572   __IOM uint32_t  SUBSCRIBE_LOWPWR;             /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR                    */
2573   __IM  uint32_t  RESERVED2[2];
2574   __IOM uint32_t  EVENTS_POFWARN;               /*!< (@ 0x00000108) Power failure warning                                      */
2575   __IM  uint32_t  RESERVED3[2];
2576   __IOM uint32_t  EVENTS_SLEEPENTER;            /*!< (@ 0x00000114) CPU entered WFI/WFE sleep                                  */
2577   __IOM uint32_t  EVENTS_SLEEPEXIT;             /*!< (@ 0x00000118) CPU exited WFI/WFE sleep                                   */
2578   __IM  uint32_t  RESERVED4[27];
2579   __IOM uint32_t  PUBLISH_POFWARN;              /*!< (@ 0x00000188) Publish configuration for event POFWARN                    */
2580   __IM  uint32_t  RESERVED5[2];
2581   __IOM uint32_t  PUBLISH_SLEEPENTER;           /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER                 */
2582   __IOM uint32_t  PUBLISH_SLEEPEXIT;            /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT                  */
2583   __IM  uint32_t  RESERVED6[89];
2584   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
2585   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
2586   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
2587   __IM  uint32_t  RESERVED7[132];
2588   __IOM uint32_t  GPREGRET[2];                  /*!< (@ 0x0000051C) Description collection: General purpose retention
2589                                                                     register                                                   */
2590 } NRF_POWER_Type;                               /*!< Size = 1316 (0x524)                                                       */
2591 
2592 
2593 /* =========================================================================================================================== */
2594 /* ================                                         RESET                                             ================ */
2595 /* =========================================================================================================================== */
2596 
2597 
2598 /**
2599   * @brief Reset control (RESET)
2600   */
2601 
2602 typedef struct {                                /*!< (@ 0x40005000) RESET_NS Structure                                         */
2603   __IM  uint32_t  RESERVED[256];
2604   __IOM uint32_t  RESETREAS;                    /*!< (@ 0x00000400) Reset reason                                               */
2605   __IM  uint32_t  RESERVED1[131];
2606   __IOM RESET_NETWORK_Type NETWORK;             /*!< (@ 0x00000610) ULP network core control                                   */
2607 } NRF_RESET_Type;                               /*!< Size = 1560 (0x618)                                                       */
2608 
2609 
2610 
2611 /* =========================================================================================================================== */
2612 /* ================                                         RADIO_NS                                          ================ */
2613 /* =========================================================================================================================== */
2614 
2615 
2616 /**
2617   * @brief 2.4 GHz radio (RADIO_NS)
2618   */
2619 
2620 typedef struct {                                /*!< (@ 0x41008000) RADIO_NS Structure                                         */
2621   __OM  uint32_t  TASKS_TXEN;                   /*!< (@ 0x00000000) Enable RADIO in TX mode                                    */
2622   __OM  uint32_t  TASKS_RXEN;                   /*!< (@ 0x00000004) Enable RADIO in RX mode                                    */
2623   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000008) Start RADIO                                                */
2624   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x0000000C) Stop RADIO                                                 */
2625   __OM  uint32_t  TASKS_DISABLE;                /*!< (@ 0x00000010) Disable RADIO                                              */
2626   __OM  uint32_t  TASKS_RSSISTART;              /*!< (@ 0x00000014) Start the RSSI and take one single sample of
2627                                                                     the receive signal strength                                */
2628   __OM  uint32_t  TASKS_RSSISTOP;               /*!< (@ 0x00000018) Stop the RSSI measurement                                  */
2629   __OM  uint32_t  TASKS_BCSTART;                /*!< (@ 0x0000001C) Start the bit counter                                      */
2630   __OM  uint32_t  TASKS_BCSTOP;                 /*!< (@ 0x00000020) Stop the bit counter                                       */
2631   __OM  uint32_t  TASKS_EDSTART;                /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE
2632                                                                     802.15.4 mode                                              */
2633   __OM  uint32_t  TASKS_EDSTOP;                 /*!< (@ 0x00000028) Stop the energy detect measurement                         */
2634   __OM  uint32_t  TASKS_CCASTART;               /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE
2635                                                                     802.15.4 mode                                              */
2636   __OM  uint32_t  TASKS_CCASTOP;                /*!< (@ 0x00000030) Stop the clear channel assessment                          */
2637   __IM  uint32_t  RESERVED[19];
2638   __IOM uint32_t  SUBSCRIBE_TXEN;               /*!< (@ 0x00000080) Subscribe configuration for task TXEN                      */
2639   __IOM uint32_t  SUBSCRIBE_RXEN;               /*!< (@ 0x00000084) Subscribe configuration for task RXEN                      */
2640   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000088) Subscribe configuration for task START                     */
2641   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x0000008C) Subscribe configuration for task STOP                      */
2642   __IOM uint32_t  SUBSCRIBE_DISABLE;            /*!< (@ 0x00000090) Subscribe configuration for task DISABLE                   */
2643   __IOM uint32_t  SUBSCRIBE_RSSISTART;          /*!< (@ 0x00000094) Subscribe configuration for task RSSISTART                 */
2644   __IOM uint32_t  SUBSCRIBE_RSSISTOP;           /*!< (@ 0x00000098) Subscribe configuration for task RSSISTOP                  */
2645   __IOM uint32_t  SUBSCRIBE_BCSTART;            /*!< (@ 0x0000009C) Subscribe configuration for task BCSTART                   */
2646   __IOM uint32_t  SUBSCRIBE_BCSTOP;             /*!< (@ 0x000000A0) Subscribe configuration for task BCSTOP                    */
2647   __IOM uint32_t  SUBSCRIBE_EDSTART;            /*!< (@ 0x000000A4) Subscribe configuration for task EDSTART                   */
2648   __IOM uint32_t  SUBSCRIBE_EDSTOP;             /*!< (@ 0x000000A8) Subscribe configuration for task EDSTOP                    */
2649   __IOM uint32_t  SUBSCRIBE_CCASTART;           /*!< (@ 0x000000AC) Subscribe configuration for task CCASTART                  */
2650   __IOM uint32_t  SUBSCRIBE_CCASTOP;            /*!< (@ 0x000000B0) Subscribe configuration for task CCASTOP                   */
2651   __IM  uint32_t  RESERVED1[19];
2652   __IOM uint32_t  EVENTS_READY;                 /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started             */
2653   __IOM uint32_t  EVENTS_ADDRESS;               /*!< (@ 0x00000104) Address sent or received                                   */
2654   __IOM uint32_t  EVENTS_PAYLOAD;               /*!< (@ 0x00000108) Packet payload sent or received                            */
2655   __IOM uint32_t  EVENTS_END;                   /*!< (@ 0x0000010C) Packet sent or received                                    */
2656   __IOM uint32_t  EVENTS_DISABLED;              /*!< (@ 0x00000110) RADIO has been disabled                                    */
2657   __IOM uint32_t  EVENTS_DEVMATCH;              /*!< (@ 0x00000114) A device address match occurred on the last received
2658                                                                     packet                                                     */
2659   __IOM uint32_t  EVENTS_DEVMISS;               /*!< (@ 0x00000118) No device address match occurred on the last
2660                                                                     received packet                                            */
2661   __IOM uint32_t  EVENTS_RSSIEND;               /*!< (@ 0x0000011C) Sampling of receive signal strength complete               */
2662   __IM  uint32_t  RESERVED2[2];
2663   __IOM uint32_t  EVENTS_BCMATCH;               /*!< (@ 0x00000128) Bit counter reached bit count value                        */
2664   __IM  uint32_t  RESERVED3;
2665   __IOM uint32_t  EVENTS_CRCOK;                 /*!< (@ 0x00000130) Packet received with CRC ok                                */
2666   __IOM uint32_t  EVENTS_CRCERROR;              /*!< (@ 0x00000134) Packet received with CRC error                             */
2667   __IOM uint32_t  EVENTS_FRAMESTART;            /*!< (@ 0x00000138) IEEE 802.15.4 length field received                        */
2668   __IOM uint32_t  EVENTS_EDEND;                 /*!< (@ 0x0000013C) Sampling of energy detection complete. A new
2669                                                                     ED sample is ready for readout from the
2670                                                                     RADIO.EDSAMPLE register.                                   */
2671   __IOM uint32_t  EVENTS_EDSTOPPED;             /*!< (@ 0x00000140) The sampling of energy detection has stopped               */
2672   __IOM uint32_t  EVENTS_CCAIDLE;               /*!< (@ 0x00000144) Wireless medium in idle - clear to send                    */
2673   __IOM uint32_t  EVENTS_CCABUSY;               /*!< (@ 0x00000148) Wireless medium busy - do not send                         */
2674   __IOM uint32_t  EVENTS_CCASTOPPED;            /*!< (@ 0x0000014C) The CCA has stopped                                        */
2675   __IOM uint32_t  EVENTS_RATEBOOST;             /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed
2676                                                                     from Ble_LR125Kbit to Ble_LR500Kbit.                       */
2677   __IOM uint32_t  EVENTS_TXREADY;               /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started
2678                                                                     TX path                                                    */
2679   __IOM uint32_t  EVENTS_RXREADY;               /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started
2680                                                                     RX path                                                    */
2681   __IOM uint32_t  EVENTS_MHRMATCH;              /*!< (@ 0x0000015C) MAC header match found                                     */
2682   __IM  uint32_t  RESERVED4[2];
2683   __IOM uint32_t  EVENTS_SYNC;                  /*!< (@ 0x00000168) Preamble indicator                                         */
2684   __IOM uint32_t  EVENTS_PHYEND;                /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received
2685                                                                     from air                                                   */
2686   __IOM uint32_t  EVENTS_CTEPRESENT;            /*!< (@ 0x00000170) CTE is present (early warning right after receiving
2687                                                                     CTEInfo byte)                                              */
2688   __IM  uint32_t  RESERVED5[3];
2689   __IOM uint32_t  PUBLISH_READY;                /*!< (@ 0x00000180) Publish configuration for event READY                      */
2690   __IOM uint32_t  PUBLISH_ADDRESS;              /*!< (@ 0x00000184) Publish configuration for event ADDRESS                    */
2691   __IOM uint32_t  PUBLISH_PAYLOAD;              /*!< (@ 0x00000188) Publish configuration for event PAYLOAD                    */
2692   __IOM uint32_t  PUBLISH_END;                  /*!< (@ 0x0000018C) Publish configuration for event END                        */
2693   __IOM uint32_t  PUBLISH_DISABLED;             /*!< (@ 0x00000190) Publish configuration for event DISABLED                   */
2694   __IOM uint32_t  PUBLISH_DEVMATCH;             /*!< (@ 0x00000194) Publish configuration for event DEVMATCH                   */
2695   __IOM uint32_t  PUBLISH_DEVMISS;              /*!< (@ 0x00000198) Publish configuration for event DEVMISS                    */
2696   __IOM uint32_t  PUBLISH_RSSIEND;              /*!< (@ 0x0000019C) Publish configuration for event RSSIEND                    */
2697   __IM  uint32_t  RESERVED6[2];
2698   __IOM uint32_t  PUBLISH_BCMATCH;              /*!< (@ 0x000001A8) Publish configuration for event BCMATCH                    */
2699   __IM  uint32_t  RESERVED7;
2700   __IOM uint32_t  PUBLISH_CRCOK;                /*!< (@ 0x000001B0) Publish configuration for event CRCOK                      */
2701   __IOM uint32_t  PUBLISH_CRCERROR;             /*!< (@ 0x000001B4) Publish configuration for event CRCERROR                   */
2702   __IOM uint32_t  PUBLISH_FRAMESTART;           /*!< (@ 0x000001B8) Publish configuration for event FRAMESTART                 */
2703   __IOM uint32_t  PUBLISH_EDEND;                /*!< (@ 0x000001BC) Publish configuration for event EDEND                      */
2704   __IOM uint32_t  PUBLISH_EDSTOPPED;            /*!< (@ 0x000001C0) Publish configuration for event EDSTOPPED                  */
2705   __IOM uint32_t  PUBLISH_CCAIDLE;              /*!< (@ 0x000001C4) Publish configuration for event CCAIDLE                    */
2706   __IOM uint32_t  PUBLISH_CCABUSY;              /*!< (@ 0x000001C8) Publish configuration for event CCABUSY                    */
2707   __IOM uint32_t  PUBLISH_CCASTOPPED;           /*!< (@ 0x000001CC) Publish configuration for event CCASTOPPED                 */
2708   __IOM uint32_t  PUBLISH_RATEBOOST;            /*!< (@ 0x000001D0) Publish configuration for event RATEBOOST                  */
2709   __IOM uint32_t  PUBLISH_TXREADY;              /*!< (@ 0x000001D4) Publish configuration for event TXREADY                    */
2710   __IOM uint32_t  PUBLISH_RXREADY;              /*!< (@ 0x000001D8) Publish configuration for event RXREADY                    */
2711   __IOM uint32_t  PUBLISH_MHRMATCH;             /*!< (@ 0x000001DC) Publish configuration for event MHRMATCH                   */
2712   __IM  uint32_t  RESERVED8[2];
2713   __IOM uint32_t  PUBLISH_SYNC;                 /*!< (@ 0x000001E8) Publish configuration for event SYNC                       */
2714   __IOM uint32_t  PUBLISH_PHYEND;               /*!< (@ 0x000001EC) Publish configuration for event PHYEND                     */
2715   __IOM uint32_t  PUBLISH_CTEPRESENT;           /*!< (@ 0x000001F0) Publish configuration for event CTEPRESENT                 */
2716   __IM  uint32_t  RESERVED9[3];
2717   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
2718   __IM  uint32_t  RESERVED10[64];
2719   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
2720   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
2721   __IM  uint32_t  RESERVED11[61];
2722   __IM  uint32_t  CRCSTATUS;                    /*!< (@ 0x00000400) CRC status                                                 */
2723   __IM  uint32_t  RESERVED12;
2724   __IM  uint32_t  RXMATCH;                      /*!< (@ 0x00000408) Received address                                           */
2725   __IM  uint32_t  RXCRC;                        /*!< (@ 0x0000040C) CRC field of previously received packet                    */
2726   __IM  uint32_t  DAI;                          /*!< (@ 0x00000410) Device address match index                                 */
2727   __IM  uint32_t  PDUSTAT;                      /*!< (@ 0x00000414) Payload status                                             */
2728   __IM  uint32_t  RESERVED13[13];
2729   __IM  uint32_t  CTESTATUS;                    /*!< (@ 0x0000044C) CTEInfo parsed from received packet                        */
2730   __IM  uint32_t  RESERVED14[2];
2731   __IM  uint32_t  DFESTATUS;                    /*!< (@ 0x00000458) DFE status information                                     */
2732   __IM  uint32_t  RESERVED15[42];
2733   __IOM uint32_t  PACKETPTR;                    /*!< (@ 0x00000504) Packet pointer                                             */
2734   __IOM uint32_t  FREQUENCY;                    /*!< (@ 0x00000508) Frequency                                                  */
2735   __IOM uint32_t  TXPOWER;                      /*!< (@ 0x0000050C) Output power                                               */
2736   __IOM uint32_t  MODE;                         /*!< (@ 0x00000510) Data rate and modulation                                   */
2737   __IOM uint32_t  PCNF0;                        /*!< (@ 0x00000514) Packet configuration register 0                            */
2738   __IOM uint32_t  PCNF1;                        /*!< (@ 0x00000518) Packet configuration register 1                            */
2739   __IOM uint32_t  BASE0;                        /*!< (@ 0x0000051C) Base address 0                                             */
2740   __IOM uint32_t  BASE1;                        /*!< (@ 0x00000520) Base address 1                                             */
2741   __IOM uint32_t  PREFIX0;                      /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3                   */
2742   __IOM uint32_t  PREFIX1;                      /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7                   */
2743   __IOM uint32_t  TXADDRESS;                    /*!< (@ 0x0000052C) Transmit address select                                    */
2744   __IOM uint32_t  RXADDRESSES;                  /*!< (@ 0x00000530) Receive address select                                     */
2745   __IOM uint32_t  CRCCNF;                       /*!< (@ 0x00000534) CRC configuration                                          */
2746   __IOM uint32_t  CRCPOLY;                      /*!< (@ 0x00000538) CRC polynomial                                             */
2747   __IOM uint32_t  CRCINIT;                      /*!< (@ 0x0000053C) CRC initial value                                          */
2748   __IM  uint32_t  RESERVED16;
2749   __IOM uint32_t  TIFS;                         /*!< (@ 0x00000544) Interframe spacing in us                                   */
2750   __IM  uint32_t  RSSISAMPLE;                   /*!< (@ 0x00000548) RSSI sample                                                */
2751   __IM  uint32_t  RESERVED17;
2752   __IM  uint32_t  STATE;                        /*!< (@ 0x00000550) Current radio state                                        */
2753   __IOM uint32_t  DATAWHITEIV;                  /*!< (@ 0x00000554) Data whitening initial value                               */
2754   __IM  uint32_t  RESERVED18[2];
2755   __IOM uint32_t  BCC;                          /*!< (@ 0x00000560) Bit counter compare                                        */
2756   __IM  uint32_t  RESERVED19[39];
2757   __IOM uint32_t  DAB[8];                       /*!< (@ 0x00000600) Description collection: Device address base segment
2758                                                                     n                                                          */
2759   __IOM uint32_t  DAP[8];                       /*!< (@ 0x00000620) Description collection: Device address prefix
2760                                                                     n                                                          */
2761   __IOM uint32_t  DACNF;                        /*!< (@ 0x00000640) Device address match configuration                         */
2762   __IOM uint32_t  MHRMATCHCONF;                 /*!< (@ 0x00000644) Search pattern configuration                               */
2763   __IOM uint32_t  MHRMATCHMAS;                  /*!< (@ 0x00000648) Pattern mask                                               */
2764   __IM  uint32_t  RESERVED20;
2765   __IOM uint32_t  MODECNF0;                     /*!< (@ 0x00000650) Radio mode configuration register 0                        */
2766   __IM  uint32_t  RESERVED21[3];
2767   __IOM uint32_t  SFD;                          /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter                     */
2768   __IOM uint32_t  EDCNT;                        /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count                     */
2769   __IM  uint32_t  EDSAMPLE;                     /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level                          */
2770   __IOM uint32_t  CCACTRL;                      /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control             */
2771   __IM  uint32_t  RESERVED22[164];
2772   __IOM uint32_t  DFEMODE;                      /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure
2773                                                                     (AOD)                                                      */
2774   __IOM uint32_t  CTEINLINECONF;                /*!< (@ 0x00000904) Configuration for CTE inline mode                          */
2775   __IM  uint32_t  RESERVED23[2];
2776   __IOM uint32_t  DFECTRL1;                     /*!< (@ 0x00000910) Various configuration for Direction finding                */
2777   __IOM uint32_t  DFECTRL2;                     /*!< (@ 0x00000914) Start offset for Direction finding                         */
2778   __IM  uint32_t  RESERVED24[4];
2779   __IOM uint32_t  SWITCHPATTERN;                /*!< (@ 0x00000928) GPIO patterns to be used for each antenna                  */
2780   __IOM uint32_t  CLEARPATTERN;                 /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control           */
2781   __IOM RADIO_PSEL_Type PSEL;                   /*!< (@ 0x00000930) Unspecified                                                */
2782   __IOM RADIO_DFEPACKET_Type DFEPACKET;         /*!< (@ 0x00000950) DFE packet EasyDMA channel                                 */
2783   __IM  uint32_t  RESERVED25[424];
2784   __IOM uint32_t  POWER;                        /*!< (@ 0x00000FFC) Peripheral power control                                   */
2785 } NRF_RADIO_Type;                               /*!< Size = 4096 (0x1000)                                                      */
2786 
2787 
2788 /* Peripheral: RADIO */
2789 /* Description: 2.4 GHz radio */
2790 
2791 /* Register: RADIO_TASKS_TXEN */
2792 /* Description: Enable RADIO in TX mode */
2793 
2794 /* Bit 0 : Enable RADIO in TX mode */
2795 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */
2796 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */
2797 #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */
2798 
2799 /* Register: RADIO_TASKS_RXEN */
2800 /* Description: Enable RADIO in RX mode */
2801 
2802 /* Bit 0 : Enable RADIO in RX mode */
2803 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */
2804 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */
2805 #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */
2806 
2807 /* Register: RADIO_TASKS_START */
2808 /* Description: Start RADIO */
2809 
2810 /* Bit 0 : Start RADIO */
2811 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
2812 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
2813 #define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
2814 
2815 /* Register: RADIO_TASKS_STOP */
2816 /* Description: Stop RADIO */
2817 
2818 /* Bit 0 : Stop RADIO */
2819 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
2820 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
2821 #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
2822 
2823 /* Register: RADIO_TASKS_DISABLE */
2824 /* Description: Disable RADIO */
2825 
2826 /* Bit 0 : Disable RADIO */
2827 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */
2828 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */
2829 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */
2830 
2831 /* Register: RADIO_TASKS_RSSISTART */
2832 /* Description: Start the RSSI and take one single sample of the receive signal strength */
2833 
2834 /* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */
2835 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */
2836 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */
2837 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */
2838 
2839 /* Register: RADIO_TASKS_RSSISTOP */
2840 /* Description: Stop the RSSI measurement */
2841 
2842 /* Bit 0 : Stop the RSSI measurement */
2843 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */
2844 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */
2845 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */
2846 
2847 /* Register: RADIO_TASKS_BCSTART */
2848 /* Description: Start the bit counter */
2849 
2850 /* Bit 0 : Start the bit counter */
2851 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */
2852 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */
2853 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */
2854 
2855 /* Register: RADIO_TASKS_BCSTOP */
2856 /* Description: Stop the bit counter */
2857 
2858 /* Bit 0 : Stop the bit counter */
2859 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */
2860 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */
2861 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */
2862 
2863 /* Register: RADIO_TASKS_EDSTART */
2864 /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */
2865 
2866 /* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */
2867 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */
2868 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */
2869 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */
2870 
2871 /* Register: RADIO_TASKS_EDSTOP */
2872 /* Description: Stop the energy detect measurement */
2873 
2874 /* Bit 0 : Stop the energy detect measurement */
2875 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */
2876 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */
2877 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */
2878 
2879 /* Register: RADIO_TASKS_CCASTART */
2880 /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */
2881 
2882 /* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */
2883 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */
2884 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */
2885 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */
2886 
2887 /* Register: RADIO_TASKS_CCASTOP */
2888 /* Description: Stop the clear channel assessment */
2889 
2890 /* Bit 0 : Stop the clear channel assessment */
2891 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */
2892 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */
2893 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */
2894 
2895 /* Register: RADIO_SUBSCRIBE_TXEN */
2896 /* Description: Subscribe configuration for task TXEN */
2897 
2898 /* Bit 31 :   */
2899 #define RADIO_SUBSCRIBE_TXEN_EN_Pos (31UL) /*!< Position of EN field. */
2900 #define RADIO_SUBSCRIBE_TXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_TXEN_EN_Pos) /*!< Bit mask of EN field. */
2901 #define RADIO_SUBSCRIBE_TXEN_EN_Disabled (0UL) /*!< Disable subscription */
2902 #define RADIO_SUBSCRIBE_TXEN_EN_Enabled (1UL) /*!< Enable subscription */
2903 
2904 /* Bits 7..0 : DPPI channel that task TXEN will subscribe to */
2905 #define RADIO_SUBSCRIBE_TXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2906 #define RADIO_SUBSCRIBE_TXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_TXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2907 
2908 /* Register: RADIO_SUBSCRIBE_RXEN */
2909 /* Description: Subscribe configuration for task RXEN */
2910 
2911 /* Bit 31 :   */
2912 #define RADIO_SUBSCRIBE_RXEN_EN_Pos (31UL) /*!< Position of EN field. */
2913 #define RADIO_SUBSCRIBE_RXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RXEN_EN_Pos) /*!< Bit mask of EN field. */
2914 #define RADIO_SUBSCRIBE_RXEN_EN_Disabled (0UL) /*!< Disable subscription */
2915 #define RADIO_SUBSCRIBE_RXEN_EN_Enabled (1UL) /*!< Enable subscription */
2916 
2917 /* Bits 7..0 : DPPI channel that task RXEN will subscribe to */
2918 #define RADIO_SUBSCRIBE_RXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2919 #define RADIO_SUBSCRIBE_RXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2920 
2921 /* Register: RADIO_SUBSCRIBE_START */
2922 /* Description: Subscribe configuration for task START */
2923 
2924 /* Bit 31 :   */
2925 #define RADIO_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
2926 #define RADIO_SUBSCRIBE_START_EN_Msk (0x1UL << RADIO_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
2927 #define RADIO_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
2928 #define RADIO_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
2929 
2930 /* Bits 7..0 : DPPI channel that task START will subscribe to */
2931 #define RADIO_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2932 #define RADIO_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2933 
2934 /* Register: RADIO_SUBSCRIBE_STOP */
2935 /* Description: Subscribe configuration for task STOP */
2936 
2937 /* Bit 31 :   */
2938 #define RADIO_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
2939 #define RADIO_SUBSCRIBE_STOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
2940 #define RADIO_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
2941 #define RADIO_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
2942 
2943 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
2944 #define RADIO_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2945 #define RADIO_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2946 
2947 /* Register: RADIO_SUBSCRIBE_DISABLE */
2948 /* Description: Subscribe configuration for task DISABLE */
2949 
2950 /* Bit 31 :   */
2951 #define RADIO_SUBSCRIBE_DISABLE_EN_Pos (31UL) /*!< Position of EN field. */
2952 #define RADIO_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << RADIO_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field. */
2953 #define RADIO_SUBSCRIBE_DISABLE_EN_Disabled (0UL) /*!< Disable subscription */
2954 #define RADIO_SUBSCRIBE_DISABLE_EN_Enabled (1UL) /*!< Enable subscription */
2955 
2956 /* Bits 7..0 : DPPI channel that task DISABLE will subscribe to */
2957 #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2958 #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2959 
2960 /* Register: RADIO_SUBSCRIBE_RSSISTART */
2961 /* Description: Subscribe configuration for task RSSISTART */
2962 
2963 /* Bit 31 :   */
2964 #define RADIO_SUBSCRIBE_RSSISTART_EN_Pos (31UL) /*!< Position of EN field. */
2965 #define RADIO_SUBSCRIBE_RSSISTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTART_EN_Pos) /*!< Bit mask of EN field. */
2966 #define RADIO_SUBSCRIBE_RSSISTART_EN_Disabled (0UL) /*!< Disable subscription */
2967 #define RADIO_SUBSCRIBE_RSSISTART_EN_Enabled (1UL) /*!< Enable subscription */
2968 
2969 /* Bits 7..0 : DPPI channel that task RSSISTART will subscribe to */
2970 #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2971 #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2972 
2973 /* Register: RADIO_SUBSCRIBE_RSSISTOP */
2974 /* Description: Subscribe configuration for task RSSISTOP */
2975 
2976 /* Bit 31 :   */
2977 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Pos (31UL) /*!< Position of EN field. */
2978 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTOP_EN_Pos) /*!< Bit mask of EN field. */
2979 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Disabled (0UL) /*!< Disable subscription */
2980 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Enabled (1UL) /*!< Enable subscription */
2981 
2982 /* Bits 7..0 : DPPI channel that task RSSISTOP will subscribe to */
2983 #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2984 #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2985 
2986 /* Register: RADIO_SUBSCRIBE_BCSTART */
2987 /* Description: Subscribe configuration for task BCSTART */
2988 
2989 /* Bit 31 :   */
2990 #define RADIO_SUBSCRIBE_BCSTART_EN_Pos (31UL) /*!< Position of EN field. */
2991 #define RADIO_SUBSCRIBE_BCSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTART_EN_Pos) /*!< Bit mask of EN field. */
2992 #define RADIO_SUBSCRIBE_BCSTART_EN_Disabled (0UL) /*!< Disable subscription */
2993 #define RADIO_SUBSCRIBE_BCSTART_EN_Enabled (1UL) /*!< Enable subscription */
2994 
2995 /* Bits 7..0 : DPPI channel that task BCSTART will subscribe to */
2996 #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
2997 #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
2998 
2999 /* Register: RADIO_SUBSCRIBE_BCSTOP */
3000 /* Description: Subscribe configuration for task BCSTOP */
3001 
3002 /* Bit 31 :   */
3003 #define RADIO_SUBSCRIBE_BCSTOP_EN_Pos (31UL) /*!< Position of EN field. */
3004 #define RADIO_SUBSCRIBE_BCSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTOP_EN_Pos) /*!< Bit mask of EN field. */
3005 #define RADIO_SUBSCRIBE_BCSTOP_EN_Disabled (0UL) /*!< Disable subscription */
3006 #define RADIO_SUBSCRIBE_BCSTOP_EN_Enabled (1UL) /*!< Enable subscription */
3007 
3008 /* Bits 7..0 : DPPI channel that task BCSTOP will subscribe to */
3009 #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3010 #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3011 
3012 /* Register: RADIO_SUBSCRIBE_EDSTART */
3013 /* Description: Subscribe configuration for task EDSTART */
3014 
3015 /* Bit 31 :   */
3016 #define RADIO_SUBSCRIBE_EDSTART_EN_Pos (31UL) /*!< Position of EN field. */
3017 #define RADIO_SUBSCRIBE_EDSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTART_EN_Pos) /*!< Bit mask of EN field. */
3018 #define RADIO_SUBSCRIBE_EDSTART_EN_Disabled (0UL) /*!< Disable subscription */
3019 #define RADIO_SUBSCRIBE_EDSTART_EN_Enabled (1UL) /*!< Enable subscription */
3020 
3021 /* Bits 7..0 : DPPI channel that task EDSTART will subscribe to */
3022 #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3023 #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3024 
3025 /* Register: RADIO_SUBSCRIBE_EDSTOP */
3026 /* Description: Subscribe configuration for task EDSTOP */
3027 
3028 /* Bit 31 :   */
3029 #define RADIO_SUBSCRIBE_EDSTOP_EN_Pos (31UL) /*!< Position of EN field. */
3030 #define RADIO_SUBSCRIBE_EDSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTOP_EN_Pos) /*!< Bit mask of EN field. */
3031 #define RADIO_SUBSCRIBE_EDSTOP_EN_Disabled (0UL) /*!< Disable subscription */
3032 #define RADIO_SUBSCRIBE_EDSTOP_EN_Enabled (1UL) /*!< Enable subscription */
3033 
3034 /* Bits 7..0 : DPPI channel that task EDSTOP will subscribe to */
3035 #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3036 #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3037 
3038 /* Register: RADIO_SUBSCRIBE_CCASTART */
3039 /* Description: Subscribe configuration for task CCASTART */
3040 
3041 /* Bit 31 :   */
3042 #define RADIO_SUBSCRIBE_CCASTART_EN_Pos (31UL) /*!< Position of EN field. */
3043 #define RADIO_SUBSCRIBE_CCASTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTART_EN_Pos) /*!< Bit mask of EN field. */
3044 #define RADIO_SUBSCRIBE_CCASTART_EN_Disabled (0UL) /*!< Disable subscription */
3045 #define RADIO_SUBSCRIBE_CCASTART_EN_Enabled (1UL) /*!< Enable subscription */
3046 
3047 /* Bits 7..0 : DPPI channel that task CCASTART will subscribe to */
3048 #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3049 #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3050 
3051 /* Register: RADIO_SUBSCRIBE_CCASTOP */
3052 /* Description: Subscribe configuration for task CCASTOP */
3053 
3054 /* Bit 31 :   */
3055 #define RADIO_SUBSCRIBE_CCASTOP_EN_Pos (31UL) /*!< Position of EN field. */
3056 #define RADIO_SUBSCRIBE_CCASTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTOP_EN_Pos) /*!< Bit mask of EN field. */
3057 #define RADIO_SUBSCRIBE_CCASTOP_EN_Disabled (0UL) /*!< Disable subscription */
3058 #define RADIO_SUBSCRIBE_CCASTOP_EN_Enabled (1UL) /*!< Enable subscription */
3059 
3060 /* Bits 7..0 : DPPI channel that task CCASTOP will subscribe to */
3061 #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3062 #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3063 
3064 /* Register: RADIO_EVENTS_READY */
3065 /* Description: RADIO has ramped up and is ready to be started */
3066 
3067 /* Bit 0 : RADIO has ramped up and is ready to be started */
3068 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */
3069 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */
3070 #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */
3071 #define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */
3072 
3073 /* Register: RADIO_EVENTS_ADDRESS */
3074 /* Description: Address sent or received */
3075 
3076 /* Bit 0 : Address sent or received */
3077 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */
3078 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */
3079 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */
3080 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */
3081 
3082 /* Register: RADIO_EVENTS_PAYLOAD */
3083 /* Description: Packet payload sent or received */
3084 
3085 /* Bit 0 : Packet payload sent or received */
3086 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */
3087 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */
3088 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */
3089 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */
3090 
3091 /* Register: RADIO_EVENTS_END */
3092 /* Description: Packet sent or received */
3093 
3094 /* Bit 0 : Packet sent or received */
3095 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */
3096 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */
3097 #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */
3098 #define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */
3099 
3100 /* Register: RADIO_EVENTS_DISABLED */
3101 /* Description: RADIO has been disabled */
3102 
3103 /* Bit 0 : RADIO has been disabled */
3104 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */
3105 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */
3106 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */
3107 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */
3108 
3109 /* Register: RADIO_EVENTS_DEVMATCH */
3110 /* Description: A device address match occurred on the last received packet */
3111 
3112 /* Bit 0 : A device address match occurred on the last received packet */
3113 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */
3114 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */
3115 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */
3116 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */
3117 
3118 /* Register: RADIO_EVENTS_DEVMISS */
3119 /* Description: No device address match occurred on the last received packet */
3120 
3121 /* Bit 0 : No device address match occurred on the last received packet */
3122 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */
3123 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */
3124 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */
3125 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */
3126 
3127 /* Register: RADIO_EVENTS_RSSIEND */
3128 /* Description: Sampling of receive signal strength complete */
3129 
3130 /* Bit 0 : Sampling of receive signal strength complete */
3131 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */
3132 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */
3133 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */
3134 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */
3135 
3136 /* Register: RADIO_EVENTS_BCMATCH */
3137 /* Description: Bit counter reached bit count value */
3138 
3139 /* Bit 0 : Bit counter reached bit count value */
3140 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */
3141 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */
3142 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */
3143 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */
3144 
3145 /* Register: RADIO_EVENTS_CRCOK */
3146 /* Description: Packet received with CRC ok */
3147 
3148 /* Bit 0 : Packet received with CRC ok */
3149 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */
3150 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */
3151 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */
3152 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */
3153 
3154 /* Register: RADIO_EVENTS_CRCERROR */
3155 /* Description: Packet received with CRC error */
3156 
3157 /* Bit 0 : Packet received with CRC error */
3158 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */
3159 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */
3160 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */
3161 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */
3162 
3163 /* Register: RADIO_EVENTS_FRAMESTART */
3164 /* Description: IEEE 802.15.4 length field received */
3165 
3166 /* Bit 0 : IEEE 802.15.4 length field received */
3167 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */
3168 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */
3169 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */
3170 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */
3171 
3172 /* Register: RADIO_EVENTS_EDEND */
3173 /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
3174 
3175 /* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */
3176 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */
3177 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */
3178 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */
3179 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */
3180 
3181 /* Register: RADIO_EVENTS_EDSTOPPED */
3182 /* Description: The sampling of energy detection has stopped */
3183 
3184 /* Bit 0 : The sampling of energy detection has stopped */
3185 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */
3186 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */
3187 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */
3188 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */
3189 
3190 /* Register: RADIO_EVENTS_CCAIDLE */
3191 /* Description: Wireless medium in idle - clear to send */
3192 
3193 /* Bit 0 : Wireless medium in idle - clear to send */
3194 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */
3195 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */
3196 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */
3197 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */
3198 
3199 /* Register: RADIO_EVENTS_CCABUSY */
3200 /* Description: Wireless medium busy - do not send */
3201 
3202 /* Bit 0 : Wireless medium busy - do not send */
3203 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */
3204 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */
3205 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */
3206 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */
3207 
3208 /* Register: RADIO_EVENTS_CCASTOPPED */
3209 /* Description: The CCA has stopped */
3210 
3211 /* Bit 0 : The CCA has stopped */
3212 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */
3213 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */
3214 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */
3215 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */
3216 
3217 /* Register: RADIO_EVENTS_RATEBOOST */
3218 /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
3219 
3220 /* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
3221 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */
3222 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */
3223 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */
3224 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */
3225 
3226 /* Register: RADIO_EVENTS_TXREADY */
3227 /* Description: RADIO has ramped up and is ready to be started TX path */
3228 
3229 /* Bit 0 : RADIO has ramped up and is ready to be started TX path */
3230 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */
3231 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */
3232 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */
3233 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */
3234 
3235 /* Register: RADIO_EVENTS_RXREADY */
3236 /* Description: RADIO has ramped up and is ready to be started RX path */
3237 
3238 /* Bit 0 : RADIO has ramped up and is ready to be started RX path */
3239 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */
3240 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */
3241 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */
3242 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */
3243 
3244 /* Register: RADIO_EVENTS_MHRMATCH */
3245 /* Description: MAC header match found */
3246 
3247 /* Bit 0 : MAC header match found */
3248 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */
3249 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */
3250 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */
3251 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */
3252 
3253 /* Register: RADIO_EVENTS_SYNC */
3254 /* Description: Preamble indicator */
3255 
3256 /* Bit 0 : Preamble indicator */
3257 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */
3258 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */
3259 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */
3260 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */
3261 
3262 /* Register: RADIO_EVENTS_PHYEND */
3263 /* Description: Generated when last bit is sent on air, or received from air */
3264 
3265 /* Bit 0 : Generated when last bit is sent on air, or received from air */
3266 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */
3267 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */
3268 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */
3269 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */
3270 
3271 /* Register: RADIO_EVENTS_CTEPRESENT */
3272 /* Description: CTE is present (early warning right after receiving CTEInfo byte) */
3273 
3274 /* Bit 0 : CTE is present (early warning right after receiving CTEInfo byte) */
3275 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */
3276 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask of EVENTS_CTEPRESENT field. */
3277 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0UL) /*!< Event not generated */
3278 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (1UL) /*!< Event generated */
3279 
3280 /* Register: RADIO_PUBLISH_READY */
3281 /* Description: Publish configuration for event READY */
3282 
3283 /* Bit 31 :   */
3284 #define RADIO_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */
3285 #define RADIO_PUBLISH_READY_EN_Msk (0x1UL << RADIO_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */
3286 #define RADIO_PUBLISH_READY_EN_Disabled (0UL) /*!< Disable publishing */
3287 #define RADIO_PUBLISH_READY_EN_Enabled (1UL) /*!< Enable publishing */
3288 
3289 /* Bits 7..0 : DPPI channel that event READY will publish to. */
3290 #define RADIO_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3291 #define RADIO_PUBLISH_READY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3292 
3293 /* Register: RADIO_PUBLISH_ADDRESS */
3294 /* Description: Publish configuration for event ADDRESS */
3295 
3296 /* Bit 31 :   */
3297 #define RADIO_PUBLISH_ADDRESS_EN_Pos (31UL) /*!< Position of EN field. */
3298 #define RADIO_PUBLISH_ADDRESS_EN_Msk (0x1UL << RADIO_PUBLISH_ADDRESS_EN_Pos) /*!< Bit mask of EN field. */
3299 #define RADIO_PUBLISH_ADDRESS_EN_Disabled (0UL) /*!< Disable publishing */
3300 #define RADIO_PUBLISH_ADDRESS_EN_Enabled (1UL) /*!< Enable publishing */
3301 
3302 /* Bits 7..0 : DPPI channel that event ADDRESS will publish to. */
3303 #define RADIO_PUBLISH_ADDRESS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3304 #define RADIO_PUBLISH_ADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_ADDRESS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3305 
3306 /* Register: RADIO_PUBLISH_PAYLOAD */
3307 /* Description: Publish configuration for event PAYLOAD */
3308 
3309 /* Bit 31 :   */
3310 #define RADIO_PUBLISH_PAYLOAD_EN_Pos (31UL) /*!< Position of EN field. */
3311 #define RADIO_PUBLISH_PAYLOAD_EN_Msk (0x1UL << RADIO_PUBLISH_PAYLOAD_EN_Pos) /*!< Bit mask of EN field. */
3312 #define RADIO_PUBLISH_PAYLOAD_EN_Disabled (0UL) /*!< Disable publishing */
3313 #define RADIO_PUBLISH_PAYLOAD_EN_Enabled (1UL) /*!< Enable publishing */
3314 
3315 /* Bits 7..0 : DPPI channel that event PAYLOAD will publish to. */
3316 #define RADIO_PUBLISH_PAYLOAD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3317 #define RADIO_PUBLISH_PAYLOAD_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PAYLOAD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3318 
3319 /* Register: RADIO_PUBLISH_END */
3320 /* Description: Publish configuration for event END */
3321 
3322 /* Bit 31 :   */
3323 #define RADIO_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */
3324 #define RADIO_PUBLISH_END_EN_Msk (0x1UL << RADIO_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */
3325 #define RADIO_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */
3326 #define RADIO_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */
3327 
3328 /* Bits 7..0 : DPPI channel that event END will publish to. */
3329 #define RADIO_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3330 #define RADIO_PUBLISH_END_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3331 
3332 /* Register: RADIO_PUBLISH_DISABLED */
3333 /* Description: Publish configuration for event DISABLED */
3334 
3335 /* Bit 31 :   */
3336 #define RADIO_PUBLISH_DISABLED_EN_Pos (31UL) /*!< Position of EN field. */
3337 #define RADIO_PUBLISH_DISABLED_EN_Msk (0x1UL << RADIO_PUBLISH_DISABLED_EN_Pos) /*!< Bit mask of EN field. */
3338 #define RADIO_PUBLISH_DISABLED_EN_Disabled (0UL) /*!< Disable publishing */
3339 #define RADIO_PUBLISH_DISABLED_EN_Enabled (1UL) /*!< Enable publishing */
3340 
3341 /* Bits 7..0 : DPPI channel that event DISABLED will publish to. */
3342 #define RADIO_PUBLISH_DISABLED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3343 #define RADIO_PUBLISH_DISABLED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DISABLED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3344 
3345 /* Register: RADIO_PUBLISH_DEVMATCH */
3346 /* Description: Publish configuration for event DEVMATCH */
3347 
3348 /* Bit 31 :   */
3349 #define RADIO_PUBLISH_DEVMATCH_EN_Pos (31UL) /*!< Position of EN field. */
3350 #define RADIO_PUBLISH_DEVMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMATCH_EN_Pos) /*!< Bit mask of EN field. */
3351 #define RADIO_PUBLISH_DEVMATCH_EN_Disabled (0UL) /*!< Disable publishing */
3352 #define RADIO_PUBLISH_DEVMATCH_EN_Enabled (1UL) /*!< Enable publishing */
3353 
3354 /* Bits 7..0 : DPPI channel that event DEVMATCH will publish to. */
3355 #define RADIO_PUBLISH_DEVMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3356 #define RADIO_PUBLISH_DEVMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3357 
3358 /* Register: RADIO_PUBLISH_DEVMISS */
3359 /* Description: Publish configuration for event DEVMISS */
3360 
3361 /* Bit 31 :   */
3362 #define RADIO_PUBLISH_DEVMISS_EN_Pos (31UL) /*!< Position of EN field. */
3363 #define RADIO_PUBLISH_DEVMISS_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMISS_EN_Pos) /*!< Bit mask of EN field. */
3364 #define RADIO_PUBLISH_DEVMISS_EN_Disabled (0UL) /*!< Disable publishing */
3365 #define RADIO_PUBLISH_DEVMISS_EN_Enabled (1UL) /*!< Enable publishing */
3366 
3367 /* Bits 7..0 : DPPI channel that event DEVMISS will publish to. */
3368 #define RADIO_PUBLISH_DEVMISS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3369 #define RADIO_PUBLISH_DEVMISS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMISS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3370 
3371 /* Register: RADIO_PUBLISH_RSSIEND */
3372 /* Description: Publish configuration for event RSSIEND */
3373 
3374 /* Bit 31 :   */
3375 #define RADIO_PUBLISH_RSSIEND_EN_Pos (31UL) /*!< Position of EN field. */
3376 #define RADIO_PUBLISH_RSSIEND_EN_Msk (0x1UL << RADIO_PUBLISH_RSSIEND_EN_Pos) /*!< Bit mask of EN field. */
3377 #define RADIO_PUBLISH_RSSIEND_EN_Disabled (0UL) /*!< Disable publishing */
3378 #define RADIO_PUBLISH_RSSIEND_EN_Enabled (1UL) /*!< Enable publishing */
3379 
3380 /* Bits 7..0 : DPPI channel that event RSSIEND will publish to. */
3381 #define RADIO_PUBLISH_RSSIEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3382 #define RADIO_PUBLISH_RSSIEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RSSIEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3383 
3384 /* Register: RADIO_PUBLISH_BCMATCH */
3385 /* Description: Publish configuration for event BCMATCH */
3386 
3387 /* Bit 31 :   */
3388 #define RADIO_PUBLISH_BCMATCH_EN_Pos (31UL) /*!< Position of EN field. */
3389 #define RADIO_PUBLISH_BCMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_BCMATCH_EN_Pos) /*!< Bit mask of EN field. */
3390 #define RADIO_PUBLISH_BCMATCH_EN_Disabled (0UL) /*!< Disable publishing */
3391 #define RADIO_PUBLISH_BCMATCH_EN_Enabled (1UL) /*!< Enable publishing */
3392 
3393 /* Bits 7..0 : DPPI channel that event BCMATCH will publish to. */
3394 #define RADIO_PUBLISH_BCMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3395 #define RADIO_PUBLISH_BCMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_BCMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3396 
3397 /* Register: RADIO_PUBLISH_CRCOK */
3398 /* Description: Publish configuration for event CRCOK */
3399 
3400 /* Bit 31 :   */
3401 #define RADIO_PUBLISH_CRCOK_EN_Pos (31UL) /*!< Position of EN field. */
3402 #define RADIO_PUBLISH_CRCOK_EN_Msk (0x1UL << RADIO_PUBLISH_CRCOK_EN_Pos) /*!< Bit mask of EN field. */
3403 #define RADIO_PUBLISH_CRCOK_EN_Disabled (0UL) /*!< Disable publishing */
3404 #define RADIO_PUBLISH_CRCOK_EN_Enabled (1UL) /*!< Enable publishing */
3405 
3406 /* Bits 7..0 : DPPI channel that event CRCOK will publish to. */
3407 #define RADIO_PUBLISH_CRCOK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3408 #define RADIO_PUBLISH_CRCOK_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCOK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3409 
3410 /* Register: RADIO_PUBLISH_CRCERROR */
3411 /* Description: Publish configuration for event CRCERROR */
3412 
3413 /* Bit 31 :   */
3414 #define RADIO_PUBLISH_CRCERROR_EN_Pos (31UL) /*!< Position of EN field. */
3415 #define RADIO_PUBLISH_CRCERROR_EN_Msk (0x1UL << RADIO_PUBLISH_CRCERROR_EN_Pos) /*!< Bit mask of EN field. */
3416 #define RADIO_PUBLISH_CRCERROR_EN_Disabled (0UL) /*!< Disable publishing */
3417 #define RADIO_PUBLISH_CRCERROR_EN_Enabled (1UL) /*!< Enable publishing */
3418 
3419 /* Bits 7..0 : DPPI channel that event CRCERROR will publish to. */
3420 #define RADIO_PUBLISH_CRCERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3421 #define RADIO_PUBLISH_CRCERROR_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3422 
3423 /* Register: RADIO_PUBLISH_FRAMESTART */
3424 /* Description: Publish configuration for event FRAMESTART */
3425 
3426 /* Bit 31 :   */
3427 #define RADIO_PUBLISH_FRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */
3428 #define RADIO_PUBLISH_FRAMESTART_EN_Msk (0x1UL << RADIO_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field. */
3429 #define RADIO_PUBLISH_FRAMESTART_EN_Disabled (0UL) /*!< Disable publishing */
3430 #define RADIO_PUBLISH_FRAMESTART_EN_Enabled (1UL) /*!< Enable publishing */
3431 
3432 /* Bits 7..0 : DPPI channel that event FRAMESTART will publish to. */
3433 #define RADIO_PUBLISH_FRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3434 #define RADIO_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3435 
3436 /* Register: RADIO_PUBLISH_EDEND */
3437 /* Description: Publish configuration for event EDEND */
3438 
3439 /* Bit 31 :   */
3440 #define RADIO_PUBLISH_EDEND_EN_Pos (31UL) /*!< Position of EN field. */
3441 #define RADIO_PUBLISH_EDEND_EN_Msk (0x1UL << RADIO_PUBLISH_EDEND_EN_Pos) /*!< Bit mask of EN field. */
3442 #define RADIO_PUBLISH_EDEND_EN_Disabled (0UL) /*!< Disable publishing */
3443 #define RADIO_PUBLISH_EDEND_EN_Enabled (1UL) /*!< Enable publishing */
3444 
3445 /* Bits 7..0 : DPPI channel that event EDEND will publish to. */
3446 #define RADIO_PUBLISH_EDEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3447 #define RADIO_PUBLISH_EDEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3448 
3449 /* Register: RADIO_PUBLISH_EDSTOPPED */
3450 /* Description: Publish configuration for event EDSTOPPED */
3451 
3452 /* Bit 31 :   */
3453 #define RADIO_PUBLISH_EDSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */
3454 #define RADIO_PUBLISH_EDSTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_EDSTOPPED_EN_Pos) /*!< Bit mask of EN field. */
3455 #define RADIO_PUBLISH_EDSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */
3456 #define RADIO_PUBLISH_EDSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
3457 
3458 /* Bits 7..0 : DPPI channel that event EDSTOPPED will publish to. */
3459 #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3460 #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3461 
3462 /* Register: RADIO_PUBLISH_CCAIDLE */
3463 /* Description: Publish configuration for event CCAIDLE */
3464 
3465 /* Bit 31 :   */
3466 #define RADIO_PUBLISH_CCAIDLE_EN_Pos (31UL) /*!< Position of EN field. */
3467 #define RADIO_PUBLISH_CCAIDLE_EN_Msk (0x1UL << RADIO_PUBLISH_CCAIDLE_EN_Pos) /*!< Bit mask of EN field. */
3468 #define RADIO_PUBLISH_CCAIDLE_EN_Disabled (0UL) /*!< Disable publishing */
3469 #define RADIO_PUBLISH_CCAIDLE_EN_Enabled (1UL) /*!< Enable publishing */
3470 
3471 /* Bits 7..0 : DPPI channel that event CCAIDLE will publish to. */
3472 #define RADIO_PUBLISH_CCAIDLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3473 #define RADIO_PUBLISH_CCAIDLE_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCAIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3474 
3475 /* Register: RADIO_PUBLISH_CCABUSY */
3476 /* Description: Publish configuration for event CCABUSY */
3477 
3478 /* Bit 31 :   */
3479 #define RADIO_PUBLISH_CCABUSY_EN_Pos (31UL) /*!< Position of EN field. */
3480 #define RADIO_PUBLISH_CCABUSY_EN_Msk (0x1UL << RADIO_PUBLISH_CCABUSY_EN_Pos) /*!< Bit mask of EN field. */
3481 #define RADIO_PUBLISH_CCABUSY_EN_Disabled (0UL) /*!< Disable publishing */
3482 #define RADIO_PUBLISH_CCABUSY_EN_Enabled (1UL) /*!< Enable publishing */
3483 
3484 /* Bits 7..0 : DPPI channel that event CCABUSY will publish to. */
3485 #define RADIO_PUBLISH_CCABUSY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3486 #define RADIO_PUBLISH_CCABUSY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCABUSY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3487 
3488 /* Register: RADIO_PUBLISH_CCASTOPPED */
3489 /* Description: Publish configuration for event CCASTOPPED */
3490 
3491 /* Bit 31 :   */
3492 #define RADIO_PUBLISH_CCASTOPPED_EN_Pos (31UL) /*!< Position of EN field. */
3493 #define RADIO_PUBLISH_CCASTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_CCASTOPPED_EN_Pos) /*!< Bit mask of EN field. */
3494 #define RADIO_PUBLISH_CCASTOPPED_EN_Disabled (0UL) /*!< Disable publishing */
3495 #define RADIO_PUBLISH_CCASTOPPED_EN_Enabled (1UL) /*!< Enable publishing */
3496 
3497 /* Bits 7..0 : DPPI channel that event CCASTOPPED will publish to. */
3498 #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3499 #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3500 
3501 /* Register: RADIO_PUBLISH_RATEBOOST */
3502 /* Description: Publish configuration for event RATEBOOST */
3503 
3504 /* Bit 31 :   */
3505 #define RADIO_PUBLISH_RATEBOOST_EN_Pos (31UL) /*!< Position of EN field. */
3506 #define RADIO_PUBLISH_RATEBOOST_EN_Msk (0x1UL << RADIO_PUBLISH_RATEBOOST_EN_Pos) /*!< Bit mask of EN field. */
3507 #define RADIO_PUBLISH_RATEBOOST_EN_Disabled (0UL) /*!< Disable publishing */
3508 #define RADIO_PUBLISH_RATEBOOST_EN_Enabled (1UL) /*!< Enable publishing */
3509 
3510 /* Bits 7..0 : DPPI channel that event RATEBOOST will publish to. */
3511 #define RADIO_PUBLISH_RATEBOOST_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3512 #define RADIO_PUBLISH_RATEBOOST_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RATEBOOST_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3513 
3514 /* Register: RADIO_PUBLISH_TXREADY */
3515 /* Description: Publish configuration for event TXREADY */
3516 
3517 /* Bit 31 :   */
3518 #define RADIO_PUBLISH_TXREADY_EN_Pos (31UL) /*!< Position of EN field. */
3519 #define RADIO_PUBLISH_TXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_TXREADY_EN_Pos) /*!< Bit mask of EN field. */
3520 #define RADIO_PUBLISH_TXREADY_EN_Disabled (0UL) /*!< Disable publishing */
3521 #define RADIO_PUBLISH_TXREADY_EN_Enabled (1UL) /*!< Enable publishing */
3522 
3523 /* Bits 7..0 : DPPI channel that event TXREADY will publish to. */
3524 #define RADIO_PUBLISH_TXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3525 #define RADIO_PUBLISH_TXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_TXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3526 
3527 /* Register: RADIO_PUBLISH_RXREADY */
3528 /* Description: Publish configuration for event RXREADY */
3529 
3530 /* Bit 31 :   */
3531 #define RADIO_PUBLISH_RXREADY_EN_Pos (31UL) /*!< Position of EN field. */
3532 #define RADIO_PUBLISH_RXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_RXREADY_EN_Pos) /*!< Bit mask of EN field. */
3533 #define RADIO_PUBLISH_RXREADY_EN_Disabled (0UL) /*!< Disable publishing */
3534 #define RADIO_PUBLISH_RXREADY_EN_Enabled (1UL) /*!< Enable publishing */
3535 
3536 /* Bits 7..0 : DPPI channel that event RXREADY will publish to. */
3537 #define RADIO_PUBLISH_RXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3538 #define RADIO_PUBLISH_RXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3539 
3540 /* Register: RADIO_PUBLISH_MHRMATCH */
3541 /* Description: Publish configuration for event MHRMATCH */
3542 
3543 /* Bit 31 :   */
3544 #define RADIO_PUBLISH_MHRMATCH_EN_Pos (31UL) /*!< Position of EN field. */
3545 #define RADIO_PUBLISH_MHRMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_MHRMATCH_EN_Pos) /*!< Bit mask of EN field. */
3546 #define RADIO_PUBLISH_MHRMATCH_EN_Disabled (0UL) /*!< Disable publishing */
3547 #define RADIO_PUBLISH_MHRMATCH_EN_Enabled (1UL) /*!< Enable publishing */
3548 
3549 /* Bits 7..0 : DPPI channel that event MHRMATCH will publish to. */
3550 #define RADIO_PUBLISH_MHRMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3551 #define RADIO_PUBLISH_MHRMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_MHRMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3552 
3553 /* Register: RADIO_PUBLISH_SYNC */
3554 /* Description: Publish configuration for event SYNC */
3555 
3556 /* Bit 31 :   */
3557 #define RADIO_PUBLISH_SYNC_EN_Pos (31UL) /*!< Position of EN field. */
3558 #define RADIO_PUBLISH_SYNC_EN_Msk (0x1UL << RADIO_PUBLISH_SYNC_EN_Pos) /*!< Bit mask of EN field. */
3559 #define RADIO_PUBLISH_SYNC_EN_Disabled (0UL) /*!< Disable publishing */
3560 #define RADIO_PUBLISH_SYNC_EN_Enabled (1UL) /*!< Enable publishing */
3561 
3562 /* Bits 7..0 : DPPI channel that event SYNC will publish to. */
3563 #define RADIO_PUBLISH_SYNC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3564 #define RADIO_PUBLISH_SYNC_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_SYNC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3565 
3566 /* Register: RADIO_PUBLISH_PHYEND */
3567 /* Description: Publish configuration for event PHYEND */
3568 
3569 /* Bit 31 :   */
3570 #define RADIO_PUBLISH_PHYEND_EN_Pos (31UL) /*!< Position of EN field. */
3571 #define RADIO_PUBLISH_PHYEND_EN_Msk (0x1UL << RADIO_PUBLISH_PHYEND_EN_Pos) /*!< Bit mask of EN field. */
3572 #define RADIO_PUBLISH_PHYEND_EN_Disabled (0UL) /*!< Disable publishing */
3573 #define RADIO_PUBLISH_PHYEND_EN_Enabled (1UL) /*!< Enable publishing */
3574 
3575 /* Bits 7..0 : DPPI channel that event PHYEND will publish to. */
3576 #define RADIO_PUBLISH_PHYEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3577 #define RADIO_PUBLISH_PHYEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PHYEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3578 
3579 /* Register: RADIO_PUBLISH_CTEPRESENT */
3580 /* Description: Publish configuration for event CTEPRESENT */
3581 
3582 /* Bit 31 :   */
3583 #define RADIO_PUBLISH_CTEPRESENT_EN_Pos (31UL) /*!< Position of EN field. */
3584 #define RADIO_PUBLISH_CTEPRESENT_EN_Msk (0x1UL << RADIO_PUBLISH_CTEPRESENT_EN_Pos) /*!< Bit mask of EN field. */
3585 #define RADIO_PUBLISH_CTEPRESENT_EN_Disabled (0UL) /*!< Disable publishing */
3586 #define RADIO_PUBLISH_CTEPRESENT_EN_Enabled (1UL) /*!< Enable publishing */
3587 
3588 /* Bits 7..0 : DPPI channel that event CTEPRESENT will publish to. */
3589 #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
3590 #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
3591 
3592 /* Register: RADIO_SHORTS */
3593 /* Description: Shortcuts between local events and tasks */
3594 
3595 /* Bit 21 : Shortcut between event PHYEND and task START */
3596 #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */
3597 #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */
3598 #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */
3599 #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */
3600 
3601 /* Bit 20 : Shortcut between event PHYEND and task DISABLE */
3602 #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */
3603 #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */
3604 #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
3605 #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
3606 
3607 /* Bit 19 : Shortcut between event RXREADY and task START */
3608 #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */
3609 #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */
3610 #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */
3611 #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */
3612 
3613 /* Bit 18 : Shortcut between event TXREADY and task START */
3614 #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */
3615 #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */
3616 #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */
3617 #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */
3618 
3619 /* Bit 17 : Shortcut between event CCAIDLE and task STOP */
3620 #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */
3621 #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */
3622 #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */
3623 #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */
3624 
3625 /* Bit 16 : Shortcut between event EDEND and task DISABLE */
3626 #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */
3627 #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */
3628 #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
3629 #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
3630 
3631 /* Bit 15 : Shortcut between event READY and task EDSTART */
3632 #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */
3633 #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */
3634 #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */
3635 #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */
3636 
3637 /* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */
3638 #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */
3639 #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */
3640 #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */
3641 #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */
3642 
3643 /* Bit 13 : Shortcut between event CCABUSY and task DISABLE */
3644 #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */
3645 #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */
3646 #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */
3647 #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */
3648 
3649 /* Bit 12 : Shortcut between event CCAIDLE and task TXEN */
3650 #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */
3651 #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */
3652 #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */
3653 #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */
3654 
3655 /* Bit 11 : Shortcut between event RXREADY and task CCASTART */
3656 #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */
3657 #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */
3658 #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */
3659 #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */
3660 
3661 /* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */
3662 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
3663 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
3664 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
3665 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
3666 
3667 /* Bit 6 : Shortcut between event ADDRESS and task BCSTART */
3668 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
3669 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
3670 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
3671 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
3672 
3673 /* Bit 5 : Shortcut between event END and task START */
3674 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
3675 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
3676 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
3677 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
3678 
3679 /* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */
3680 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
3681 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
3682 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
3683 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
3684 
3685 /* Bit 3 : Shortcut between event DISABLED and task RXEN */
3686 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
3687 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
3688 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
3689 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
3690 
3691 /* Bit 2 : Shortcut between event DISABLED and task TXEN */
3692 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
3693 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
3694 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
3695 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
3696 
3697 /* Bit 1 : Shortcut between event END and task DISABLE */
3698 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
3699 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
3700 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
3701 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
3702 
3703 /* Bit 0 : Shortcut between event READY and task START */
3704 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
3705 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
3706 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
3707 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
3708 
3709 /* Register: RADIO_INTENSET */
3710 /* Description: Enable interrupt */
3711 
3712 /* Bit 28 : Write '1' to enable interrupt for event CTEPRESENT */
3713 #define RADIO_INTENSET_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
3714 #define RADIO_INTENSET_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
3715 #define RADIO_INTENSET_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
3716 #define RADIO_INTENSET_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
3717 #define RADIO_INTENSET_CTEPRESENT_Set (1UL) /*!< Enable */
3718 
3719 /* Bit 27 : Write '1' to enable interrupt for event PHYEND */
3720 #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
3721 #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
3722 #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */
3723 #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */
3724 #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */
3725 
3726 /* Bit 26 : Write '1' to enable interrupt for event SYNC */
3727 #define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */
3728 #define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */
3729 #define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */
3730 #define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */
3731 #define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */
3732 
3733 /* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */
3734 #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
3735 #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
3736 #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
3737 #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
3738 #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */
3739 
3740 /* Bit 22 : Write '1' to enable interrupt for event RXREADY */
3741 #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
3742 #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
3743 #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */
3744 #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */
3745 #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */
3746 
3747 /* Bit 21 : Write '1' to enable interrupt for event TXREADY */
3748 #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
3749 #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
3750 #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */
3751 #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */
3752 #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */
3753 
3754 /* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */
3755 #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
3756 #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
3757 #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
3758 #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
3759 #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */
3760 
3761 /* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */
3762 #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
3763 #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
3764 #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
3765 #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
3766 #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */
3767 
3768 /* Bit 18 : Write '1' to enable interrupt for event CCABUSY */
3769 #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
3770 #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
3771 #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
3772 #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
3773 #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */
3774 
3775 /* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */
3776 #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
3777 #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
3778 #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
3779 #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
3780 #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */
3781 
3782 /* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */
3783 #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
3784 #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
3785 #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
3786 #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
3787 #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */
3788 
3789 /* Bit 15 : Write '1' to enable interrupt for event EDEND */
3790 #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */
3791 #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */
3792 #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */
3793 #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */
3794 #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */
3795 
3796 /* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */
3797 #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
3798 #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
3799 #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
3800 #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
3801 #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */
3802 
3803 /* Bit 13 : Write '1' to enable interrupt for event CRCERROR */
3804 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
3805 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
3806 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
3807 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
3808 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
3809 
3810 /* Bit 12 : Write '1' to enable interrupt for event CRCOK */
3811 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
3812 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
3813 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
3814 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
3815 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
3816 
3817 /* Bit 10 : Write '1' to enable interrupt for event BCMATCH */
3818 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
3819 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
3820 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
3821 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
3822 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
3823 
3824 /* Bit 7 : Write '1' to enable interrupt for event RSSIEND */
3825 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
3826 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
3827 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
3828 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
3829 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
3830 
3831 /* Bit 6 : Write '1' to enable interrupt for event DEVMISS */
3832 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
3833 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
3834 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
3835 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
3836 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
3837 
3838 /* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */
3839 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
3840 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
3841 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
3842 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
3843 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
3844 
3845 /* Bit 4 : Write '1' to enable interrupt for event DISABLED */
3846 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
3847 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
3848 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
3849 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
3850 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
3851 
3852 /* Bit 3 : Write '1' to enable interrupt for event END */
3853 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
3854 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
3855 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
3856 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
3857 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
3858 
3859 /* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */
3860 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
3861 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
3862 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
3863 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
3864 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
3865 
3866 /* Bit 1 : Write '1' to enable interrupt for event ADDRESS */
3867 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
3868 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
3869 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
3870 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
3871 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
3872 
3873 /* Bit 0 : Write '1' to enable interrupt for event READY */
3874 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
3875 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
3876 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
3877 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
3878 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
3879 
3880 /* Register: RADIO_INTENCLR */
3881 /* Description: Disable interrupt */
3882 
3883 /* Bit 28 : Write '1' to disable interrupt for event CTEPRESENT */
3884 #define RADIO_INTENCLR_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */
3885 #define RADIO_INTENCLR_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */
3886 #define RADIO_INTENCLR_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */
3887 #define RADIO_INTENCLR_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */
3888 #define RADIO_INTENCLR_CTEPRESENT_Clear (1UL) /*!< Disable */
3889 
3890 /* Bit 27 : Write '1' to disable interrupt for event PHYEND */
3891 #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */
3892 #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */
3893 #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */
3894 #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */
3895 #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */
3896 
3897 /* Bit 26 : Write '1' to disable interrupt for event SYNC */
3898 #define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */
3899 #define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */
3900 #define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */
3901 #define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */
3902 #define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */
3903 
3904 /* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */
3905 #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
3906 #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
3907 #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
3908 #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
3909 #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */
3910 
3911 /* Bit 22 : Write '1' to disable interrupt for event RXREADY */
3912 #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
3913 #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
3914 #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */
3915 #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */
3916 #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */
3917 
3918 /* Bit 21 : Write '1' to disable interrupt for event TXREADY */
3919 #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
3920 #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
3921 #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */
3922 #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */
3923 #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */
3924 
3925 /* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */
3926 #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
3927 #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
3928 #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
3929 #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
3930 #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */
3931 
3932 /* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */
3933 #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
3934 #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
3935 #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
3936 #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
3937 #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */
3938 
3939 /* Bit 18 : Write '1' to disable interrupt for event CCABUSY */
3940 #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
3941 #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
3942 #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
3943 #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
3944 #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */
3945 
3946 /* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */
3947 #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
3948 #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
3949 #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
3950 #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
3951 #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */
3952 
3953 /* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */
3954 #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
3955 #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
3956 #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
3957 #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
3958 #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */
3959 
3960 /* Bit 15 : Write '1' to disable interrupt for event EDEND */
3961 #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */
3962 #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */
3963 #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */
3964 #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */
3965 #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */
3966 
3967 /* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */
3968 #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
3969 #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
3970 #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
3971 #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
3972 #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */
3973 
3974 /* Bit 13 : Write '1' to disable interrupt for event CRCERROR */
3975 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
3976 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
3977 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
3978 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
3979 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
3980 
3981 /* Bit 12 : Write '1' to disable interrupt for event CRCOK */
3982 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
3983 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
3984 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
3985 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
3986 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
3987 
3988 /* Bit 10 : Write '1' to disable interrupt for event BCMATCH */
3989 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
3990 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
3991 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
3992 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
3993 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
3994 
3995 /* Bit 7 : Write '1' to disable interrupt for event RSSIEND */
3996 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
3997 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
3998 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
3999 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
4000 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
4001 
4002 /* Bit 6 : Write '1' to disable interrupt for event DEVMISS */
4003 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
4004 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
4005 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
4006 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
4007 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
4008 
4009 /* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */
4010 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
4011 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
4012 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
4013 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
4014 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
4015 
4016 /* Bit 4 : Write '1' to disable interrupt for event DISABLED */
4017 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
4018 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
4019 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
4020 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
4021 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
4022 
4023 /* Bit 3 : Write '1' to disable interrupt for event END */
4024 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
4025 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
4026 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
4027 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
4028 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
4029 
4030 /* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */
4031 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
4032 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
4033 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
4034 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
4035 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
4036 
4037 /* Bit 1 : Write '1' to disable interrupt for event ADDRESS */
4038 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
4039 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
4040 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
4041 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
4042 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
4043 
4044 /* Bit 0 : Write '1' to disable interrupt for event READY */
4045 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
4046 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
4047 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
4048 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
4049 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
4050 
4051 /* Register: RADIO_CRCSTATUS */
4052 /* Description: CRC status */
4053 
4054 /* Bit 0 : CRC status of packet received */
4055 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
4056 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
4057 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
4058 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
4059 
4060 /* Register: RADIO_RXMATCH */
4061 /* Description: Received address */
4062 
4063 /* Bits 2..0 : Received address */
4064 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
4065 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
4066 
4067 /* Register: RADIO_RXCRC */
4068 /* Description: CRC field of previously received packet */
4069 
4070 /* Bits 23..0 : CRC field of previously received packet */
4071 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
4072 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
4073 
4074 /* Register: RADIO_DAI */
4075 /* Description: Device address match index */
4076 
4077 /* Bits 2..0 : Device address match index */
4078 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
4079 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
4080 
4081 /* Register: RADIO_PDUSTAT */
4082 /* Description: Payload status */
4083 
4084 /* Bits 2..1 : Status on what rate packet is received with in Long Range */
4085 #define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */
4086 #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */
4087 #define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125 kbps */
4088 #define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500 kbps */
4089 
4090 /* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */
4091 #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */
4092 #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */
4093 #define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */
4094 #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */
4095 
4096 /* Register: RADIO_CTESTATUS */
4097 /* Description: CTEInfo parsed from received packet */
4098 
4099 /* Bits 7..6 : CTEType parsed from packet */
4100 #define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */
4101 #define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */
4102 
4103 /* Bit 5 : RFU parsed from packet */
4104 #define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */
4105 #define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */
4106 
4107 /* Bits 4..0 : CTETime parsed from packet */
4108 #define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */
4109 #define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */
4110 
4111 /* Register: RADIO_DFESTATUS */
4112 /* Description: DFE status information */
4113 
4114 /* Bit 4 : Internal state of sampling state machine */
4115 #define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */
4116 #define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */
4117 #define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0UL) /*!< Sampling state Idle */
4118 #define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (1UL) /*!< Sampling state Sampling */
4119 
4120 /* Bits 2..0 : Internal state of switching state machine */
4121 #define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */
4122 #define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE field. */
4123 #define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0UL) /*!< Switching state Idle */
4124 #define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (1UL) /*!< Switching state Offset */
4125 #define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (2UL) /*!< Switching state Guard */
4126 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (3UL) /*!< Switching state Ref */
4127 #define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (4UL) /*!< Switching state Switching */
4128 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (5UL) /*!< Switching state Ending */
4129 
4130 /* Register: RADIO_PACKETPTR */
4131 /* Description: Packet pointer */
4132 
4133 /* Bits 31..0 : Packet pointer */
4134 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
4135 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
4136 
4137 /* Register: RADIO_FREQUENCY */
4138 /* Description: Frequency */
4139 
4140 /* Bit 8 : Channel map selection */
4141 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
4142 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
4143 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHz and 2500 MHz */
4144 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHz and 2460 MHz */
4145 
4146 /* Bits 6..0 : Radio channel frequency */
4147 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
4148 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
4149 
4150 /* Register: RADIO_TXPOWER */
4151 /* Description: Output power */
4152 
4153 /* Bits 7..0 : RADIO output power */
4154 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
4155 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
4156 #define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */
4157 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
4158 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator -  -40 dBm */
4159 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
4160 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
4161 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
4162 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
4163 #define RADIO_TXPOWER_TXPOWER_Neg7dBm (0xF9UL) /*!< -7 dBm */
4164 #define RADIO_TXPOWER_TXPOWER_Neg6dBm (0xFAUL) /*!< -6 dBm */
4165 #define RADIO_TXPOWER_TXPOWER_Neg5dBm (0xFBUL) /*!< -5 dBm */
4166 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
4167 #define RADIO_TXPOWER_TXPOWER_Neg3dBm (0xFDUL) /*!< -3 dBm */
4168 #define RADIO_TXPOWER_TXPOWER_Neg2dBm (0xFEUL) /*!< -2 dBm */
4169 #define RADIO_TXPOWER_TXPOWER_Neg1dBm (0xFFUL) /*!< -1 dBm */
4170 
4171 /* Register: RADIO_MODE */
4172 /* Description: Data rate and modulation */
4173 
4174 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */
4175 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
4176 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
4177 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbps Nordic proprietary radio mode */
4178 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */
4179 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */
4180 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */
4181 #define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long Range 125 kbps TX, 125 kbps and 500 kbps RX */
4182 #define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long Range 500 kbps TX, 125 kbps and 500 kbps RX */
4183 #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbps */
4184 
4185 /* Register: RADIO_PCNF0 */
4186 /* Description: Packet configuration register 0 */
4187 
4188 /* Bits 30..29 : Length of TERM field in Long Range operation */
4189 #define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */
4190 #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */
4191 
4192 /* Bit 26 : Indicates if LENGTH field contains CRC or not */
4193 #define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */
4194 #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */
4195 #define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */
4196 #define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */
4197 
4198 /* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */
4199 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
4200 #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
4201 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
4202 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
4203 #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
4204 #define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for Bluetooth LE Long Range */
4205 
4206 /* Bits 23..22 : Length of code indicator - Long Range */
4207 #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */
4208 #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */
4209 
4210 /* Bit 20 : Include or exclude S1 field in RAM */
4211 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
4212 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
4213 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
4214 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
4215 
4216 /* Bits 19..16 : Length on air of S1 field in number of bits */
4217 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
4218 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
4219 
4220 /* Bit 8 : Length on air of S0 field in number of bytes */
4221 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
4222 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
4223 
4224 /* Bits 3..0 : Length on air of LENGTH field in number of bits */
4225 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
4226 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
4227 
4228 /* Register: RADIO_PCNF1 */
4229 /* Description: Packet configuration register 1 */
4230 
4231 /* Bit 25 : Enable or disable packet whitening */
4232 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
4233 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
4234 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
4235 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
4236 
4237 /* Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */
4238 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
4239 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
4240 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
4241 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
4242 
4243 /* Bits 18..16 : Base address length in number of bytes */
4244 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
4245 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
4246 
4247 /* Bits 15..8 : Static length in number of bytes */
4248 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
4249 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
4250 
4251 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
4252 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
4253 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
4254 
4255 /* Register: RADIO_BASE0 */
4256 /* Description: Base address 0 */
4257 
4258 /* Bits 31..0 : Base address 0 */
4259 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
4260 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
4261 
4262 /* Register: RADIO_BASE1 */
4263 /* Description: Base address 1 */
4264 
4265 /* Bits 31..0 : Base address 1 */
4266 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
4267 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
4268 
4269 /* Register: RADIO_PREFIX0 */
4270 /* Description: Prefixes bytes for logical addresses 0-3 */
4271 
4272 /* Bits 31..24 : Address prefix 3. */
4273 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
4274 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
4275 
4276 /* Bits 23..16 : Address prefix 2. */
4277 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
4278 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
4279 
4280 /* Bits 15..8 : Address prefix 1. */
4281 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
4282 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
4283 
4284 /* Bits 7..0 : Address prefix 0. */
4285 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
4286 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
4287 
4288 /* Register: RADIO_PREFIX1 */
4289 /* Description: Prefixes bytes for logical addresses 4-7 */
4290 
4291 /* Bits 31..24 : Address prefix 7. */
4292 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
4293 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
4294 
4295 /* Bits 23..16 : Address prefix 6. */
4296 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
4297 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
4298 
4299 /* Bits 15..8 : Address prefix 5. */
4300 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
4301 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
4302 
4303 /* Bits 7..0 : Address prefix 4. */
4304 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
4305 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
4306 
4307 /* Register: RADIO_TXADDRESS */
4308 /* Description: Transmit address select */
4309 
4310 /* Bits 2..0 : Transmit address select */
4311 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
4312 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
4313 
4314 /* Register: RADIO_RXADDRESSES */
4315 /* Description: Receive address select */
4316 
4317 /* Bit 7 : Enable or disable reception on logical address 7. */
4318 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
4319 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
4320 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
4321 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
4322 
4323 /* Bit 6 : Enable or disable reception on logical address 6. */
4324 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
4325 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
4326 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
4327 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
4328 
4329 /* Bit 5 : Enable or disable reception on logical address 5. */
4330 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
4331 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
4332 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
4333 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
4334 
4335 /* Bit 4 : Enable or disable reception on logical address 4. */
4336 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
4337 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
4338 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
4339 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
4340 
4341 /* Bit 3 : Enable or disable reception on logical address 3. */
4342 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
4343 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
4344 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
4345 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
4346 
4347 /* Bit 2 : Enable or disable reception on logical address 2. */
4348 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
4349 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
4350 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
4351 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
4352 
4353 /* Bit 1 : Enable or disable reception on logical address 1. */
4354 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
4355 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
4356 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
4357 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
4358 
4359 /* Bit 0 : Enable or disable reception on logical address 0. */
4360 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
4361 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
4362 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
4363 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
4364 
4365 /* Register: RADIO_CRCCNF */
4366 /* Description: CRC configuration */
4367 
4368 /* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */
4369 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
4370 #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
4371 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
4372 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
4373 #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */
4374 
4375 /* Bits 1..0 : CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported */
4376 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
4377 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
4378 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
4379 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
4380 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
4381 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
4382 
4383 /* Register: RADIO_CRCPOLY */
4384 /* Description: CRC polynomial */
4385 
4386 /* Bits 23..0 : CRC polynomial */
4387 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
4388 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
4389 
4390 /* Register: RADIO_CRCINIT */
4391 /* Description: CRC initial value */
4392 
4393 /* Bits 23..0 : CRC initial value */
4394 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
4395 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
4396 
4397 /* Register: RADIO_TIFS */
4398 /* Description: Interframe spacing in us */
4399 
4400 /* Bits 9..0 : Interframe spacing in us. */
4401 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
4402 #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
4403 
4404 /* Register: RADIO_RSSISAMPLE */
4405 /* Description: RSSI sample */
4406 
4407 /* Bits 6..0 : RSSI sample. */
4408 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
4409 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
4410 
4411 /* Register: RADIO_STATE */
4412 /* Description: Current radio state */
4413 
4414 /* Bits 3..0 : Current radio state */
4415 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
4416 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
4417 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
4418 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
4419 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
4420 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
4421 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
4422 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
4423 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
4424 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
4425 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
4426 
4427 /* Register: RADIO_DATAWHITEIV */
4428 /* Description: Data whitening initial value */
4429 
4430 /* Bits 6..0 : Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
4431 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
4432 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
4433 
4434 /* Register: RADIO_BCC */
4435 /* Description: Bit counter compare */
4436 
4437 /* Bits 31..0 : Bit counter compare */
4438 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
4439 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
4440 
4441 /* Register: RADIO_DAB */
4442 /* Description: Description collection: Device address base segment n */
4443 
4444 /* Bits 31..0 : Device address base segment n */
4445 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
4446 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
4447 
4448 /* Register: RADIO_DAP */
4449 /* Description: Description collection: Device address prefix n */
4450 
4451 /* Bits 15..0 : Device address prefix n */
4452 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
4453 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
4454 
4455 /* Register: RADIO_DACNF */
4456 /* Description: Device address match configuration */
4457 
4458 /* Bit 15 : TxAdd for device address 7 */
4459 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
4460 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
4461 
4462 /* Bit 14 : TxAdd for device address 6 */
4463 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
4464 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
4465 
4466 /* Bit 13 : TxAdd for device address 5 */
4467 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
4468 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
4469 
4470 /* Bit 12 : TxAdd for device address 4 */
4471 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
4472 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
4473 
4474 /* Bit 11 : TxAdd for device address 3 */
4475 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
4476 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
4477 
4478 /* Bit 10 : TxAdd for device address 2 */
4479 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
4480 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
4481 
4482 /* Bit 9 : TxAdd for device address 1 */
4483 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
4484 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
4485 
4486 /* Bit 8 : TxAdd for device address 0 */
4487 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
4488 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
4489 
4490 /* Bit 7 : Enable or disable device address matching using device address 7 */
4491 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
4492 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
4493 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
4494 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
4495 
4496 /* Bit 6 : Enable or disable device address matching using device address 6 */
4497 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
4498 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
4499 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
4500 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
4501 
4502 /* Bit 5 : Enable or disable device address matching using device address 5 */
4503 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
4504 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
4505 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
4506 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
4507 
4508 /* Bit 4 : Enable or disable device address matching using device address 4 */
4509 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
4510 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
4511 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
4512 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
4513 
4514 /* Bit 3 : Enable or disable device address matching using device address 3 */
4515 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
4516 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
4517 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
4518 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
4519 
4520 /* Bit 2 : Enable or disable device address matching using device address 2 */
4521 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
4522 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
4523 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
4524 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
4525 
4526 /* Bit 1 : Enable or disable device address matching using device address 1 */
4527 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
4528 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
4529 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
4530 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
4531 
4532 /* Bit 0 : Enable or disable device address matching using device address 0 */
4533 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
4534 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
4535 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
4536 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
4537 
4538 /* Register: RADIO_MHRMATCHCONF */
4539 /* Description: Search pattern configuration */
4540 
4541 /* Bits 31..0 : Search pattern configuration */
4542 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */
4543 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */
4544 
4545 /* Register: RADIO_MHRMATCHMAS */
4546 /* Description: Pattern mask */
4547 
4548 /* Bits 31..0 : Pattern mask */
4549 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */
4550 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */
4551 
4552 /* Register: RADIO_MODECNF0 */
4553 /* Description: Radio mode configuration register 0 */
4554 
4555 /* Bits 9..8 : Default TX value */
4556 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
4557 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
4558 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
4559 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
4560 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
4561 
4562 /* Bit 0 : Radio ramp-up time */
4563 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
4564 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
4565 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */
4566 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */
4567 
4568 /* Register: RADIO_SFD */
4569 /* Description: IEEE 802.15.4 start of frame delimiter */
4570 
4571 /* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */
4572 #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */
4573 #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */
4574 
4575 /* Register: RADIO_EDCNT */
4576 /* Description: IEEE 802.15.4 energy detect loop count */
4577 
4578 /* Bits 20..0 : IEEE 802.15.4 energy detect loop count */
4579 #define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */
4580 #define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */
4581 
4582 /* Register: RADIO_EDSAMPLE */
4583 /* Description: IEEE 802.15.4 energy detect level */
4584 
4585 /* Bits 7..0 : IEEE 802.15.4 energy detect level */
4586 #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */
4587 #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */
4588 
4589 /* Register: RADIO_CCACTRL */
4590 /* Description: IEEE 802.15.4 clear channel assessment control */
4591 
4592 /* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */
4593 #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */
4594 #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */
4595 
4596 /* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. */
4597 #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */
4598 #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */
4599 
4600 /* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */
4601 #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */
4602 #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */
4603 
4604 /* Bits 2..0 : CCA mode of operation */
4605 #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */
4606 #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */
4607 #define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */
4608 #define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */
4609 #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */
4610 #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */
4611 #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */
4612 
4613 /* Register: RADIO_DFEMODE */
4614 /* Description: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */
4615 
4616 /* Bits 1..0 : Direction finding operation mode */
4617 #define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */
4618 #define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */
4619 #define RADIO_DFEMODE_DFEOPMODE_Disabled (0UL) /*!< Direction finding mode disabled */
4620 #define RADIO_DFEMODE_DFEOPMODE_AoD (2UL) /*!< Direction finding mode set to AoD */
4621 #define RADIO_DFEMODE_DFEOPMODE_AoA (3UL) /*!< Direction finding mode set to AoA */
4622 
4623 /* Register: RADIO_CTEINLINECONF */
4624 /* Description: Configuration for CTE inline mode */
4625 
4626 /* Bits 31..24 : S0 bit mask to set which bit to match */
4627 #define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */
4628 #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */
4629 
4630 /* Bits 23..16 : S0 bit pattern to match */
4631 #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */
4632 #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */
4633 
4634 /* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */
4635 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */
4636 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */
4637 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4 us */
4638 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2 us */
4639 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1 us */
4640 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5 us */
4641 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25 us */
4642 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125 us */
4643 
4644 /* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */
4645 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */
4646 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */
4647 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4 us */
4648 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2 us */
4649 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1 us */
4650 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5 us */
4651 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25 us */
4652 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125 us */
4653 
4654 /* Bits 7..6 : Max range of CTETime */
4655 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */
4656 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */
4657 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 */
4658 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8 us unit */
4659 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8 us unit */
4660 
4661 /* Bit 4 : Sampling/switching if CRC is not OK */
4662 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */
4663 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of CTEERRORHANDLING field. */
4664 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0UL) /*!< No sampling and antenna switching when CRC is not OK */
4665 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (1UL) /*!< Sampling and antenna switching also when CRC is not OK */
4666 
4667 /* Bit 3 : CTEInfo is S1 byte or not */
4668 #define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */
4669 #define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 field. */
4670 #define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */
4671 #define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (1UL) /*!< CTEInfo is in S1 byte (data PDU) */
4672 
4673 /* Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */
4674 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */
4675 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of CTEINLINECTRLEN field. */
4676 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0UL) /*!< Parsing of CTEInfo is disabled */
4677 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (1UL) /*!< Parsing of CTEInfo is enabled */
4678 
4679 /* Register: RADIO_DFECTRL1 */
4680 /* Description: Various configuration for Direction finding */
4681 
4682 /* Bits 27..24 : Gain will be lowered by the specified number of gain steps at the start of CTE */
4683 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */
4684 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field. */
4685 
4686 /* Bits 23..20 : Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. */
4687 #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL) /*!< Position of REPEATPATTERN field. */
4688 #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field. */
4689 #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0UL) /*!< Do not repeat (1 time in total) */
4690 
4691 /* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */
4692 #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */
4693 #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */
4694 #define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4 us */
4695 #define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2 us */
4696 #define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1 us */
4697 #define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5 us */
4698 #define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25 us */
4699 #define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125 us */
4700 
4701 /* Bit 15 : Whether to sample I/Q or magnitude/phase */
4702 #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */
4703 #define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */
4704 #define RADIO_DFECTRL1_SAMPLETYPE_IQ (0UL) /*!< Complex samples in I and Q */
4705 #define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (1UL) /*!< Complex samples as magnitude and phase */
4706 
4707 /* Bits 14..12 : Interval between samples in the REFERENCE period */
4708 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */
4709 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */
4710 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4 us */
4711 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2 us */
4712 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1 us */
4713 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5 us */
4714 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25 us */
4715 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125 us */
4716 
4717 /* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */
4718 #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */
4719 #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */
4720 #define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4 us */
4721 #define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2 us */
4722 #define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1 us */
4723 
4724 /* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */
4725 #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */
4726 #define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field. */
4727 #define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0UL) /*!< Antenna switching/sampling is done in the packet payload */
4728 #define RADIO_DFECTRL1_DFEINEXTENSION_CRC (1UL) /*!< AoA/AoD procedure triggered at end of CRC */
4729 
4730 /* Bits 5..0 : Length of the AoA/AoD procedure in number of 8 us units */
4731 #define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */
4732 #define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */
4733 
4734 /* Register: RADIO_DFECTRL2 */
4735 /* Description: Start offset for Direction finding */
4736 
4737 /* Bits 27..16 : Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period */
4738 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */
4739 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */
4740 
4741 /* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles */
4742 #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */
4743 #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */
4744 
4745 /* Register: RADIO_SWITCHPATTERN */
4746 /* Description: GPIO patterns to be used for each antenna */
4747 
4748 /* Bits 7..0 : Fill array of GPIO patterns for antenna control. */
4749 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */
4750 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */
4751 
4752 /* Register: RADIO_CLEARPATTERN */
4753 /* Description: Clear the GPIO pattern array for antenna control */
4754 
4755 /* Bit 0 : Clears GPIO pattern array for antenna control */
4756 #define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */
4757 #define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN field. */
4758 #define RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL) /*!< Clear the GPIO pattern */
4759 
4760 /* Register: RADIO_PSEL_DFEGPIO */
4761 /* Description: Description collection: Pin select for DFE pin n */
4762 
4763 /* Bit 31 : Connection */
4764 #define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
4765 #define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
4766 #define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0UL) /*!< Connect */
4767 #define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (1UL) /*!< Disconnect */
4768 
4769 /* Bit 5 : Port number */
4770 #define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL) /*!< Position of PORT field. */
4771 #define RADIO_PSEL_DFEGPIO_PORT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field. */
4772 
4773 /* Bits 4..0 : Pin number */
4774 #define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */
4775 #define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */
4776 
4777 /* Register: RADIO_DFEPACKET_PTR */
4778 /* Description: Data pointer */
4779 
4780 /* Bits 31..0 : Data pointer */
4781 #define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
4782 #define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
4783 
4784 /* Register: RADIO_DFEPACKET_MAXCNT */
4785 /* Description: Maximum number of buffer words to transfer */
4786 
4787 /* Bits 13..0 : Maximum number of buffer words to transfer */
4788 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
4789 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0x3FFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
4790 
4791 /* Register: RADIO_DFEPACKET_AMOUNT */
4792 /* Description: Number of samples transferred in the last transaction */
4793 
4794 /* Bits 15..0 : Number of samples transferred in the last transaction */
4795 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
4796 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
4797 
4798 /* Register: RADIO_POWER */
4799 /* Description: Peripheral power control */
4800 
4801 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
4802 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
4803 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
4804 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
4805 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
4806 
4807 
4808 
4809 /* =========================================================================================================================== */
4810 /* ================                                          RNG_NS                                           ================ */
4811 /* =========================================================================================================================== */
4812 
4813 
4814 /**
4815   * @brief Random Number Generator (RNG_NS)
4816   */
4817 
4818 typedef struct {                                /*!< (@ 0x41009000) RNG_NS Structure                                           */
4819   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000000) Task starting the random number generator                  */
4820   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000004) Task stopping the random number generator                  */
4821   __IM  uint32_t  RESERVED[30];
4822   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000080) Subscribe configuration for task START                     */
4823   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000084) Subscribe configuration for task STOP                      */
4824   __IM  uint32_t  RESERVED1[30];
4825   __IOM uint32_t  EVENTS_VALRDY;                /*!< (@ 0x00000100) Event being generated for every new random number
4826                                                                     written to the VALUE register                              */
4827   __IM  uint32_t  RESERVED2[31];
4828   __IOM uint32_t  PUBLISH_VALRDY;               /*!< (@ 0x00000180) Publish configuration for event VALRDY                     */
4829   __IM  uint32_t  RESERVED3[31];
4830   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
4831   __IM  uint32_t  RESERVED4[64];
4832   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
4833   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
4834   __IM  uint32_t  RESERVED5[126];
4835   __IOM uint32_t  CONFIG;                       /*!< (@ 0x00000504) Configuration register                                     */
4836   __IM  uint32_t  VALUE;                        /*!< (@ 0x00000508) Output random number                                       */
4837 } NRF_RNG_Type;                                 /*!< Size = 1292 (0x50c)                                                       */
4838 
4839 
4840 /* Peripheral: RNG */
4841 /* Description: Random Number Generator */
4842 
4843 /* Register: RNG_TASKS_START */
4844 /* Description: Task starting the random number generator */
4845 
4846 /* Bit 0 : Task starting the random number generator */
4847 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
4848 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
4849 #define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
4850 
4851 /* Register: RNG_TASKS_STOP */
4852 /* Description: Task stopping the random number generator */
4853 
4854 /* Bit 0 : Task stopping the random number generator */
4855 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
4856 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
4857 #define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
4858 
4859 /* Register: RNG_SUBSCRIBE_START */
4860 /* Description: Subscribe configuration for task START */
4861 
4862 /* Bit 31 :   */
4863 #define RNG_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
4864 #define RNG_SUBSCRIBE_START_EN_Msk (0x1UL << RNG_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
4865 #define RNG_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
4866 #define RNG_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
4867 
4868 /* Bits 7..0 : DPPI channel that task START will subscribe to */
4869 #define RNG_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4870 #define RNG_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4871 
4872 /* Register: RNG_SUBSCRIBE_STOP */
4873 /* Description: Subscribe configuration for task STOP */
4874 
4875 /* Bit 31 :   */
4876 #define RNG_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
4877 #define RNG_SUBSCRIBE_STOP_EN_Msk (0x1UL << RNG_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
4878 #define RNG_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
4879 #define RNG_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
4880 
4881 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
4882 #define RNG_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4883 #define RNG_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4884 
4885 /* Register: RNG_EVENTS_VALRDY */
4886 /* Description: Event being generated for every new random number written to the VALUE register */
4887 
4888 /* Bit 0 : Event being generated for every new random number written to the VALUE register */
4889 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */
4890 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */
4891 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */
4892 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */
4893 
4894 /* Register: RNG_PUBLISH_VALRDY */
4895 /* Description: Publish configuration for event VALRDY */
4896 
4897 /* Bit 31 :   */
4898 #define RNG_PUBLISH_VALRDY_EN_Pos (31UL) /*!< Position of EN field. */
4899 #define RNG_PUBLISH_VALRDY_EN_Msk (0x1UL << RNG_PUBLISH_VALRDY_EN_Pos) /*!< Bit mask of EN field. */
4900 #define RNG_PUBLISH_VALRDY_EN_Disabled (0UL) /*!< Disable publishing */
4901 #define RNG_PUBLISH_VALRDY_EN_Enabled (1UL) /*!< Enable publishing */
4902 
4903 /* Bits 7..0 : DPPI channel that event VALRDY will publish to. */
4904 #define RNG_PUBLISH_VALRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
4905 #define RNG_PUBLISH_VALRDY_CHIDX_Msk (0xFFUL << RNG_PUBLISH_VALRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
4906 
4907 /* Register: RNG_SHORTS */
4908 /* Description: Shortcuts between local events and tasks */
4909 
4910 /* Bit 0 : Shortcut between event VALRDY and task STOP */
4911 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
4912 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
4913 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
4914 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
4915 
4916 /* Register: RNG_INTENSET */
4917 /* Description: Enable interrupt */
4918 
4919 /* Bit 0 : Write '1' to enable interrupt for event VALRDY */
4920 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
4921 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
4922 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
4923 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
4924 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
4925 
4926 /* Register: RNG_INTENCLR */
4927 /* Description: Disable interrupt */
4928 
4929 /* Bit 0 : Write '1' to disable interrupt for event VALRDY */
4930 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
4931 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
4932 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
4933 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
4934 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
4935 
4936 /* Register: RNG_CONFIG */
4937 /* Description: Configuration register */
4938 
4939 /* Bit 0 : Bias correction */
4940 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
4941 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
4942 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
4943 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
4944 
4945 /* Register: RNG_VALUE */
4946 /* Description: Output random number */
4947 
4948 /* Bits 7..0 : Generated random number */
4949 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
4950 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
4951 
4952 /* =========================================================================================================================== */
4953 /* ================                                          RTC                                              ================ */
4954 /* =========================================================================================================================== */
4955 
4956 
4957 /**
4958   * @brief Real-time counter 0 (RTC0_NS)
4959   */
4960 
4961 typedef struct {                                /*!< (@ 0x41011000) RTC0_NS Structure                                          */
4962   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000000) Start RTC counter                                          */
4963   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000004) Stop RTC counter                                           */
4964   __OM  uint32_t  TASKS_CLEAR;                  /*!< (@ 0x00000008) Clear RTC counter                                          */
4965   __OM  uint32_t  TASKS_TRIGOVRFLW;             /*!< (@ 0x0000000C) Set counter to 0xFFFFF0                                    */
4966   __IM  uint32_t  RESERVED[12];
4967   __OM  uint32_t  TASKS_CAPTURE[4];             /*!< (@ 0x00000040) Description collection: Capture RTC counter to
4968                                                                     CC[n] register                                             */
4969   __IM  uint32_t  RESERVED1[12];
4970   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000080) Subscribe configuration for task START                     */
4971   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000084) Subscribe configuration for task STOP                      */
4972   __IOM uint32_t  SUBSCRIBE_CLEAR;              /*!< (@ 0x00000088) Subscribe configuration for task CLEAR                     */
4973   __IOM uint32_t  SUBSCRIBE_TRIGOVRFLW;         /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW                */
4974   __IM  uint32_t  RESERVED2[12];
4975   __IOM uint32_t  SUBSCRIBE_CAPTURE[4];         /*!< (@ 0x000000C0) Description collection: Subscribe configuration
4976                                                                     for task CAPTURE[n]                                        */
4977   __IM  uint32_t  RESERVED3[12];
4978   __IOM uint32_t  EVENTS_TICK;                  /*!< (@ 0x00000100) Event on counter increment                                 */
4979   __IOM uint32_t  EVENTS_OVRFLW;                /*!< (@ 0x00000104) Event on counter overflow                                  */
4980   __IM  uint32_t  RESERVED4[14];
4981   __IOM uint32_t  EVENTS_COMPARE[4];            /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
4982                                                                     match                                                      */
4983   __IM  uint32_t  RESERVED5[12];
4984   __IOM uint32_t  PUBLISH_TICK;                 /*!< (@ 0x00000180) Publish configuration for event TICK                       */
4985   __IOM uint32_t  PUBLISH_OVRFLW;               /*!< (@ 0x00000184) Publish configuration for event OVRFLW                     */
4986   __IM  uint32_t  RESERVED6[14];
4987   __IOM uint32_t  PUBLISH_COMPARE[4];           /*!< (@ 0x000001C0) Description collection: Publish configuration
4988                                                                     for event COMPARE[n]                                       */
4989   __IM  uint32_t  RESERVED7[12];
4990   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
4991   __IM  uint32_t  RESERVED8[64];
4992   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
4993   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
4994   __IM  uint32_t  RESERVED9[13];
4995   __IOM uint32_t  EVTEN;                        /*!< (@ 0x00000340) Enable or disable event routing                            */
4996   __IOM uint32_t  EVTENSET;                     /*!< (@ 0x00000344) Enable event routing                                       */
4997   __IOM uint32_t  EVTENCLR;                     /*!< (@ 0x00000348) Disable event routing                                      */
4998   __IM  uint32_t  RESERVED10[110];
4999   __IM  uint32_t  COUNTER;                      /*!< (@ 0x00000504) Current counter value                                      */
5000   __IOM uint32_t  PRESCALER;                    /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768
5001                                                                     / (PRESCALER + 1)). Must be written when
5002                                                                     RTC is stopped.                                            */
5003   __IM  uint32_t  RESERVED11[13];
5004   __IOM uint32_t  CC[4];                        /*!< (@ 0x00000540) Description collection: Compare register n                 */
5005 } NRF_RTC_Type;                                 /*!< Size = 1360 (0x550)                                                       */
5006 
5007 
5008 /* Peripheral: RTC */
5009 /* Description: Real-time counter 0 */
5010 
5011 /* Register: RTC_TASKS_START */
5012 /* Description: Start RTC counter */
5013 
5014 /* Bit 0 : Start RTC counter */
5015 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
5016 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
5017 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5018 
5019 /* Register: RTC_TASKS_STOP */
5020 /* Description: Stop RTC counter */
5021 
5022 /* Bit 0 : Stop RTC counter */
5023 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5024 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5025 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5026 
5027 /* Register: RTC_TASKS_CLEAR */
5028 /* Description: Clear RTC counter */
5029 
5030 /* Bit 0 : Clear RTC counter */
5031 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
5032 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
5033 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
5034 
5035 /* Register: RTC_TASKS_TRIGOVRFLW */
5036 /* Description: Set counter to 0xFFFFF0 */
5037 
5038 /* Bit 0 : Set counter to 0xFFFFF0 */
5039 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */
5040 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */
5041 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */
5042 
5043 /* Register: RTC_TASKS_CAPTURE */
5044 /* Description: Description collection: Capture RTC counter to CC[n] register */
5045 
5046 /* Bit 0 : Capture RTC counter to CC[n] register */
5047 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
5048 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
5049 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
5050 
5051 /* Register: RTC_SUBSCRIBE_START */
5052 /* Description: Subscribe configuration for task START */
5053 
5054 /* Bit 31 :   */
5055 #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
5056 #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
5057 #define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
5058 #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5059 
5060 /* Bits 7..0 : DPPI channel that task START will subscribe to */
5061 #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5062 #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5063 
5064 /* Register: RTC_SUBSCRIBE_STOP */
5065 /* Description: Subscribe configuration for task STOP */
5066 
5067 /* Bit 31 :   */
5068 #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
5069 #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
5070 #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
5071 #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5072 
5073 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
5074 #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5075 #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5076 
5077 /* Register: RTC_SUBSCRIBE_CLEAR */
5078 /* Description: Subscribe configuration for task CLEAR */
5079 
5080 /* Bit 31 :   */
5081 #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
5082 #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
5083 #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
5084 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
5085 
5086 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
5087 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5088 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5089 
5090 /* Register: RTC_SUBSCRIBE_TRIGOVRFLW */
5091 /* Description: Subscribe configuration for task TRIGOVRFLW */
5092 
5093 /* Bit 31 :   */
5094 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
5095 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */
5096 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */
5097 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */
5098 
5099 /* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */
5100 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5101 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5102 
5103 /* Register: RTC_SUBSCRIBE_CAPTURE */
5104 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */
5105 
5106 /* Bit 31 :   */
5107 #define RTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
5108 #define RTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << RTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
5109 #define RTC_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */
5110 #define RTC_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
5111 
5112 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
5113 #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5114 #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5115 
5116 /* Register: RTC_EVENTS_TICK */
5117 /* Description: Event on counter increment */
5118 
5119 /* Bit 0 : Event on counter increment */
5120 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */
5121 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */
5122 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */
5123 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */
5124 
5125 /* Register: RTC_EVENTS_OVRFLW */
5126 /* Description: Event on counter overflow */
5127 
5128 /* Bit 0 : Event on counter overflow */
5129 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */
5130 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */
5131 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */
5132 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */
5133 
5134 /* Register: RTC_EVENTS_COMPARE */
5135 /* Description: Description collection: Compare event on CC[n] match */
5136 
5137 /* Bit 0 : Compare event on CC[n] match */
5138 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
5139 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
5140 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
5141 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
5142 
5143 /* Register: RTC_PUBLISH_TICK */
5144 /* Description: Publish configuration for event TICK */
5145 
5146 /* Bit 31 :   */
5147 #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */
5148 #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */
5149 #define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */
5150 #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */
5151 
5152 /* Bits 7..0 : DPPI channel that event TICK will publish to. */
5153 #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5154 #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5155 
5156 /* Register: RTC_PUBLISH_OVRFLW */
5157 /* Description: Publish configuration for event OVRFLW */
5158 
5159 /* Bit 31 :   */
5160 #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */
5161 #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */
5162 #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */
5163 #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */
5164 
5165 /* Bits 7..0 : DPPI channel that event OVRFLW will publish to. */
5166 #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5167 #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5168 
5169 /* Register: RTC_PUBLISH_COMPARE */
5170 /* Description: Description collection: Publish configuration for event COMPARE[n] */
5171 
5172 /* Bit 31 :   */
5173 #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
5174 #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
5175 #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
5176 #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
5177 
5178 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */
5179 #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5180 #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5181 
5182 /* Register: RTC_SHORTS */
5183 /* Description: Shortcuts between local events and tasks */
5184 
5185 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */
5186 #define RTC_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
5187 #define RTC_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
5188 #define RTC_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
5189 #define RTC_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
5190 
5191 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
5192 #define RTC_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
5193 #define RTC_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
5194 #define RTC_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
5195 #define RTC_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
5196 
5197 /* Register: RTC_INTENSET */
5198 /* Description: Enable interrupt */
5199 
5200 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */
5201 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5202 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5203 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5204 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5205 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
5206 
5207 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
5208 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5209 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5210 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5211 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5212 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
5213 
5214 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */
5215 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5216 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5217 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5218 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5219 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
5220 
5221 /* Bit 0 : Write '1' to enable interrupt for event TICK */
5222 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
5223 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
5224 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
5225 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5226 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
5227 
5228 /* Register: RTC_INTENCLR */
5229 /* Description: Disable interrupt */
5230 
5231 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */
5232 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5233 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5234 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5235 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5236 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
5237 
5238 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
5239 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5240 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5241 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5242 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5243 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
5244 
5245 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */
5246 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5247 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5248 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5249 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5250 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
5251 
5252 /* Bit 0 : Write '1' to disable interrupt for event TICK */
5253 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
5254 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
5255 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
5256 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
5257 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
5258 
5259 /* Register: RTC_EVTEN */
5260 /* Description: Enable or disable event routing */
5261 
5262 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */
5263 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5264 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5265 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
5266 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
5267 
5268 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */
5269 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5270 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5271 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
5272 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
5273 
5274 /* Bit 1 : Enable or disable event routing for event OVRFLW */
5275 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5276 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5277 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
5278 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
5279 
5280 /* Bit 0 : Enable or disable event routing for event TICK */
5281 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
5282 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
5283 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
5284 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
5285 
5286 /* Register: RTC_EVTENSET */
5287 /* Description: Enable event routing */
5288 
5289 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */
5290 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5291 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5292 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5293 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5294 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
5295 
5296 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */
5297 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5298 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5299 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5300 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5301 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
5302 
5303 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */
5304 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5305 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5306 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5307 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5308 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
5309 
5310 /* Bit 0 : Write '1' to enable event routing for event TICK */
5311 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
5312 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
5313 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
5314 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
5315 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
5316 
5317 /* Register: RTC_EVTENCLR */
5318 /* Description: Disable event routing */
5319 
5320 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */
5321 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
5322 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
5323 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5324 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
5325 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
5326 
5327 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */
5328 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5329 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5330 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5331 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5332 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
5333 
5334 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */
5335 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
5336 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
5337 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5338 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
5339 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
5340 
5341 /* Bit 0 : Write '1' to disable event routing for event TICK */
5342 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
5343 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
5344 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
5345 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
5346 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
5347 
5348 /* Register: RTC_COUNTER */
5349 /* Description: Current counter value */
5350 
5351 /* Bits 23..0 : Counter value */
5352 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
5353 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
5354 
5355 /* Register: RTC_PRESCALER */
5356 /* Description: 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. */
5357 
5358 /* Bits 11..0 : Prescaler value */
5359 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
5360 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
5361 
5362 /* Register: RTC_CC */
5363 /* Description: Description collection: Compare register n */
5364 
5365 /* Bits 23..0 : Compare value */
5366 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
5367 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
5368 
5369 
5370 /* =========================================================================================================================== */
5371 /* ================                                           SPU_S                                           ================ */
5372 /* =========================================================================================================================== */
5373 
5374 
5375 /**
5376   * @brief System protection unit (SPU_S)
5377   */
5378 
5379 typedef struct {                                /*!< (@ 0x50003000) SPU_S Structure                                            */
5380   __IM  uint32_t  RESERVED[64];
5381   __IOM uint32_t  EVENTS_RAMACCERR;             /*!< (@ 0x00000100) A security violation has been detected for the
5382                                                                     RAM memory space                                           */
5383   __IOM uint32_t  EVENTS_FLASHACCERR;           /*!< (@ 0x00000104) A security violation has been detected for the
5384                                                                     flash memory space                                         */
5385   __IOM uint32_t  EVENTS_PERIPHACCERR;          /*!< (@ 0x00000108) A security violation has been detected on one
5386                                                                     or several peripherals                                     */
5387   __IM  uint32_t  RESERVED1[29];
5388   __IOM uint32_t  PUBLISH_RAMACCERR;            /*!< (@ 0x00000180) Publish configuration for event RAMACCERR                  */
5389   __IOM uint32_t  PUBLISH_FLASHACCERR;          /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR                */
5390   __IOM uint32_t  PUBLISH_PERIPHACCERR;         /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR               */
5391   __IM  uint32_t  RESERVED2[93];
5392   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
5393   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
5394   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
5395   __IM  uint32_t  RESERVED3[61];
5396   __IM  uint32_t  CAP;                          /*!< (@ 0x00000400) Show implemented features for the current device           */
5397   __IOM uint32_t  CPULOCK;                      /*!< (@ 0x00000404) Configure bits to lock down CPU features at runtime        */
5398   __IM  uint32_t  RESERVED4[14];
5399   __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1];        /*!< (@ 0x00000440) Unspecified                                                */
5400   __IM  uint32_t  RESERVED5[15];
5401   __IOM SPU_DPPI_Type DPPI[1];                  /*!< (@ 0x00000480) Unspecified                                                */
5402   __IM  uint32_t  RESERVED6[14];
5403   __IOM SPU_GPIOPORT_Type GPIOPORT[2];          /*!< (@ 0x000004C0) Unspecified                                                */
5404   __IM  uint32_t  RESERVED7[12];
5405   __IOM SPU_FLASHNSC_Type FLASHNSC[2];          /*!< (@ 0x00000500) Unspecified                                                */
5406   __IM  uint32_t  RESERVED8[12];
5407   __IOM SPU_RAMNSC_Type RAMNSC[2];              /*!< (@ 0x00000540) Unspecified                                                */
5408   __IM  uint32_t  RESERVED9[44];
5409   __IOM SPU_FLASHREGION_Type FLASHREGION[64];   /*!< (@ 0x00000600) Unspecified                                                */
5410   __IOM SPU_RAMREGION_Type RAMREGION[64];       /*!< (@ 0x00000700) Unspecified                                                */
5411   __IOM SPU_PERIPHID_Type PERIPHID[256];        /*!< (@ 0x00000800) Unspecified                                                */
5412 } NRF_SPU_Type;                                 /*!< Size = 3072 (0xc00)                                                       */
5413 
5414 
5415 /* =========================================================================================================================== */
5416 /* ================                                          TEMP                                             ================ */
5417 /* =========================================================================================================================== */
5418 
5419 
5420 /**
5421   * @brief Temperature Sensor (TEMP)
5422   */
5423 
5424 typedef struct {                                /*!< (@ 0x41010000) TEMP_NS Structure                                          */
5425   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000000) Start temperature measurement                              */
5426   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000004) Stop temperature measurement                               */
5427   __IM  uint32_t  RESERVED[30];
5428   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000080) Subscribe configuration for task START                     */
5429   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000084) Subscribe configuration for task STOP                      */
5430   __IM  uint32_t  RESERVED1[30];
5431   __IOM uint32_t  EVENTS_DATARDY;               /*!< (@ 0x00000100) Temperature measurement complete, data ready               */
5432   __IM  uint32_t  RESERVED2[31];
5433   __IOM uint32_t  PUBLISH_DATARDY;              /*!< (@ 0x00000180) Publish configuration for event DATARDY                    */
5434   __IM  uint32_t  RESERVED3[96];
5435   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
5436   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
5437   __IM  uint32_t  RESERVED4[127];
5438   __IM  int32_t   TEMP;                         /*!< (@ 0x00000508) Temperature in degC (0.25deg steps)                        */
5439   __IM  uint32_t  RESERVED5[5];
5440   __IOM uint32_t  A0;                           /*!< (@ 0x00000520) Slope of first piecewise linear function                   */
5441   __IOM uint32_t  A1;                           /*!< (@ 0x00000524) Slope of second piecewise linear function                  */
5442   __IOM uint32_t  A2;                           /*!< (@ 0x00000528) Slope of third piecewise linear function                   */
5443   __IOM uint32_t  A3;                           /*!< (@ 0x0000052C) Slope of fourth piecewise linear function                  */
5444   __IOM uint32_t  A4;                           /*!< (@ 0x00000530) Slope of fifth piecewise linear function                   */
5445   __IOM uint32_t  A5;                           /*!< (@ 0x00000534) Slope of sixth piecewise linear function                   */
5446   __IM  uint32_t  RESERVED6[2];
5447   __IOM uint32_t  B0;                           /*!< (@ 0x00000540) y-intercept of first piecewise linear function             */
5448   __IOM uint32_t  B1;                           /*!< (@ 0x00000544) y-intercept of second piecewise linear function            */
5449   __IOM uint32_t  B2;                           /*!< (@ 0x00000548) y-intercept of third piecewise linear function             */
5450   __IOM uint32_t  B3;                           /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function            */
5451   __IOM uint32_t  B4;                           /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function             */
5452   __IOM uint32_t  B5;                           /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function             */
5453   __IM  uint32_t  RESERVED7[2];
5454   __IOM uint32_t  T0;                           /*!< (@ 0x00000560) Endpoint of first piecewise linear function                */
5455   __IOM uint32_t  T1;                           /*!< (@ 0x00000564) Endpoint of second piecewise linear function               */
5456   __IOM uint32_t  T2;                           /*!< (@ 0x00000568) Endpoint of third piecewise linear function                */
5457   __IOM uint32_t  T3;                           /*!< (@ 0x0000056C) Endpoint of fourth piecewise linear function               */
5458   __IOM uint32_t  T4;                           /*!< (@ 0x00000570) Endpoint of fifth piecewise linear function                */
5459 } NRF_TEMP_Type;                                /*!< Size = 1396 (0x574)                                                       */
5460 
5461 
5462 /* Peripheral: TEMP */
5463 /* Description: Temperature Sensor */
5464 
5465 /* Register: TEMP_TASKS_START */
5466 /* Description: Start temperature measurement */
5467 
5468 /* Bit 0 : Start temperature measurement */
5469 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
5470 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
5471 #define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5472 
5473 /* Register: TEMP_TASKS_STOP */
5474 /* Description: Stop temperature measurement */
5475 
5476 /* Bit 0 : Stop temperature measurement */
5477 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5478 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5479 #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5480 
5481 /* Register: TEMP_SUBSCRIBE_START */
5482 /* Description: Subscribe configuration for task START */
5483 
5484 /* Bit 31 :   */
5485 #define TEMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
5486 #define TEMP_SUBSCRIBE_START_EN_Msk (0x1UL << TEMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
5487 #define TEMP_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
5488 #define TEMP_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5489 
5490 /* Bits 7..0 : DPPI channel that task START will subscribe to */
5491 #define TEMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5492 #define TEMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5493 
5494 /* Register: TEMP_SUBSCRIBE_STOP */
5495 /* Description: Subscribe configuration for task STOP */
5496 
5497 /* Bit 31 :   */
5498 #define TEMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
5499 #define TEMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << TEMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
5500 #define TEMP_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
5501 #define TEMP_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5502 
5503 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
5504 #define TEMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5505 #define TEMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5506 
5507 /* Register: TEMP_EVENTS_DATARDY */
5508 /* Description: Temperature measurement complete, data ready */
5509 
5510 /* Bit 0 : Temperature measurement complete, data ready */
5511 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */
5512 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */
5513 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */
5514 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */
5515 
5516 /* Register: TEMP_PUBLISH_DATARDY */
5517 /* Description: Publish configuration for event DATARDY */
5518 
5519 /* Bit 31 :   */
5520 #define TEMP_PUBLISH_DATARDY_EN_Pos (31UL) /*!< Position of EN field. */
5521 #define TEMP_PUBLISH_DATARDY_EN_Msk (0x1UL << TEMP_PUBLISH_DATARDY_EN_Pos) /*!< Bit mask of EN field. */
5522 #define TEMP_PUBLISH_DATARDY_EN_Disabled (0UL) /*!< Disable publishing */
5523 #define TEMP_PUBLISH_DATARDY_EN_Enabled (1UL) /*!< Enable publishing */
5524 
5525 /* Bits 7..0 : DPPI channel that event DATARDY will publish to. */
5526 #define TEMP_PUBLISH_DATARDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5527 #define TEMP_PUBLISH_DATARDY_CHIDX_Msk (0xFFUL << TEMP_PUBLISH_DATARDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5528 
5529 /* Register: TEMP_INTENSET */
5530 /* Description: Enable interrupt */
5531 
5532 /* Bit 0 : Write '1' to enable interrupt for event DATARDY */
5533 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
5534 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
5535 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
5536 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
5537 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
5538 
5539 /* Register: TEMP_INTENCLR */
5540 /* Description: Disable interrupt */
5541 
5542 /* Bit 0 : Write '1' to disable interrupt for event DATARDY */
5543 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
5544 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
5545 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
5546 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
5547 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
5548 
5549 /* Register: TEMP_TEMP */
5550 /* Description: Temperature in degC (0.25deg steps) */
5551 
5552 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
5553 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
5554 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
5555 
5556 /* Register: TEMP_A0 */
5557 /* Description: Slope of first piecewise linear function */
5558 
5559 /* Bits 11..0 : Slope of first piecewise linear function */
5560 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
5561 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
5562 
5563 /* Register: TEMP_A1 */
5564 /* Description: Slope of second piecewise linear function */
5565 
5566 /* Bits 11..0 : Slope of second piecewise linear function */
5567 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
5568 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
5569 
5570 /* Register: TEMP_A2 */
5571 /* Description: Slope of third piecewise linear function */
5572 
5573 /* Bits 11..0 : Slope of third piecewise linear function */
5574 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
5575 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
5576 
5577 /* Register: TEMP_A3 */
5578 /* Description: Slope of fourth piecewise linear function */
5579 
5580 /* Bits 11..0 : Slope of fourth piecewise linear function */
5581 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
5582 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
5583 
5584 /* Register: TEMP_A4 */
5585 /* Description: Slope of fifth piecewise linear function */
5586 
5587 /* Bits 11..0 : Slope of fifth piecewise linear function */
5588 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
5589 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
5590 
5591 /* Register: TEMP_A5 */
5592 /* Description: Slope of sixth piecewise linear function */
5593 
5594 /* Bits 11..0 : Slope of sixth piecewise linear function */
5595 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
5596 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
5597 
5598 /* Register: TEMP_B0 */
5599 /* Description: y-intercept of first piecewise linear function */
5600 
5601 /* Bits 11..0 : y-intercept of first piecewise linear function */
5602 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
5603 #define TEMP_B0_B0_Msk (0xFFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
5604 
5605 /* Register: TEMP_B1 */
5606 /* Description: y-intercept of second piecewise linear function */
5607 
5608 /* Bits 11..0 : y-intercept of second piecewise linear function */
5609 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
5610 #define TEMP_B1_B1_Msk (0xFFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
5611 
5612 /* Register: TEMP_B2 */
5613 /* Description: y-intercept of third piecewise linear function */
5614 
5615 /* Bits 11..0 : y-intercept of third piecewise linear function */
5616 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
5617 #define TEMP_B2_B2_Msk (0xFFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
5618 
5619 /* Register: TEMP_B3 */
5620 /* Description: y-intercept of fourth piecewise linear function */
5621 
5622 /* Bits 11..0 : y-intercept of fourth piecewise linear function */
5623 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
5624 #define TEMP_B3_B3_Msk (0xFFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
5625 
5626 /* Register: TEMP_B4 */
5627 /* Description: y-intercept of fifth piecewise linear function */
5628 
5629 /* Bits 11..0 : y-intercept of fifth piecewise linear function */
5630 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
5631 #define TEMP_B4_B4_Msk (0xFFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
5632 
5633 /* Register: TEMP_B5 */
5634 /* Description: y-intercept of sixth piecewise linear function */
5635 
5636 /* Bits 11..0 : y-intercept of sixth piecewise linear function */
5637 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
5638 #define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
5639 
5640 /* Register: TEMP_T0 */
5641 /* Description: Endpoint of first piecewise linear function */
5642 
5643 /* Bits 7..0 : Endpoint of first piecewise linear function */
5644 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
5645 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
5646 
5647 /* Register: TEMP_T1 */
5648 /* Description: Endpoint of second piecewise linear function */
5649 
5650 /* Bits 7..0 : Endpoint of second piecewise linear function */
5651 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
5652 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
5653 
5654 /* Register: TEMP_T2 */
5655 /* Description: Endpoint of third piecewise linear function */
5656 
5657 /* Bits 7..0 : Endpoint of third piecewise linear function */
5658 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
5659 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
5660 
5661 /* Register: TEMP_T3 */
5662 /* Description: Endpoint of fourth piecewise linear function */
5663 
5664 /* Bits 7..0 : Endpoint of fourth piecewise linear function */
5665 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
5666 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
5667 
5668 /* Register: TEMP_T4 */
5669 /* Description: Endpoint of fifth piecewise linear function */
5670 
5671 /* Bits 7..0 : Endpoint of fifth piecewise linear function */
5672 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
5673 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
5674 
5675 
5676 
5677 /* =========================================================================================================================== */
5678 /* ================                                         TIMER                                             ================ */
5679 /* =========================================================================================================================== */
5680 
5681 
5682 /**
5683   * @brief Timer/Counter 0 (TIMER0_NS)
5684   */
5685 
5686 typedef struct {                                /*!< (@ 0x4100C000) TIMER0_NS Structure                                        */
5687   __OM  uint32_t  TASKS_START;                  /*!< (@ 0x00000000) Start Timer                                                */
5688   __OM  uint32_t  TASKS_STOP;                   /*!< (@ 0x00000004) Stop Timer                                                 */
5689   __OM  uint32_t  TASKS_COUNT;                  /*!< (@ 0x00000008) Increment Timer (Counter mode only)                        */
5690   __OM  uint32_t  TASKS_CLEAR;                  /*!< (@ 0x0000000C) Clear time                                                 */
5691   __OM  uint32_t  TASKS_SHUTDOWN;               /*!< (@ 0x00000010) Deprecated register - Shut down timer                      */
5692   __IM  uint32_t  RESERVED[11];
5693   __OM  uint32_t  TASKS_CAPTURE[8];             /*!< (@ 0x00000040) Description collection: Capture Timer value to
5694                                                                     CC[n] register                                             */
5695   __IM  uint32_t  RESERVED1[8];
5696   __IOM uint32_t  SUBSCRIBE_START;              /*!< (@ 0x00000080) Subscribe configuration for task START                     */
5697   __IOM uint32_t  SUBSCRIBE_STOP;               /*!< (@ 0x00000084) Subscribe configuration for task STOP                      */
5698   __IOM uint32_t  SUBSCRIBE_COUNT;              /*!< (@ 0x00000088) Subscribe configuration for task COUNT                     */
5699   __IOM uint32_t  SUBSCRIBE_CLEAR;              /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR                     */
5700   __IOM uint32_t  SUBSCRIBE_SHUTDOWN;           /*!< (@ 0x00000090) Deprecated register - Subscribe configuration
5701                                                                     for task SHUTDOWN                                          */
5702   __IM  uint32_t  RESERVED2[11];
5703   __IOM uint32_t  SUBSCRIBE_CAPTURE[8];         /*!< (@ 0x000000C0) Description collection: Subscribe configuration
5704                                                                     for task CAPTURE[n]                                        */
5705   __IM  uint32_t  RESERVED3[24];
5706   __IOM uint32_t  EVENTS_COMPARE[8];            /*!< (@ 0x00000140) Description collection: Compare event on CC[n]
5707                                                                     match                                                      */
5708   __IM  uint32_t  RESERVED4[24];
5709   __IOM uint32_t  PUBLISH_COMPARE[8];           /*!< (@ 0x000001C0) Description collection: Publish configuration
5710                                                                     for event COMPARE[n]                                       */
5711   __IM  uint32_t  RESERVED5[8];
5712   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
5713   __IM  uint32_t  RESERVED6[63];
5714   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
5715   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
5716   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
5717   __IM  uint32_t  RESERVED7[126];
5718   __IOM uint32_t  MODE;                         /*!< (@ 0x00000504) Timer mode selection                                       */
5719   __IOM uint32_t  BITMODE;                      /*!< (@ 0x00000508) Configure the number of bits used by the TIMER             */
5720   __IM  uint32_t  RESERVED8;
5721   __IOM uint32_t  PRESCALER;                    /*!< (@ 0x00000510) Timer prescaler register                                   */
5722   __IM  uint32_t  RESERVED9[11];
5723   __IOM uint32_t  CC[8];                        /*!< (@ 0x00000540) Description collection: Capture/Compare register
5724                                                                     n                                                          */
5725   __IM  uint32_t  RESERVED10[8];
5726   __IOM uint32_t  ONESHOTEN[8];                 /*!< (@ 0x00000580) Description collection: Enable one-shot operation
5727                                                                     for Capture/Compare channel n                              */
5728 } NRF_TIMER_Type;                               /*!< Size = 1440 (0x5a0)                                                       */
5729 
5730 
5731 /* Peripheral: TIMER */
5732 /* Description: Timer/Counter 0 */
5733 
5734 /* Register: TIMER_TASKS_START */
5735 /* Description: Start Timer */
5736 
5737 /* Bit 0 : Start Timer */
5738 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */
5739 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */
5740 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */
5741 
5742 /* Register: TIMER_TASKS_STOP */
5743 /* Description: Stop Timer */
5744 
5745 /* Bit 0 : Stop Timer */
5746 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */
5747 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */
5748 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */
5749 
5750 /* Register: TIMER_TASKS_COUNT */
5751 /* Description: Increment Timer (Counter mode only) */
5752 
5753 /* Bit 0 : Increment Timer (Counter mode only) */
5754 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */
5755 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */
5756 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */
5757 
5758 /* Register: TIMER_TASKS_CLEAR */
5759 /* Description: Clear time */
5760 
5761 /* Bit 0 : Clear time */
5762 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */
5763 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */
5764 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */
5765 
5766 /* Register: TIMER_TASKS_SHUTDOWN */
5767 /* Description: Deprecated register - Shut down timer */
5768 
5769 /* Bit 0 : Deprecated field -  Shut down timer */
5770 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */
5771 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */
5772 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */
5773 
5774 /* Register: TIMER_TASKS_CAPTURE */
5775 /* Description: Description collection: Capture Timer value to CC[n] register */
5776 
5777 /* Bit 0 : Capture Timer value to CC[n] register */
5778 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */
5779 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */
5780 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */
5781 
5782 /* Register: TIMER_SUBSCRIBE_START */
5783 /* Description: Subscribe configuration for task START */
5784 
5785 /* Bit 31 :   */
5786 #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */
5787 #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */
5788 #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */
5789 #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */
5790 
5791 /* Bits 7..0 : DPPI channel that task START will subscribe to */
5792 #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5793 #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5794 
5795 /* Register: TIMER_SUBSCRIBE_STOP */
5796 /* Description: Subscribe configuration for task STOP */
5797 
5798 /* Bit 31 :   */
5799 #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */
5800 #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */
5801 #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */
5802 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */
5803 
5804 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */
5805 #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5806 #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5807 
5808 /* Register: TIMER_SUBSCRIBE_COUNT */
5809 /* Description: Subscribe configuration for task COUNT */
5810 
5811 /* Bit 31 :   */
5812 #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */
5813 #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */
5814 #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */
5815 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */
5816 
5817 /* Bits 7..0 : DPPI channel that task COUNT will subscribe to */
5818 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5819 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5820 
5821 /* Register: TIMER_SUBSCRIBE_CLEAR */
5822 /* Description: Subscribe configuration for task CLEAR */
5823 
5824 /* Bit 31 :   */
5825 #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */
5826 #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */
5827 #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */
5828 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */
5829 
5830 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */
5831 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5832 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5833 
5834 /* Register: TIMER_SUBSCRIBE_SHUTDOWN */
5835 /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */
5836 
5837 /* Bit 31 :   */
5838 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */
5839 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */
5840 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */
5841 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */
5842 
5843 /* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */
5844 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5845 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5846 
5847 /* Register: TIMER_SUBSCRIBE_CAPTURE */
5848 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */
5849 
5850 /* Bit 31 :   */
5851 #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */
5852 #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */
5853 #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */
5854 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */
5855 
5856 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */
5857 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5858 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5859 
5860 /* Register: TIMER_EVENTS_COMPARE */
5861 /* Description: Description collection: Compare event on CC[n] match */
5862 
5863 /* Bit 0 : Compare event on CC[n] match */
5864 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */
5865 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */
5866 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */
5867 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */
5868 
5869 /* Register: TIMER_PUBLISH_COMPARE */
5870 /* Description: Description collection: Publish configuration for event COMPARE[n] */
5871 
5872 /* Bit 31 :   */
5873 #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */
5874 #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */
5875 #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */
5876 #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */
5877 
5878 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */
5879 #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */
5880 #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */
5881 
5882 /* Register: TIMER_SHORTS */
5883 /* Description: Shortcuts between local events and tasks */
5884 
5885 /* Bit 23 : Shortcut between event COMPARE[7] and task STOP */
5886 #define TIMER_SHORTS_COMPARE7_STOP_Pos (23UL) /*!< Position of COMPARE7_STOP field. */
5887 #define TIMER_SHORTS_COMPARE7_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE7_STOP_Pos) /*!< Bit mask of COMPARE7_STOP field. */
5888 #define TIMER_SHORTS_COMPARE7_STOP_Disabled (0UL) /*!< Disable shortcut */
5889 #define TIMER_SHORTS_COMPARE7_STOP_Enabled (1UL) /*!< Enable shortcut */
5890 
5891 /* Bit 16 : Shortcut between event COMPARE[0] and task STOP */
5892 #define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL) /*!< Position of COMPARE0_STOP field. */
5893 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
5894 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
5895 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
5896 
5897 /* Bit 7 : Shortcut between event COMPARE[7] and task CLEAR */
5898 #define TIMER_SHORTS_COMPARE7_CLEAR_Pos (7UL) /*!< Position of COMPARE7_CLEAR field. */
5899 #define TIMER_SHORTS_COMPARE7_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE7_CLEAR_Pos) /*!< Bit mask of COMPARE7_CLEAR field. */
5900 #define TIMER_SHORTS_COMPARE7_CLEAR_Disabled (0UL) /*!< Disable shortcut */
5901 #define TIMER_SHORTS_COMPARE7_CLEAR_Enabled (1UL) /*!< Enable shortcut */
5902 
5903 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */
5904 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
5905 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
5906 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
5907 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
5908 
5909 /* Register: TIMER_INTEN */
5910 /* Description: Enable or disable interrupt */
5911 
5912 /* Bit 23 : Enable or disable interrupt for event COMPARE[7] */
5913 #define TIMER_INTEN_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */
5914 #define TIMER_INTEN_COMPARE7_Msk (0x1UL << TIMER_INTEN_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */
5915 #define TIMER_INTEN_COMPARE7_Disabled (0UL) /*!< Disable */
5916 #define TIMER_INTEN_COMPARE7_Enabled (1UL) /*!< Enable */
5917 
5918 /* Bit 16 : Enable or disable interrupt for event COMPARE[0] */
5919 #define TIMER_INTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5920 #define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5921 #define TIMER_INTEN_COMPARE0_Disabled (0UL) /*!< Disable */
5922 #define TIMER_INTEN_COMPARE0_Enabled (1UL) /*!< Enable */
5923 
5924 /* Register: TIMER_INTENSET */
5925 /* Description: Enable interrupt */
5926 
5927 /* Bit 23 : Write '1' to enable interrupt for event COMPARE[7] */
5928 #define TIMER_INTENSET_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */
5929 #define TIMER_INTENSET_COMPARE7_Msk (0x1UL << TIMER_INTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */
5930 #define TIMER_INTENSET_COMPARE7_Disabled (0UL) /*!< Read: Disabled */
5931 #define TIMER_INTENSET_COMPARE7_Enabled (1UL) /*!< Read: Enabled */
5932 #define TIMER_INTENSET_COMPARE7_Set (1UL) /*!< Enable */
5933 
5934 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */
5935 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5936 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5937 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5938 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5939 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
5940 
5941 /* Register: TIMER_INTENCLR */
5942 /* Description: Disable interrupt */
5943 
5944 /* Bit 23 : Write '1' to disable interrupt for event COMPARE[7] */
5945 #define TIMER_INTENCLR_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */
5946 #define TIMER_INTENCLR_COMPARE7_Msk (0x1UL << TIMER_INTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */
5947 #define TIMER_INTENCLR_COMPARE7_Disabled (0UL) /*!< Read: Disabled */
5948 #define TIMER_INTENCLR_COMPARE7_Enabled (1UL) /*!< Read: Enabled */
5949 #define TIMER_INTENCLR_COMPARE7_Clear (1UL) /*!< Disable */
5950 
5951 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */
5952 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
5953 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
5954 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5955 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
5956 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
5957 
5958 /* Register: TIMER_MODE */
5959 /* Description: Timer mode selection */
5960 
5961 /* Bits 1..0 : Timer mode */
5962 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
5963 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
5964 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
5965 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
5966 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
5967 
5968 /* Register: TIMER_BITMODE */
5969 /* Description: Configure the number of bits used by the TIMER */
5970 
5971 /* Bits 1..0 : Timer bit width */
5972 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
5973 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
5974 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
5975 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
5976 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
5977 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
5978 
5979 /* Register: TIMER_PRESCALER */
5980 /* Description: Timer prescaler register */
5981 
5982 /* Bits 3..0 : Prescaler value */
5983 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
5984 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
5985 
5986 /* Register: TIMER_CC */
5987 /* Description: Description collection: Capture/Compare register n */
5988 
5989 /* Bits 31..0 : Capture/Compare value */
5990 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
5991 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
5992 
5993 /* Register: TIMER_ONESHOTEN */
5994 /* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */
5995 
5996 /* Bit 0 : Enable one-shot operation */
5997 #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */
5998 #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */
5999 #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL) /*!< Disable one-shot operation */
6000 #define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL) /*!< Enable one-shot operation */
6001 
6002 
6003 /* =========================================================================================================================== */
6004 /* ================                                           UART0                                           ================ */
6005 /* =========================================================================================================================== */
6006 
6007 /**
6008   * @brief Universal Asynchronous Receiver/Transmitter (UART0)
6009   */
6010 
6011 typedef struct {                                /*!< (@ 0x40002000) UART0 Structure                                            */
6012   __OM  uint32_t  TASKS_STARTRX;                /*!< (@ 0x00000000) Start UART receiver                                        */
6013   __OM  uint32_t  TASKS_STOPRX;                 /*!< (@ 0x00000004) Stop UART receiver                                         */
6014   __OM  uint32_t  TASKS_STARTTX;                /*!< (@ 0x00000008) Start UART transmitter                                     */
6015   __OM  uint32_t  TASKS_STOPTX;                 /*!< (@ 0x0000000C) Stop UART transmitter                                      */
6016   __IM  uint32_t  RESERVED[3];
6017   __OM  uint32_t  TASKS_SUSPEND;                /*!< (@ 0x0000001C) Suspend UART                                               */
6018   __IM  uint32_t  RESERVED1[56];
6019   __IOM uint32_t  EVENTS_CTS;                   /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send.                 */
6020   __IOM uint32_t  EVENTS_NCTS;                  /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send.          */
6021   __IOM uint32_t  EVENTS_RXDRDY;                /*!< (@ 0x00000108) Data received in RXD                                       */
6022   __IM  uint32_t  RESERVED2[4];
6023   __IOM uint32_t  EVENTS_TXDRDY;                /*!< (@ 0x0000011C) Data sent from TXD                                         */
6024   __IM  uint32_t  RESERVED3;
6025   __IOM uint32_t  EVENTS_ERROR;                 /*!< (@ 0x00000124) Error detected                                             */
6026   __IM  uint32_t  RESERVED4[7];
6027   __IOM uint32_t  EVENTS_RXTO;                  /*!< (@ 0x00000144) Receiver timeout                                           */
6028   __IM  uint32_t  RESERVED5[46];
6029   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
6030   __IM  uint32_t  RESERVED6[64];
6031   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
6032   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
6033   __IM  uint32_t  RESERVED7[93];
6034   __IOM uint32_t  ERRORSRC;                     /*!< (@ 0x00000480) Error source                                               */
6035   __IM  uint32_t  RESERVED8[31];
6036   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable UART                                                */
6037   __IM  uint32_t  RESERVED9;
6038   __IOM UART_PSEL_Type PSEL;                    /*!< (@ 0x00000508) Unspecified                                                */
6039   __IM  uint32_t  RXD;                          /*!< (@ 0x00000518) RXD register                                               */
6040   __OM  uint32_t  TXD;                          /*!< (@ 0x0000051C) TXD register                                               */
6041   __IM  uint32_t  RESERVED10;
6042   __IOM uint32_t  BAUDRATE;                     /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source
6043                                                                     selected.                                                  */
6044   __IM  uint32_t  RESERVED11[17];
6045   __IOM uint32_t  CONFIG;                       /*!< (@ 0x0000056C) Configuration of parity and hardware flow control          */
6046 } NRF_UART_Type;                                /*!< Size = 1392 (0x570)                                                       */
6047 
6048 
6049 /* Peripheral: UART */
6050 /* Description: Universal Asynchronous Receiver/Transmitter */
6051 
6052 /* Register: UART_SHORTS */
6053 /* Description: Shortcuts between local events and tasks */
6054 
6055 /* Bit 4 : Shortcut between event NCTS and task STOPRX */
6056 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
6057 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
6058 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
6059 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
6060 
6061 /* Bit 3 : Shortcut between event CTS and task STARTRX */
6062 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
6063 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
6064 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
6065 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
6066 
6067 /* Register: UART_ERRORSRC */
6068 /* Description: Error source */
6069 
6070 /* Bit 3 : Break condition */
6071 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
6072 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
6073 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
6074 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
6075 
6076 /* Bit 2 : Framing error occurred */
6077 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
6078 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
6079 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
6080 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
6081 
6082 /* Bit 1 : Parity error */
6083 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
6084 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
6085 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
6086 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
6087 
6088 /* Bit 0 : Overrun error */
6089 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
6090 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
6091 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
6092 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
6093 
6094 /* Register: UART_ENABLE */
6095 /* Description: Enable UART */
6096 
6097 /* Bits 3..0 : Enable or disable UART */
6098 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6099 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6100 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
6101 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
6102 
6103 /* Register: UART_PSEL_RTS */
6104 /* Description: Pin select for RTS */
6105 
6106 /* Bit 31 : Connection */
6107 #define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6108 #define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6109 #define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
6110 #define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
6111 
6112 /* Bit 5 : Port number */
6113 #define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
6114 #define UART_PSEL_RTS_PORT_Msk (0x1UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
6115 
6116 /* Bits 4..0 : Pin number */
6117 #define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
6118 #define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
6119 
6120 /* Register: UART_PSEL_TXD */
6121 /* Description: Pin select for TXD */
6122 
6123 /* Bit 31 : Connection */
6124 #define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6125 #define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6126 #define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
6127 #define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
6128 
6129 /* Bit 5 : Port number */
6130 #define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
6131 #define UART_PSEL_TXD_PORT_Msk (0x1UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
6132 
6133 /* Bits 4..0 : Pin number */
6134 #define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
6135 #define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
6136 
6137 /* Register: UART_PSEL_CTS */
6138 /* Description: Pin select for CTS */
6139 
6140 /* Bit 31 : Connection */
6141 #define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6142 #define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6143 #define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
6144 #define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
6145 
6146 /* Bit 5 : Port number */
6147 #define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
6148 #define UART_PSEL_CTS_PORT_Msk (0x1UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
6149 
6150 /* Bits 4..0 : Pin number */
6151 #define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
6152 #define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
6153 
6154 /* Register: UART_PSEL_RXD */
6155 /* Description: Pin select for RXD */
6156 
6157 /* Bit 31 : Connection */
6158 #define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6159 #define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6160 #define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
6161 #define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
6162 
6163 /* Bit 5 : Port number */
6164 #define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
6165 #define UART_PSEL_RXD_PORT_Msk (0x1UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
6166 
6167 /* Bits 4..0 : Pin number */
6168 #define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
6169 #define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
6170 
6171 /* Register: UART_RXD */
6172 /* Description: RXD register */
6173 
6174 /* Bits 7..0 : RX data received in previous transfers, double buffered */
6175 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
6176 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
6177 
6178 /* Register: UART_TXD */
6179 /* Description: TXD register */
6180 
6181 /* Bits 7..0 : TX data to be transferred */
6182 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
6183 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
6184 
6185 /* Register: UART_BAUDRATE */
6186 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
6187 
6188 /* Bits 31..0 : Baud rate */
6189 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
6190 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
6191 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
6192 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
6193 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
6194 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
6195 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
6196 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
6197 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
6198 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
6199 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
6200 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
6201 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
6202 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
6203 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
6204 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
6205 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
6206 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
6207 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
6208 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
6209 
6210 /* Register: UART_CONFIG */
6211 /* Description: Configuration of parity and hardware flow control */
6212 
6213 /* Bit 8 : Even or odd parity type */
6214 #define UART_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */
6215 #define UART_CONFIG_PARITYTYPE_Msk (0x1UL << UART_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */
6216 #define UART_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */
6217 #define UART_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */
6218 
6219 /* Bit 4 : Stop bits */
6220 #define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
6221 #define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
6222 #define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */
6223 #define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
6224 
6225 /* Bits 3..1 : Parity */
6226 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
6227 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
6228 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
6229 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
6230 
6231 /* Bit 0 : Hardware flow control */
6232 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
6233 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
6234 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
6235 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
6236 
6237 
6238 /* =========================================================================================================================== */
6239 /* ================                                         UARTE0_NS                                         ================ */
6240 /* =========================================================================================================================== */
6241 
6242 
6243 /**
6244   * @brief UART with EasyDMA 0 (UARTE0_NS)
6245   */
6246 
6247 typedef struct {                                /*!< (@ 0x40008000) UARTE0_NS Structure                                        */
6248   __OM  uint32_t  TASKS_STARTRX;                /*!< (@ 0x00000000) Start UART receiver                                        */
6249   __OM  uint32_t  TASKS_STOPRX;                 /*!< (@ 0x00000004) Stop UART receiver                                         */
6250   __OM  uint32_t  TASKS_STARTTX;                /*!< (@ 0x00000008) Start UART transmitter                                     */
6251   __OM  uint32_t  TASKS_STOPTX;                 /*!< (@ 0x0000000C) Stop UART transmitter                                      */
6252   __IM  uint32_t  RESERVED[7];
6253   __OM  uint32_t  TASKS_FLUSHRX;                /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer                               */
6254   __IM  uint32_t  RESERVED1[20];
6255   __IOM uint32_t  SUBSCRIBE_STARTRX;            /*!< (@ 0x00000080) Subscribe configuration for task STARTRX                   */
6256   __IOM uint32_t  SUBSCRIBE_STOPRX;             /*!< (@ 0x00000084) Subscribe configuration for task STOPRX                    */
6257   __IOM uint32_t  SUBSCRIBE_STARTTX;            /*!< (@ 0x00000088) Subscribe configuration for task STARTTX                   */
6258   __IOM uint32_t  SUBSCRIBE_STOPTX;             /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX                    */
6259   __IM  uint32_t  RESERVED2[7];
6260   __IOM uint32_t  SUBSCRIBE_FLUSHRX;            /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX                   */
6261   __IM  uint32_t  RESERVED3[20];
6262   __IOM uint32_t  EVENTS_CTS;                   /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send.                 */
6263   __IOM uint32_t  EVENTS_NCTS;                  /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send.          */
6264   __IOM uint32_t  EVENTS_RXDRDY;                /*!< (@ 0x00000108) Data received in RXD (but potentially not yet
6265                                                                     transferred to Data RAM)                                   */
6266   __IM  uint32_t  RESERVED4;
6267   __IOM uint32_t  EVENTS_ENDRX;                 /*!< (@ 0x00000110) Receive buffer is filled up                                */
6268   __IM  uint32_t  RESERVED5[2];
6269   __IOM uint32_t  EVENTS_TXDRDY;                /*!< (@ 0x0000011C) Data sent from TXD                                         */
6270   __IOM uint32_t  EVENTS_ENDTX;                 /*!< (@ 0x00000120) Last TX byte transmitted                                   */
6271   __IOM uint32_t  EVENTS_ERROR;                 /*!< (@ 0x00000124) Error detected                                             */
6272   __IM  uint32_t  RESERVED6[7];
6273   __IOM uint32_t  EVENTS_RXTO;                  /*!< (@ 0x00000144) Receiver timeout                                           */
6274   __IM  uint32_t  RESERVED7;
6275   __IOM uint32_t  EVENTS_RXSTARTED;             /*!< (@ 0x0000014C) UART receiver has started                                  */
6276   __IOM uint32_t  EVENTS_TXSTARTED;             /*!< (@ 0x00000150) UART transmitter has started                               */
6277   __IM  uint32_t  RESERVED8;
6278   __IOM uint32_t  EVENTS_TXSTOPPED;             /*!< (@ 0x00000158) Transmitter stopped                                        */
6279   __IM  uint32_t  RESERVED9[9];
6280   __IOM uint32_t  PUBLISH_CTS;                  /*!< (@ 0x00000180) Publish configuration for event CTS                        */
6281   __IOM uint32_t  PUBLISH_NCTS;                 /*!< (@ 0x00000184) Publish configuration for event NCTS                       */
6282   __IOM uint32_t  PUBLISH_RXDRDY;               /*!< (@ 0x00000188) Publish configuration for event RXDRDY                     */
6283   __IM  uint32_t  RESERVED10;
6284   __IOM uint32_t  PUBLISH_ENDRX;                /*!< (@ 0x00000190) Publish configuration for event ENDRX                      */
6285   __IM  uint32_t  RESERVED11[2];
6286   __IOM uint32_t  PUBLISH_TXDRDY;               /*!< (@ 0x0000019C) Publish configuration for event TXDRDY                     */
6287   __IOM uint32_t  PUBLISH_ENDTX;                /*!< (@ 0x000001A0) Publish configuration for event ENDTX                      */
6288   __IOM uint32_t  PUBLISH_ERROR;                /*!< (@ 0x000001A4) Publish configuration for event ERROR                      */
6289   __IM  uint32_t  RESERVED12[7];
6290   __IOM uint32_t  PUBLISH_RXTO;                 /*!< (@ 0x000001C4) Publish configuration for event RXTO                       */
6291   __IM  uint32_t  RESERVED13;
6292   __IOM uint32_t  PUBLISH_RXSTARTED;            /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED                  */
6293   __IOM uint32_t  PUBLISH_TXSTARTED;            /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED                  */
6294   __IM  uint32_t  RESERVED14;
6295   __IOM uint32_t  PUBLISH_TXSTOPPED;            /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED                  */
6296   __IM  uint32_t  RESERVED15[9];
6297   __IOM uint32_t  SHORTS;                       /*!< (@ 0x00000200) Shortcuts between local events and tasks                   */
6298   __IM  uint32_t  RESERVED16[63];
6299   __IOM uint32_t  INTEN;                        /*!< (@ 0x00000300) Enable or disable interrupt                                */
6300   __IOM uint32_t  INTENSET;                     /*!< (@ 0x00000304) Enable interrupt                                           */
6301   __IOM uint32_t  INTENCLR;                     /*!< (@ 0x00000308) Disable interrupt                                          */
6302   __IM  uint32_t  RESERVED17[93];
6303   __IOM uint32_t  ERRORSRC;                     /*!< (@ 0x00000480) Error source                                               */
6304   __IM  uint32_t  RESERVED18[31];
6305   __IOM uint32_t  ENABLE;                       /*!< (@ 0x00000500) Enable UART                                                */
6306   __IM  uint32_t  RESERVED19;
6307   __IOM UARTE_PSEL_Type PSEL;                   /*!< (@ 0x00000508) Unspecified                                                */
6308   __IM  uint32_t  RESERVED20[3];
6309   __IOM uint32_t  BAUDRATE;                     /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source
6310                                                                     selected.                                                  */
6311   __IM  uint32_t  RESERVED21[3];
6312   __IOM UARTE_RXD_Type RXD;                     /*!< (@ 0x00000534) RXD EasyDMA channel                                        */
6313   __IM  uint32_t  RESERVED22;
6314   __IOM UARTE_TXD_Type TXD;                     /*!< (@ 0x00000544) TXD EasyDMA channel                                        */
6315   __IM  uint32_t  RESERVED23[7];
6316   __IOM uint32_t  CONFIG;                       /*!< (@ 0x0000056C) Configuration of parity and hardware flow control          */
6317 } NRF_UARTE_Type;                               /*!< Size = 1392 (0x570)                                                       */
6318 
6319 
6320 /* Peripheral: UARTE */
6321 /* Description: UART with EasyDMA 0 */
6322 
6323 /* Register: UARTE_SHORTS */
6324 /* Description: Shortcuts between local events and tasks */
6325 
6326 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */
6327 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
6328 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
6329 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
6330 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
6331 
6332 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */
6333 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
6334 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
6335 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
6336 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
6337 
6338 /* Register: UARTE_INTENSET */
6339 /* Description: Enable interrupt */
6340 
6341 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */
6342 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
6343 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
6344 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
6345 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
6346 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
6347 
6348 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */
6349 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
6350 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
6351 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
6352 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
6353 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
6354 
6355 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */
6356 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
6357 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
6358 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
6359 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
6360 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
6361 
6362 /* Bit 17 : Write '1' to enable interrupt for event RXTO */
6363 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
6364 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
6365 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
6366 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
6367 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
6368 
6369 /* Bit 9 : Write '1' to enable interrupt for event ERROR */
6370 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
6371 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
6372 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
6373 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
6374 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
6375 
6376 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */
6377 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
6378 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
6379 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
6380 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
6381 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
6382 
6383 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */
6384 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
6385 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
6386 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
6387 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
6388 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
6389 
6390 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */
6391 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
6392 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
6393 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
6394 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
6395 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
6396 
6397 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */
6398 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
6399 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
6400 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
6401 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
6402 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
6403 
6404 /* Bit 1 : Write '1' to enable interrupt for event NCTS */
6405 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
6406 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
6407 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
6408 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
6409 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
6410 
6411 /* Bit 0 : Write '1' to enable interrupt for event CTS */
6412 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
6413 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
6414 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
6415 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
6416 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
6417 
6418 
6419 /* Register: UARTE_ERRORSRC */
6420 /* Description: Error source This register is read/write one to clear. */
6421 
6422 /* Bit 3 : Break condition */
6423 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
6424 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
6425 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
6426 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
6427 
6428 /* Bit 2 : Framing error occurred */
6429 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
6430 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
6431 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
6432 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
6433 
6434 /* Bit 1 : Parity error */
6435 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
6436 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
6437 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
6438 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
6439 
6440 /* Bit 0 : Overrun error */
6441 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
6442 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
6443 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
6444 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
6445 
6446 /* Register: UARTE_ENABLE */
6447 /* Description: Enable UART */
6448 
6449 /* Bits 3..0 : Enable or disable UARTE */
6450 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6451 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6452 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
6453 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
6454 
6455 /* Register: UARTE_PSEL_RTS */
6456 /* Description: Pin select for RTS signal */
6457 
6458 /* Bit 31 : Connection */
6459 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6460 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6461 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
6462 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
6463 
6464 /* Bit 5 : Port number */
6465 #define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
6466 #define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
6467 
6468 /* Bits 4..0 : Pin number */
6469 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
6470 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
6471 
6472 /* Register: UARTE_PSEL_TXD */
6473 /* Description: Pin select for TXD signal */
6474 
6475 /* Bit 31 : Connection */
6476 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6477 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6478 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
6479 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
6480 
6481 /* Bit 5 : Port number */
6482 #define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
6483 #define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
6484 
6485 /* Bits 4..0 : Pin number */
6486 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
6487 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
6488 
6489 /* Register: UARTE_PSEL_CTS */
6490 /* Description: Pin select for CTS signal */
6491 
6492 /* Bit 31 : Connection */
6493 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6494 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6495 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
6496 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
6497 
6498 /* Bit 5 : Port number */
6499 #define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
6500 #define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
6501 
6502 /* Bits 4..0 : Pin number */
6503 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
6504 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
6505 
6506 /* Register: UARTE_PSEL_RXD */
6507 /* Description: Pin select for RXD signal */
6508 
6509 /* Bit 31 : Connection */
6510 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6511 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6512 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
6513 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
6514 
6515 /* Bit 5 : Port number */
6516 #define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
6517 #define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
6518 
6519 /* Bits 4..0 : Pin number */
6520 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
6521 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
6522 
6523 /* Register: UARTE_BAUDRATE */
6524 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
6525 
6526 /* Bits 31..0 : Baud rate */
6527 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
6528 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
6529 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
6530 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
6531 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
6532 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
6533 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
6534 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
6535 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
6536 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
6537 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
6538 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
6539 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
6540 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
6541 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
6542 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
6543 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
6544 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
6545 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
6546 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */
6547 
6548 /* Register: UARTE_RXD_PTR */
6549 /* Description: Data pointer */
6550 
6551 /* Bits 31..0 : Data pointer */
6552 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
6553 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
6554 
6555 /* Register: UARTE_RXD_MAXCNT */
6556 /* Description: Maximum number of bytes in receive buffer */
6557 
6558 /* Bits 15..0 : Maximum number of bytes in receive buffer */
6559 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
6560 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
6561 
6562 /* Register: UARTE_RXD_AMOUNT */
6563 /* Description: Number of bytes transferred in the last transaction */
6564 
6565 /* Bits 15..0 : Number of bytes transferred in the last transaction */
6566 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
6567 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
6568 
6569 /* Register: UARTE_TXD_PTR */
6570 /* Description: Data pointer */
6571 
6572 /* Bits 31..0 : Data pointer */
6573 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
6574 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
6575 
6576 /* Register: UARTE_TXD_MAXCNT */
6577 /* Description: Maximum number of bytes in transmit buffer */
6578 
6579 /* Bits 15..0 : Maximum number of bytes in transmit buffer */
6580 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
6581 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
6582 
6583 /* Register: UARTE_TXD_AMOUNT */
6584 /* Description: Number of bytes transferred in the last transaction */
6585 
6586 /* Bits 15..0 : Number of bytes transferred in the last transaction */
6587 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
6588 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
6589 
6590 /* Register: UARTE_CONFIG */
6591 /* Description: Configuration of parity and hardware flow control */
6592 
6593 /* Bit 8 : Even or odd parity type */
6594 #define UARTE_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */
6595 #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */
6596 #define UARTE_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */
6597 #define UARTE_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */
6598 
6599 /* Bit 4 : Stop bits */
6600 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
6601 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
6602 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
6603 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
6604 
6605 /* Bits 3..1 : Parity */
6606 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
6607 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
6608 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
6609 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
6610 
6611 /* Bit 0 : Hardware flow control */
6612 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
6613 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
6614 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
6615 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
6616 
6617 
6618 /* =========================================================================================================================== */
6619 /* ================                                          UICR                                             ================ */
6620 /* =========================================================================================================================== */
6621 
6622 
6623 /**
6624   * @brief User Information Configuration Registers (UICR)
6625   * At this point just a chunk of reserved space of 2KiB
6626   */
6627 
6628 typedef struct {                                /*!< (@ 0x10001000) UICR Structure                                          */
6629   __IM  uint32_t  RESERVED[1024];
6630 } NRF_UICR_Type;                                /*!< Size = 4096 */
6631 
6632 
6633 
6634 /* =========================================================================================================================== */
6635 /* ================                                        VREQCTRL                                           ================ */
6636 /* =========================================================================================================================== */
6637 
6638 
6639 /**
6640   * @brief Voltage request control (VREQCTRL)
6641   */
6642 
6643 typedef struct {                                /*!< (@ 0x41004000) VREQCTRL_NS Structure                                      */
6644   __IM  uint32_t  RESERVED[320];
6645   __IOM VREQCTRL_VREGRADIO_Type VREGRADIO;      /*!< (@ 0x00000500) Unspecified                                                */
6646 } NRF_VREQCTRL_Type;                            /*!< Size = 1292 (0x50c)                                                       */
6647 
6648 
6649 
6650 #ifdef __cplusplus
6651 }
6652 #endif
6653 
6654 #endif /* _NRF5340_PERI_TYPES_H */
6655