1 /* 2 * Copyright (c) 2023 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * This file configures the HW models based on the variant being built 7 */ 8 #ifndef _NRF_HW_CONFIG_H 9 #define _NRF_HW_CONFIG_H 10 11 /* 12 * For each peripheral the following may be defined 13 * NHW_<PERIPH_TYPE>_TOTAL_INST <val> : Total number of instances of the peripheral in the whole SOC 14 * NHW_<PERIPH_TYPE>_<CORE>_<INST> <val> : Index of that peripheral instant in list of peripherals 15 * 16 * NHW_<PERIPH_TYPE>_INT_MAP : List of irq controller mapping, for each instante: {irq ctrl number, irq line} 17 */ 18 19 #if defined(NRF52833) || defined(NRF52833_XXAA) 20 21 #define NHW_CORE_NAMES {""} 22 23 #define NHW_HAS_PPI 1 24 #define NHW_HAS_DPPI 0 25 #define NHW_USE_MDK_TYPES 1 /* The HW registers layout types are taken from the MDK */ 26 27 #define NHW_AAR_TOTAL_INST 1 28 #define NHW_AAR_0 0 29 #define NHW_AAR_INT_MAP {{0 , 15}} /*Only core,CCM_AAR_IRQn*/ 30 #define NHW_AAR_t_AAR 6 31 32 #define NHW_CCM_TOTAL_INST 1 33 #define NHW_CCM_0 0 34 #define NHW_CCM_INT_MAP {{0 , 15}} /*Only core,CCM_AAR_IRQn*/ 35 36 #define NHW_CLKPWR_TOTAL_INST 1 37 #define NHW_CLKPWR_0 0 38 #define NHW_CLKPWR_INT_MAP {{0 , 0}} /*Only core, POWER_CLOCK_IRQn*/ 39 #define NHW_CLKPWR_HAS_RESET 0 40 #define NHW_CLKPWR_HAS_CALTIMER 1 41 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK 0 42 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK_I {0} 43 #define NHW_CLKPWR_HAS_HFCLK192MCLK 0 44 #define NHW_CLKPWR_HAS_HFCLK192MCLK_I {0} 45 46 #define NHW_ECB_TOTAL_INST 1 47 #define NHW_ECB_0 0 48 #define NHW_ECB_INT_MAP {{0 , 14}} /*Only core,ECB_IRQn*/ 49 #define NHW_ECB_t_ECB 7 /* 7.2 */ 50 51 #define NHW_EGU_TOTAL_INST 6 52 #define NHW_EGU_0 0 53 #define NHW_EGU_1 1 54 #define NHW_EGU_2 2 55 #define NHW_EGU_3 3 56 #define NHW_EGU_4 4 57 #define NHW_EGU_5 5 58 #define NHW_EGU_INT_MAP {{0 , 20}, \ 59 {0 , 21}, \ 60 {0 , 22}, \ 61 {0 , 23}, \ 62 {0 , 24}, \ 63 {0 , 25}, \ 64 } /*Only core,SWI0..5_EGU0_IRQn*/ 65 #define NHW_EGU_N_EVENTS {16, 16, 16, 16, 16, 16} 66 67 #define NHW_GPIO_TOTAL_INST 2 68 #define NHW_GPIO_P0 0 69 #define NHW_GPIO_P1 1 70 #define NHW_GPIO_MAX_PINS_PER_PORT 32 71 #define NHW_GPIO_NBR_PINS {32, 10} /* Number of IOs per port */ 72 #define NHW_GPIO_PARTNER_GPIOTE {0, 0} /* GPIOTE nbr to which the DETECT signal(s) will be sent */ 73 #define NHW_GPIO_HAS_PIN_SENSE {1} /* Per instance, does it have pin sense/detect mechanism */ 74 75 #define NHW_GPIOTE_TOTAL_INST 1 76 #define NHW_GPIOTE_0 0 77 #define NHW_GPIOTE_N_INT 1 /* Number of interrupts lines, common for all instances */ 78 #define NHW_GPIOTE_INT_MAP {{{0 , 6}}} /* Only core, GPIOTE_IRQn */ 79 #define NHW_GPIOTE_MAX_CHANNELS 8 /* Maximum number of channels in any instance */ 80 #define NHW_GPIOTE_CHANNELS {8} /* Number of channels per instance */ 81 #define NHW_GPIOTE_IS_54 0 82 83 #define NHW_INTCTRL_TOTAL_INST 1 84 #define NHW_INTCTRL_MAX_INTLINES 48 85 86 /* These names are taken from the IRQn_Type in the MDK header */ 87 #define NHW_INT_NAMES { [0] = {\ 88 [0 ] = "POWER_CLOCK",\ 89 [1 ] = "RADIO",\ 90 [2 ] = "UARTE0_UART0",\ 91 [3 ] = "SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0",\ 92 [4 ] = "SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1",\ 93 [5 ] = "NFCT",\ 94 [6 ] = "GPIOTE",\ 95 [7 ] = "SAADC",\ 96 [8 ] = "TIMER0",\ 97 [9 ] = "TIMER1",\ 98 [10] = "TIMER2",\ 99 [11] = "RTC0",\ 100 [12] = "TEMP",\ 101 [13] = "RNG",\ 102 [14] = "ECB",\ 103 [15] = "CCM_AAR",\ 104 [16] = "WDT",\ 105 [17] = "RTC1",\ 106 [18] = "QDEC",\ 107 [19] = "COMP_LPCOMP",\ 108 [20] = "SWI0_EGU0",\ 109 [21] = "SWI1_EGU1",\ 110 [22] = "SWI2_EGU2",\ 111 [23] = "SWI3_EGU3",\ 112 [24] = "SWI4_EGU4",\ 113 [25] = "SWI5_EGU5",\ 114 [26] = "TIMER3",\ 115 [27] = "TIMER4",\ 116 [28] = "PWM0",\ 117 [29] = "PDM",\ 118 [32] = "MWU",\ 119 [33] = "PWM1",\ 120 [34] = "PWM2",\ 121 [35] = "SPIM2_SPIS2_SPI2",\ 122 [36] = "RTC2",\ 123 [37] = "I2S",\ 124 [38] = "FPU",\ 125 [39] = "USBD",\ 126 [40] = "UARTE1",\ 127 [45] = "PWM3",\ 128 [47] = "SPIM3",\ 129 }} 130 131 #define NHW_NVMC_UICR_TOTAL_INST 1 132 #define NHW_NVMC_HAS_ERASEREGS 1 133 #define NHW_FLASH_START_ADDR {0x00000000} 134 #define NHW_FLASH_PAGESIZE {(4*1024)} 135 #define NHW_FLASH_N_PAGES {128} 136 #define NHW_UICR_SIZE {776 /*64*4*/ /*bytes*/} 137 /* In case somebody tries to access the UICR registers, we book 138 * more space than its actual flash area (64*4)*/ 139 #define NHW_NVMC_FLASH_T_ERASEALL (173000) 140 #define NHW_NVMC_FLASH_T_ERASEPAGE (87500) 141 #define NHW_NVMC_FLASH_T_WRITE (42) 142 #define NHW_NVMC_FLASH_PARTIAL_ERASE_FACTOR (1.0) 143 144 #define NHW_RADIO_TOTAL_INST 1 145 #define NHW_RADIO_0 0 146 #define NHW_RADIO_N_INT 1 147 #define NHW_RADIO_INT_MAP {{0 , 1}} /*Only core,RADIO_IRQn*/ 148 #define NHW_RADIO_ED_RSSIOFFS (-93) 149 #define NHW_RADIO_IS_54 0 150 151 #define NHW_RNG_TOTAL_INST 1 152 #define NHW_RNG_0 0 153 #define NHW_RNG_INT_MAP {{0 , 13}} /*Only core,RNG_IRQn*/ 154 #define NHW_RNG_tRNG_START 128 155 #define NHW_RNG_tRNG_RAW 30 156 #define NHW_RNG_tRNG_BC 120 157 158 #define NHW_RTC_TOTAL_INST 3 159 #define NHW_RTC_0 0 160 #define NHW_RTC_1 1 161 #define NHW_RTC_2 2 162 #define NHW_RTC_INT_MAP {{0 , 11}, \ 163 {0 , 17}, \ 164 {0 , 36}, \ 165 } /*Only core,RTC0..2_IRQn*/ 166 #define NHW_RTC_HAS_CAPTURE 0 167 #define NHW_RTC_HAS_SHORT_COMP_CLEAR 0 168 #define NHW_RTC_N_CC {3, 4, 4} 169 170 #define NHW_TEMP_TOTAL_INST 1 171 #define NHW_TEMP_0 0 172 #define NHW_TEMP_INT_MAP {{0 , 12}} /*Only core,TEMP_IRQn*/ 173 #define NHW_TEMP_t_TEMP 36 /* microseconds */ 174 #define NHW_TEMP_FBITS 2 /* fractional bits => 0.25C resolution */ 175 176 #define NHW_TIMER_TOTAL_INST 5 177 #define NHW_TIMER_0 0 178 #define NHW_TIMER_1 1 179 #define NHW_TIMER_2 2 180 #define NHW_TIMER_3 3 181 #define NHW_TIMER_4 4 182 #define NHW_TIMER_INT_MAP {{0 , 8}, \ 183 {0 , 9}, \ 184 {0 , 10}, \ 185 {0 , 26}, \ 186 {0 , 27}, \ 187 } /* Only core, TIMER0..4_IRQn */ 188 #define NHW_TIMER_HAS_ONE_SHOT 0 189 #define NHW_TIMER_N_CC {4, 4, 4, 6, 6} 190 #define NHW_TIMER_MAX_N_CC 6 191 #define NHW_TIMER_FREQ {16, 16, 16, 16, 16} 192 193 #define NHW_UARTE_TOTAL_INST 2 194 #define NHW_UART_0 0 195 #define NHW_UART_1 1 196 #define NHW_UARTE_INT_MAP {{0 , 2}, \ 197 {0 , 40}, \ 198 } /* Only core, UARTE0_UART0_IRQn, UARTE1_IRQn */ 199 #define NHW_UARTE_HAS_UART 1 200 #define NHW_UARTE_NAMES {"UARTE0", \ 201 "UARTE1"} 202 #define NHW_UARTE_54NAMING 0 203 #define NHW_UARTE_FLUSH_AMOUNT_BUG 0 204 #define NHW_UARTE_HAS_FRAMETIMEOUT 0 205 #define NHW_UARTE_HAS_MATCH 0 206 #define NHW_UARTE_CLOCKS {16, 16} 207 208 #define NHW_BSTICKER_TOTAL_INST 1 209 #define NHW_BSTICKER_TIMER_INT_MAP {{0 , 0}} /*Only core, -*/ 210 211 #define NHW_FAKE_TIMER_TOTAL_INST 1 212 #define NHW_FAKE_TIMER_INT_MAP {{0 , 0}} /*Only core, -*/ 213 214 /*************************************************************************/ 215 /*************************************************************************/ 216 /*************************************************************************/ 217 #elif defined(NRF5340) || defined(NRF5340_XXAA_NETWORK) || defined(NRF5340_XXAA_APPLICATION) 218 219 /* 220 * The Application core/domain is indexed as domain 0 221 * The Network core/domain is indexed as domain 1 222 */ 223 224 #define NHW_HAS_PPI 0 225 #define NHW_HAS_DPPI 1 226 #define NHW_USE_MDK_TYPES 0 227 228 #define NHW_AAR_TOTAL_INST 1 229 #define NHW_AAR_NET0 0 230 #define NHW_AAR_INT_MAP {{1 , 14}} /*Net core,AAR_CCM */ 231 #define NHW_AAR_DPPI_MAP {1} 232 #define NHW_AAR_t_AAR 6 233 234 #define NHW_CCM_TOTAL_INST 1 235 #define NHW_CCM_NET0 0 236 #define NHW_CCM_INT_MAP {{1 , 14}} /*Net core,AAR_CCM*/ 237 #define NHW_CCM_DPPI_MAP {1} 238 239 #define NHW_CLKPWR_TOTAL_INST 2 240 #define NHW_CLKPWR_APP0 0 241 #define NHW_CLKPWR_NET0 1 242 #define NHW_CLKPWR_INT_MAP {{0 , 5}, \ 243 {1 , 5} \ 244 } /* {App, CLOCK_POWER} 245 * {Net, CLOCK_POWER} 246 */ 247 #define NHW_CLKPWR_DPPI_MAP {0, 1} 248 #define NHW_CLKPWR_HAS_RESET 1 249 #define NHW_CLKPWR_HAS_CALTIMER 0 250 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK 1 251 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK_I {1, 0} 252 #define NHW_CLKPWR_HAS_HFCLK192MCLK 1 253 #define NHW_CLKPWR_HAS_HFCLK192MCLK_I {1, 0} 254 255 #define NHW_ECB_TOTAL_INST 1 256 #define NHW_ECB_NET0 0 257 #define NHW_ECB_INT_MAP {{1 , 13}} /*Net core, ECB_IRQn*/ 258 #define NHW_ECB_DPPI_MAP {1} 259 #define NHW_ECB_t_ECB 6 /* 6.2 */ 260 261 #define NHW_EGU_TOTAL_INST 7 262 #define NHW_EGU_APP0 0 263 #define NHW_EGU_APP1 1 264 #define NHW_EGU_APP2 2 265 #define NHW_EGU_APP3 3 266 #define NHW_EGU_APP4 4 267 #define NHW_EGU_APP5 5 268 #define NHW_EGU_NET0 6 269 #define NHW_EGU_INT_MAP {{0 , 27}, \ 270 {0 , 28}, \ 271 {0 , 29}, \ 272 {0 , 30}, \ 273 {0 , 31}, \ 274 {0 , 32}, \ 275 {1 , 20}, \ 276 } 277 /* {App, EGU0} 278 * .. 279 * {App, EGU5} 280 * {Network, EGU0} 281 * */ 282 #define NHW_EGU_DPPI_MAP {0, 0, 0, 0, 0, 0,\ 283 1} 284 #define NHW_EGU_N_EVENTS {16, 16, 16, 16, 16, 16,\ 285 16} 286 287 #define NHW_DPPI_TOTAL_INST 2 288 #define NHW_DPPI_APP_0 0 289 #define NHW_DPPI_NET_0 1 290 /* The DPPI does not generate interrupts */ 291 #define NHW_DPPI_DPPI_MAP {0,1} /*App DPPI connects to itself, network DPPI to itself*/ 292 #define NHW_DPPI_N_CH {32, 32} /* Number of channels in each DPPI */ 293 #define NHW_DPPI_N_CHG {6, 6} /* Number of channel groups in each DPPI */ 294 295 #define NHW_IPC_TOTAL_INST 2 296 #define NHW_IPC_APP0 0 297 #define NHW_IPC_NET0 1 298 #define NHW_IPC_INT_MAP {{0 , 42}, \ 299 {1 , 18}} 300 /* {App, IPC} 301 * {Network, IPC} 302 * */ 303 #define NHW_IPC_DPPI_MAP {0, 1} /*App, network */ 304 #define NHW_IPC_N_CH {16, 16} 305 306 #define NHW_FICR_APP 0 307 #define NHW_FICR_NET 1 308 309 /* Note the net and app core ports are fully separate */ 310 #define NHW_GPIO_TOTAL_INST 4 311 #define NHW_GPIO_NET_P0 0 312 #define NHW_GPIO_NET_P1 1 313 #define NHW_GPIO_APP_P0 2 314 #define NHW_GPIO_APP_P1 3 315 #define NHW_GPIO_MAX_PINS_PER_PORT 32 316 #define NHW_GPIO_NBR_PINS {32, 16, 32, 16} /* Number of IOs per port */ 317 #define NHW_GPIO_PARTNER_GPIOTE {0, 0, 2, 2} /* NET_P0->GPIOT_NET, NET_P1->GPIOTE_NET */ 318 /* APP_P0/1->APP GPIOTE1 (NS) 319 * (secure connection handled in code as special case)*/ 320 #define NHW_GPIO_HAS_PIN_SENSE {1, 1, 1, 1} /* Per instance, does it have pin sense/detect mechanism */ 321 322 #define NHW_GPIOTE_TOTAL_INST 3 323 #define NHW_GPIOTE_NET 0 324 #define NHW_GPIOTE_APP0 1 /* AKA GPIOTESEC */ 325 #define NHW_GPIOTE_APP1 2 326 #define NHW_GPIOTE_MAX_CHANNELS 8 /* Maximum number of channels in any instance */ 327 #define NHW_GPIOTE_CHANNELS {8, 8, 8} /* Number of channels per instance */ 328 #define NHW_GPIOTE_N_INT 1 /* Number of interrupts lines, common for all instances */ 329 #define NHW_GPIOTE_INT_MAP {{{1, 10}},\ 330 {{0, 13}},\ 331 {{0, 47}}} 332 /* Net, GPIOTE_IRQn */ 333 /* App, GPIOTE0_IRQn */ 334 /* App, GPIOTE1_IRQn */ 335 #define NHW_GPIOTE_DPPI_MAP {1, 0 ,0} /* Net, App, App */ 336 #define NHW_GPIOTE_IS_54 0 /* Multiple int. lines and PORTxSECURE/NONSECURE */ 337 338 #define NHW_INTCTRL_TOTAL_INST 2 339 #define NHW_INTCTRL_MAX_INTLINES 58 340 341 /* These names are taken from the IRQn_Type in the MDK header */ 342 #define NHW_INT_NAMES { [0 /*Application core*/] = {\ 343 [0 ]= "FPU",\ 344 [1 ]= "CACHE",\ 345 [3 ]= "SPU",\ 346 [5 ]= "CLOCK_POWER",\ 347 [8 ]= "SERIAL0",\ 348 [9 ]= "SERIAL1",\ 349 [10]= "SPIM4",\ 350 [11]= "SERIAL2",\ 351 [12]= "SERIAL3",\ 352 [13]= "GPIOTE0",\ 353 [14]= "SAADC",\ 354 [15]= "TIMER0",\ 355 [16]= "TIMER1",\ 356 [17]= "TIMER2",\ 357 [20]= "RTC0",\ 358 [21]= "RTC1",\ 359 [24]= "WDT0",\ 360 [25]= "WDT1",\ 361 [26]= "COMP_LPCOMP",\ 362 [27]= "EGU0",\ 363 [28]= "EGU1",\ 364 [29]= "EGU2",\ 365 [30]= "EGU3",\ 366 [31]= "EGU4",\ 367 [32]= "EGU5",\ 368 [33]= "PWM0",\ 369 [34]= "PWM1",\ 370 [35]= "PWM2",\ 371 [36]= "PWM3",\ 372 [38]= "PDM0",\ 373 [40]= "I2S0",\ 374 [42]= "IPC",\ 375 [43]= "QSPI",\ 376 [45]= "NFCT",\ 377 [47]= "GPIOTE1",\ 378 [51]= "QDEC0",\ 379 [52]= "QDEC1",\ 380 [54]= "USBD",\ 381 [55]= "USBREGULATOR",\ 382 [57]= "KMU",\ 383 /*[68]= "CRYPTOCELL",*/\ 384 }, [1 /*Network core*/] = {\ 385 [5 ] = "CLOCK_POWER",\ 386 [8 ] = "RADIO",\ 387 [9 ] = "RNG",\ 388 [10] = "GPIOTE",\ 389 [11] = "WDT",\ 390 [12] = "TIMER0",\ 391 [13] = "ECB",\ 392 [14] = "AAR_CCM",\ 393 [16] = "TEMP",\ 394 [17] = "RTC0",\ 395 [18] = "IPC",\ 396 [19] = "SERIAL0",\ 397 [20] = "EGU0",\ 398 [22] = "RTC1",\ 399 [24] = "TIMER1",\ 400 [25] = "TIMER2",\ 401 [26] = "SWI0",\ 402 [27] = "SWI1",\ 403 [28] = "SWI2",\ 404 [29] = "SWI3",\ 405 }} 406 407 #define NHW_CORE_NAMES {"Application", "Network"} 408 409 #define NHW_NVMC_UICR_TOTAL_INST 2 410 #define NHW_NVMC_APP0 0 411 #define NHW_NVMC_NET0 1 412 #define NHW_UICR_APP0 0 413 #define NHW_UICR_NET0 1 414 #define NHW_NVMC_HAS_ERASEREGS 0 415 #define NHW_FLASH_START_ADDR {0x00000000, 0x01000000} 416 #define NHW_FLASH_PAGESIZE {(4*1024), (2*1024)} 417 #define NHW_FLASH_N_PAGES {256, 128} 418 #define NHW_UICR_SIZE {4096, 800 /*bytes*/} 419 //App UICR size including the KEYSLOT 420 #define NHW_NVMC_FLASH_T_ERASEALL (173000) 421 #define NHW_NVMC_FLASH_T_ERASEPAGE (87500) 422 #define NHW_NVMC_FLASH_T_WRITE (43) 423 #define NHW_NVMC_FLASH_PARTIAL_ERASE_FACTOR (1.0) 424 425 #define NHW_RADIO_TOTAL_INST 1 426 #define NHW_RADIO_NET0 0 427 #define NHW_RADIO_N_INT 1 428 #define NHW_RADIO_INT_MAP {{1 , 8}} /*Net core,RADIO_IRQn*/ 429 #define NHW_RADIO_DPPI_MAP {1} /*Network core*/ 430 #define NHW_RADIO_ED_RSSIOFFS (-93) 431 #define NHW_RADIO_IS_54 0 432 433 #define NHW_RNG_TOTAL_INST 1 434 #define NHW_RNG_NET_0 0 435 #define NHW_RNG_INT_MAP {{1, 9}} /*Network core, "RNG_IRQn"*/ 436 #define NHW_RNG_DPPI_MAP {1} /*Network core*/ 437 #define NHW_RNG_tRNG_START 128 438 #define NHW_RNG_tRNG_RAW 32 439 #define NHW_RNG_tRNG_BC 122 440 441 #define NHW_RTC_TOTAL_INST 4 442 #define NHW_RTC_APP0 0 443 #define NHW_RTC_APP1 1 444 #define NHW_RTC_NET0 2 445 #define NHW_RTC_NET1 3 446 #define NHW_RTC_INT_MAP {{0 , 20}, \ 447 {0 , 21}, \ 448 {1 , 17}, \ 449 {1 , 22}, \ 450 } /*App core,RTC0..1_IRQn*/ 451 /*Net core,RTC0..1_IRQn*/ 452 #define NHW_RTC_DPPI_MAP {0, 0, 1, 1} /*2xApp core, 2xNetwork core*/ 453 #define NHW_RTC_HAS_CAPTURE 1 454 #define NHW_RTC_HAS_SHORT_COMP_CLEAR 1 455 #define NHW_RTC_N_CC {4, 4, 4, 4} 456 457 #define NHW_SPU_TOTAL_INST 1 458 #define NHW_SPU_APP0 0 459 460 #define NHW_SWI_TOTAL_INST 4 461 #define NHW_SWI_NET0 0 462 #define NHW_SWI_NET1 1 463 #define NHW_SWI_NET2 2 464 #define NHW_SWI_NET3 3 465 466 #define NHW_TEMP_TOTAL_INST 1 467 #define NHW_TEMP_NET0 0 468 #define NHW_TEMP_INT_MAP {{1 , 16}} /*Net core,TEMP_IRQn*/ 469 #define NHW_TEMP_DPPI_MAP {1} /*Network core*/ 470 #define NHW_TEMP_t_TEMP 36 /* microseconds */ 471 #define NHW_TEMP_FBITS 2 /* fractional bits => 0.25C resolution */ 472 473 #define NHW_TIMER_TOTAL_INST 6 474 #define NHW_TIMER_APP0 0 475 #define NHW_TIMER_APP1 1 476 #define NHW_TIMER_APP2 2 477 #define NHW_TIMER_NET0 3 478 #define NHW_TIMER_NET1 4 479 #define NHW_TIMER_NET2 5 480 #define NHW_TIMER_INT_MAP {{0 , 15}, \ 481 {0 , 16}, \ 482 {0 , 17}, \ 483 {1 , 12}, \ 484 {1 , 24}, \ 485 {1 , 25}, \ 486 } /* AppCore, TIMER0..2_IRQn */ 487 /* NetCore, TIMER0..2_IRQn */ 488 #define NHW_TIMER_HAS_ONE_SHOT 1 489 #define NHW_TIMER_N_CC {6, 6, 6, 8, 8, 8} 490 #define NHW_TIMER_MAX_N_CC 8 491 #define NHW_TIMER_FREQ {16, 16, 16, 16, 16, 16} 492 #define NHW_TIMER_DPPI_MAP {0, 0, 0, 1, 1, 1} /*3xApp core, 3xNetwork core*/ 493 494 #define NHW_UARTE_TOTAL_INST 5 495 #define NHW_UARTE_APP0 0 496 #define NHW_UARTE_APP1 1 497 #define NHW_UARTE_APP2 2 498 #define NHW_UARTE_APP3 3 499 #define NHW_UARTE_NET0 4 500 #define NHW_UARTE_INT_MAP {{0 , 8}, \ 501 {0 , 9}, \ 502 {0 , 11}, \ 503 {0 , 12}, \ 504 {1 , 19}, \ 505 } /* App core, SERIAL0..3_IRQn, 506 Net core, SERIAL0_IRQn */ 507 #define NHW_UARTE_DPPI_MAP {0, 0, 0, 0, 1} /*4xApp core, 1xNetwork core*/ 508 #define NHW_UARTE_HAS_UART 0 509 #define NHW_UARTE_NAMES {"App UARTE0", \ 510 "App UARTE1", \ 511 "App UARTE2", \ 512 "App UARTE3", \ 513 "Net UARTE0"} 514 #define NHW_UARTE_54NAMING 0 515 #define NHW_UARTE_FLUSH_AMOUNT_BUG 0 516 #define NHW_UARTE_HAS_FRAMETIMEOUT 0 517 #define NHW_UARTE_HAS_MATCH 0 518 #define NHW_UARTE_CLOCKS {16, 16, 16, 16, 16} 519 520 #define NHW_FAKE_TIMER_TOTAL_INST 2 521 #define NHW_FAKE_TIMER_INT_MAP {{0 , 0}, \ 522 {1 , 0}} /*App core & Net core, -*/ 523 524 #define NHW_BSTICKER_TOTAL_INST 2 525 #define NHW_BSTICKER_TIMER_INT_MAP {{0 , 0}, \ 526 {1 , 0}} /*App core & Net core, -*/ 527 528 #define NHW_APPCORE_RAM_ADDR 0x20000000 529 #define NHW_APPCORE_RAM_SIZE 0x80000 /*512KiB*/ 530 531 /*************************************************************************/ 532 /*************************************************************************/ 533 /*************************************************************************/ 534 #elif defined(NRF54L15) || defined(NRF54L15_XXAA) 535 536 #define NHW_HAS_PPI 0 537 #define NHW_HAS_DPPI 1 538 #define NHW_USE_MDK_TYPES 1 /* The HW registers layout types are taken from the MDK */ 539 #define NHW_CORE_NAMES {"Application", "Flipper"} 540 541 #define NHW_AARCCMECB_TOTAL_INST 1 542 #define NHW_AARCCMECB_00 0 543 #define NHW_AARCCMECB_DPPI_MAP {0} /* Global */ 544 #define NHW_AARCCM_INTMAP {{0, 70}} 545 /* AAR00_CCM00_IRQn */ 546 #define NHW_ECB_INTMAP {{0, 71}} 547 /* ECB00_IRQn */ 548 #define NHW_AARCCMECB_CLOCK {128} /* MHz */ 549 #define NHW_ECB_t_ECB {1} /* In micros (~73cc/128MHz in real HW)*/ 550 551 #define NHW_CLKPWR_TOTAL_INST 1 552 #define NHW_CLKPWR_0 0 553 #define NHW_CLKPWR_DPPI_MAP {0} /* Global */ 554 #define NHW_CLKPWR_INT_MAP {{0, 261}} /* {App, CLOCK_POWER_IRQn} */ 555 556 #define NHW_CRACEN_TOTAL_INST 1 557 /* #define NHW_CRACEN_DDPI_MAP no PPI events from CRACEN */ 558 #define NHW_CRACEN_INT_MAP {{0, 72}} /* {App, CRACEN_IRQn} */ 559 #define NHW_CRACEN_RNG_G_log2fifodepth 4 /* log2 of the FIFO depth in 32bit words */ 560 #define NHW_CRACEN_FREQ_MHZ 128 561 #define NHW_CRACEN_STARTUPTEST_DUR 4 /*In microseconds duration of the startup tests and other start overhead */ 562 #define NHW_CRACEN_CM_AES_t_ECB {1, 1, 1} /* In microseconds time it takes for key size of 128, 192 and 256 */ 563 /* The real time would be < ~0.25 micros for the ECB itself and another so much for the DMA */ 564 565 #define NHW_DPPI_TOTAL_INST 4 566 #define NHW_DPPI_00 0 /* Global */ 567 #define NHW_DPPI_10 1 /* Radio */ 568 #define NHW_DPPI_20 2 /* Peri */ 569 #define NHW_DPPI_30 3 /* LP */ 570 /* The DPPI does not generate interrupts */ 571 #define NHW_DPPI_DPPI_MAP {0, 1, 2, 3} /* DPPI connect to themselves */ 572 #define NHW_DPPI_N_CH {8, 24, 16, 4} /* Number of channels in each DPPI */ 573 #define NHW_DPPI_N_CHG {2, 6, 6, 2} /* Number of channel groups in each DPPI */ 574 575 #define NHW_EGU_TOTAL_INST 2 576 #define NHW_EGU_10 0 577 #define NHW_EGU_20 1 578 #define NHW_EGU_INT_MAP {{0 , 135}, \ 579 {0 , 201}, \ 580 } 581 /* {App, EGU10} 582 * {App, EGU20} 583 * */ 584 #define NHW_EGU_DPPI_MAP {1, 2} /* Radio, Peri */ 585 #define NHW_EGU_N_EVENTS {16, 6} 586 587 #define NHW_GPIO_TOTAL_INST 3 588 #define NHW_GPIO_P0 0 589 #define NHW_GPIO_P1 1 590 #define NHW_GPIO_P2 2 591 #define NHW_GPIO_MAX_PINS_PER_PORT 32 592 #define NHW_GPIO_NBR_PINS {7, 17, 11} /* Number of IOs per port */ 593 #define NHW_GPIO_PARTNER_GPIOTE {1, 0, -1} /* P0->GPIOTE30, P1->GPIOTE20, P2->nothing */ 594 #define NHW_GPIO_HAS_PIN_SENSE {1, 1, 0} /* Per instance, does it have pin sense/detect mechanism */ 595 596 #define NHW_GPIOTE_TOTAL_INST 2 597 #define NHW_GPIOTE_20 0 598 #define NHW_GPIOTE_30 1 599 #define NHW_GPIOTE_MAX_CHANNELS 8 /* Maximum number of channels in any instance */ 600 #define NHW_GPIOTE_CHANNELS {8, 4} /* Number of channels per instance */ 601 #define NHW_GPIOTE_N_INT 2 /* Number of interrupts lines, common for all instances */ 602 #define NHW_GPIOTE_INT_MAP {{{0, 218}, \ 603 {0, 219}}, \ 604 {{0, 268}, \ 605 {0, 269}}} 606 /* App, GPIOTE20_0_IRQn */ 607 /* App, GPIOTE20_1_IRQn */ 608 /* App, GPIOTE30_0_IRQn */ 609 /* App, GPIOTE30_1_IRQn */ 610 #define NHW_GPIOTE_DPPI_MAP {2, 3} /* GPIOTE20 in Peri , GPIOTE30 in LP */ 611 #define NHW_GPIOTE_IS_54 1 612 613 #define NHW_GRTC_TOTAL_INST 1 614 #define NHW_GRTC_N_INT 4 615 #define NHW_GRTC_INT_MAP { \ 616 {0 , 226}, \ 617 {0 , 227}, \ 618 {0 , 228}, \ 619 {0 , 229}, \ 620 } 621 /* {App, GRTC_0..3_IRQn} */ 622 #define NHW_GRTC_DPPI_MAP {2 /* Peripheral domain */} 623 #define NHW_GRTC_N_CC 12 624 #define NHW_GRTC_N_DOMAINS 4 625 #define NHW_GRTC_SYSCOUNTER_BW 52 626 #define NHW_GRTC_HAS_CLKOUT 0 627 #define NHW_GRTC_HAS_PWM 1 628 629 630 #define NHW_INTCTRL_TOTAL_INST 2 631 #define NHW_INTCTRL_MAX_INTLINES 271 632 633 /* These names are taken from the IRQn_Type in the MDK header */ 634 #define NHW_INT_NAMES { [0 /*Application core*/] = {\ 635 [28 ]="SWI00",\ 636 [29 ]="SWI01",\ 637 [30 ]="SWI02",\ 638 [31 ]="SWI03",\ 639 [64 ]="SPU00",\ 640 [65 ]="MPC00",\ 641 [70 ]="AAR00_CCM00",\ 642 [71 ]="ECB00",\ 643 [72 ]="CRACEN",\ 644 [74 ]="SERIAL00",\ 645 [75 ]="RRAMC",\ 646 [76 ]="VPR00",\ 647 [82 ]="CTRLAP",\ 648 [83 ]="CM33SS",\ 649 [85 ]="TIMER00",\ 650 [128]="SPU10",\ 651 [133]="TIMER10",\ 652 [134]="-",\ 653 [135]="EGU10",\ 654 [138]="RADIO_0",\ 655 [139]="RADIO_1",\ 656 [192]="SPU20",\ 657 [198]="SERIAL20",\ 658 [199]="SERIAL21",\ 659 [200]="SERIAL22",\ 660 [201]="EGU20",\ 661 [202]="TIMER20",\ 662 [203]="TIMER21",\ 663 [204]="TIMER22",\ 664 [205]="TIMER23",\ 665 [206]="TIMER24",\ 666 [208]="PDM20",\ 667 [209]="PDM21",\ 668 [210]="PWM20",\ 669 [211]="PWM21",\ 670 [212]="PWM22",\ 671 [213]="SAADC",\ 672 [214]="NFCT",\ 673 [215]="TEMP",\ 674 [218]="GPIOTE20_0",\ 675 [219]="GPIOTE20_1",\ 676 [220]="TAMPC",\ 677 [221]="I2S20",\ 678 [224]="QDEC20",\ 679 [225]="QDEC21",\ 680 [226]="GRTC_0",\ 681 [227]="GRTC_1",\ 682 [228]="GRTC_2",\ 683 [229]="GRTC_3",\ 684 [256]="SPU30",\ 685 [260]="SERIAL30",\ 686 [261]="CLOCK_POWER",\ 687 [262]="COMP_LPCOMP",\ 688 [264]="WDT30",\ 689 [265]="WDT31",\ 690 [268]="GPIOTE30_0",\ 691 [269]="GPIOTE30_1",\ 692 [270]="CLOCK_POWER",\ 693 }, [1 /*Flipper core*/] = {\ 694 [0 ]="VPRCLIC_0",\ 695 [1 ]="VPRCLIC_1",\ 696 [2 ]="VPRCLIC_2",\ 697 [3 ]="VPRCLIC_3",\ 698 [4 ]="VPRCLIC_4",\ 699 [5 ]="VPRCLIC_5",\ 700 [6 ]="VPRCLIC_6",\ 701 [7 ]="VPRCLIC_7",\ 702 [8 ]="VPRCLIC_8",\ 703 [9 ]="VPRCLIC_9",\ 704 [10 ]="VPRCLIC_10",\ 705 [11 ]="VPRCLIC_11",\ 706 [12 ]="VPRCLIC_12",\ 707 [13 ]="VPRCLIC_13",\ 708 [14 ]="VPRCLIC_14",\ 709 [15 ]="VPRCLIC_15",\ 710 [16 ]="VPRCLIC_16",\ 711 [17 ]="VPRCLIC_17",\ 712 [18 ]="VPRCLIC_18",\ 713 [19 ]="VPRCLIC_19",\ 714 [20 ]="VPRCLIC_20",\ 715 [21 ]="VPRCLIC_21",\ 716 [22 ]="VPRCLIC_22",\ 717 [23 ]="VPRCLIC_23",\ 718 [24 ]="VPRCLIC_24",\ 719 [25 ]="VPRCLIC_25",\ 720 [26 ]="VPRCLIC_26",\ 721 [27 ]="VPRCLIC_27",\ 722 [28 ]="VPRCLIC_28",\ 723 [29 ]="VPRCLIC_29",\ 724 [30 ]="VPRCLIC_30",\ 725 [31 ]="VPRCLIC_31",\ 726 [64 ]="SPU00",\ 727 [65 ]="MPC00",\ 728 [70 ]="AAR00_CCM00",\ 729 [71 ]="ECB00",\ 730 [72 ]="CRACEN",\ 731 [74 ]="SERIAL00",\ 732 [75 ]="RRAMC",\ 733 [76 ]="VPR00",\ 734 [82 ]="CTRLAP",\ 735 [85 ]="TIMER00",\ 736 [128]="SPU10",\ 737 [133]="TIMER10",\ 738 [134]="-",\ 739 [135]="EGU10",\ 740 [138]="RADIO_0",\ 741 [139]="RADIO_1",\ 742 [192]="SPU20",\ 743 [198]="SERIAL20",\ 744 [199]="SERIAL21",\ 745 [200]="SERIAL22",\ 746 [201]="EGU20",\ 747 [202]="TIMER20",\ 748 [203]="TIMER21",\ 749 [204]="TIMER22",\ 750 [205]="TIMER23",\ 751 [206]="TIMER24",\ 752 [208]="PDM20",\ 753 [209]="PDM21",\ 754 [210]="PWM20",\ 755 [211]="PWM21",\ 756 [212]="PWM22",\ 757 [213]="SAADC",\ 758 [214]="NFCT",\ 759 [215]="TEMP",\ 760 [218]="GPIOTE20_0",\ 761 [219]="GPIOTE20_1",\ 762 [220]="TAMPC",\ 763 [221]="I2S20",\ 764 [224]="QDEC20",\ 765 [225]="QDEC21",\ 766 [226]="GRTC_0",\ 767 [227]="GRTC_1",\ 768 [228]="GRTC_2",\ 769 [229]="GRTC_3",\ 770 [256]="SPU30",\ 771 [260]="SERIAL30",\ 772 [261]="CLOCK_POWER",\ 773 [262]="COMP_LPCOMP",\ 774 [264]="WDT30",\ 775 [265]="WDT31",\ 776 [268]="GPIOTE30_0",\ 777 [269]="GPIOTE30_1",\ 778 [270]="CLOCK_POWER",\ 779 }} 780 781 #define NHW_PPIB_TOTAL_INST 8 782 #define NHW_PPIB_00 0 783 #define NHW_PPIB_01 1 784 #define NHW_PPIB_10 2 785 #define NHW_PPIB_11 3 786 #define NHW_PPIB_20 4 787 #define NHW_PPIB_21 5 788 #define NHW_PPIB_22 6 789 #define NHW_PPIB_30 7 790 #define NHW_PPIB_DPPI_MAP {0, 0, 1, 1, 2, 2, 2, 3} 791 #define NHW_PPIB_N_CH {8, 8, 8, 16, 8, 16, 4, 4} 792 #define NHW_PPIB_MATE {2,/*00->10*/ \ 793 4,/*01->20*/ \ 794 0,/*10->00*/ \ 795 5,/*11->21*/ \ 796 1,/*20->01*/ \ 797 3,/*21->11*/ \ 798 7,/*22->30*/ \ 799 6,/*30->22*/ \ 800 } 801 #define HWH_PPIB_HARDWIRESCHANNELS 0 802 803 #define NHW_RADIO_TOTAL_INST 1 804 #define NHW_RADIO_0 0 805 #define NHW_RADIO_N_INT 2 806 #define NHW_RADIO_INT_MAP {{0 , 138}, \ 807 {0 , 139}} 808 /*{App, RADIO_0_IRQn}, 809 *{App, RADIO_1_IRQn} */ 810 #define NHW_RADIO_DPPI_MAP {1} /* Radio domain */ 811 #define NHW_RADIO_ED_RSSIOFFS (-92) 812 #define NHW_RADIO_IS_54 1 813 814 #define NHW_RRAMC_UICR_TOTAL_INST 1 815 #define NHW_RRAM_START_ADDR {0x00000000} 816 #define NHW_RRAM_SIZE {(1524*1024)} 817 #define NHW_UICR_SIZE {2560 /*bytes*/} 818 819 #define NHW_SPU_TOTAL_INST 4 820 #define NHW_SPU_00 0 821 #define NHW_SPU_10 1 822 #define NHW_SPU_20 2 823 #define NHW_SPU_30 3 824 825 #define NHW_SWI_TOTAL_INST 4 826 827 #define NHW_TEMP_TOTAL_INST 1 828 #define NHW_TEMP_APP0 0 829 #define NHW_TEMP_INT_MAP {{0 , 215}} /*App core,TEMP_IRQn*/ 830 #define NHW_TEMP_DPPI_MAP {2} /*Peri domain*/ 831 #define NHW_TEMP_t_TEMP 36 /* microseconds, Unknown, assuming by now same as 52833 & 5340 */ 832 #define NHW_TEMP_FBITS 2 /* fractional bits => 0.25C resolution */ 833 834 #define NHW_TIMER_TOTAL_INST 7 835 #define NHW_TIMER_00 0 836 #define NHW_TIMER_10 1 837 #define NHW_TIMER_20 2 838 #define NHW_TIMER_21 3 839 #define NHW_TIMER_22 4 840 #define NHW_TIMER_23 5 841 #define NHW_TIMER_24 6 842 #define NHW_TIMER_INT_MAP {{0 , 85}, \ 843 {0 , 133}, \ 844 {0 , 202}, \ 845 {0 , 203}, \ 846 {0 , 204}, \ 847 {0 , 205}, \ 848 {0 , 206}, \ 849 } /* App, TIMER00..24_IRQn */ 850 #define NHW_TIMER_HAS_ONE_SHOT 1 851 #define NHW_TIMER_N_CC {6, 8, 6, 6, 6, 6, 6} 852 #define NHW_TIMER_MAX_N_CC 8 853 #define NHW_TIMER_FREQ {128, 32, 16, 16, 16, 16, 16} 854 #define NHW_TIMER_DPPI_MAP {0, 1, 2, 2, 2, 2, 2} 855 856 857 #define NHW_UARTE_TOTAL_INST 5 858 #define NHW_UARTE00 0 859 #define NHW_UARTE20 1 860 #define NHW_UARTE21 2 861 #define NHW_UARTE22 3 862 #define NHW_UARTE30 4 863 #define NHW_UARTE_INT_MAP {{0 , 74}, \ 864 {0 , 198}, \ 865 {0 , 199}, \ 866 {0 , 200}, \ 867 {0 , 260}, \ 868 } /* App, SERIAL00_IRQn, 869 App, SERIAL20_IRQn, 870 App, SERIAL21_IRQn, 871 App, SERIAL22_IRQn, 872 App, SERIAL30_IRQn, 873 */ 874 #define NHW_UARTE_DPPI_MAP {0, 2, 2, 2, 3} /* Global, 4xPeri, LP */ 875 #define NHW_UARTE_HAS_UART 0 876 #define NHW_UARTE_HAS_FRAMETIMEOUT 1 877 #define NHW_UARTE_HAS_MATCH 1 878 #define NHW_UARTE_N_MATCH {4, 4, 4, 4, 4} 879 #define NHW_UARTE_MAX_N_MATCH 4 880 #define NHW_UARTE_NAMES {"UARTE00", \ 881 "UARTE20", \ 882 "UARTE21", \ 883 "UARTE22", \ 884 "UARTE30"} 885 #define NHW_UARTE_54NAMING 1 886 #define NHW_UARTE_FLUSH_AMOUNT_BUG 0 887 #define NHW_UARTE_CLOCKS {128, 16, 16, 16, 16} 888 889 #define NHW_FAKE_TIMER_TOTAL_INST 2 890 #define NHW_FAKE_TIMER_INT_MAP {{0 , 0}, \ 891 {1 , 0}} /*App core & flpr core, -*/ 892 893 #define NHW_BSTICKER_TOTAL_INST 2 894 #define NHW_BSTICKER_TIMER_INT_MAP {{0 , 0}, \ 895 {1 , 0}} /*App core & flpr core, -*/ 896 897 #else 898 #error "No valid platform was selected" 899 #endif 900 901 #endif /* _NRF_HW_CONFIG_H */ 902
