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Searched refs:mask (Results 1 – 22 of 22) sorted by relevance

/nrf_hw_models-3.7.0/src/nrfx/hal/
Dnrf_temp.c25 void nrf_temp_int_enable(NRF_TEMP_Type * p_reg, uint32_t mask) in nrf_temp_int_enable() argument
27 NRF_TEMP_regs.INTENSET = mask; in nrf_temp_int_enable()
31 void nrf_temp_int_disable(NRF_TEMP_Type * p_reg, uint32_t mask) in nrf_temp_int_disable() argument
33 NRF_TEMP_regs.INTENCLR = mask; in nrf_temp_int_disable()
Dnrf_rng.c27 void nrf_rng_int_enable(NRF_RNG_Type * p_reg, uint32_t mask) in nrf_rng_int_enable() argument
29 NRF_RNG_regs.INTENSET = mask; in nrf_rng_int_enable()
33 void nrf_rng_int_disable(NRF_RNG_Type * p_reg, uint32_t mask) in nrf_rng_int_disable() argument
35 NRF_RNG_regs.INTENCLR = mask; in nrf_rng_int_disable()
Dnrf_ecb.c25 void nrf_ecb_int_enable(NRF_ECB_Type * p_reg, uint32_t mask) in nrf_ecb_int_enable() argument
27 p_reg->INTENSET = mask; in nrf_ecb_int_enable()
31 void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask) in nrf_ecb_int_disable() argument
33 p_reg->INTENCLR = mask; in nrf_ecb_int_disable()
Dnrf_aar.c13 void nrf_aar_int_enable(NRF_AAR_Type * p_reg, uint32_t mask) in nrf_aar_int_enable() argument
15 p_reg->INTENSET = mask; in nrf_aar_int_enable()
19 void nrf_aar_int_disable(NRF_AAR_Type * p_reg, uint32_t mask) in nrf_aar_int_disable() argument
21 p_reg->INTENCLR = mask; in nrf_aar_int_disable()
Dnrf_radio.c49 void nrf_radio_int_enable(NRF_RADIO_Type * p_reg, uint32_t mask) in nrf_radio_int_enable() argument
52 p_reg->INTENSET = mask; in nrf_radio_int_enable()
54 p_reg->INTENSET00 = mask; in nrf_radio_int_enable()
59 void nrf_radio_int_disable(NRF_RADIO_Type * p_reg, uint32_t mask) in nrf_radio_int_disable() argument
62 p_reg->INTENCLR = mask; in nrf_radio_int_disable()
64 p_reg->INTENCLR00 = mask; in nrf_radio_int_disable()
Dnrf_ccm.c28 void nrf_ccm_int_enable(NRF_CCM_Type * p_reg, uint32_t mask) in nrf_ccm_int_enable() argument
30 p_reg->INTENSET = mask; in nrf_ccm_int_enable()
34 void nrf_ccm_int_disable(NRF_CCM_Type * p_reg, uint32_t mask) in nrf_ccm_int_disable() argument
36 p_reg->INTENCLR = mask; in nrf_ccm_int_disable()
Dnrf_rtc.c25 void nrf_rtc_int_enable(NRF_RTC_Type * p_reg, uint32_t mask) in nrf_rtc_int_enable() argument
28 p_reg->INTENSET = mask; in nrf_rtc_int_enable()
32 void nrf_rtc_int_disable(NRF_RTC_Type * p_reg, uint32_t mask) in nrf_rtc_int_disable() argument
35 p_reg->INTENCLR = mask; in nrf_rtc_int_disable()
78 void nrf_rtc_event_enable(NRF_RTC_Type * p_reg, uint32_t mask) in nrf_rtc_event_enable() argument
81 p_reg->EVTENSET = mask; in nrf_rtc_event_enable()
Dnrf_ipc.c34 void nrf_ipc_int_enable(NRF_IPC_Type * p_reg, uint32_t mask) in nrf_ipc_int_enable() argument
36 p_reg->INTENSET = mask; in nrf_ipc_int_enable()
42 void nrf_ipc_int_disable(NRF_IPC_Type * p_reg, uint32_t mask) in nrf_ipc_int_disable() argument
44 p_reg->INTENCLR = mask; in nrf_ipc_int_disable()
Dnrf_egu.c37 void nrf_egu_int_enable(NRF_EGU_Type * p_reg, uint32_t mask) in nrf_egu_int_enable() argument
39 p_reg->INTENSET = mask; in nrf_egu_int_enable()
45 void nrf_egu_int_disable(NRF_EGU_Type * p_reg, uint32_t mask) in nrf_egu_int_disable() argument
47 p_reg->INTENCLR = mask; in nrf_egu_int_disable()
Dnrf_ppi.c24 void nrf_ppi_channels_enable(NRF_PPI_Type * p_reg, uint32_t mask) in nrf_ppi_channels_enable() argument
26 p_reg->CHENSET = mask; in nrf_ppi_channels_enable()
30 void nrf_ppi_channels_disable(NRF_PPI_Type * p_reg, uint32_t mask) in nrf_ppi_channels_disable() argument
32 p_reg->CHENCLR = mask; in nrf_ppi_channels_disable()
Dnrf_timer.c64 uint32_t mask) in nrf_timer_int_enable() argument
67 p_reg->INTENSET = mask; in nrf_timer_int_enable()
72 uint32_t mask) in nrf_timer_int_disable() argument
75 p_reg->INTENCLR = mask; in nrf_timer_int_disable()
Dnrf_uarte.c41 void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask) in nrf_uarte_int_enable() argument
44 p_reg->INTENSET = mask; in nrf_uarte_int_enable()
48 void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask) in nrf_uarte_int_disable() argument
51 p_reg->INTENCLR = mask; in nrf_uarte_int_disable()
Dnrf_clock.c25 void nrf_clock_int_enable(NRF_CLOCK_Type * p_reg, uint32_t mask) in nrf_clock_int_enable() argument
27 p_reg->INTENSET = mask; in nrf_clock_int_enable()
33 void nrf_clock_int_disable(NRF_CLOCK_Type * p_reg, uint32_t mask) in nrf_clock_int_disable() argument
35 p_reg->INTENCLR = mask; in nrf_clock_int_disable()
Dnrf_uart.c41 void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t mask) in nrf_uart_int_enable() argument
44 p_reg->INTENSET = mask; in nrf_uart_int_enable()
48 void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t mask) in nrf_uart_int_disable() argument
51 p_reg->INTENCLR = mask; in nrf_uart_int_disable()
Dnrf_gpiote.c80 void nrf_gpiote_int_enable(NRF_GPIOTE_Type * p_reg, uint32_t mask) in nrf_gpiote_int_enable() argument
82 p_reg->NRFX_CONCAT_2(INTENSET, NRF_GPIOTE_IRQ_GROUP) = mask; in nrf_gpiote_int_enable()
87 void nrf_gpiote_int_disable(NRF_GPIOTE_Type * p_reg, uint32_t mask) in nrf_gpiote_int_disable() argument
89 p_reg->NRFX_CONCAT_2(INTENCLR, NRF_GPIOTE_IRQ_GROUP) = mask; in nrf_gpiote_int_disable()
Dnrf_dppi.c45 void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask) in nrf_dppi_channels_enable() argument
47 p_reg->CHENSET = mask; in nrf_dppi_channels_enable()
53 void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask) in nrf_dppi_channels_disable() argument
55 p_reg->CHENCLR = mask; in nrf_dppi_channels_disable()
Dnrf_grtc.c49 void nrf_grtc_int_enable(NRF_GRTC_Type * p_reg, uint32_t mask) in nrf_grtc_int_enable() argument
51 p_reg->GRTC_INTENSET = mask; in nrf_grtc_int_enable()
55 void nrf_grtc_int_disable(NRF_GRTC_Type * p_reg, uint32_t mask) in nrf_grtc_int_disable() argument
57 p_reg->GRTC_INTENCLR = mask; in nrf_grtc_int_disable()
/nrf_hw_models-3.7.0/src/HW_models/
DNRF_GPIOTE.c120 int mask; in nrf_gpiote_eval_interrupt() local
123 mask = (GPIOTE_ITEN >> i) & 0x1; in nrf_gpiote_eval_interrupt()
124 if (NRF_GPIOTE_regs.EVENTS_IN[i] && mask) { in nrf_gpiote_eval_interrupt()
129 mask = (GPIOTE_ITEN & GPIOTE_INTENCLR_PORT_Msk) >> GPIOTE_INTENCLR_PORT_Pos; in nrf_gpiote_eval_interrupt()
130 if (NRF_GPIOTE_regs.EVENTS_PORT && mask) { in nrf_gpiote_eval_interrupt()
DNRF_GPIO.c207 uint32_t mask = 1<<n; in nrf_gpio_peri_pin_control() local
212 out_override[port] &= ~mask; in nrf_gpio_peri_pin_control()
217 input_override[port] &= ~mask; in nrf_gpio_peri_pin_control()
220 input_override_connected[port] &= ~mask; in nrf_gpio_peri_pin_control()
226 dir_override[port] &= ~mask; in nrf_gpio_peri_pin_control()
229 dir_override_set[port] &= ~mask; in nrf_gpio_peri_pin_control()
Dirq_ctrl.h21 void nhw_irq_controller_set_irq_mask(unsigned int inst, uint64_t mask);
DNHW_RTC.c574 int mask = this->INTEN & (RTC_INTENSET_COMPARE0_Msk << cc); in nhw_rtc_eval_interrupts() local
575 if (NRF_RTC_regs[rtc].EVENTS_COMPARE[cc] && mask) { in nhw_rtc_eval_interrupts()
614 uint32_t mask = RTC_EVTEN_COMPARE0_Msk << cc; in nhw_rtc_signal_COMPARE() local
616 if (!((RTC_regs->EVTEN | this->INTEN) & mask)) { in nhw_rtc_signal_COMPARE()
622 if (RTC_regs->EVTEN & mask) { in nhw_rtc_signal_COMPARE()
DNHW_TIMER.c244 int mask = this->INTEN & (TIMER_INTENSET_COMPARE0_Msk << cc); in nhw_timer_eval_interrupts() local
245 if (NRF_TIMER_regs[t].EVENTS_COMPARE[cc] && mask) { in nhw_timer_eval_interrupts()