1 /* 2 * Copyright (c) 2023 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * This file configures the HW models based on the variant being built 7 */ 8 #ifndef _NRF_HW_CONFIG_H 9 #define _NRF_HW_CONFIG_H 10 11 /* 12 * For each peripheral the following may be defined 13 * NHW_<PERIPH_TYPE>_TOTAL_INST <val> : Total number of instances of the peripheral in the whole SOC 14 * NHW_<PERIPH_TYPE>_<CORE>_<INST> <val> : Index of that peripheral instant in list of peripherals 15 * 16 * NHW_<PERIPH_TYPE>_INT_MAP : List of irq controller mapping, for each instante: {irq ctrl number, irq line} 17 */ 18 19 #if defined(NRF52833) || defined(NRF52833_XXAA) 20 21 #define NHW_CORE_NAMES {""} 22 23 #define NHW_HAS_PPI 1 24 #define NHW_HAS_DPPI 0 25 #define NHW_USE_MDK_TYPES 1 /* The HW registers layout types are taken from the MDK */ 26 27 #define NHW_AAR_TOTAL_INST 1 28 #define NHW_AAR_0 0 29 #define NHW_AAR_INT_MAP {{0 , 15}} /*Only core,CCM_AAR_IRQn*/ 30 #define NHW_AAR_t_AAR 6 31 32 #define NHW_CCM_TOTAL_INST 1 33 #define NHW_CCM_0 0 34 #define NHW_CCM_INT_MAP {{0 , 15}} /*Only core,CCM_AAR_IRQn*/ 35 36 #define NHW_CLKPWR_TOTAL_INST 1 37 #define NHW_CLKPWR_0 0 38 #define NHW_CLKPWR_INT_MAP {{0 , 0}} /*Only core, POWER_CLOCK_IRQn*/ 39 #define NHW_CLKPWR_HAS_RESET 0 40 #define NHW_CLKPWR_HAS_CALTIMER 1 41 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK 0 42 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK_I {0} 43 #define NHW_CLKPWR_HAS_HFCLK192MCLK 0 44 #define NHW_CLKPWR_HAS_HFCLK192MCLK_I {0} 45 46 #define NHW_ECB_TOTAL_INST 1 47 #define NHW_ECB_0 0 48 #define NHW_ECB_INT_MAP {{0 , 14}} /*Only core,ECB_IRQn*/ 49 #define NHW_ECB_t_ECB 7 /* 7.2 */ 50 51 #define NHW_EGU_TOTAL_INST 6 52 #define NHW_EGU_0 0 53 #define NHW_EGU_1 1 54 #define NHW_EGU_2 2 55 #define NHW_EGU_3 3 56 #define NHW_EGU_4 4 57 #define NHW_EGU_5 5 58 #define NHW_EGU_INT_MAP {{0 , 20}, \ 59 {0 , 21}, \ 60 {0 , 22}, \ 61 {0 , 23}, \ 62 {0 , 24}, \ 63 {0 , 25}, \ 64 } /*Only core,SWI0..5_EGU0_IRQn*/ 65 #define NHW_EGU_N_EVENTS {16, 16, 16, 16, 16, 16} 66 67 #define NHW_GPIOTE_TOTAL_INST 1 68 #define NHW_GPIOTE_0 0 69 #define NHW_GPIOTE_INT_MAP {{0 , 6}} /*Only core,GPIOTE_IRQn*/ 70 71 #define NHW_INTCTRL_TOTAL_INST 1 72 #define NHW_INTCTRL_MAX_INTLINES 48 73 74 /* These names are taken from the IRQn_Type in the MDK header */ 75 #define NHW_INT_NAMES { [0] = {\ 76 [0 ] = "POWER_CLOCK",\ 77 [1 ] = "RADIO",\ 78 [2 ] = "UARTE0_UART0",\ 79 [3 ] = "SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0",\ 80 [4 ] = "SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1",\ 81 [5 ] = "NFCT",\ 82 [6 ] = "GPIOTE",\ 83 [7 ] = "SAADC",\ 84 [8 ] = "TIMER0",\ 85 [9 ] = "TIMER1",\ 86 [10] = "TIMER2",\ 87 [11] = "RTC0",\ 88 [12] = "TEMP",\ 89 [13] = "RNG",\ 90 [14] = "ECB",\ 91 [15] = "CCM_AAR",\ 92 [16] = "WDT",\ 93 [17] = "RTC1",\ 94 [18] = "QDEC",\ 95 [19] = "COMP_LPCOMP",\ 96 [20] = "SWI0_EGU0",\ 97 [21] = "SWI1_EGU1",\ 98 [22] = "SWI2_EGU2",\ 99 [23] = "SWI3_EGU3",\ 100 [24] = "SWI4_EGU4",\ 101 [25] = "SWI5_EGU5",\ 102 [26] = "TIMER3",\ 103 [27] = "TIMER4",\ 104 [28] = "PWM0",\ 105 [29] = "PDM",\ 106 [32] = "MWU",\ 107 [33] = "PWM1",\ 108 [34] = "PWM2",\ 109 [35] = "SPIM2_SPIS2_SPI2",\ 110 [36] = "RTC2",\ 111 [37] = "I2S",\ 112 [38] = "FPU",\ 113 [39] = "USBD",\ 114 [40] = "UARTE1",\ 115 [45] = "PWM3",\ 116 [47] = "SPIM3",\ 117 }} 118 119 #define NHW_NVMC_UICR_TOTAL_INST 1 120 #define NHW_NVMC_HAS_ERASEREGS 1 121 #define NHW_FLASH_START_ADDR {0x00000000} 122 #define NHW_FLASH_PAGESIZE {(4*1024)} 123 #define NHW_FLASH_N_PAGES {128} 124 #define NHW_UICR_SIZE {776 /*64*4*/ /*bytes*/} 125 /* In case somebody tries to access the UICR registers, we book 126 * more space than its actual flash area (64*4)*/ 127 #define NHW_NVMC_FLASH_T_ERASEALL (173000) 128 #define NHW_NVMC_FLASH_T_ERASEPAGE (87500) 129 #define NHW_NVMC_FLASH_T_WRITE (42) 130 #define NHW_NVMC_FLASH_PARTIAL_ERASE_FACTOR (1.0) 131 132 #define NHW_RADIO_TOTAL_INST 1 133 #define NHW_RADIO_0 0 134 #define NHW_RADIO_N_INT 1 135 #define NHW_RADIO_INT_MAP {{0 , 1}} /*Only core,RADIO_IRQn*/ 136 #define NHW_RADIO_ED_RSSIOFFS (-93) 137 #define NHW_RADIO_IS_54 0 138 139 #define NHW_RNG_TOTAL_INST 1 140 #define NHW_RNG_0 0 141 #define NHW_RNG_INT_MAP {{0 , 13}} /*Only core,RNG_IRQn*/ 142 #define NHW_RNG_tRNG_START 128 143 #define NHW_RNG_tRNG_RAW 30 144 #define NHW_RNG_tRNG_BC 120 145 146 #define NHW_RTC_TOTAL_INST 3 147 #define NHW_RTC_0 0 148 #define NHW_RTC_1 1 149 #define NHW_RTC_2 2 150 #define NHW_RTC_INT_MAP {{0 , 11}, \ 151 {0 , 17}, \ 152 {0 , 36}, \ 153 } /*Only core,RTC0..2_IRQn*/ 154 #define NHW_RTC_HAS_CAPTURE 0 155 #define NHW_RTC_HAS_SHORT_COMP_CLEAR 0 156 #define NHW_RTC_N_CC {3, 4, 4} 157 158 #define NHW_TEMP_TOTAL_INST 1 159 #define NHW_TEMP_0 0 160 #define NHW_TEMP_INT_MAP {{0 , 12}} /*Only core,TEMP_IRQn*/ 161 #define NHW_TEMP_t_TEMP 36 /* microseconds */ 162 #define NHW_TEMP_FBITS 2 /* fractional bits => 0.25C resolution */ 163 164 #define NHW_TIMER_TOTAL_INST 5 165 #define NHW_TIMER_0 0 166 #define NHW_TIMER_1 1 167 #define NHW_TIMER_2 2 168 #define NHW_TIMER_3 3 169 #define NHW_TIMER_4 4 170 #define NHW_TIMER_INT_MAP {{0 , 8}, \ 171 {0 , 9}, \ 172 {0 , 10}, \ 173 {0 , 26}, \ 174 {0 , 27}, \ 175 } /* Only core, TIMER0..4_IRQn */ 176 #define NHW_TIMER_HAS_ONE_SHOT 0 177 #define NHW_TIMER_N_CC {4, 4, 4, 6, 6} 178 #define NHW_TIMER_MAX_N_CC 6 179 #define NHW_TIMER_FREQ {16, 16, 16, 16, 16} 180 181 #define NHW_UARTE_TOTAL_INST 2 182 #define NHW_UART_0 0 183 #define NHW_UART_1 1 184 #define NHW_UARTE_INT_MAP {{0 , 2}, \ 185 {0 , 40}, \ 186 } /* Only core, UARTE0_UART0_IRQn, UARTE1_IRQn */ 187 #define NHW_UARTE_HAS_UART 1 188 #define NHW_UARTE_NAMES {"UATE0", \ 189 "UATE1"} 190 191 #define NHW_BSTICKER_TOTAL_INST 1 192 #define NHW_BSTICKER_TIMER_INT_MAP {{0 , 0}} /*Only core, -*/ 193 194 #define NHW_FAKE_TIMER_TOTAL_INST 1 195 #define NHW_FAKE_TIMER_INT_MAP {{0 , 0}} /*Only core, -*/ 196 197 /*************************************************************************/ 198 /*************************************************************************/ 199 /*************************************************************************/ 200 #elif defined(NRF5340) || defined(NRF5340_XXAA_NETWORK) || defined(NRF5340_XXAA_APPLICATION) 201 202 /* 203 * The Application core/domain is indexed as domain 0 204 * The Network core/domain is indexed as domain 1 205 */ 206 207 #define NHW_HAS_PPI 0 208 #define NHW_HAS_DPPI 1 209 #define NHW_USE_MDK_TYPES 0 210 211 #define NHW_AAR_TOTAL_INST 1 212 #define NHW_AAR_NET0 0 213 #define NHW_AAR_INT_MAP {{1 , 14}} /*Net core,AAR_CCM */ 214 #define NHW_AAR_DPPI_MAP {1} 215 #define NHW_AAR_t_AAR 6 216 217 #define NHW_CCM_TOTAL_INST 1 218 #define NHW_CCM_NET0 0 219 #define NHW_CCM_INT_MAP {{1 , 14}} /*Net core,AAR_CCM*/ 220 #define NHW_CCM_DPPI_MAP {1} 221 222 #define NHW_CLKPWR_TOTAL_INST 2 223 #define NHW_CLKPWR_APP0 0 224 #define NHW_CLKPWR_NET0 1 225 #define NHW_CLKPWR_INT_MAP {{0 , 5}, \ 226 {1 , 5} \ 227 } /* {App, CLOCK_POWER} 228 * {Net, CLOCK_POWER} 229 */ 230 #define NHW_CLKPWR_DPPI_MAP {0, 1} 231 #define NHW_CLKPWR_HAS_RESET 1 232 #define NHW_CLKPWR_HAS_CALTIMER 0 233 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK 1 234 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK_I {1, 0} 235 #define NHW_CLKPWR_HAS_HFCLK192MCLK 1 236 #define NHW_CLKPWR_HAS_HFCLK192MCLK_I {1, 0} 237 238 #define NHW_ECB_TOTAL_INST 1 239 #define NHW_ECB_NET0 0 240 #define NHW_ECB_INT_MAP {{1 , 13}} /*Net core, ECB_IRQn*/ 241 #define NHW_ECB_DPPI_MAP {1} 242 #define NHW_ECB_t_ECB 6 /* 6.2 */ 243 244 #define NHW_EGU_TOTAL_INST 7 245 #define NHW_EGU_APP0 0 246 #define NHW_EGU_APP1 1 247 #define NHW_EGU_APP2 2 248 #define NHW_EGU_APP3 3 249 #define NHW_EGU_APP4 4 250 #define NHW_EGU_APP5 5 251 #define NHW_EGU_NET0 6 252 #define NHW_EGU_INT_MAP {{0 , 27}, \ 253 {0 , 28}, \ 254 {0 , 29}, \ 255 {0 , 30}, \ 256 {0 , 31}, \ 257 {0 , 32}, \ 258 {1 , 20}, \ 259 } 260 /* {App, EGU0} 261 * .. 262 * {App, EGU5} 263 * {Network, EGU0} 264 * */ 265 #define NHW_EGU_DPPI_MAP {0, 0, 0, 0, 0, 0,\ 266 1} 267 #define NHW_EGU_N_EVENTS {16, 16, 16, 16, 16, 16,\ 268 16} 269 270 #define NHW_DPPI_TOTAL_INST 2 271 #define NHW_DPPI_APP_0 0 272 #define NHW_DPPI_NET_0 1 273 /* The DPPI does not generate interrupts */ 274 #define NHW_DPPI_DPPI_MAP {0,1} /*App DPPI connects to itself, network DPPI to itself*/ 275 #define NHW_DPPI_N_CH {32, 32} /* Number of channels in each DPPI */ 276 #define NHW_DPPI_N_CHG {6, 6} /* Number of channel groups in each DPPI */ 277 278 #define NHW_IPC_TOTAL_INST 2 279 #define NHW_IPC_APP0 0 280 #define NHW_IPC_NET0 1 281 #define NHW_IPC_INT_MAP {{0 , 42}, \ 282 {1 , 18}} 283 /* {App, IPC} 284 * {Network, IPC} 285 * */ 286 #define NHW_IPC_DPPI_MAP {0, 1} /*App, network */ 287 #define NHW_IPC_N_CH {16, 16} 288 289 #define NHW_FICR_APP 0 290 #define NHW_FICR_NET 1 291 292 #define NHW_INTCTRL_TOTAL_INST 2 293 #define NHW_INTCTRL_MAX_INTLINES 58 294 295 /* These names are taken from the IRQn_Type in the MDK header */ 296 #define NHW_INT_NAMES { [0 /*Application core*/] = {\ 297 [0 ]= "FPU",\ 298 [1 ]= "CACHE",\ 299 [3 ]= "SPU",\ 300 [5 ]= "CLOCK_POWER",\ 301 [8 ]= "SERIAL0",\ 302 [9 ]= "SERIAL1",\ 303 [10]= "SPIM4",\ 304 [11]= "SERIAL2",\ 305 [12]= "SERIAL3",\ 306 [13]= "GPIOTE0",\ 307 [14]= "SAADC",\ 308 [15]= "TIMER0",\ 309 [16]= "TIMER1",\ 310 [17]= "TIMER2",\ 311 [20]= "RTC0",\ 312 [21]= "RTC1",\ 313 [24]= "WDT0",\ 314 [25]= "WDT1",\ 315 [26]= "COMP_LPCOMP",\ 316 [27]= "EGU0",\ 317 [28]= "EGU1",\ 318 [29]= "EGU2",\ 319 [30]= "EGU3",\ 320 [31]= "EGU4",\ 321 [32]= "EGU5",\ 322 [33]= "PWM0",\ 323 [34]= "PWM1",\ 324 [35]= "PWM2",\ 325 [36]= "PWM3",\ 326 [38]= "PDM0",\ 327 [40]= "I2S0",\ 328 [42]= "IPC",\ 329 [43]= "QSPI",\ 330 [45]= "NFCT",\ 331 [47]= "GPIOTE1",\ 332 [51]= "QDEC0",\ 333 [52]= "QDEC1",\ 334 [54]= "USBD",\ 335 [55]= "USBREGULATOR",\ 336 [57]= "KMU",\ 337 /*[68]= "CRYPTOCELL",*/\ 338 }, [1 /*Network core*/] = {\ 339 [5 ] = "CLOCK_POWER",\ 340 [8 ] = "RADIO",\ 341 [9 ] = "RNG",\ 342 [10] = "GPIOTE",\ 343 [11] = "WDT",\ 344 [12] = "TIMER0",\ 345 [13] = "ECB",\ 346 [14] = "AAR_CCM",\ 347 [16] = "TEMP",\ 348 [17] = "RTC0",\ 349 [18] = "IPC",\ 350 [19] = "SERIAL0",\ 351 [20] = "EGU0",\ 352 [22] = "RTC1",\ 353 [24] = "TIMER1",\ 354 [25] = "TIMER2",\ 355 [26] = "SWI0",\ 356 [27] = "SWI1",\ 357 [28] = "SWI2",\ 358 [29] = "SWI3",\ 359 }} 360 361 #define NHW_CORE_NAMES {"Application", "Network"} 362 363 #define NHW_NVMC_UICR_TOTAL_INST 2 364 #define NHW_NVMC_APP0 0 365 #define NHW_NVMC_NET0 1 366 #define NHW_UICR_APP0 0 367 #define NHW_UICR_NET0 1 368 #define NHW_NVMC_HAS_ERASEREGS 0 369 #define NHW_FLASH_START_ADDR {0x00000000, 0x01000000} 370 #define NHW_FLASH_PAGESIZE {(4*1024), (2*1024)} 371 #define NHW_FLASH_N_PAGES {256, 128} 372 #define NHW_UICR_SIZE {4096, 800 /*bytes*/} 373 //App UICR size including the KEYSLOT 374 #define NHW_NVMC_FLASH_T_ERASEALL (173000) 375 #define NHW_NVMC_FLASH_T_ERASEPAGE (87500) 376 #define NHW_NVMC_FLASH_T_WRITE (43) 377 #define NHW_NVMC_FLASH_PARTIAL_ERASE_FACTOR (1.0) 378 379 #define NHW_RADIO_TOTAL_INST 1 380 #define NHW_RADIO_NET0 0 381 #define NHW_RADIO_N_INT 1 382 #define NHW_RADIO_INT_MAP {{1 , 8}} /*Net core,RADIO_IRQn*/ 383 #define NHW_RADIO_DPPI_MAP {1} /*Network core*/ 384 #define NHW_RADIO_ED_RSSIOFFS (-93) 385 #define NHW_RADIO_IS_54 0 386 387 #define NHW_RNG_TOTAL_INST 1 388 #define NHW_RNG_NET_0 0 389 #define NHW_RNG_INT_MAP {{1, 9}} /*Network core, "RNG_IRQn"*/ 390 #define NHW_RNG_DPPI_MAP {1} /*Network core*/ 391 #define NHW_RNG_tRNG_START 128 392 #define NHW_RNG_tRNG_RAW 32 393 #define NHW_RNG_tRNG_BC 122 394 395 #define NHW_RTC_TOTAL_INST 4 396 #define NHW_RTC_APP0 0 397 #define NHW_RTC_APP1 1 398 #define NHW_RTC_NET0 2 399 #define NHW_RTC_NET1 3 400 #define NHW_RTC_INT_MAP {{0 , 20}, \ 401 {0 , 21}, \ 402 {1 , 17}, \ 403 {1 , 22}, \ 404 } /*App core,RTC0..1_IRQn*/ 405 /*Net core,RTC0..1_IRQn*/ 406 #define NHW_RTC_DPPI_MAP {0, 0, 1, 1} /*2xApp core, 2xNetwork core*/ 407 #define NHW_RTC_HAS_CAPTURE 1 408 #define NHW_RTC_HAS_SHORT_COMP_CLEAR 1 409 #define NHW_RTC_N_CC {4, 4, 4, 4} 410 411 #define NHW_SWI_TOTAL_INST 4 412 #define NHW_SWI_NET0 0 413 #define NHW_SWI_NET1 1 414 #define NHW_SWI_NET2 2 415 #define NHW_SWI_NET3 3 416 417 #define NHW_TEMP_TOTAL_INST 1 418 #define NHW_TEMP_NET0 0 419 #define NHW_TEMP_INT_MAP {{1 , 16}} /*Net core,TEMP_IRQn*/ 420 #define NHW_TEMP_DPPI_MAP {1} /*Network core*/ 421 #define NHW_TEMP_t_TEMP 36 /* microseconds */ 422 #define NHW_TEMP_FBITS 2 /* fractional bits => 0.25C resolution */ 423 424 #define NHW_TIMER_TOTAL_INST 6 425 #define NHW_TIMER_APP0 0 426 #define NHW_TIMER_APP1 1 427 #define NHW_TIMER_APP2 2 428 #define NHW_TIMER_NET0 3 429 #define NHW_TIMER_NET1 4 430 #define NHW_TIMER_NET2 5 431 #define NHW_TIMER_INT_MAP {{0 , 15}, \ 432 {0 , 16}, \ 433 {0 , 17}, \ 434 {1 , 12}, \ 435 {1 , 24}, \ 436 {1 , 25}, \ 437 } /* AppCore, TIMER0..2_IRQn */ 438 /* NetCore, TIMER0..2_IRQn */ 439 #define NHW_TIMER_HAS_ONE_SHOT 1 440 #define NHW_TIMER_N_CC {6, 6, 6, 8, 8, 8} 441 #define NHW_TIMER_MAX_N_CC 8 442 #define NHW_TIMER_FREQ {16, 16, 16, 16, 16, 16} 443 #define NHW_TIMER_DPPI_MAP {0, 0, 0, 1, 1, 1} /*3xApp core, 3xNetwork core*/ 444 445 #define NHW_UARTE_TOTAL_INST 5 446 #define NHW_UARTE_APP0 0 447 #define NHW_UARTE_APP1 1 448 #define NHW_UARTE_APP2 2 449 #define NHW_UARTE_APP3 3 450 #define NHW_UARTE_NET0 4 451 #define NHW_UARTE_INT_MAP {{0 , 8}, \ 452 {0 , 9}, \ 453 {0 , 11}, \ 454 {0 , 12}, \ 455 {1 , 19}, \ 456 } /* App core, SERIAL0..3_IRQn, 457 Net core, SERIAL0_IRQn */ 458 #define NHW_UARTE_DPPI_MAP {0, 0, 0, 0, 1} /*4xApp core, 1xNetwork core*/ 459 #define NHW_UARTE_HAS_UART 0 460 #define NHW_UARTE_NAMES {"App UATE0", \ 461 "App UATE1", \ 462 "App UATE2", \ 463 "App UATE3", \ 464 "Net UATE0"} 465 466 #define NHW_FAKE_TIMER_TOTAL_INST 2 467 #define NHW_FAKE_TIMER_INT_MAP {{0 , 0}, \ 468 {1 , 0}} /*App core & Net core, -*/ 469 470 #define NHW_BSTICKER_TOTAL_INST 2 471 #define NHW_BSTICKER_TIMER_INT_MAP {{0 , 0}, \ 472 {1 , 0}} /*App core & Net core, -*/ 473 474 /*************************************************************************/ 475 /*************************************************************************/ 476 /*************************************************************************/ 477 #elif defined(NRF54L15) || defined(NRF54L15_XXAA) 478 479 #define NHW_HAS_PPI 0 480 #define NHW_HAS_DPPI 1 481 #define NHW_USE_MDK_TYPES 1 /* The HW registers layout types are taken from the MDK */ 482 #define NHW_CORE_NAMES {"Application", "Flipper"} 483 484 #define NHW_CLKPWR_TOTAL_INST 1 485 #define NHW_CLKPWR_0 0 486 #define NHW_CLKPWR_DPPI_MAP {0} /* Global */ 487 #define NHW_CLKPWR_INT_MAP {{0, 270}} /* {App, CLOCK_POWER_IRQn} */ 488 489 #define NHW_DPPI_TOTAL_INST 4 490 #define NHW_DPPI_00 0 /* Global */ 491 #define NHW_DPPI_10 1 /* Radio */ 492 #define NHW_DPPI_20 2 /* Peri */ 493 #define NHW_DPPI_30 3 /* LP */ 494 /* The DPPI does not generate interrupts */ 495 #define NHW_DPPI_DPPI_MAP {0, 1, 2, 3} /* DPPI connect to themselves */ 496 #define NHW_DPPI_N_CH {8, 24, 16, 4} /* Number of channels in each DPPI */ 497 #define NHW_DPPI_N_CHG {2, 6, 6, 2} /* Number of channel groups in each DPPI */ 498 499 #define NHW_EGU_TOTAL_INST 2 500 #define NHW_EGU_10 0 501 #define NHW_EGU_20 1 502 #define NHW_EGU_INT_MAP {{0 , 135}, \ 503 {0 , 201}, \ 504 } 505 /* {App, EGU10} 506 * {App, EGU20} 507 * */ 508 #define NHW_EGU_DPPI_MAP {1, 2} /* Radio, Peri */ 509 #define NHW_EGU_N_EVENTS {16, 6} 510 511 #define NHW_GRTC_TOTAL_INST 1 512 #define NHW_GRTC_N_INT 4 513 #define NHW_GRTC_INT_MAP { \ 514 {0 , 226}, \ 515 {0 , 227}, \ 516 {0 , 228}, \ 517 {0 , 229}, \ 518 } 519 /* {App, GRTC_0..3_IRQn} */ 520 #define NHW_GRTC_DPPI_MAP {2 /* Peripheral domain */} 521 #define NHW_GRTC_N_CC 12 522 #define NHW_GRTC_N_DOMAINS 4 523 #define NHW_GRTC_SYSCOUNTER_BW 52 524 #define NHW_GRTC_HAS_CLKOUT 0 525 #define NHW_GRTC_HAS_PWM 1 526 527 528 #define NHW_INTCTRL_TOTAL_INST 2 529 #define NHW_INTCTRL_MAX_INTLINES 271 530 531 /* These names are taken from the IRQn_Type in the MDK header */ 532 #define NHW_INT_NAMES { [0 /*Application core*/] = {\ 533 [28 ]="SWI00",\ 534 [29 ]="SWI01",\ 535 [30 ]="SWI02",\ 536 [31 ]="SWI03",\ 537 [64 ]="SPU00",\ 538 [65 ]="MPC00",\ 539 [70 ]="AAR00_CCM00",\ 540 [71 ]="ECB00",\ 541 [72 ]="CRACEN",\ 542 [74 ]="SERIAL00",\ 543 [75 ]="RRAMC",\ 544 [76 ]="VPR00",\ 545 [82 ]="CTRLAP",\ 546 [83 ]="CM33SS",\ 547 [85 ]="TIMER00",\ 548 [128]="SPU10",\ 549 [133]="TIMER10",\ 550 [134]="RTC10",\ 551 [135]="EGU10",\ 552 [138]="RADIO_0",\ 553 [139]="RADIO_1",\ 554 [192]="SPU20",\ 555 [198]="SERIAL20",\ 556 [199]="SERIAL21",\ 557 [200]="SERIAL22",\ 558 [201]="EGU20",\ 559 [202]="TIMER20",\ 560 [203]="TIMER21",\ 561 [204]="TIMER22",\ 562 [205]="TIMER23",\ 563 [206]="TIMER24",\ 564 [208]="PDM20",\ 565 [209]="PDM21",\ 566 [210]="PWM20",\ 567 [211]="PWM21",\ 568 [212]="PWM22",\ 569 [213]="SAADC",\ 570 [214]="NFCT",\ 571 [215]="TEMP",\ 572 [218]="GPIOTE20_0",\ 573 [219]="GPIOTE20_1",\ 574 [220]="TAMPC",\ 575 [221]="I2S20",\ 576 [224]="QDEC20",\ 577 [225]="QDEC21",\ 578 [226]="GRTC_0",\ 579 [227]="GRTC_1",\ 580 [228]="GRTC_2",\ 581 [229]="GRTC_3",\ 582 [256]="SPU30",\ 583 [260]="SERIAL30",\ 584 [261]="RTC30",\ 585 [262]="COMP_LPCOMP",\ 586 [264]="WDT30",\ 587 [265]="WDT31",\ 588 [268]="GPIOTE30_0",\ 589 [269]="GPIOTE30_1",\ 590 [270]="CLOCK_POWER",\ 591 }, [1 /*Flipper core*/] = {\ 592 [0 ]="VPRCLIC_0",\ 593 [1 ]="VPRCLIC_1",\ 594 [2 ]="VPRCLIC_2",\ 595 [3 ]="VPRCLIC_3",\ 596 [4 ]="VPRCLIC_4",\ 597 [5 ]="VPRCLIC_5",\ 598 [6 ]="VPRCLIC_6",\ 599 [7 ]="VPRCLIC_7",\ 600 [8 ]="VPRCLIC_8",\ 601 [9 ]="VPRCLIC_9",\ 602 [10 ]="VPRCLIC_10",\ 603 [11 ]="VPRCLIC_11",\ 604 [12 ]="VPRCLIC_12",\ 605 [13 ]="VPRCLIC_13",\ 606 [14 ]="VPRCLIC_14",\ 607 [15 ]="VPRCLIC_15",\ 608 [16 ]="VPRCLIC_16",\ 609 [17 ]="VPRCLIC_17",\ 610 [18 ]="VPRCLIC_18",\ 611 [19 ]="VPRCLIC_19",\ 612 [20 ]="VPRCLIC_20",\ 613 [21 ]="VPRCLIC_21",\ 614 [22 ]="VPRCLIC_22",\ 615 [23 ]="VPRCLIC_23",\ 616 [24 ]="VPRCLIC_24",\ 617 [25 ]="VPRCLIC_25",\ 618 [26 ]="VPRCLIC_26",\ 619 [27 ]="VPRCLIC_27",\ 620 [28 ]="VPRCLIC_28",\ 621 [29 ]="VPRCLIC_29",\ 622 [30 ]="VPRCLIC_30",\ 623 [31 ]="VPRCLIC_31",\ 624 [64 ]="SPU00",\ 625 [65 ]="MPC00",\ 626 [70 ]="AAR00_CCM00",\ 627 [71 ]="ECB00",\ 628 [72 ]="CRACEN",\ 629 [74 ]="SERIAL00",\ 630 [75 ]="RRAMC",\ 631 [76 ]="VPR00",\ 632 [82 ]="CTRLAP",\ 633 [85 ]="TIMER00",\ 634 [128]="SPU10",\ 635 [133]="TIMER10",\ 636 [134]="RTC10",\ 637 [135]="EGU10",\ 638 [138]="RADIO_0",\ 639 [139]="RADIO_1",\ 640 [192]="SPU20",\ 641 [198]="SERIAL20",\ 642 [199]="SERIAL21",\ 643 [200]="SERIAL22",\ 644 [201]="EGU20",\ 645 [202]="TIMER20",\ 646 [203]="TIMER21",\ 647 [204]="TIMER22",\ 648 [205]="TIMER23",\ 649 [206]="TIMER24",\ 650 [208]="PDM20",\ 651 [209]="PDM21",\ 652 [210]="PWM20",\ 653 [211]="PWM21",\ 654 [212]="PWM22",\ 655 [213]="SAADC",\ 656 [214]="NFCT",\ 657 [215]="TEMP",\ 658 [218]="GPIOTE20_0",\ 659 [219]="GPIOTE20_1",\ 660 [220]="TAMPC",\ 661 [221]="I2S20",\ 662 [224]="QDEC20",\ 663 [225]="QDEC21",\ 664 [226]="GRTC_0",\ 665 [227]="GRTC_1",\ 666 [228]="GRTC_2",\ 667 [229]="GRTC_3",\ 668 [256]="SPU30",\ 669 [260]="SERIAL30",\ 670 [261]="RTC30",\ 671 [262]="COMP_LPCOMP",\ 672 [264]="WDT30",\ 673 [265]="WDT31",\ 674 [268]="GPIOTE30_0",\ 675 [269]="GPIOTE30_1",\ 676 [270]="CLOCK_POWER",\ 677 }} 678 679 #define NHW_PPIB_TOTAL_INST 8 680 #define NHW_PPIB_00 0 681 #define NHW_PPIB_01 1 682 #define NHW_PPIB_10 2 683 #define NHW_PPIB_11 3 684 #define NHW_PPIB_20 4 685 #define NHW_PPIB_21 5 686 #define NHW_PPIB_22 6 687 #define NHW_PPIB_30 7 688 #define NHW_PPIB_DPPI_MAP {0, 0, 1, 1, 2, 2, 2, 3} 689 #define NHW_PPIB_N_CH {8, 8, 8, 16, 8, 16, 4, 4} 690 #define NHW_PPIB_MATE {2,/*00->10*/ \ 691 4,/*01->20*/ \ 692 0,/*10->00*/ \ 693 5,/*11->21*/ \ 694 1,/*20->01*/ \ 695 3,/*21->11*/ \ 696 7,/*22->30*/ \ 697 6,/*30->22*/ \ 698 } 699 #define HWH_PPIB_HARDWIRESCHANNELS 0 700 701 #define NHW_RADIO_TOTAL_INST 1 702 #define NHW_RADIO_0 0 703 #define NHW_RADIO_N_INT 2 704 #define NHW_RADIO_INT_MAP {{0 , 138}, \ 705 {0 , 139}} 706 /*{App, RADIO_0_IRQn}, 707 *{App, RADIO_1_IRQn} */ 708 #define NHW_RADIO_DPPI_MAP {1} /* Radio domain */ 709 #define NHW_RADIO_ED_RSSIOFFS (-92) 710 #define NHW_RADIO_IS_54 1 711 712 #define NHW_RRAMC_UICR_TOTAL_INST 1 713 #define NHW_RRAM_START_ADDR {0x00000000} 714 #define NHW_RRAM_SIZE {(1524*1024)} 715 #define NHW_UICR_SIZE {2560 /*bytes*/} 716 717 #define NHW_RTC_TOTAL_INST 2 718 #define NHW_RTC_10 0 719 #define NHW_RTC_30 1 720 #define NHW_RTC_INT_MAP {{0 , 134}, \ 721 {0 , 261}, \ 722 } /*App core,RTC10_IRQn*/ 723 /*Net core,RTC30_IRQn*/ 724 #define NHW_RTC_DPPI_MAP {1, 3} 725 #define NHW_RTC_HAS_CAPTURE 1 726 #define NHW_RTC_HAS_SHORT_COMP_CLEAR 1 727 #define NHW_RTC_N_CC {4, 4} 728 729 #define NHW_SWI_TOTAL_INST 4 730 731 #define NHW_TEMP_TOTAL_INST 1 732 #define NHW_TEMP_APP0 0 733 #define NHW_TEMP_INT_MAP {{0 , 215}} /*App core,TEMP_IRQn*/ 734 #define NHW_TEMP_DPPI_MAP {2} /*Peri domain*/ 735 #define NHW_TEMP_t_TEMP 36 /* microseconds, Unknown, assuming by now same as 52833 & 5340 */ 736 #define NHW_TEMP_FBITS 2 /* fractional bits => 0.25C resolution */ 737 738 #define NHW_TIMER_TOTAL_INST 7 739 #define NHW_TIMER_00 0 740 #define NHW_TIMER_10 1 741 #define NHW_TIMER_20 2 742 #define NHW_TIMER_21 3 743 #define NHW_TIMER_22 4 744 #define NHW_TIMER_23 5 745 #define NHW_TIMER_24 6 746 #define NHW_TIMER_INT_MAP {{0 , 85}, \ 747 {0 , 133}, \ 748 {0 , 202}, \ 749 {0 , 203}, \ 750 {0 , 204}, \ 751 {0 , 205}, \ 752 {0 , 206}, \ 753 } /* App, TIMER00..24_IRQn */ 754 #define NHW_TIMER_HAS_ONE_SHOT 1 755 #define NHW_TIMER_N_CC {6, 8, 6, 6, 6, 6, 6} 756 #define NHW_TIMER_MAX_N_CC 8 757 #define NHW_TIMER_FREQ {128, 32, 16, 16, 16, 16, 16} 758 #define NHW_TIMER_DPPI_MAP {0, 1, 2, 2, 2, 2, 2} 759 760 761 #define NHW_FAKE_TIMER_TOTAL_INST 2 762 #define NHW_FAKE_TIMER_INT_MAP {{0 , 0}, \ 763 {1 , 0}} /*App core & flpr core, -*/ 764 765 #define NHW_BSTICKER_TOTAL_INST 2 766 #define NHW_BSTICKER_TIMER_INT_MAP {{0 , 0}, \ 767 {1 , 0}} /*App core & flpr core, -*/ 768 769 #else 770 #error "No valid platform was selected" 771 #endif 772 773 #endif /* _NRF_HW_CONFIG_H */ 774
