1 /* 2 * Copyright (c) 2023 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * This file configures the HW models based on the variant being built 7 */ 8 #ifndef _NRF_HW_CONFIG_H 9 #define _NRF_HW_CONFIG_H 10 11 /* 12 * For each peripheral the following may be defined 13 * NHW_<PERIPH_TYPE>_TOTAL_INST <val> : Total number of instances of the peripheral in the whole SOC 14 * NHW_<PERIPH_TYPE>_<CORE>_<INST> <val> : Index of that peripheral instant in list of peripherals 15 * 16 * NHW_<PERIPH_TYPE>_INT_MAP : List of irq controller mapping, for each instante: {irq ctrl number, irq line} 17 */ 18 19 #if defined(NRF52833) || defined(NRF52833_XXAA) 20 21 #define NHW_CORE_NAMES {""} 22 23 #define NHW_HAS_PPI 1 24 #define NHW_HAS_DPPI 0 25 #define NHW_USE_MDK_TYPES 1 /* The HW registers layout types are taken from the MDK */ 26 27 #define NHW_AAR_TOTAL_INST 1 28 #define NHW_AAR_0 0 29 #define NHW_AAR_INT_MAP {{0 , 15}} /*Only core,CCM_AAR_IRQn*/ 30 #define NHW_AAR_t_AAR 6 31 32 #define NHW_CCM_TOTAL_INST 1 33 #define NHW_CCM_0 0 34 #define NHW_CCM_INT_MAP {{0 , 15}} /*Only core,CCM_AAR_IRQn*/ 35 36 #define NHW_CLKPWR_TOTAL_INST 1 37 #define NHW_CLKPWR_0 0 38 #define NHW_CLKPWR_INT_MAP {{0 , 0}} /*Only core, POWER_CLOCK_IRQn*/ 39 #define NHW_CLKPWR_HAS_RESET 0 40 #define NHW_CLKPWR_HAS_CALTIMER 1 41 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK 0 42 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK_I {0} 43 #define NHW_CLKPWR_HAS_HFCLK192MCLK 0 44 #define NHW_CLKPWR_HAS_HFCLK192MCLK_I {0} 45 46 #define NHW_ECB_TOTAL_INST 1 47 #define NHW_ECB_0 0 48 #define NHW_ECB_INT_MAP {{0 , 14}} /*Only core,ECB_IRQn*/ 49 #define NHW_ECB_t_ECB 7 /* 7.2 */ 50 51 #define NHW_EGU_TOTAL_INST 6 52 #define NHW_EGU_0 0 53 #define NHW_EGU_1 1 54 #define NHW_EGU_2 2 55 #define NHW_EGU_3 3 56 #define NHW_EGU_4 4 57 #define NHW_EGU_5 5 58 #define NHW_EGU_INT_MAP {{0 , 20}, \ 59 {0 , 21}, \ 60 {0 , 22}, \ 61 {0 , 23}, \ 62 {0 , 24}, \ 63 {0 , 25}, \ 64 } /*Only core,SWI0..5_EGU0_IRQn*/ 65 #define NHW_EGU_N_EVENTS {16, 16, 16, 16, 16, 16} 66 67 #define NHW_GPIOTE_TOTAL_INST 1 68 #define NHW_GPIOTE_0 0 69 #define NHW_GPIOTE_INT_MAP {{0 , 6}} /*Only core,GPIOTE_IRQn*/ 70 71 #define NHW_INTCTRL_TOTAL_INST 1 72 #define NHW_INTCTRL_MAX_INTLINES 48 73 74 /* These names are taken from the IRQn_Type in the MDK header */ 75 #define NHW_INT_NAMES { [0] = {\ 76 [0 ] = "POWER_CLOCK",\ 77 [1 ] = "RADIO",\ 78 [2 ] = "UARTE0_UART0",\ 79 [3 ] = "SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0",\ 80 [4 ] = "SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1",\ 81 [5 ] = "NFCT",\ 82 [6 ] = "GPIOTE",\ 83 [7 ] = "SAADC",\ 84 [8 ] = "TIMER0",\ 85 [9 ] = "TIMER1",\ 86 [10] = "TIMER2",\ 87 [11] = "RTC0",\ 88 [12] = "TEMP",\ 89 [13] = "RNG",\ 90 [14] = "ECB",\ 91 [15] = "CCM_AAR",\ 92 [16] = "WDT",\ 93 [17] = "RTC1",\ 94 [18] = "QDEC",\ 95 [19] = "COMP_LPCOMP",\ 96 [20] = "SWI0_EGU0",\ 97 [21] = "SWI1_EGU1",\ 98 [22] = "SWI2_EGU2",\ 99 [23] = "SWI3_EGU3",\ 100 [24] = "SWI4_EGU4",\ 101 [25] = "SWI5_EGU5",\ 102 [26] = "TIMER3",\ 103 [27] = "TIMER4",\ 104 [28] = "PWM0",\ 105 [29] = "PDM",\ 106 [32] = "MWU",\ 107 [33] = "PWM1",\ 108 [34] = "PWM2",\ 109 [35] = "SPIM2_SPIS2_SPI2",\ 110 [36] = "RTC2",\ 111 [37] = "I2S",\ 112 [38] = "FPU",\ 113 [39] = "USBD",\ 114 [40] = "UARTE1",\ 115 [45] = "PWM3",\ 116 [47] = "SPIM3",\ 117 }} 118 119 #define NHW_NVMC_UICR_TOTAL_INST 1 120 #define NHW_NVMC_HAS_ERASEREGS 1 121 #define NHW_FLASH_START_ADDR {0x00000000} 122 #define NHW_FLASH_PAGESIZE {(4*1024)} 123 #define NHW_FLASH_N_PAGES {128} 124 #define NHW_UICR_SIZE {776 /*64*4*/ /*bytes*/} 125 /* In case somebody tries to access the UICR registers, we book 126 * more space than its actual flash area (64*4)*/ 127 #define NHW_NVMC_FLASH_T_ERASEALL (173000) 128 #define NHW_NVMC_FLASH_T_ERASEPAGE (87500) 129 #define NHW_NVMC_FLASH_T_WRITE (42) 130 #define NHW_NVMC_FLASH_PARTIAL_ERASE_FACTOR (1.0) 131 132 #define NHW_RADIO_TOTAL_INST 1 133 #define NHW_RADIO_0 0 134 #define NHW_RADIO_INT_MAP {{0 , 1}} /*Only core,RADIO_IRQn*/ 135 #define NHW_RADIO_ED_RSSIOFFS (-93) 136 137 #define NHW_RNG_TOTAL_INST 1 138 #define NHW_RNG_0 0 139 #define NHW_RNG_INT_MAP {{0 , 13}} /*Only core,RNG_IRQn*/ 140 #define NHW_RNG_tRNG_START 128 141 #define NHW_RNG_tRNG_RAW 30 142 #define NHW_RNG_tRNG_BC 120 143 144 #define NHW_RTC_TOTAL_INST 3 145 #define NHW_RTC_0 0 146 #define NHW_RTC_1 1 147 #define NHW_RTC_2 2 148 #define NHW_RTC_INT_MAP {{0 , 11}, \ 149 {0 , 17}, \ 150 {0 , 36}, \ 151 } /*Only core,RTC0..2_IRQn*/ 152 #define NHW_RTC_HAS_CAPTURE 0 153 #define NHW_RTC_HAS_SHORT_COMP_CLEAR 0 154 #define NHW_RTC_N_CC {3, 4, 4} 155 156 #define NHW_TEMP_TOTAL_INST 1 157 #define NHW_TEMP_0 0 158 #define NHW_TEMP_INT_MAP {{0 , 12}} /*Only core,TEMP_IRQn*/ 159 #define NHW_TEMP_t_TEMP 36 /* microseconds */ 160 #define NHW_TEMP_FBITS 2 /* fractional bits => 0.25C resolution */ 161 162 #define NHW_TIMER_TOTAL_INST 5 163 #define NHW_TIMER_0 0 164 #define NHW_TIMER_1 1 165 #define NHW_TIMER_2 2 166 #define NHW_TIMER_3 3 167 #define NHW_TIMER_4 4 168 #define NHW_TIMER_INT_MAP {{0 , 8}, \ 169 {0 , 9}, \ 170 {0 , 10}, \ 171 {0 , 26}, \ 172 {0 , 27}, \ 173 } /* Only core, TIMER0..4_IRQn */ 174 #define NHW_TIMER_HAS_ONE_SHOT 0 175 #define NHW_TIMER_N_CC {4, 4, 4, 6, 6} 176 #define NHW_TIMER_MAX_N_CC 6 177 #define NHW_TIMER_FREQ {16, 16, 16, 16, 16} 178 179 #define NHW_UARTE_TOTAL_INST 2 180 #define NHW_UART_0 0 181 #define NHW_UART_1 1 182 #define NHW_UARTE_INT_MAP {{0 , 2}, \ 183 {0 , 40}, \ 184 } /* Only core, UARTE0_UART0_IRQn, UARTE1_IRQn */ 185 #define NHW_UARTE_HAS_UART 1 186 #define NHW_UARTE_NAMES {"UATE0", \ 187 "UATE1"} 188 189 #define NHW_BSTICKER_TOTAL_INST 1 190 #define NHW_BSTICKER_TIMER_INT_MAP {{0 , 0}} /*Only core, -*/ 191 192 #define NHW_FAKE_TIMER_TOTAL_INST 1 193 #define NHW_FAKE_TIMER_INT_MAP {{0 , 0}} /*Only core, -*/ 194 195 /*************************************************************************/ 196 /*************************************************************************/ 197 /*************************************************************************/ 198 #elif defined(NRF5340) || defined(NRF5340_XXAA_NETWORK) || defined(NRF5340_XXAA_APPLICATION) 199 200 /* 201 * The Application core/domain is indexed as domain 0 202 * The Network core/domain is indexed as domain 1 203 */ 204 205 #define NHW_HAS_PPI 0 206 #define NHW_HAS_DPPI 1 207 #define NHW_USE_MDK_TYPES 0 208 209 #define NHW_AAR_TOTAL_INST 1 210 #define NHW_AAR_NET0 0 211 #define NHW_AAR_INT_MAP {{1 , 14}} /*Net core,AAR_CCM */ 212 #define NHW_AAR_DPPI_MAP {1} 213 #define NHW_AAR_t_AAR 6 214 215 #define NHW_CCM_TOTAL_INST 1 216 #define NHW_CCM_NET0 0 217 #define NHW_CCM_INT_MAP {{1 , 14}} /*Net core,AAR_CCM*/ 218 #define NHW_CCM_DPPI_MAP {1} 219 220 #define NHW_CLKPWR_TOTAL_INST 2 221 #define NHW_CLKPWR_APP0 0 222 #define NHW_CLKPWR_NET0 1 223 #define NHW_CLKPWR_INT_MAP {{0 , 5}, \ 224 {1 , 5} \ 225 } /* {App, CLOCK_POWER} 226 * {Net, CLOCK_POWER} 227 */ 228 #define NHW_CLKPWR_DPPI_MAP {0, 1} 229 #define NHW_CLKPWR_HAS_RESET 1 230 #define NHW_CLKPWR_HAS_CALTIMER 0 231 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK 1 232 #define NHW_CLKPWR_HAS_HFCLKAUDIOCLK_I {1, 0} 233 #define NHW_CLKPWR_HAS_HFCLK192MCLK 1 234 #define NHW_CLKPWR_HAS_HFCLK192MCLK_I {1, 0} 235 236 #define NHW_ECB_TOTAL_INST 1 237 #define NHW_ECB_NET0 0 238 #define NHW_ECB_INT_MAP {{1 , 13}} /*Net core, ECB_IRQn*/ 239 #define NHW_ECB_DPPI_MAP {1} 240 #define NHW_ECB_t_ECB 6 /* 6.2 */ 241 242 #define NHW_EGU_TOTAL_INST 7 243 #define NHW_EGU_APP0 0 244 #define NHW_EGU_APP1 1 245 #define NHW_EGU_APP2 2 246 #define NHW_EGU_APP3 3 247 #define NHW_EGU_APP4 4 248 #define NHW_EGU_APP5 5 249 #define NHW_EGU_NET0 6 250 #define NHW_EGU_INT_MAP {{0 , 27}, \ 251 {0 , 28}, \ 252 {0 , 29}, \ 253 {0 , 30}, \ 254 {0 , 31}, \ 255 {0 , 32}, \ 256 {1 , 20}, \ 257 } 258 /* {App, EGU0} 259 * .. 260 * {App, EGU5} 261 * {Network, EGU0} 262 * */ 263 #define NHW_EGU_DPPI_MAP {0, 0, 0, 0, 0, 0,\ 264 1} 265 #define NHW_EGU_N_EVENTS {16, 16, 16, 16, 16, 16,\ 266 16} 267 268 #define NHW_DPPI_TOTAL_INST 2 269 #define NHW_DPPI_APP_0 0 270 #define NHW_DPPI_NET_0 1 271 /* The DPPI does not generate interrupts */ 272 #define NHW_DPPI_DPPI_MAP {0,1} /*App DPPI connects to itself, network DPPI to itself*/ 273 #define NHW_DPPI_N_CH {32, 32} /* Number of channels in each DPPI */ 274 #define NHW_DPPI_N_CHG {6, 6} /* Number of channel groups in each DPPI */ 275 276 #define NHW_IPC_TOTAL_INST 2 277 #define NHW_IPC_APP0 0 278 #define NHW_IPC_NET0 1 279 #define NHW_IPC_INT_MAP {{0 , 42}, \ 280 {1 , 18}} 281 /* {App, IPC} 282 * {Network, IPC} 283 * */ 284 #define NHW_IPC_DPPI_MAP {0, 1} /*App, network */ 285 #define NHW_IPC_N_CH {16, 16} 286 287 #define NHW_FICR_APP 0 288 #define NHW_FICR_NET 1 289 290 #define NHW_INTCTRL_TOTAL_INST 2 291 #define NHW_INTCTRL_MAX_INTLINES 58 292 293 /* These names are taken from the IRQn_Type in the MDK header */ 294 #define NHW_INT_NAMES { [0 /*Application core*/] = {\ 295 [0 ]= "FPU",\ 296 [1 ]= "CACHE",\ 297 [3 ]= "SPU",\ 298 [5 ]= "CLOCK_POWER",\ 299 [8 ]= "SERIAL0",\ 300 [9 ]= "SERIAL1",\ 301 [10]= "SPIM4",\ 302 [11]= "SERIAL2",\ 303 [12]= "SERIAL3",\ 304 [13]= "GPIOTE0",\ 305 [14]= "SAADC",\ 306 [15]= "TIMER0",\ 307 [16]= "TIMER1",\ 308 [17]= "TIMER2",\ 309 [20]= "RTC0",\ 310 [21]= "RTC1",\ 311 [24]= "WDT0",\ 312 [25]= "WDT1",\ 313 [26]= "COMP_LPCOMP",\ 314 [27]= "EGU0",\ 315 [28]= "EGU1",\ 316 [29]= "EGU2",\ 317 [30]= "EGU3",\ 318 [31]= "EGU4",\ 319 [32]= "EGU5",\ 320 [33]= "PWM0",\ 321 [34]= "PWM1",\ 322 [35]= "PWM2",\ 323 [36]= "PWM3",\ 324 [38]= "PDM0",\ 325 [40]= "I2S0",\ 326 [42]= "IPC",\ 327 [43]= "QSPI",\ 328 [45]= "NFCT",\ 329 [47]= "GPIOTE1",\ 330 [51]= "QDEC0",\ 331 [52]= "QDEC1",\ 332 [54]= "USBD",\ 333 [55]= "USBREGULATOR",\ 334 [57]= "KMU",\ 335 /*[68]= "CRYPTOCELL",*/\ 336 }, [1 /*Network core*/] = {\ 337 [5 ] = "CLOCK_POWER",\ 338 [8 ] = "RADIO",\ 339 [9 ] = "RNG",\ 340 [10] = "GPIOTE",\ 341 [11] = "WDT",\ 342 [12] = "TIMER0",\ 343 [13] = "ECB",\ 344 [14] = "AAR_CCM",\ 345 [16] = "TEMP",\ 346 [17] = "RTC0",\ 347 [18] = "IPC",\ 348 [19] = "SERIAL0",\ 349 [20] = "EGU0",\ 350 [22] = "RTC1",\ 351 [24] = "TIMER1",\ 352 [25] = "TIMER2",\ 353 [26] = "SWI0",\ 354 [27] = "SWI1",\ 355 [28] = "SWI2",\ 356 [29] = "SWI3",\ 357 }} 358 359 #define NHW_CORE_NAMES {"Application", "Network"} 360 361 #define NHW_NVMC_UICR_TOTAL_INST 2 362 #define NHW_NVMC_APP0 0 363 #define NHW_NVMC_NET0 1 364 #define NHW_UICR_APP0 0 365 #define NHW_UICR_NET0 1 366 #define NHW_NVMC_HAS_ERASEREGS 0 367 #define NHW_FLASH_START_ADDR {0x00000000, 0x01000000} 368 #define NHW_FLASH_PAGESIZE {(4*1024), (2*1024)} 369 #define NHW_FLASH_N_PAGES {256, 128} 370 #define NHW_UICR_SIZE {4096, 800 /*bytes*/} 371 //App UICR size including the KEYSLOT 372 #define NHW_NVMC_FLASH_T_ERASEALL (173000) 373 #define NHW_NVMC_FLASH_T_ERASEPAGE (87500) 374 #define NHW_NVMC_FLASH_T_WRITE (43) 375 #define NHW_NVMC_FLASH_PARTIAL_ERASE_FACTOR (1.0) 376 377 #define NHW_RADIO_TOTAL_INST 1 378 #define NHW_RADIO_NET0 0 379 #define NHW_RADIO_INT_MAP {{1 , 8}} /*Net core,RADIO_IRQn*/ 380 #define NHW_RADIO_DPPI_MAP {1} /*Network core*/ 381 #define NHW_RADIO_ED_RSSIOFFS (-93) 382 383 #define NHW_RNG_TOTAL_INST 1 384 #define NHW_RNG_NET_0 0 385 #define NHW_RNG_INT_MAP {{1, 9}} /*Network core, "RNG_IRQn"*/ 386 #define NHW_RNG_DPPI_MAP {1} /*Network core*/ 387 #define NHW_RNG_tRNG_START 128 388 #define NHW_RNG_tRNG_RAW 32 389 #define NHW_RNG_tRNG_BC 122 390 391 #define NHW_RTC_TOTAL_INST 4 392 #define NHW_RTC_APP0 0 393 #define NHW_RTC_APP1 1 394 #define NHW_RTC_NET0 2 395 #define NHW_RTC_NET1 3 396 #define NHW_RTC_INT_MAP {{0 , 20}, \ 397 {0 , 21}, \ 398 {1 , 17}, \ 399 {1 , 22}, \ 400 } /*App core,RTC0..1_IRQn*/ 401 /*Net core,RTC0..1_IRQn*/ 402 #define NHW_RTC_DPPI_MAP {0, 0, 1, 1} /*2xApp core, 2xNetwork core*/ 403 #define NHW_RTC_HAS_CAPTURE 1 404 #define NHW_RTC_HAS_SHORT_COMP_CLEAR 1 405 #define NHW_RTC_N_CC {4, 4, 4, 4} 406 407 #define NHW_SWI_TOTAL_INST 4 408 #define NHW_SWI_NET0 0 409 #define NHW_SWI_NET1 1 410 #define NHW_SWI_NET2 2 411 #define NHW_SWI_NET3 3 412 413 #define NHW_TEMP_TOTAL_INST 1 414 #define NHW_TEMP_NET0 0 415 #define NHW_TEMP_INT_MAP {{1 , 16}} /*Net core,TEMP_IRQn*/ 416 #define NHW_TEMP_DPPI_MAP {1} /*Network core*/ 417 #define NHW_TEMP_t_TEMP 36 /* microseconds */ 418 #define NHW_TEMP_FBITS 2 /* fractional bits => 0.25C resolution */ 419 420 #define NHW_TIMER_TOTAL_INST 6 421 #define NHW_TIMER_APP0 0 422 #define NHW_TIMER_APP1 1 423 #define NHW_TIMER_APP2 2 424 #define NHW_TIMER_NET0 3 425 #define NHW_TIMER_NET1 4 426 #define NHW_TIMER_NET2 5 427 #define NHW_TIMER_INT_MAP {{0 , 15}, \ 428 {0 , 16}, \ 429 {0 , 17}, \ 430 {1 , 12}, \ 431 {1 , 24}, \ 432 {1 , 25}, \ 433 } /* AppCore, TIMER0..2_IRQn */ 434 /* NetCore, TIMER0..2_IRQn */ 435 #define NHW_TIMER_HAS_ONE_SHOT 1 436 #define NHW_TIMER_N_CC {6, 6, 6, 8, 8, 8} 437 #define NHW_TIMER_MAX_N_CC 8 438 #define NHW_TIMER_FREQ {16, 16, 16, 16, 16, 16} 439 #define NHW_TIMER_DPPI_MAP {0, 0, 0, 1, 1, 1} /*3xApp core, 3xNetwork core*/ 440 441 #define NHW_UARTE_TOTAL_INST 5 442 #define NHW_UARTE_APP0 0 443 #define NHW_UARTE_APP1 1 444 #define NHW_UARTE_APP2 2 445 #define NHW_UARTE_APP3 3 446 #define NHW_UARTE_NET0 4 447 #define NHW_UARTE_INT_MAP {{0 , 8}, \ 448 {0 , 9}, \ 449 {0 , 11}, \ 450 {0 , 12}, \ 451 {1 , 19}, \ 452 } /* App core, SERIAL0..3_IRQn, 453 Net core, SERIAL0_IRQn */ 454 #define NHW_UARTE_DPPI_MAP {0, 0, 0, 0, 1} /*4xApp core, 1xNetwork core*/ 455 #define NHW_UARTE_HAS_UART 0 456 #define NHW_UARTE_NAMES {"App UATE0", \ 457 "App UATE1", \ 458 "App UATE2", \ 459 "App UATE3", \ 460 "Net UATE0"} 461 462 #define NHW_FAKE_TIMER_TOTAL_INST 2 463 #define NHW_FAKE_TIMER_INT_MAP {{0 , 0}, \ 464 {1 , 0}} /*App core & Net core, -*/ 465 466 #define NHW_BSTICKER_TOTAL_INST 2 467 #define NHW_BSTICKER_TIMER_INT_MAP {{0 , 0}, \ 468 {1 , 0}} /*App core & Net core, -*/ 469 470 #else 471 #error "No valid platform was selected" 472 #endif 473 474 #endif /* _NRF_HW_CONFIG_H */ 475
