1 /* 2 * Copyright (c) 2023 Nordic Semiconductor ASA 3 * 4 * Note: Most of these file content is taken directly or with minor 5 * modifications from the Nordic nrfx MDK files, which are 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 * 9 * Therefore this file overall has that same license. 10 * 11 * HW peripherals SW regiters interface definitions 12 * For an nRF5340 SOC 13 * 14 */ 15 16 #ifndef _NRF5340_PERI_TYPES_H 17 #define _NRF5340_PERI_TYPES_H 18 19 #include <stdint.h> 20 21 #ifndef __IM 22 #define __IM 23 #endif 24 #ifndef __OM 25 #define __OM 26 #endif 27 #ifndef __IOM 28 #define __IOM 29 #endif 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /** 36 * @brief FICR_INFO [INFO] (Device info) 37 */ 38 typedef struct { 39 __IM uint32_t CONFIGID; /*!< (@ 0x00000000) Configuration identifier */ 40 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 41 __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 42 __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 43 configuration */ 44 __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 45 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 46 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 47 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size in bytes */ 48 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 49 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 50 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 51 52 53 /** 54 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 55 */ 56 typedef struct { 57 __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ 58 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 59 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 60 61 62 /** 63 * @brief FICR_NFC [NFC] (Unspecified) 64 */ 65 typedef struct { 66 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read 67 these values to populate NFCID1_3RD_LAST, 68 NFCID1_2ND_LAST and NFCID1_LAST. */ 69 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read 70 these values to populate NFCID1_3RD_LAST, 71 NFCID1_2ND_LAST and NFCID1_LAST. */ 72 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read 73 these values to populate NFCID1_3RD_LAST, 74 NFCID1_2ND_LAST and NFCID1_LAST. */ 75 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read 76 these values to populate NFCID1_3RD_LAST, 77 NFCID1_2ND_LAST and NFCID1_LAST. */ 78 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 79 80 81 /** 82 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 83 */ 84 typedef struct { 85 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 86 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 87 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 88 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 89 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 90 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 91 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 92 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 93 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 94 95 96 /** 97 * @brief RADIO_PSEL [PSEL] (Unspecified) 98 */ 99 typedef struct { 100 __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin select for DFE pin 101 n */ 102 } RADIO_PSEL_Type; /*!< Size = 32 (0x20) */ 103 104 105 /** 106 * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel) 107 */ 108 typedef struct { 109 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 110 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 111 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of samples transferred in the last transaction */ 112 } RADIO_DFEPACKET_Type; /*!< Size = 12 (0xc) */ 113 114 /** 115 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 116 */ 117 typedef struct { 118 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 119 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 120 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 121 122 123 /** 124 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 125 */ 126 typedef struct { 127 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 128 for task CHG[n].EN */ 129 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 130 for task CHG[n].DIS */ 131 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 132 133 134 /** 135 * @brief CLOCK_HFCLKAUDIO [HFCLKAUDIO] (Unspecified) 136 */ 137 typedef struct { 138 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000000) Audio PLL frequency in 11.176 MHz - 11.402 MHz 139 or 12.165 MHz - 12.411 MHz frequency bands */ 140 } CLOCK_HFCLKAUDIO_Type; /*!< Size = 4 (0x4) */ 141 142 143 /** 144 * @brief RESET_NETWORK [NETWORK] (ULP network core control) 145 */ 146 typedef struct { 147 __IM uint32_t RESERVED; 148 __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force network core off */ 149 } RESET_NETWORK_Type; /*!< Size = 8 (0x8) */ 150 151 152 /** 153 * @brief UART_PSEL [PSEL] (Unspecified) 154 */ 155 typedef struct { 156 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 157 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 158 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 159 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 160 } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 161 162 163 /** 164 * @brief UARTE_PSEL [PSEL] (Unspecified) 165 */ 166 typedef struct { 167 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 168 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 169 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 170 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 171 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 172 173 174 /** 175 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 176 */ 177 typedef struct { 178 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 179 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 180 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 181 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 182 183 184 /** 185 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 186 */ 187 typedef struct { 188 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 189 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 190 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 191 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 192 193 194 /** 195 * @brief VREQCTRL_VREGRADIO [VREGRADIO] (Unspecified) 196 */ 197 typedef struct { 198 __IOM uint32_t VREQH; /*!< (@ 0x00000000) Request high voltage on RADIO After requesting 199 high voltage, the user must wait until VREQHREADY 200 is set to Ready */ 201 __IM uint32_t RESERVED; 202 __IM uint32_t VREQHREADY; /*!< (@ 0x00000008) High voltage on RADIO is ready */ 203 } VREQCTRL_VREGRADIO_Type; /*!< Size = 12 (0xc) */ 204 205 /* =========================================================================================================================== */ 206 /* ================ AAR ================ */ 207 /* =========================================================================================================================== */ 208 209 210 /** 211 * @brief Accelerated Address Resolver (AAR) 212 */ 213 214 typedef struct { /*!< (@ 0x4100E000) AAR_NS Structure */ 215 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 216 in the IRK data structure */ 217 __IM uint32_t RESERVED; 218 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 219 __IM uint32_t RESERVED1[29]; 220 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 221 __IM uint32_t RESERVED2; 222 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 223 __IM uint32_t RESERVED3[29]; 224 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 225 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 226 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 227 __IM uint32_t RESERVED4[29]; 228 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000180) Publish configuration for event END */ 229 __IOM uint32_t PUBLISH_RESOLVED; /*!< (@ 0x00000184) Publish configuration for event RESOLVED */ 230 __IOM uint32_t PUBLISH_NOTRESOLVED; /*!< (@ 0x00000188) Publish configuration for event NOTRESOLVED */ 231 __IM uint32_t RESERVED5[94]; 232 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 233 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 234 __IM uint32_t RESERVED6[61]; 235 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 236 __IM uint32_t RESERVED7[63]; 237 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 238 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 239 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 240 __IM uint32_t RESERVED8; 241 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 242 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 243 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 244 245 /* Peripheral: AAR */ 246 /* Description: Accelerated Address Resolver */ 247 248 /* Register: AAR_TASKS_START */ 249 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ 250 251 /* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ 252 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 253 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 254 #define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 255 256 /* Register: AAR_TASKS_STOP */ 257 /* Description: Stop resolving addresses */ 258 259 /* Bit 0 : Stop resolving addresses */ 260 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 261 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 262 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 263 264 /* Register: AAR_SUBSCRIBE_START */ 265 /* Description: Subscribe configuration for task START */ 266 267 /* Bit 31 : */ 268 #define AAR_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 269 #define AAR_SUBSCRIBE_START_EN_Msk (0x1UL << AAR_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 270 #define AAR_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 271 #define AAR_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 272 273 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 274 #define AAR_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 275 #define AAR_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 276 277 /* Register: AAR_SUBSCRIBE_STOP */ 278 /* Description: Subscribe configuration for task STOP */ 279 280 /* Bit 31 : */ 281 #define AAR_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 282 #define AAR_SUBSCRIBE_STOP_EN_Msk (0x1UL << AAR_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 283 #define AAR_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 284 #define AAR_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 285 286 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 287 #define AAR_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 288 #define AAR_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 289 290 /* Register: AAR_EVENTS_END */ 291 /* Description: Address resolution procedure complete */ 292 293 /* Bit 0 : Address resolution procedure complete */ 294 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 295 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 296 #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 297 #define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 298 299 /* Register: AAR_EVENTS_RESOLVED */ 300 /* Description: Address resolved */ 301 302 /* Bit 0 : Address resolved */ 303 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ 304 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ 305 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */ 306 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */ 307 308 /* Register: AAR_EVENTS_NOTRESOLVED */ 309 /* Description: Address not resolved */ 310 311 /* Bit 0 : Address not resolved */ 312 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ 313 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ 314 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */ 315 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */ 316 317 /* Register: AAR_PUBLISH_END */ 318 /* Description: Publish configuration for event END */ 319 320 /* Bit 31 : */ 321 #define AAR_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 322 #define AAR_PUBLISH_END_EN_Msk (0x1UL << AAR_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 323 #define AAR_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ 324 #define AAR_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ 325 326 /* Bits 7..0 : DPPI channel that event END will publish to. */ 327 #define AAR_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 328 #define AAR_PUBLISH_END_CHIDX_Msk (0xFFUL << AAR_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 329 330 /* Register: AAR_PUBLISH_RESOLVED */ 331 /* Description: Publish configuration for event RESOLVED */ 332 333 /* Bit 31 : */ 334 #define AAR_PUBLISH_RESOLVED_EN_Pos (31UL) /*!< Position of EN field. */ 335 #define AAR_PUBLISH_RESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_RESOLVED_EN_Pos) /*!< Bit mask of EN field. */ 336 #define AAR_PUBLISH_RESOLVED_EN_Disabled (0UL) /*!< Disable publishing */ 337 #define AAR_PUBLISH_RESOLVED_EN_Enabled (1UL) /*!< Enable publishing */ 338 339 /* Bits 7..0 : DPPI channel that event RESOLVED will publish to. */ 340 #define AAR_PUBLISH_RESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 341 #define AAR_PUBLISH_RESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_RESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 342 343 /* Register: AAR_PUBLISH_NOTRESOLVED */ 344 /* Description: Publish configuration for event NOTRESOLVED */ 345 346 /* Bit 31 : */ 347 #define AAR_PUBLISH_NOTRESOLVED_EN_Pos (31UL) /*!< Position of EN field. */ 348 #define AAR_PUBLISH_NOTRESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_NOTRESOLVED_EN_Pos) /*!< Bit mask of EN field. */ 349 #define AAR_PUBLISH_NOTRESOLVED_EN_Disabled (0UL) /*!< Disable publishing */ 350 #define AAR_PUBLISH_NOTRESOLVED_EN_Enabled (1UL) /*!< Enable publishing */ 351 352 /* Bits 7..0 : DPPI channel that event NOTRESOLVED will publish to. */ 353 #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 354 #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 355 356 /* Register: AAR_INTENSET */ 357 /* Description: Enable interrupt */ 358 359 /* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ 360 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 361 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 362 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ 363 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ 364 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ 365 366 /* Bit 1 : Write '1' to enable interrupt for event RESOLVED */ 367 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 368 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 369 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ 370 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ 371 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ 372 373 /* Bit 0 : Write '1' to enable interrupt for event END */ 374 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ 375 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ 376 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 377 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 378 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */ 379 380 /* Register: AAR_INTENCLR */ 381 /* Description: Disable interrupt */ 382 383 /* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ 384 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 385 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 386 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ 387 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ 388 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ 389 390 /* Bit 1 : Write '1' to disable interrupt for event RESOLVED */ 391 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 392 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 393 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ 394 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ 395 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ 396 397 /* Bit 0 : Write '1' to disable interrupt for event END */ 398 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ 399 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 400 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 401 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 402 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ 403 404 /* Register: AAR_STATUS */ 405 /* Description: Resolution status */ 406 407 /* Bits 3..0 : The IRK that was used last time an address was resolved */ 408 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 409 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 410 411 /* Register: AAR_ENABLE */ 412 /* Description: Enable AAR */ 413 414 /* Bits 1..0 : Enable or disable AAR */ 415 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 416 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 417 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 418 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ 419 420 /* Register: AAR_NIRK */ 421 /* Description: Number of IRKs */ 422 423 /* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */ 424 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ 425 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ 426 427 /* Register: AAR_IRKPTR */ 428 /* Description: Pointer to IRK data structure */ 429 430 /* Bits 31..0 : Pointer to the IRK data structure */ 431 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ 432 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ 433 434 /* Register: AAR_ADDRPTR */ 435 /* Description: Pointer to the resolvable address */ 436 437 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ 438 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ 439 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ 440 441 /* Register: AAR_SCRATCHPTR */ 442 /* Description: Pointer to data area used for temporary storage */ 443 444 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */ 445 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ 446 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ 447 448 449 450 /* =========================================================================================================================== */ 451 /* ================ CCM ================ */ 452 /* =========================================================================================================================== */ 453 454 455 /** 456 * @brief AES CCM mode encryption (CCM) 457 */ 458 459 typedef struct { /*!< (@ 0x4100E000) CCM_NS Structure */ 460 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation 461 will stop by itself when completed. */ 462 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 463 stop by itself when completed. */ 464 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 465 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 466 the contents of the RATEOVERRIDE register 467 for any ongoing encryption/decryption */ 468 __IM uint32_t RESERVED[28]; 469 __IOM uint32_t SUBSCRIBE_KSGEN; /*!< (@ 0x00000080) Subscribe configuration for task KSGEN */ 470 __IOM uint32_t SUBSCRIBE_CRYPT; /*!< (@ 0x00000084) Subscribe configuration for task CRYPT */ 471 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 472 __IOM uint32_t SUBSCRIBE_RATEOVERRIDE; /*!< (@ 0x0000008C) Subscribe configuration for task RATEOVERRIDE */ 473 __IM uint32_t RESERVED1[28]; 474 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ 475 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 476 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 477 __IM uint32_t RESERVED2[29]; 478 __IOM uint32_t PUBLISH_ENDKSGEN; /*!< (@ 0x00000180) Publish configuration for event ENDKSGEN */ 479 __IOM uint32_t PUBLISH_ENDCRYPT; /*!< (@ 0x00000184) Publish configuration for event ENDCRYPT */ 480 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000188) Deprecated register - Publish configuration for 481 event ERROR */ 482 __IM uint32_t RESERVED3[29]; 483 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 484 __IM uint32_t RESERVED4[64]; 485 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 486 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 487 __IM uint32_t RESERVED5[61]; 488 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 489 __IM uint32_t RESERVED6[63]; 490 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 491 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 492 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key 493 and the NONCE vector */ 494 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 495 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 496 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 497 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH 498 = Extended */ 499 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 500 __IOM uint32_t HEADERMASK; /*!< (@ 0x00000520) Header (S0) mask. */ 501 } NRF_CCM_Type; /*!< Size = 1316 (0x524) */ 502 503 504 /* Peripheral: CCM */ 505 /* Description: AES CCM mode encryption */ 506 507 /* Register: CCM_TASKS_KSGEN */ 508 /* Description: Start generation of keystream. This operation will stop by itself when completed. */ 509 510 /* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */ 511 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ 512 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ 513 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ 514 515 /* Register: CCM_TASKS_CRYPT */ 516 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */ 517 518 /* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ 519 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ 520 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ 521 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */ 522 523 /* Register: CCM_TASKS_STOP */ 524 /* Description: Stop encryption/decryption */ 525 526 /* Bit 0 : Stop encryption/decryption */ 527 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 528 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 529 #define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 530 531 /* Register: CCM_TASKS_RATEOVERRIDE */ 532 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ 533 534 /* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ 535 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ 536 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ 537 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ 538 539 /* Register: CCM_SUBSCRIBE_KSGEN */ 540 /* Description: Subscribe configuration for task KSGEN */ 541 542 /* Bit 31 : */ 543 #define CCM_SUBSCRIBE_KSGEN_EN_Pos (31UL) /*!< Position of EN field. */ 544 #define CCM_SUBSCRIBE_KSGEN_EN_Msk (0x1UL << CCM_SUBSCRIBE_KSGEN_EN_Pos) /*!< Bit mask of EN field. */ 545 #define CCM_SUBSCRIBE_KSGEN_EN_Disabled (0UL) /*!< Disable subscription */ 546 #define CCM_SUBSCRIBE_KSGEN_EN_Enabled (1UL) /*!< Enable subscription */ 547 548 /* Bits 7..0 : DPPI channel that task KSGEN will subscribe to */ 549 #define CCM_SUBSCRIBE_KSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 550 #define CCM_SUBSCRIBE_KSGEN_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_KSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 551 552 /* Register: CCM_SUBSCRIBE_CRYPT */ 553 /* Description: Subscribe configuration for task CRYPT */ 554 555 /* Bit 31 : */ 556 #define CCM_SUBSCRIBE_CRYPT_EN_Pos (31UL) /*!< Position of EN field. */ 557 #define CCM_SUBSCRIBE_CRYPT_EN_Msk (0x1UL << CCM_SUBSCRIBE_CRYPT_EN_Pos) /*!< Bit mask of EN field. */ 558 #define CCM_SUBSCRIBE_CRYPT_EN_Disabled (0UL) /*!< Disable subscription */ 559 #define CCM_SUBSCRIBE_CRYPT_EN_Enabled (1UL) /*!< Enable subscription */ 560 561 /* Bits 7..0 : DPPI channel that task CRYPT will subscribe to */ 562 #define CCM_SUBSCRIBE_CRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 563 #define CCM_SUBSCRIBE_CRYPT_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_CRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 564 565 /* Register: CCM_SUBSCRIBE_STOP */ 566 /* Description: Subscribe configuration for task STOP */ 567 568 /* Bit 31 : */ 569 #define CCM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 570 #define CCM_SUBSCRIBE_STOP_EN_Msk (0x1UL << CCM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 571 #define CCM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 572 #define CCM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 573 574 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 575 #define CCM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 576 #define CCM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 577 578 /* Register: CCM_SUBSCRIBE_RATEOVERRIDE */ 579 /* Description: Subscribe configuration for task RATEOVERRIDE */ 580 581 /* Bit 31 : */ 582 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos (31UL) /*!< Position of EN field. */ 583 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Msk (0x1UL << CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos) /*!< Bit mask of EN field. */ 584 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Disabled (0UL) /*!< Disable subscription */ 585 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (1UL) /*!< Enable subscription */ 586 587 /* Bits 7..0 : DPPI channel that task RATEOVERRIDE will subscribe to */ 588 #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 589 #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 590 591 /* Register: CCM_EVENTS_ENDKSGEN */ 592 /* Description: Keystream generation complete */ 593 594 /* Bit 0 : Keystream generation complete */ 595 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ 596 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ 597 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ 598 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */ 599 600 /* Register: CCM_EVENTS_ENDCRYPT */ 601 /* Description: Encrypt/decrypt complete */ 602 603 /* Bit 0 : Encrypt/decrypt complete */ 604 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ 605 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ 606 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */ 607 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */ 608 609 /* Register: CCM_EVENTS_ERROR */ 610 /* Description: Deprecated register - CCM error event */ 611 612 /* Bit 0 : Deprecated field - CCM error event */ 613 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 614 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 615 #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ 616 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ 617 618 /* Register: CCM_PUBLISH_ENDKSGEN */ 619 /* Description: Publish configuration for event ENDKSGEN */ 620 621 /* Bit 31 : */ 622 #define CCM_PUBLISH_ENDKSGEN_EN_Pos (31UL) /*!< Position of EN field. */ 623 #define CCM_PUBLISH_ENDKSGEN_EN_Msk (0x1UL << CCM_PUBLISH_ENDKSGEN_EN_Pos) /*!< Bit mask of EN field. */ 624 #define CCM_PUBLISH_ENDKSGEN_EN_Disabled (0UL) /*!< Disable publishing */ 625 #define CCM_PUBLISH_ENDKSGEN_EN_Enabled (1UL) /*!< Enable publishing */ 626 627 /* Bits 7..0 : DPPI channel that event ENDKSGEN will publish to. */ 628 #define CCM_PUBLISH_ENDKSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 629 #define CCM_PUBLISH_ENDKSGEN_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDKSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 630 631 /* Register: CCM_PUBLISH_ENDCRYPT */ 632 /* Description: Publish configuration for event ENDCRYPT */ 633 634 /* Bit 31 : */ 635 #define CCM_PUBLISH_ENDCRYPT_EN_Pos (31UL) /*!< Position of EN field. */ 636 #define CCM_PUBLISH_ENDCRYPT_EN_Msk (0x1UL << CCM_PUBLISH_ENDCRYPT_EN_Pos) /*!< Bit mask of EN field. */ 637 #define CCM_PUBLISH_ENDCRYPT_EN_Disabled (0UL) /*!< Disable publishing */ 638 #define CCM_PUBLISH_ENDCRYPT_EN_Enabled (1UL) /*!< Enable publishing */ 639 640 /* Bits 7..0 : DPPI channel that event ENDCRYPT will publish to. */ 641 #define CCM_PUBLISH_ENDCRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 642 #define CCM_PUBLISH_ENDCRYPT_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDCRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 643 644 /* Register: CCM_PUBLISH_ERROR */ 645 /* Description: Deprecated register - Publish configuration for event ERROR */ 646 647 /* Bit 31 : */ 648 #define CCM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ 649 #define CCM_PUBLISH_ERROR_EN_Msk (0x1UL << CCM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ 650 #define CCM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ 651 #define CCM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ 652 653 /* Bits 7..0 : DPPI channel that event ERROR will publish to. */ 654 #define CCM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 655 #define CCM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 656 657 /* Register: CCM_SHORTS */ 658 /* Description: Shortcuts between local events and tasks */ 659 660 /* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */ 661 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ 662 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ 663 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ 664 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ 665 666 /* Register: CCM_INTENSET */ 667 /* Description: Enable interrupt */ 668 669 /* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */ 670 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 671 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 672 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 673 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 674 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ 675 676 /* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */ 677 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 678 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 679 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ 680 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ 681 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ 682 683 /* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */ 684 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 685 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 686 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ 687 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ 688 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ 689 690 /* Register: CCM_INTENCLR */ 691 /* Description: Disable interrupt */ 692 693 /* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */ 694 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 695 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 696 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 697 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 698 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 699 700 /* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */ 701 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 702 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 703 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ 704 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ 705 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ 706 707 /* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */ 708 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 709 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 710 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ 711 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ 712 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ 713 714 /* Register: CCM_MICSTATUS */ 715 /* Description: MIC check result */ 716 717 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */ 718 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ 719 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ 720 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ 721 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ 722 723 /* Register: CCM_ENABLE */ 724 /* Description: Enable */ 725 726 /* Bits 1..0 : Enable or disable CCM */ 727 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 728 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 729 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 730 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ 731 732 /* Register: CCM_MODE */ 733 /* Description: Operation mode */ 734 735 /* Bit 24 : Packet length configuration */ 736 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ 737 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ 738 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */ 739 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ 740 741 /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ 742 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ 743 #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ 744 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ 745 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ 746 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */ 747 #define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */ 748 749 /* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */ 750 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 751 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 752 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ 753 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ 754 755 /* Register: CCM_CNFPTR */ 756 /* Description: Pointer to data structure holding the AES key and the NONCE vector */ 757 758 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */ 759 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ 760 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ 761 762 /* Register: CCM_INPTR */ 763 /* Description: Input pointer */ 764 765 /* Bits 31..0 : Input pointer */ 766 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ 767 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ 768 769 /* Register: CCM_OUTPTR */ 770 /* Description: Output pointer */ 771 772 /* Bits 31..0 : Output pointer */ 773 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ 774 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ 775 776 /* Register: CCM_SCRATCHPTR */ 777 /* Description: Pointer to data area used for temporary storage */ 778 779 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation, 780 MIC generation and encryption/decryption. */ 781 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ 782 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ 783 784 /* Register: CCM_MAXPACKETSIZE */ 785 /* Description: Length of keystream generated when MODE.LENGTH = Extended */ 786 787 /* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */ 788 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ 789 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ 790 791 /* Register: CCM_RATEOVERRIDE */ 792 /* Description: Data rate override setting. */ 793 794 /* Bits 1..0 : Data rate override setting */ 795 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ 796 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ 797 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ 798 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ 799 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */ 800 #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */ 801 802 /* Register: CCM_HEADERMASK */ 803 /* Description: Header (S0) mask. */ 804 805 /* Bits 7..0 : Header (S0) mask */ 806 #define CCM_HEADERMASK_HEADERMASK_Pos (0UL) /*!< Position of HEADERMASK field. */ 807 #define CCM_HEADERMASK_HEADERMASK_Msk (0xFFUL << CCM_HEADERMASK_HEADERMASK_Pos) /*!< Bit mask of HEADERMASK field. */ 808 809 810 811 /* =========================================================================================================================== */ 812 /* ================ CLOCK ================ */ 813 /* =========================================================================================================================== */ 814 815 816 /** 817 * @brief Clock management (CLOCK) 818 */ 819 820 typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ 821 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK128M/HFCLK64M source as selected in 822 HFCLKSRC */ 823 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK128M/HFCLK64M source */ 824 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source as selected in LFCLKSRC */ 825 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 826 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 827 __IM uint32_t RESERVED; 828 __OM uint32_t TASKS_HFCLKAUDIOSTART; /*!< (@ 0x00000018) Start HFCLKAUDIO source */ 829 __OM uint32_t TASKS_HFCLKAUDIOSTOP; /*!< (@ 0x0000001C) Stop HFCLKAUDIO source */ 830 __OM uint32_t TASKS_HFCLK192MSTART; /*!< (@ 0x00000020) Start HFCLK192M source as selected in HFCLK192MSRC */ 831 __OM uint32_t TASKS_HFCLK192MSTOP; /*!< (@ 0x00000024) Stop HFCLK192M source */ 832 __IM uint32_t RESERVED1[22]; 833 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 834 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 835 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 836 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 837 __IOM uint32_t SUBSCRIBE_CAL; /*!< (@ 0x00000090) Subscribe configuration for task CAL */ 838 __IM uint32_t RESERVED2; 839 __IOM uint32_t SUBSCRIBE_HFCLKAUDIOSTART; /*!< (@ 0x00000098) Subscribe configuration for task HFCLKAUDIOSTART */ 840 __IOM uint32_t SUBSCRIBE_HFCLKAUDIOSTOP; /*!< (@ 0x0000009C) Subscribe configuration for task HFCLKAUDIOSTOP */ 841 __IOM uint32_t SUBSCRIBE_HFCLK192MSTART; /*!< (@ 0x000000A0) Subscribe configuration for task HFCLK192MSTART */ 842 __IOM uint32_t SUBSCRIBE_HFCLK192MSTOP; /*!< (@ 0x000000A4) Subscribe configuration for task HFCLK192MSTOP */ 843 __IM uint32_t RESERVED3[22]; 844 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK128M/HFCLK64M source started */ 845 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK source started */ 846 __IM uint32_t RESERVED4[5]; 847 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000011C) Calibration of LFRC oscillator complete event */ 848 __IOM uint32_t EVENTS_HFCLKAUDIOSTARTED; /*!< (@ 0x00000120) HFCLKAUDIO source started */ 849 __IOM uint32_t EVENTS_HFCLK192MSTARTED; /*!< (@ 0x00000124) HFCLK192M source started */ 850 __IM uint32_t RESERVED5[22]; 851 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 852 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 853 __IM uint32_t RESERVED6[5]; 854 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x0000019C) Publish configuration for event DONE */ 855 __IOM uint32_t PUBLISH_HFCLKAUDIOSTARTED; /*!< (@ 0x000001A0) Publish configuration for event HFCLKAUDIOSTARTED */ 856 __IOM uint32_t PUBLISH_HFCLK192MSTARTED; /*!< (@ 0x000001A4) Publish configuration for event HFCLK192MSTARTED */ 857 __IM uint32_t RESERVED7[86]; 858 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 859 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 860 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 861 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 862 __IM uint32_t RESERVED8[62]; 863 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 864 triggered */ 865 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) Status indicating which HFCLK128M/HFCLK64M source 866 is running This register value in any CLOCK 867 instance reflects status only due to configurations/action 868 in that CLOCK instance. */ 869 __IM uint32_t RESERVED9; 870 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 871 triggered */ 872 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Status indicating which LFCLK source is running 873 This register value in any CLOCK instance 874 reflects status only due to configurations/actions 875 in that CLOCK instance. */ 876 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 877 task was triggered */ 878 __IM uint32_t RESERVED10[12]; 879 __IM uint32_t HFCLKAUDIORUN; /*!< (@ 0x00000450) Status indicating that HFCLKAUDIOSTART task has 880 been triggered */ 881 __IM uint32_t HFCLKAUDIOSTAT; /*!< (@ 0x00000454) Status indicating which HFCLKAUDIO source is 882 running */ 883 __IM uint32_t HFCLK192MRUN; /*!< (@ 0x00000458) Status indicating that HFCLK192MSTART task has 884 been triggered */ 885 __IM uint32_t HFCLK192MSTAT; /*!< (@ 0x0000045C) Status indicating which HFCLK192M source is running */ 886 __IM uint32_t RESERVED11[45]; 887 __IOM uint32_t HFCLKSRC; /*!< (@ 0x00000514) Clock source for HFCLK128M/HFCLK64M */ 888 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for LFCLK */ 889 __IM uint32_t RESERVED12[15]; 890 __IOM uint32_t HFCLKCTRL; /*!< (@ 0x00000558) HFCLK128M frequency configuration */ 891 __IOM CLOCK_HFCLKAUDIO_Type HFCLKAUDIO; /*!< (@ 0x0000055C) Unspecified */ 892 __IM uint32_t RESERVED13[4]; 893 __IOM uint32_t HFCLKALWAYSRUN; /*!< (@ 0x00000570) Automatic or manual control of HFCLK128M/HFCLK64M */ 894 __IOM uint32_t LFCLKALWAYSRUN; /*!< (@ 0x00000574) Automatic or manual control of LFCLK */ 895 __IM uint32_t RESERVED14; 896 __IOM uint32_t HFCLKAUDIOALWAYSRUN; /*!< (@ 0x0000057C) Automatic or manual control of HFCLKAUDIO */ 897 __IOM uint32_t HFCLK192MSRC; /*!< (@ 0x00000580) Clock source for HFCLK192M */ 898 __IOM uint32_t HFCLK192MALWAYSRUN; /*!< (@ 0x00000584) Automatic or manual control of HFCLK192M */ 899 __IM uint32_t RESERVED15[12]; 900 __IOM uint32_t HFCLK192MCTRL; /*!< (@ 0x000005B8) HFCLK192M frequency configuration */ 901 } NRF_CLOCK_Type; /*!< Size = 1468 (0x5bc) */ 902 903 904 /* Peripheral: CLOCK */ 905 /* Description: Clock management 0 */ 906 907 /* Register: CLOCK_TASKS_HFCLKSTART */ 908 /* Description: Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */ 909 910 /* Bit 0 : Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */ 911 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ 912 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ 913 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ 914 915 /* Register: CLOCK_TASKS_HFCLKSTOP */ 916 /* Description: Stop HFCLK128M/HFCLK64M source */ 917 918 /* Bit 0 : Stop HFCLK128M/HFCLK64M source */ 919 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ 920 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ 921 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ 922 923 /* Register: CLOCK_TASKS_LFCLKSTART */ 924 /* Description: Start LFCLK source as selected in LFCLKSRC */ 925 926 /* Bit 0 : Start LFCLK source as selected in LFCLKSRC */ 927 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ 928 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ 929 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ 930 931 /* Register: CLOCK_TASKS_LFCLKSTOP */ 932 /* Description: Stop LFCLK source */ 933 934 /* Bit 0 : Stop LFCLK source */ 935 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ 936 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ 937 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ 938 939 /* Register: CLOCK_TASKS_CAL */ 940 /* Description: Start calibration of LFRC oscillator */ 941 942 /* Bit 0 : Start calibration of LFRC oscillator */ 943 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ 944 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ 945 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ 946 947 /* Register: CLOCK_TASKS_HFCLKAUDIOSTART */ 948 /* Description: Start HFCLKAUDIO source */ 949 950 /* Bit 0 : Start HFCLKAUDIO source */ 951 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTART field. */ 952 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTART field. */ 953 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Trigger (1UL) /*!< Trigger task */ 954 955 /* Register: CLOCK_TASKS_HFCLKAUDIOSTOP */ 956 /* Description: Stop HFCLKAUDIO source */ 957 958 /* Bit 0 : Stop HFCLKAUDIO source */ 959 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTOP field. */ 960 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTOP field. */ 961 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Trigger (1UL) /*!< Trigger task */ 962 963 /* Register: CLOCK_TASKS_HFCLK192MSTART */ 964 /* Description: Start HFCLK192M source as selected in HFCLK192MSRC */ 965 966 /* Bit 0 : Start HFCLK192M source as selected in HFCLK192MSRC */ 967 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTART field. */ 968 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos) /*!< Bit mask of TASKS_HFCLK192MSTART field. */ 969 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Trigger (1UL) /*!< Trigger task */ 970 971 /* Register: CLOCK_TASKS_HFCLK192MSTOP */ 972 /* Description: Stop HFCLK192M source */ 973 974 /* Bit 0 : Stop HFCLK192M source */ 975 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTOP field. */ 976 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos) /*!< Bit mask of TASKS_HFCLK192MSTOP field. */ 977 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Trigger (1UL) /*!< Trigger task */ 978 979 /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */ 980 /* Description: Subscribe configuration for task HFCLKSTART */ 981 982 /* Bit 31 : */ 983 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ 984 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ 985 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ 986 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ 987 988 /* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */ 989 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 990 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 991 992 /* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */ 993 /* Description: Subscribe configuration for task HFCLKSTOP */ 994 995 /* Bit 31 : */ 996 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 997 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ 998 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 999 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 1000 1001 /* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */ 1002 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1003 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1004 1005 /* Register: CLOCK_SUBSCRIBE_LFCLKSTART */ 1006 /* Description: Subscribe configuration for task LFCLKSTART */ 1007 1008 /* Bit 31 : */ 1009 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ 1010 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ 1011 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ 1012 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ 1013 1014 /* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */ 1015 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1016 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1017 1018 /* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */ 1019 /* Description: Subscribe configuration for task LFCLKSTOP */ 1020 1021 /* Bit 31 : */ 1022 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 1023 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ 1024 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 1025 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 1026 1027 /* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */ 1028 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1029 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1030 1031 /* Register: CLOCK_SUBSCRIBE_CAL */ 1032 /* Description: Subscribe configuration for task CAL */ 1033 1034 /* Bit 31 : */ 1035 #define CLOCK_SUBSCRIBE_CAL_EN_Pos (31UL) /*!< Position of EN field. */ 1036 #define CLOCK_SUBSCRIBE_CAL_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_CAL_EN_Pos) /*!< Bit mask of EN field. */ 1037 #define CLOCK_SUBSCRIBE_CAL_EN_Disabled (0UL) /*!< Disable subscription */ 1038 #define CLOCK_SUBSCRIBE_CAL_EN_Enabled (1UL) /*!< Enable subscription */ 1039 1040 /* Bits 7..0 : DPPI channel that task CAL will subscribe to */ 1041 #define CLOCK_SUBSCRIBE_CAL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1042 #define CLOCK_SUBSCRIBE_CAL_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_CAL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1043 1044 /* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTART */ 1045 /* Description: Subscribe configuration for task HFCLKAUDIOSTART */ 1046 1047 /* Bit 31 : */ 1048 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos (31UL) /*!< Position of EN field. */ 1049 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos) /*!< Bit mask of EN field. */ 1050 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Disabled (0UL) /*!< Disable subscription */ 1051 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Enabled (1UL) /*!< Enable subscription */ 1052 1053 /* Bits 7..0 : DPPI channel that task HFCLKAUDIOSTART will subscribe to */ 1054 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1055 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1056 1057 /* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP */ 1058 /* Description: Subscribe configuration for task HFCLKAUDIOSTOP */ 1059 1060 /* Bit 31 : */ 1061 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 1062 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos) /*!< Bit mask of EN field. */ 1063 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 1064 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 1065 1066 /* Bits 7..0 : DPPI channel that task HFCLKAUDIOSTOP will subscribe to */ 1067 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1068 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1069 1070 /* Register: CLOCK_SUBSCRIBE_HFCLK192MSTART */ 1071 /* Description: Subscribe configuration for task HFCLK192MSTART */ 1072 1073 /* Bit 31 : */ 1074 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos (31UL) /*!< Position of EN field. */ 1075 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos) /*!< Bit mask of EN field. */ 1076 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Disabled (0UL) /*!< Disable subscription */ 1077 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Enabled (1UL) /*!< Enable subscription */ 1078 1079 /* Bits 7..0 : DPPI channel that task HFCLK192MSTART will subscribe to */ 1080 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1081 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1082 1083 /* Register: CLOCK_SUBSCRIBE_HFCLK192MSTOP */ 1084 /* Description: Subscribe configuration for task HFCLK192MSTOP */ 1085 1086 /* Bit 31 : */ 1087 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 1088 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos) /*!< Bit mask of EN field. */ 1089 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 1090 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 1091 1092 /* Bits 7..0 : DPPI channel that task HFCLK192MSTOP will subscribe to */ 1093 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1094 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1095 1096 /* Register: CLOCK_EVENTS_HFCLKSTARTED */ 1097 /* Description: HFCLK128M/HFCLK64M source started */ 1098 1099 /* Bit 0 : HFCLK128M/HFCLK64M source started */ 1100 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ 1101 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ 1102 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ 1103 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ 1104 1105 /* Register: CLOCK_EVENTS_LFCLKSTARTED */ 1106 /* Description: LFCLK source started */ 1107 1108 /* Bit 0 : LFCLK source started */ 1109 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ 1110 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ 1111 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ 1112 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ 1113 1114 /* Register: CLOCK_EVENTS_DONE */ 1115 /* Description: Calibration of LFRC oscillator complete event */ 1116 1117 /* Bit 0 : Calibration of LFRC oscillator complete event */ 1118 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ 1119 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ 1120 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ 1121 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ 1122 1123 /* Register: CLOCK_EVENTS_HFCLKAUDIOSTARTED */ 1124 /* Description: HFCLKAUDIO source started */ 1125 1126 /* Bit 0 : HFCLKAUDIO source started */ 1127 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKAUDIOSTARTED field. */ 1128 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKAUDIOSTARTED field. */ 1129 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_NotGenerated (0UL) /*!< Event not generated */ 1130 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Generated (1UL) /*!< Event generated */ 1131 1132 /* Register: CLOCK_EVENTS_HFCLK192MSTARTED */ 1133 /* Description: HFCLK192M source started */ 1134 1135 /* Bit 0 : HFCLK192M source started */ 1136 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLK192MSTARTED field. */ 1137 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLK192MSTARTED field. */ 1138 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_NotGenerated (0UL) /*!< Event not generated */ 1139 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Generated (1UL) /*!< Event generated */ 1140 1141 /* Register: CLOCK_PUBLISH_HFCLKSTARTED */ 1142 /* Description: Publish configuration for event HFCLKSTARTED */ 1143 1144 /* Bit 31 : */ 1145 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 1146 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 1147 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 1148 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 1149 1150 /* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to. */ 1151 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1152 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1153 1154 /* Register: CLOCK_PUBLISH_LFCLKSTARTED */ 1155 /* Description: Publish configuration for event LFCLKSTARTED */ 1156 1157 /* Bit 31 : */ 1158 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 1159 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 1160 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 1161 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 1162 1163 /* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to. */ 1164 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1165 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1166 1167 /* Register: CLOCK_PUBLISH_DONE */ 1168 /* Description: Publish configuration for event DONE */ 1169 1170 /* Bit 31 : */ 1171 #define CLOCK_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */ 1172 #define CLOCK_PUBLISH_DONE_EN_Msk (0x1UL << CLOCK_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */ 1173 #define CLOCK_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */ 1174 #define CLOCK_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */ 1175 1176 /* Bits 7..0 : DPPI channel that event DONE will publish to. */ 1177 #define CLOCK_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1178 #define CLOCK_PUBLISH_DONE_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1179 1180 /* Register: CLOCK_PUBLISH_HFCLKAUDIOSTARTED */ 1181 /* Description: Publish configuration for event HFCLKAUDIOSTARTED */ 1182 1183 /* Bit 31 : */ 1184 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 1185 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 1186 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 1187 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 1188 1189 /* Bits 7..0 : DPPI channel that event HFCLKAUDIOSTARTED will publish to. */ 1190 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1191 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1192 1193 /* Register: CLOCK_PUBLISH_HFCLK192MSTARTED */ 1194 /* Description: Publish configuration for event HFCLK192MSTARTED */ 1195 1196 /* Bit 31 : */ 1197 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 1198 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 1199 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 1200 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 1201 1202 /* Bits 7..0 : DPPI channel that event HFCLK192MSTARTED will publish to. */ 1203 #define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1204 #define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1205 1206 /* Register: CLOCK_INTEN */ 1207 /* Description: Enable or disable interrupt */ 1208 1209 /* Bit 9 : Enable or disable interrupt for event HFCLK192MSTARTED */ 1210 #define CLOCK_INTEN_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ 1211 #define CLOCK_INTEN_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ 1212 #define CLOCK_INTEN_HFCLK192MSTARTED_Disabled (0UL) /*!< Disable */ 1213 #define CLOCK_INTEN_HFCLK192MSTARTED_Enabled (1UL) /*!< Enable */ 1214 1215 /* Bit 8 : Enable or disable interrupt for event HFCLKAUDIOSTARTED */ 1216 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ 1217 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ 1218 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Disable */ 1219 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Enable */ 1220 1221 /* Bit 7 : Enable or disable interrupt for event DONE */ 1222 #define CLOCK_INTEN_DONE_Pos (7UL) /*!< Position of DONE field. */ 1223 #define CLOCK_INTEN_DONE_Msk (0x1UL << CLOCK_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ 1224 #define CLOCK_INTEN_DONE_Disabled (0UL) /*!< Disable */ 1225 #define CLOCK_INTEN_DONE_Enabled (1UL) /*!< Enable */ 1226 1227 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */ 1228 #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 1229 #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 1230 #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */ 1231 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */ 1232 1233 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */ 1234 #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 1235 #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 1236 #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */ 1237 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */ 1238 1239 /* Register: CLOCK_INTENSET */ 1240 /* Description: Enable interrupt */ 1241 1242 /* Bit 9 : Write '1' to enable interrupt for event HFCLK192MSTARTED */ 1243 #define CLOCK_INTENSET_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ 1244 #define CLOCK_INTENSET_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ 1245 #define CLOCK_INTENSET_HFCLK192MSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1246 #define CLOCK_INTENSET_HFCLK192MSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1247 #define CLOCK_INTENSET_HFCLK192MSTARTED_Set (1UL) /*!< Enable */ 1248 1249 /* Bit 8 : Write '1' to enable interrupt for event HFCLKAUDIOSTARTED */ 1250 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ 1251 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ 1252 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1253 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1254 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Set (1UL) /*!< Enable */ 1255 1256 /* Bit 7 : Write '1' to enable interrupt for event DONE */ 1257 #define CLOCK_INTENSET_DONE_Pos (7UL) /*!< Position of DONE field. */ 1258 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 1259 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ 1260 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ 1261 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ 1262 1263 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ 1264 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 1265 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 1266 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1267 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1268 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ 1269 1270 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ 1271 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 1272 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 1273 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1274 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1275 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ 1276 1277 /* Register: CLOCK_INTENCLR */ 1278 /* Description: Disable interrupt */ 1279 1280 /* Bit 9 : Write '1' to disable interrupt for event HFCLK192MSTARTED */ 1281 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ 1282 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ 1283 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1284 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1285 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Clear (1UL) /*!< Disable */ 1286 1287 /* Bit 8 : Write '1' to disable interrupt for event HFCLKAUDIOSTARTED */ 1288 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ 1289 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ 1290 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1291 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1292 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Clear (1UL) /*!< Disable */ 1293 1294 /* Bit 7 : Write '1' to disable interrupt for event DONE */ 1295 #define CLOCK_INTENCLR_DONE_Pos (7UL) /*!< Position of DONE field. */ 1296 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 1297 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ 1298 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ 1299 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ 1300 1301 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ 1302 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 1303 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 1304 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1305 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1306 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ 1307 1308 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ 1309 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 1310 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 1311 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1312 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1313 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ 1314 1315 /* Register: CLOCK_INTPEND */ 1316 /* Description: Pending interrupts */ 1317 1318 /* Bit 9 : Read pending status of interrupt for event HFCLK192MSTARTED */ 1319 #define CLOCK_INTPEND_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ 1320 #define CLOCK_INTPEND_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ 1321 #define CLOCK_INTPEND_HFCLK192MSTARTED_NotPending (0UL) /*!< Read: Not pending */ 1322 #define CLOCK_INTPEND_HFCLK192MSTARTED_Pending (1UL) /*!< Read: Pending */ 1323 1324 /* Bit 8 : Read pending status of interrupt for event HFCLKAUDIOSTARTED */ 1325 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ 1326 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ 1327 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_NotPending (0UL) /*!< Read: Not pending */ 1328 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pending (1UL) /*!< Read: Pending */ 1329 1330 /* Bit 7 : Read pending status of interrupt for event DONE */ 1331 #define CLOCK_INTPEND_DONE_Pos (7UL) /*!< Position of DONE field. */ 1332 #define CLOCK_INTPEND_DONE_Msk (0x1UL << CLOCK_INTPEND_DONE_Pos) /*!< Bit mask of DONE field. */ 1333 #define CLOCK_INTPEND_DONE_NotPending (0UL) /*!< Read: Not pending */ 1334 #define CLOCK_INTPEND_DONE_Pending (1UL) /*!< Read: Pending */ 1335 1336 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */ 1337 #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 1338 #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 1339 #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */ 1340 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */ 1341 1342 /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */ 1343 #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 1344 #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 1345 #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */ 1346 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */ 1347 1348 /* Register: CLOCK_HFCLKRUN */ 1349 /* Description: Status indicating that HFCLKSTART task has been triggered */ 1350 1351 /* Bit 0 : HFCLKSTART task triggered or not */ 1352 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1353 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1354 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 1355 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 1356 1357 /* Register: CLOCK_HFCLKSTAT */ 1358 /* Description: Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ 1359 1360 /* Bit 16 : HFCLK state */ 1361 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 1362 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 1363 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ 1364 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ 1365 1366 /* Bit 4 : ALWAYSRUN activated */ 1367 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */ 1368 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */ 1369 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */ 1370 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */ 1371 1372 /* Bit 0 : Active clock source */ 1373 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 1374 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 1375 #define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< Clock source: HFINT - 128 MHz on-chip oscillator */ 1376 #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator */ 1377 1378 /* Register: CLOCK_LFCLKRUN */ 1379 /* Description: Status indicating that LFCLKSTART task has been triggered */ 1380 1381 /* Bit 0 : LFCLKSTART task triggered or not */ 1382 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1383 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1384 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 1385 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 1386 1387 /* Register: CLOCK_LFCLKSTAT */ 1388 /* Description: Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ 1389 1390 /* Bit 16 : LFCLK state */ 1391 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 1392 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 1393 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ 1394 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ 1395 1396 /* Bit 4 : ALWAYSRUN activated */ 1397 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */ 1398 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */ 1399 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */ 1400 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */ 1401 1402 /* Bits 1..0 : Active clock source */ 1403 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 1404 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 1405 #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ 1406 #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ 1407 #define CLOCK_LFCLKSTAT_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ 1408 1409 /* Register: CLOCK_LFCLKSRCCOPY */ 1410 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ 1411 1412 /* Bits 1..0 : Clock source */ 1413 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ 1414 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ 1415 #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ 1416 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ 1417 #define CLOCK_LFCLKSRCCOPY_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ 1418 1419 /* Register: CLOCK_HFCLKAUDIORUN */ 1420 /* Description: Status indicating that HFCLKAUDIOSTART task has been triggered */ 1421 1422 /* Bit 0 : HFCLKAUDIOSTART task triggered or not */ 1423 #define CLOCK_HFCLKAUDIORUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1424 #define CLOCK_HFCLKAUDIORUN_STATUS_Msk (0x1UL << CLOCK_HFCLKAUDIORUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1425 #define CLOCK_HFCLKAUDIORUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 1426 #define CLOCK_HFCLKAUDIORUN_STATUS_Triggered (1UL) /*!< Task triggered */ 1427 1428 /* Register: CLOCK_HFCLKAUDIOSTAT */ 1429 /* Description: Status indicating which HFCLKAUDIO source is running */ 1430 1431 /* Bit 16 : HFCLKAUDIO state */ 1432 #define CLOCK_HFCLKAUDIOSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 1433 #define CLOCK_HFCLKAUDIOSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 1434 #define CLOCK_HFCLKAUDIOSTAT_STATE_NotRunning (0UL) /*!< HFCLKAUDIO not running */ 1435 #define CLOCK_HFCLKAUDIOSTAT_STATE_Running (1UL) /*!< HFCLKAUDIO running */ 1436 1437 /* Bit 4 : ALWAYSRUN activated */ 1438 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */ 1439 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */ 1440 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */ 1441 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */ 1442 1443 /* Register: CLOCK_HFCLK192MRUN */ 1444 /* Description: Status indicating that HFCLK192MSTART task has been triggered */ 1445 1446 /* Bit 0 : HFCLK192MSTART task triggered or not */ 1447 #define CLOCK_HFCLK192MRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1448 #define CLOCK_HFCLK192MRUN_STATUS_Msk (0x1UL << CLOCK_HFCLK192MRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1449 #define CLOCK_HFCLK192MRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 1450 #define CLOCK_HFCLK192MRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 1451 1452 /* Register: CLOCK_HFCLK192MSTAT */ 1453 /* Description: Status indicating which HFCLK192M source is running */ 1454 1455 /* Bit 16 : HFCLK192M state */ 1456 #define CLOCK_HFCLK192MSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 1457 #define CLOCK_HFCLK192MSTAT_STATE_Msk (0x1UL << CLOCK_HFCLK192MSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 1458 #define CLOCK_HFCLK192MSTAT_STATE_NotRunning (0UL) /*!< HFCLK192M not running */ 1459 #define CLOCK_HFCLK192MSTAT_STATE_Running (1UL) /*!< HFCLK192M running */ 1460 1461 /* Bit 4 : ALWAYSRUN activated */ 1462 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */ 1463 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */ 1464 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */ 1465 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */ 1466 1467 /* Bit 0 : Active clock source */ 1468 #define CLOCK_HFCLK192MSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 1469 #define CLOCK_HFCLK192MSTAT_SRC_Msk (0x1UL << CLOCK_HFCLK192MSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 1470 #define CLOCK_HFCLK192MSTAT_SRC_HFINT (0UL) /*!< Clock source: HFINT - on-chip oscillator */ 1471 #define CLOCK_HFCLK192MSTAT_SRC_HFXO (1UL) /*!< Clock source: HFXO - derived from external 32 MHz crystal oscillator */ 1472 1473 /* Register: CLOCK_HFCLKSRC */ 1474 /* Description: Clock source for HFCLK128M/HFCLK64M */ 1475 1476 /* Bit 0 : Select which HFCLK source is started by the HFCLKSTART task */ 1477 #define CLOCK_HFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 1478 #define CLOCK_HFCLKSRC_SRC_Msk (0x1UL << CLOCK_HFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 1479 #define CLOCK_HFCLKSRC_SRC_HFINT (0UL) /*!< HFCLKSTART task starts HFINT oscillator */ 1480 #define CLOCK_HFCLKSRC_SRC_HFXO (1UL) /*!< HFCLKSTART task starts HFXO oscillator */ 1481 1482 /* Register: CLOCK_LFCLKSRC */ 1483 /* Description: Clock source for LFCLK */ 1484 1485 /* Bits 1..0 : Select which LFCLK source is started by the LFCLKSTART task */ 1486 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 1487 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 1488 #define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ 1489 #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ 1490 #define CLOCK_LFCLKSRC_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ 1491 1492 /* Register: CLOCK_HFCLKCTRL */ 1493 /* Description: HFCLK128M frequency configuration */ 1494 1495 /* Bits 1..0 : High frequency clock HCLK */ 1496 #define CLOCK_HFCLKCTRL_HCLK_Pos (0UL) /*!< Position of HCLK field. */ 1497 #define CLOCK_HFCLKCTRL_HCLK_Msk (0x3UL << CLOCK_HFCLKCTRL_HCLK_Pos) /*!< Bit mask of HCLK field. */ 1498 #define CLOCK_HFCLKCTRL_HCLK_Div1 (0UL) /*!< Divide HFCLK by 1 */ 1499 #define CLOCK_HFCLKCTRL_HCLK_Div2 (1UL) /*!< Divide HFCLK by 2 */ 1500 1501 /* Register: CLOCK_HFCLKAUDIO_FREQUENCY */ 1502 /* Description: Audio PLL frequency in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands */ 1503 1504 /* Bits 15..0 : Frequency 0: 10.666 MHz 65535: 13.333 MHz */ 1505 #define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 1506 #define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Msk (0xFFFFUL << CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 1507 1508 /* Register: CLOCK_HFCLKALWAYSRUN */ 1509 /* Description: Automatic or manual control of HFCLK128M/HFCLK64M */ 1510 1511 /* Bit 0 : Ensure clock is always running */ 1512 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */ 1513 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */ 1514 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */ 1515 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */ 1516 1517 /* Register: CLOCK_LFCLKALWAYSRUN */ 1518 /* Description: Automatic or manual control of LFCLK */ 1519 1520 /* Bit 0 : Ensure clock is always running */ 1521 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */ 1522 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */ 1523 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */ 1524 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */ 1525 1526 /* Register: CLOCK_HFCLKAUDIOALWAYSRUN */ 1527 /* Description: Automatic or manual control of HFCLKAUDIO */ 1528 1529 /* Bit 0 : Ensure clock is always running */ 1530 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */ 1531 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */ 1532 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */ 1533 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */ 1534 1535 /* Register: CLOCK_HFCLK192MSRC */ 1536 /* Description: Clock source for HFCLK192M */ 1537 1538 /* Bit 0 : Select which HFCLK192M source is started by the HFCLK192MSTART task */ 1539 #define CLOCK_HFCLK192MSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 1540 #define CLOCK_HFCLK192MSRC_SRC_Msk (0x1UL << CLOCK_HFCLK192MSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 1541 #define CLOCK_HFCLK192MSRC_SRC_HFINT (0UL) /*!< HFCLK192MSTART task starts HFINT oscillator */ 1542 #define CLOCK_HFCLK192MSRC_SRC_HFXO (1UL) /*!< HFCLK192MSTART task starts HFXO oscillator */ 1543 1544 /* Register: CLOCK_HFCLK192MALWAYSRUN */ 1545 /* Description: Automatic or manual control of HFCLK192M */ 1546 1547 /* Bit 0 : Ensure clock is always running */ 1548 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */ 1549 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */ 1550 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */ 1551 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */ 1552 1553 /* Register: CLOCK_HFCLK192MCTRL */ 1554 /* Description: HFCLK192M frequency configuration */ 1555 1556 /* Bits 1..0 : High frequency clock HCLK192M */ 1557 #define CLOCK_HFCLK192MCTRL_HCLK192M_Pos (0UL) /*!< Position of HCLK192M field. */ 1558 #define CLOCK_HFCLK192MCTRL_HCLK192M_Msk (0x3UL << CLOCK_HFCLK192MCTRL_HCLK192M_Pos) /*!< Bit mask of HCLK192M field. */ 1559 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div1 (0UL) /*!< Divide HFCLK192M by 1 */ 1560 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div2 (1UL) /*!< Divide HFCLK192M by 2 */ 1561 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div4 (2UL) /*!< Divide HFCLK192M by 4 */ 1562 1563 /* =========================================================================================================================== */ 1564 /* ================ ECB_NS ================ */ 1565 /* =========================================================================================================================== */ 1566 1567 1568 /** 1569 * @brief AES ECB Mode Encryption (ECB_NS) 1570 */ 1571 1572 typedef struct { /*!< (@ 0x4100D000) ECB_NS Structure */ 1573 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1574 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1575 __IM uint32_t RESERVED[30]; 1576 __IOM uint32_t SUBSCRIBE_STARTECB; /*!< (@ 0x00000080) Subscribe configuration for task STARTECB */ 1577 __IOM uint32_t SUBSCRIBE_STOPECB; /*!< (@ 0x00000084) Subscribe configuration for task STOPECB */ 1578 __IM uint32_t RESERVED1[30]; 1579 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1580 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1581 task or due to an error */ 1582 __IM uint32_t RESERVED2[30]; 1583 __IOM uint32_t PUBLISH_ENDECB; /*!< (@ 0x00000180) Publish configuration for event ENDECB */ 1584 __IOM uint32_t PUBLISH_ERRORECB; /*!< (@ 0x00000184) Publish configuration for event ERRORECB */ 1585 __IM uint32_t RESERVED3[95]; 1586 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1587 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1588 __IM uint32_t RESERVED4[126]; 1589 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1590 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1591 1592 1593 /* Peripheral: ECB */ 1594 /* Description: AES ECB Mode Encryption */ 1595 1596 /* Register: ECB_TASKS_STARTECB */ 1597 /* Description: Start ECB block encrypt */ 1598 1599 /* Bit 0 : Start ECB block encrypt */ 1600 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ 1601 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ 1602 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */ 1603 1604 /* Register: ECB_TASKS_STOPECB */ 1605 /* Description: Abort a possible executing ECB operation */ 1606 1607 /* Bit 0 : Abort a possible executing ECB operation */ 1608 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ 1609 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ 1610 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */ 1611 1612 /* Register: ECB_SUBSCRIBE_STARTECB */ 1613 /* Description: Subscribe configuration for task STARTECB */ 1614 1615 /* Bit 31 : */ 1616 #define ECB_SUBSCRIBE_STARTECB_EN_Pos (31UL) /*!< Position of EN field. */ 1617 #define ECB_SUBSCRIBE_STARTECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STARTECB_EN_Pos) /*!< Bit mask of EN field. */ 1618 #define ECB_SUBSCRIBE_STARTECB_EN_Disabled (0UL) /*!< Disable subscription */ 1619 #define ECB_SUBSCRIBE_STARTECB_EN_Enabled (1UL) /*!< Enable subscription */ 1620 1621 /* Bits 7..0 : DPPI channel that task STARTECB will subscribe to */ 1622 #define ECB_SUBSCRIBE_STARTECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1623 #define ECB_SUBSCRIBE_STARTECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STARTECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1624 1625 /* Register: ECB_SUBSCRIBE_STOPECB */ 1626 /* Description: Subscribe configuration for task STOPECB */ 1627 1628 /* Bit 31 : */ 1629 #define ECB_SUBSCRIBE_STOPECB_EN_Pos (31UL) /*!< Position of EN field. */ 1630 #define ECB_SUBSCRIBE_STOPECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STOPECB_EN_Pos) /*!< Bit mask of EN field. */ 1631 #define ECB_SUBSCRIBE_STOPECB_EN_Disabled (0UL) /*!< Disable subscription */ 1632 #define ECB_SUBSCRIBE_STOPECB_EN_Enabled (1UL) /*!< Enable subscription */ 1633 1634 /* Bits 7..0 : DPPI channel that task STOPECB will subscribe to */ 1635 #define ECB_SUBSCRIBE_STOPECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1636 #define ECB_SUBSCRIBE_STOPECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STOPECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1637 1638 /* Register: ECB_EVENTS_ENDECB */ 1639 /* Description: ECB block encrypt complete */ 1640 1641 /* Bit 0 : ECB block encrypt complete */ 1642 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ 1643 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ 1644 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */ 1645 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */ 1646 1647 /* Register: ECB_EVENTS_ERRORECB */ 1648 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ 1649 1650 /* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */ 1651 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ 1652 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ 1653 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */ 1654 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */ 1655 1656 /* Register: ECB_PUBLISH_ENDECB */ 1657 /* Description: Publish configuration for event ENDECB */ 1658 1659 /* Bit 31 : */ 1660 #define ECB_PUBLISH_ENDECB_EN_Pos (31UL) /*!< Position of EN field. */ 1661 #define ECB_PUBLISH_ENDECB_EN_Msk (0x1UL << ECB_PUBLISH_ENDECB_EN_Pos) /*!< Bit mask of EN field. */ 1662 #define ECB_PUBLISH_ENDECB_EN_Disabled (0UL) /*!< Disable publishing */ 1663 #define ECB_PUBLISH_ENDECB_EN_Enabled (1UL) /*!< Enable publishing */ 1664 1665 /* Bits 7..0 : DPPI channel that event ENDECB will publish to. */ 1666 #define ECB_PUBLISH_ENDECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1667 #define ECB_PUBLISH_ENDECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ENDECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1668 1669 /* Register: ECB_PUBLISH_ERRORECB */ 1670 /* Description: Publish configuration for event ERRORECB */ 1671 1672 /* Bit 31 : */ 1673 #define ECB_PUBLISH_ERRORECB_EN_Pos (31UL) /*!< Position of EN field. */ 1674 #define ECB_PUBLISH_ERRORECB_EN_Msk (0x1UL << ECB_PUBLISH_ERRORECB_EN_Pos) /*!< Bit mask of EN field. */ 1675 #define ECB_PUBLISH_ERRORECB_EN_Disabled (0UL) /*!< Disable publishing */ 1676 #define ECB_PUBLISH_ERRORECB_EN_Enabled (1UL) /*!< Enable publishing */ 1677 1678 /* Bits 7..0 : DPPI channel that event ERRORECB will publish to. */ 1679 #define ECB_PUBLISH_ERRORECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1680 #define ECB_PUBLISH_ERRORECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ERRORECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1681 1682 /* Register: ECB_INTENSET */ 1683 /* Description: Enable interrupt */ 1684 1685 /* Bit 1 : Write '1' to enable interrupt for event ERRORECB */ 1686 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 1687 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 1688 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ 1689 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ 1690 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ 1691 1692 /* Bit 0 : Write '1' to enable interrupt for event ENDECB */ 1693 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 1694 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 1695 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ 1696 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ 1697 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ 1698 1699 /* Register: ECB_INTENCLR */ 1700 /* Description: Disable interrupt */ 1701 1702 /* Bit 1 : Write '1' to disable interrupt for event ERRORECB */ 1703 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 1704 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 1705 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ 1706 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ 1707 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ 1708 1709 /* Bit 0 : Write '1' to disable interrupt for event ENDECB */ 1710 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 1711 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 1712 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ 1713 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ 1714 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ 1715 1716 /* Register: ECB_ECBDATAPTR */ 1717 /* Description: ECB block encrypt memory pointers */ 1718 1719 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ 1720 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ 1721 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ 1722 1723 1724 /* =========================================================================================================================== */ 1725 /* ================ EGU ================ */ 1726 /* =========================================================================================================================== */ 1727 1728 1729 /** 1730 * @brief Event generator unit 0 (EGU0_NS) 1731 */ 1732 1733 typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ 1734 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1735 the corresponding TRIGGERED[n] event */ 1736 __IM uint32_t RESERVED[16]; 1737 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1738 for task TRIGGER[n] */ 1739 __IM uint32_t RESERVED1[16]; 1740 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1741 by triggering the corresponding TRIGGER[n] 1742 task */ 1743 __IM uint32_t RESERVED2[16]; 1744 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 1745 for event TRIGGERED[n] */ 1746 __IM uint32_t RESERVED3[80]; 1747 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1748 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1749 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1750 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1751 1752 /* Peripheral: EGU */ 1753 /* Description: Event generator unit */ 1754 1755 /* Register: EGU_TASKS_TRIGGER */ 1756 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ 1757 1758 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ 1759 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ 1760 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ 1761 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ 1762 1763 /* Register: EGU_SUBSCRIBE_TRIGGER */ 1764 /* Description: Description collection: Subscribe configuration for task TRIGGER[n] */ 1765 1766 /* Bit 31 : */ 1767 #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ 1768 #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */ 1769 #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */ 1770 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */ 1771 1772 /* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */ 1773 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1774 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1775 1776 /* Register: EGU_EVENTS_TRIGGERED */ 1777 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ 1778 1779 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ 1780 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ 1781 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ 1782 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ 1783 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ 1784 1785 /* Register: EGU_PUBLISH_TRIGGERED */ 1786 /* Description: Description collection: Publish configuration for event TRIGGERED[n] */ 1787 1788 /* Bit 31 : */ 1789 #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ 1790 #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */ 1791 #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */ 1792 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */ 1793 1794 /* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to. */ 1795 #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1796 #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1797 1798 /* Register: EGU_INTEN */ 1799 /* Description: Enable or disable interrupt */ 1800 1801 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ 1802 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1803 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1804 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ 1805 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ 1806 1807 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ 1808 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1809 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1810 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ 1811 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ 1812 1813 /* Register: EGU_INTENSET */ 1814 /* Description: Enable interrupt */ 1815 1816 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ 1817 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1818 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1819 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 1820 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 1821 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ 1822 1823 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ 1824 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1825 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1826 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 1827 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 1828 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ 1829 1830 /* Register: EGU_INTENCLR */ 1831 /* Description: Disable interrupt */ 1832 1833 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ 1834 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1835 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1836 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 1837 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 1838 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ 1839 1840 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ 1841 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1842 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1843 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 1844 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 1845 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ 1846 1847 1848 1849 1850 /* =========================================================================================================================== */ 1851 /* ================ DPPIC_NS ================ */ 1852 /* =========================================================================================================================== */ 1853 1854 1855 /** 1856 * @brief Distributed programmable peripheral interconnect controller (DPPIC_NS) 1857 */ 1858 1859 typedef struct { /*!< (@ 0x4100F000) DPPIC_NS Structure */ 1860 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1861 __IM uint32_t RESERVED[20]; 1862 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 1863 __IM uint32_t RESERVED1[276]; 1864 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1865 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1866 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1867 __IM uint32_t RESERVED2[189]; 1868 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 1869 Writes to this register are ignored if either 1870 SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS 1871 is enabled */ 1872 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 1873 1874 1875 1876 /* Peripheral: DPPIC */ 1877 /* Description: Distributed programmable peripheral interconnect controller */ 1878 1879 /* Register: DPPIC_TASKS_CHG_EN */ 1880 /* Description: Description cluster: Enable channel group n */ 1881 1882 /* Bit 0 : Enable channel group n */ 1883 #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ 1884 #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ 1885 #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ 1886 1887 /* Register: DPPIC_TASKS_CHG_DIS */ 1888 /* Description: Description cluster: Disable channel group n */ 1889 1890 /* Bit 0 : Disable channel group n */ 1891 #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ 1892 #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ 1893 #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ 1894 1895 /* Register: DPPIC_SUBSCRIBE_CHG_EN */ 1896 /* Description: Description cluster: Subscribe configuration for task CHG[n].EN */ 1897 1898 /* Bit 31 : */ 1899 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */ 1900 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ 1901 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */ 1902 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */ 1903 1904 /* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */ 1905 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1906 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1907 1908 /* Register: DPPIC_SUBSCRIBE_CHG_DIS */ 1909 /* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */ 1910 1911 /* Bit 31 : */ 1912 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */ 1913 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */ 1914 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */ 1915 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */ 1916 1917 /* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */ 1918 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1919 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1920 1921 /* Register: DPPIC_CHEN */ 1922 /* Description: Channel enable register */ 1923 1924 /* Bit 31 : Enable or disable channel 31 */ 1925 #define DPPIC_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ 1926 #define DPPIC_CHEN_CH31_Msk (0x1UL << DPPIC_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ 1927 #define DPPIC_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ 1928 #define DPPIC_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ 1929 1930 /* Bit 0 : Enable or disable channel 0 */ 1931 #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ 1932 #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ 1933 #define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ 1934 #define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ 1935 1936 /* Register: DPPIC_CHENSET */ 1937 /* Description: Channel enable set register */ 1938 1939 /* Bit 31 : Channel 31 enable set register. Writing 0 has no effect. */ 1940 #define DPPIC_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ 1941 #define DPPIC_CHENSET_CH31_Msk (0x1UL << DPPIC_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ 1942 #define DPPIC_CHENSET_CH31_Disabled (0UL) /*!< Read: Channel disabled */ 1943 #define DPPIC_CHENSET_CH31_Enabled (1UL) /*!< Read: Channel enabled */ 1944 #define DPPIC_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ 1945 1946 /* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */ 1947 #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ 1948 #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ 1949 #define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */ 1950 #define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */ 1951 #define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ 1952 1953 /* Register: DPPIC_CHENCLR */ 1954 /* Description: Channel enable clear register */ 1955 1956 /* Bit 31 : Channel 31 enable clear register. Writing 0 has no effect. */ 1957 #define DPPIC_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ 1958 #define DPPIC_CHENCLR_CH31_Msk (0x1UL << DPPIC_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ 1959 #define DPPIC_CHENCLR_CH31_Disabled (0UL) /*!< Read: Channel disabled */ 1960 #define DPPIC_CHENCLR_CH31_Enabled (1UL) /*!< Read: Channel enabled */ 1961 #define DPPIC_CHENCLR_CH31_Clear (1UL) /*!< Write: Disable channel */ 1962 1963 /* Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */ 1964 #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ 1965 #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ 1966 #define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */ 1967 #define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */ 1968 #define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */ 1969 1970 /* Register: DPPIC_CHG */ 1971 /* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */ 1972 1973 /* Bit 31 : Include or exclude channel 31 */ 1974 #define DPPIC_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ 1975 #define DPPIC_CHG_CH31_Msk (0x1UL << DPPIC_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ 1976 #define DPPIC_CHG_CH31_Excluded (0UL) /*!< Exclude */ 1977 #define DPPIC_CHG_CH31_Included (1UL) /*!< Include */ 1978 1979 /* Bit 0 : Include or exclude channel 0 */ 1980 #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ 1981 #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ 1982 #define DPPIC_CHG_CH0_Excluded (0UL) /*!< Exclude */ 1983 #define DPPIC_CHG_CH0_Included (1UL) /*!< Include */ 1984 1985 /* =========================================================================================================================== */ 1986 /* ================ FICR ================ */ 1987 /* =========================================================================================================================== */ 1988 1989 1990 /** 1991 * @brief Factory Information Configuration Registers (FICR) 1992 */ 1993 1994 typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ 1995 __IM uint32_t RESERVED[128]; 1996 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 1997 __IM uint32_t RESERVED1[53]; 1998 __IOM FICR_TRIMCNF_Type TRIMCNF[32]; /*!< (@ 0x00000300) Unspecified */ 1999 __IM uint32_t RESERVED2[20]; 2000 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 2001 __IM uint32_t RESERVED3[488]; 2002 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 2003 __IM uint32_t XOSC32MTRIM; /*!< (@ 0x00000C20) XOSC32M capacitor selection trim values */ 2004 } NRF_FICR_APP_Type; /*!< Size = 3108 (0xc24) */ 2005 2006 typedef struct { /*!< (@ 0x01FF0000) FICR_NS Structure */ 2007 __IM uint32_t RESERVED[128]; 2008 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 2009 __IM uint32_t RESERVED1[21]; 2010 __IM uint32_t ER[4]; /*!< (@ 0x00000280) Description collection: Encryption Root, word 2011 n */ 2012 __IM uint32_t IR[4]; /*!< (@ 0x00000290) Description collection: Identity Root, word n */ 2013 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000002A0) Device address type */ 2014 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000002A4) Description collection: Device address n */ 2015 __IM uint32_t RESERVED2[21]; 2016 __IOM FICR_TRIMCNF_Type TRIMCNF[32]; /*!< (@ 0x00000300) Unspecified */ 2017 } NRF_FICR_NET_Type; /*!< Size = 1024 (0x400) */ 2018 2019 2020 2021 /* =========================================================================================================================== */ 2022 /* ================ IPC_NS ================ */ 2023 /* =========================================================================================================================== */ 2024 2025 2026 /** 2027 * @brief Interprocessor communication (IPC_NS) 2028 */ 2029 2030 typedef struct { /*!< (@ 0x41012000) IPC_NS Structure */ 2031 __OM uint32_t TASKS_SEND[16]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC 2032 channel enabled in SEND_CNF[n] */ 2033 __IM uint32_t RESERVED[16]; 2034 __IOM uint32_t SUBSCRIBE_SEND[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 2035 for task SEND[n] */ 2036 __IM uint32_t RESERVED1[16]; 2037 __IOM uint32_t EVENTS_RECEIVE[16]; /*!< (@ 0x00000100) Description collection: Event received on one 2038 or more of the enabled IPC channels in RECEIVE_CNF[n] */ 2039 __IM uint32_t RESERVED2[16]; 2040 __IOM uint32_t PUBLISH_RECEIVE[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 2041 for event RECEIVE[n] */ 2042 __IM uint32_t RESERVED3[80]; 2043 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2044 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2045 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2046 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 2047 __IM uint32_t RESERVED4[128]; 2048 __IOM uint32_t SEND_CNF[16]; /*!< (@ 0x00000510) Description collection: Send event configuration 2049 for TASKS_SEND[n] */ 2050 __IM uint32_t RESERVED5[16]; 2051 __IOM uint32_t RECEIVE_CNF[16]; /*!< (@ 0x00000590) Description collection: Receive event configuration 2052 for EVENTS_RECEIVE[n] */ 2053 __IM uint32_t RESERVED6[16]; 2054 __IOM uint32_t GPMEM[2]; /*!< (@ 0x00000610) Description collection: General purpose memory */ 2055 } NRF_IPC_Type; /*!< Size = 1560 (0x618) */ 2056 2057 2058 /* =========================================================================================================================== */ 2059 /* ================ APPMUTEX_NS ================ */ 2060 /* =========================================================================================================================== */ 2061 2062 2063 /** 2064 * @brief MUTEX 0 (APPMUTEX_NS) 2065 */ 2066 2067 typedef struct { /*!< (@ 0x40030000) APPMUTEX_NS Structure */ 2068 __IM uint32_t RESERVED[256]; 2069 __IOM uint32_t MUTEX[16]; /*!< (@ 0x00000400) Description collection: Mutex register */ 2070 } NRF_MUTEX_Type; /*!< Size = 1088 (0x440) */ 2071 2072 2073 2074 /* =========================================================================================================================== */ 2075 /* ================ NVMC ================ */ 2076 /* =========================================================================================================================== */ 2077 2078 2079 /** 2080 * @brief Non-volatile memory controller (NVMC) 2081 * 2082 * Note: This is the app core register layouts 2083 * as by now the icache registers are just ignored 2084 */ 2085 2086 typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ 2087 __IM uint32_t RESERVED[256]; 2088 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2089 __IM uint32_t RESERVED1; 2090 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 2091 __IM uint32_t RESERVED2[62]; 2092 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2093 __IM uint32_t RESERVED3; 2094 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2095 __IM uint32_t RESERVED4[3]; 2096 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 2097 __IM uint32_t RESERVED5[25]; 2098 __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Non-secure configuration register */ 2099 __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ 2100 } NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ 2101 2102 2103 /* Peripheral: NVMC */ 2104 /* Description: Non-volatile memory controller */ 2105 2106 /* Register: NVMC_READY */ 2107 /* Description: Ready flag */ 2108 2109 /* Bit 0 : NVMC is ready or busy */ 2110 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ 2111 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ 2112 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */ 2113 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ 2114 2115 /* Register: NVMC_READYNEXT */ 2116 /* Description: Ready flag */ 2117 2118 /* Bit 0 : NVMC can accept a new write operation */ 2119 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */ 2120 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ 2121 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */ 2122 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */ 2123 2124 /* Register: NVMC_CONFIG */ 2125 /* Description: Configuration register */ 2126 2127 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ 2128 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ 2129 #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ 2130 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ 2131 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ 2132 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ 2133 #define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */ 2134 2135 /* Register: NVMC_ERASEALL */ 2136 /* Description: Register for erasing all non-volatile user memory */ 2137 2138 /* Bit 0 : Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. */ 2139 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ 2140 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ 2141 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ 2142 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ 2143 2144 /* Register: NVMC_ERASEPAGEPARTIALCFG */ 2145 /* Description: Register for partial erase configuration */ 2146 2147 /* Bits 6..0 : Duration of the partial erase in milliseconds */ 2148 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ 2149 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ 2150 2151 2152 /* =========================================================================================================================== */ 2153 /* ================ POWER_NS ================ */ 2154 /* =========================================================================================================================== */ 2155 2156 2157 /** 2158 * @brief Power control 0 (POWER_NS) 2159 */ 2160 2161 typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ 2162 __IM uint32_t RESERVED[30]; 2163 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 2164 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-Power mode (variable latency) */ 2165 __IM uint32_t RESERVED1[30]; 2166 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 2167 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 2168 __IM uint32_t RESERVED2[2]; 2169 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 2170 __IM uint32_t RESERVED3[2]; 2171 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 2172 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 2173 __IM uint32_t RESERVED4[27]; 2174 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 2175 __IM uint32_t RESERVED5[2]; 2176 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 2177 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 2178 __IM uint32_t RESERVED6[89]; 2179 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2180 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2181 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2182 __IM uint32_t RESERVED7[132]; 2183 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 2184 register */ 2185 } NRF_POWER_Type; /*!< Size = 1316 (0x524) */ 2186 2187 2188 /* =========================================================================================================================== */ 2189 /* ================ RESET ================ */ 2190 /* =========================================================================================================================== */ 2191 2192 2193 /** 2194 * @brief Reset control (RESET) 2195 */ 2196 2197 typedef struct { /*!< (@ 0x40005000) RESET_NS Structure */ 2198 __IM uint32_t RESERVED[256]; 2199 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 2200 __IM uint32_t RESERVED1[131]; 2201 __IOM RESET_NETWORK_Type NETWORK; /*!< (@ 0x00000610) ULP network core control */ 2202 } NRF_RESET_Type; /*!< Size = 1560 (0x618) */ 2203 2204 2205 2206 /* =========================================================================================================================== */ 2207 /* ================ RADIO_NS ================ */ 2208 /* =========================================================================================================================== */ 2209 2210 2211 /** 2212 * @brief 2.4 GHz radio (RADIO_NS) 2213 */ 2214 2215 typedef struct { /*!< (@ 0x41008000) RADIO_NS Structure */ 2216 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 2217 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 2218 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 2219 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 2220 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 2221 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 2222 the receive signal strength */ 2223 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 2224 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 2225 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 2226 __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 2227 802.15.4 mode */ 2228 __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 2229 __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 2230 802.15.4 mode */ 2231 __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 2232 __IM uint32_t RESERVED[19]; 2233 __IOM uint32_t SUBSCRIBE_TXEN; /*!< (@ 0x00000080) Subscribe configuration for task TXEN */ 2234 __IOM uint32_t SUBSCRIBE_RXEN; /*!< (@ 0x00000084) Subscribe configuration for task RXEN */ 2235 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000088) Subscribe configuration for task START */ 2236 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x0000008C) Subscribe configuration for task STOP */ 2237 __IOM uint32_t SUBSCRIBE_DISABLE; /*!< (@ 0x00000090) Subscribe configuration for task DISABLE */ 2238 __IOM uint32_t SUBSCRIBE_RSSISTART; /*!< (@ 0x00000094) Subscribe configuration for task RSSISTART */ 2239 __IOM uint32_t SUBSCRIBE_RSSISTOP; /*!< (@ 0x00000098) Subscribe configuration for task RSSISTOP */ 2240 __IOM uint32_t SUBSCRIBE_BCSTART; /*!< (@ 0x0000009C) Subscribe configuration for task BCSTART */ 2241 __IOM uint32_t SUBSCRIBE_BCSTOP; /*!< (@ 0x000000A0) Subscribe configuration for task BCSTOP */ 2242 __IOM uint32_t SUBSCRIBE_EDSTART; /*!< (@ 0x000000A4) Subscribe configuration for task EDSTART */ 2243 __IOM uint32_t SUBSCRIBE_EDSTOP; /*!< (@ 0x000000A8) Subscribe configuration for task EDSTOP */ 2244 __IOM uint32_t SUBSCRIBE_CCASTART; /*!< (@ 0x000000AC) Subscribe configuration for task CCASTART */ 2245 __IOM uint32_t SUBSCRIBE_CCASTOP; /*!< (@ 0x000000B0) Subscribe configuration for task CCASTOP */ 2246 __IM uint32_t RESERVED1[19]; 2247 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 2248 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 2249 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 2250 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 2251 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 2252 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 2253 packet */ 2254 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 2255 received packet */ 2256 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 2257 __IM uint32_t RESERVED2[2]; 2258 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 2259 __IM uint32_t RESERVED3; 2260 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 2261 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 2262 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 2263 __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 2264 ED sample is ready for readout from the 2265 RADIO.EDSAMPLE register. */ 2266 __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 2267 __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 2268 __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 2269 __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 2270 __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 2271 from Ble_LR125Kbit to Ble_LR500Kbit. */ 2272 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 2273 TX path */ 2274 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 2275 RX path */ 2276 __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 2277 __IM uint32_t RESERVED4[2]; 2278 __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator */ 2279 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received 2280 from air */ 2281 __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving 2282 CTEInfo byte) */ 2283 __IM uint32_t RESERVED5[3]; 2284 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 2285 __IOM uint32_t PUBLISH_ADDRESS; /*!< (@ 0x00000184) Publish configuration for event ADDRESS */ 2286 __IOM uint32_t PUBLISH_PAYLOAD; /*!< (@ 0x00000188) Publish configuration for event PAYLOAD */ 2287 __IOM uint32_t PUBLISH_END; /*!< (@ 0x0000018C) Publish configuration for event END */ 2288 __IOM uint32_t PUBLISH_DISABLED; /*!< (@ 0x00000190) Publish configuration for event DISABLED */ 2289 __IOM uint32_t PUBLISH_DEVMATCH; /*!< (@ 0x00000194) Publish configuration for event DEVMATCH */ 2290 __IOM uint32_t PUBLISH_DEVMISS; /*!< (@ 0x00000198) Publish configuration for event DEVMISS */ 2291 __IOM uint32_t PUBLISH_RSSIEND; /*!< (@ 0x0000019C) Publish configuration for event RSSIEND */ 2292 __IM uint32_t RESERVED6[2]; 2293 __IOM uint32_t PUBLISH_BCMATCH; /*!< (@ 0x000001A8) Publish configuration for event BCMATCH */ 2294 __IM uint32_t RESERVED7; 2295 __IOM uint32_t PUBLISH_CRCOK; /*!< (@ 0x000001B0) Publish configuration for event CRCOK */ 2296 __IOM uint32_t PUBLISH_CRCERROR; /*!< (@ 0x000001B4) Publish configuration for event CRCERROR */ 2297 __IOM uint32_t PUBLISH_FRAMESTART; /*!< (@ 0x000001B8) Publish configuration for event FRAMESTART */ 2298 __IOM uint32_t PUBLISH_EDEND; /*!< (@ 0x000001BC) Publish configuration for event EDEND */ 2299 __IOM uint32_t PUBLISH_EDSTOPPED; /*!< (@ 0x000001C0) Publish configuration for event EDSTOPPED */ 2300 __IOM uint32_t PUBLISH_CCAIDLE; /*!< (@ 0x000001C4) Publish configuration for event CCAIDLE */ 2301 __IOM uint32_t PUBLISH_CCABUSY; /*!< (@ 0x000001C8) Publish configuration for event CCABUSY */ 2302 __IOM uint32_t PUBLISH_CCASTOPPED; /*!< (@ 0x000001CC) Publish configuration for event CCASTOPPED */ 2303 __IOM uint32_t PUBLISH_RATEBOOST; /*!< (@ 0x000001D0) Publish configuration for event RATEBOOST */ 2304 __IOM uint32_t PUBLISH_TXREADY; /*!< (@ 0x000001D4) Publish configuration for event TXREADY */ 2305 __IOM uint32_t PUBLISH_RXREADY; /*!< (@ 0x000001D8) Publish configuration for event RXREADY */ 2306 __IOM uint32_t PUBLISH_MHRMATCH; /*!< (@ 0x000001DC) Publish configuration for event MHRMATCH */ 2307 __IM uint32_t RESERVED8[2]; 2308 __IOM uint32_t PUBLISH_SYNC; /*!< (@ 0x000001E8) Publish configuration for event SYNC */ 2309 __IOM uint32_t PUBLISH_PHYEND; /*!< (@ 0x000001EC) Publish configuration for event PHYEND */ 2310 __IOM uint32_t PUBLISH_CTEPRESENT; /*!< (@ 0x000001F0) Publish configuration for event CTEPRESENT */ 2311 __IM uint32_t RESERVED9[3]; 2312 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2313 __IM uint32_t RESERVED10[64]; 2314 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2315 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2316 __IM uint32_t RESERVED11[61]; 2317 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 2318 __IM uint32_t RESERVED12; 2319 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 2320 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 2321 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 2322 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 2323 __IM uint32_t RESERVED13[13]; 2324 __IM uint32_t CTESTATUS; /*!< (@ 0x0000044C) CTEInfo parsed from received packet */ 2325 __IM uint32_t RESERVED14[2]; 2326 __IM uint32_t DFESTATUS; /*!< (@ 0x00000458) DFE status information */ 2327 __IM uint32_t RESERVED15[42]; 2328 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 2329 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 2330 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 2331 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 2332 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 2333 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 2334 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 2335 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 2336 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 2337 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 2338 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 2339 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 2340 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 2341 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 2342 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 2343 __IM uint32_t RESERVED16; 2344 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 2345 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 2346 __IM uint32_t RESERVED17; 2347 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 2348 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 2349 __IM uint32_t RESERVED18[2]; 2350 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 2351 __IM uint32_t RESERVED19[39]; 2352 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 2353 n */ 2354 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 2355 n */ 2356 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 2357 __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 2358 __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 2359 __IM uint32_t RESERVED20; 2360 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 2361 __IM uint32_t RESERVED21[3]; 2362 __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 2363 __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 2364 __IM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 2365 __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 2366 __IM uint32_t RESERVED22[164]; 2367 __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure 2368 (AOD) */ 2369 __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000904) Configuration for CTE inline mode */ 2370 __IM uint32_t RESERVED23[2]; 2371 __IOM uint32_t DFECTRL1; /*!< (@ 0x00000910) Various configuration for Direction finding */ 2372 __IOM uint32_t DFECTRL2; /*!< (@ 0x00000914) Start offset for Direction finding */ 2373 __IM uint32_t RESERVED24[4]; 2374 __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000928) GPIO patterns to be used for each antenna */ 2375 __IOM uint32_t CLEARPATTERN; /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control */ 2376 __IOM RADIO_PSEL_Type PSEL; /*!< (@ 0x00000930) Unspecified */ 2377 __IOM RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000950) DFE packet EasyDMA channel */ 2378 __IM uint32_t RESERVED25[424]; 2379 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 2380 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 2381 2382 2383 /* Peripheral: RADIO */ 2384 /* Description: 2.4 GHz radio */ 2385 2386 /* Register: RADIO_TASKS_TXEN */ 2387 /* Description: Enable RADIO in TX mode */ 2388 2389 /* Bit 0 : Enable RADIO in TX mode */ 2390 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ 2391 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ 2392 #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */ 2393 2394 /* Register: RADIO_TASKS_RXEN */ 2395 /* Description: Enable RADIO in RX mode */ 2396 2397 /* Bit 0 : Enable RADIO in RX mode */ 2398 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ 2399 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ 2400 #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */ 2401 2402 /* Register: RADIO_TASKS_START */ 2403 /* Description: Start RADIO */ 2404 2405 /* Bit 0 : Start RADIO */ 2406 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 2407 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 2408 #define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 2409 2410 /* Register: RADIO_TASKS_STOP */ 2411 /* Description: Stop RADIO */ 2412 2413 /* Bit 0 : Stop RADIO */ 2414 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 2415 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 2416 #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 2417 2418 /* Register: RADIO_TASKS_DISABLE */ 2419 /* Description: Disable RADIO */ 2420 2421 /* Bit 0 : Disable RADIO */ 2422 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ 2423 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ 2424 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ 2425 2426 /* Register: RADIO_TASKS_RSSISTART */ 2427 /* Description: Start the RSSI and take one single sample of the receive signal strength */ 2428 2429 /* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ 2430 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ 2431 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ 2432 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */ 2433 2434 /* Register: RADIO_TASKS_RSSISTOP */ 2435 /* Description: Stop the RSSI measurement */ 2436 2437 /* Bit 0 : Stop the RSSI measurement */ 2438 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ 2439 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ 2440 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */ 2441 2442 /* Register: RADIO_TASKS_BCSTART */ 2443 /* Description: Start the bit counter */ 2444 2445 /* Bit 0 : Start the bit counter */ 2446 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ 2447 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ 2448 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */ 2449 2450 /* Register: RADIO_TASKS_BCSTOP */ 2451 /* Description: Stop the bit counter */ 2452 2453 /* Bit 0 : Stop the bit counter */ 2454 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ 2455 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ 2456 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */ 2457 2458 /* Register: RADIO_TASKS_EDSTART */ 2459 /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */ 2460 2461 /* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */ 2462 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ 2463 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */ 2464 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */ 2465 2466 /* Register: RADIO_TASKS_EDSTOP */ 2467 /* Description: Stop the energy detect measurement */ 2468 2469 /* Bit 0 : Stop the energy detect measurement */ 2470 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ 2471 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */ 2472 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */ 2473 2474 /* Register: RADIO_TASKS_CCASTART */ 2475 /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */ 2476 2477 /* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */ 2478 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ 2479 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */ 2480 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */ 2481 2482 /* Register: RADIO_TASKS_CCASTOP */ 2483 /* Description: Stop the clear channel assessment */ 2484 2485 /* Bit 0 : Stop the clear channel assessment */ 2486 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ 2487 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */ 2488 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */ 2489 2490 /* Register: RADIO_SUBSCRIBE_TXEN */ 2491 /* Description: Subscribe configuration for task TXEN */ 2492 2493 /* Bit 31 : */ 2494 #define RADIO_SUBSCRIBE_TXEN_EN_Pos (31UL) /*!< Position of EN field. */ 2495 #define RADIO_SUBSCRIBE_TXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_TXEN_EN_Pos) /*!< Bit mask of EN field. */ 2496 #define RADIO_SUBSCRIBE_TXEN_EN_Disabled (0UL) /*!< Disable subscription */ 2497 #define RADIO_SUBSCRIBE_TXEN_EN_Enabled (1UL) /*!< Enable subscription */ 2498 2499 /* Bits 7..0 : DPPI channel that task TXEN will subscribe to */ 2500 #define RADIO_SUBSCRIBE_TXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2501 #define RADIO_SUBSCRIBE_TXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_TXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2502 2503 /* Register: RADIO_SUBSCRIBE_RXEN */ 2504 /* Description: Subscribe configuration for task RXEN */ 2505 2506 /* Bit 31 : */ 2507 #define RADIO_SUBSCRIBE_RXEN_EN_Pos (31UL) /*!< Position of EN field. */ 2508 #define RADIO_SUBSCRIBE_RXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RXEN_EN_Pos) /*!< Bit mask of EN field. */ 2509 #define RADIO_SUBSCRIBE_RXEN_EN_Disabled (0UL) /*!< Disable subscription */ 2510 #define RADIO_SUBSCRIBE_RXEN_EN_Enabled (1UL) /*!< Enable subscription */ 2511 2512 /* Bits 7..0 : DPPI channel that task RXEN will subscribe to */ 2513 #define RADIO_SUBSCRIBE_RXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2514 #define RADIO_SUBSCRIBE_RXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2515 2516 /* Register: RADIO_SUBSCRIBE_START */ 2517 /* Description: Subscribe configuration for task START */ 2518 2519 /* Bit 31 : */ 2520 #define RADIO_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 2521 #define RADIO_SUBSCRIBE_START_EN_Msk (0x1UL << RADIO_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 2522 #define RADIO_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 2523 #define RADIO_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 2524 2525 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 2526 #define RADIO_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2527 #define RADIO_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2528 2529 /* Register: RADIO_SUBSCRIBE_STOP */ 2530 /* Description: Subscribe configuration for task STOP */ 2531 2532 /* Bit 31 : */ 2533 #define RADIO_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 2534 #define RADIO_SUBSCRIBE_STOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 2535 #define RADIO_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 2536 #define RADIO_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 2537 2538 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 2539 #define RADIO_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2540 #define RADIO_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2541 2542 /* Register: RADIO_SUBSCRIBE_DISABLE */ 2543 /* Description: Subscribe configuration for task DISABLE */ 2544 2545 /* Bit 31 : */ 2546 #define RADIO_SUBSCRIBE_DISABLE_EN_Pos (31UL) /*!< Position of EN field. */ 2547 #define RADIO_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << RADIO_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field. */ 2548 #define RADIO_SUBSCRIBE_DISABLE_EN_Disabled (0UL) /*!< Disable subscription */ 2549 #define RADIO_SUBSCRIBE_DISABLE_EN_Enabled (1UL) /*!< Enable subscription */ 2550 2551 /* Bits 7..0 : DPPI channel that task DISABLE will subscribe to */ 2552 #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2553 #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2554 2555 /* Register: RADIO_SUBSCRIBE_RSSISTART */ 2556 /* Description: Subscribe configuration for task RSSISTART */ 2557 2558 /* Bit 31 : */ 2559 #define RADIO_SUBSCRIBE_RSSISTART_EN_Pos (31UL) /*!< Position of EN field. */ 2560 #define RADIO_SUBSCRIBE_RSSISTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTART_EN_Pos) /*!< Bit mask of EN field. */ 2561 #define RADIO_SUBSCRIBE_RSSISTART_EN_Disabled (0UL) /*!< Disable subscription */ 2562 #define RADIO_SUBSCRIBE_RSSISTART_EN_Enabled (1UL) /*!< Enable subscription */ 2563 2564 /* Bits 7..0 : DPPI channel that task RSSISTART will subscribe to */ 2565 #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2566 #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2567 2568 /* Register: RADIO_SUBSCRIBE_RSSISTOP */ 2569 /* Description: Subscribe configuration for task RSSISTOP */ 2570 2571 /* Bit 31 : */ 2572 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Pos (31UL) /*!< Position of EN field. */ 2573 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTOP_EN_Pos) /*!< Bit mask of EN field. */ 2574 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Disabled (0UL) /*!< Disable subscription */ 2575 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Enabled (1UL) /*!< Enable subscription */ 2576 2577 /* Bits 7..0 : DPPI channel that task RSSISTOP will subscribe to */ 2578 #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2579 #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2580 2581 /* Register: RADIO_SUBSCRIBE_BCSTART */ 2582 /* Description: Subscribe configuration for task BCSTART */ 2583 2584 /* Bit 31 : */ 2585 #define RADIO_SUBSCRIBE_BCSTART_EN_Pos (31UL) /*!< Position of EN field. */ 2586 #define RADIO_SUBSCRIBE_BCSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTART_EN_Pos) /*!< Bit mask of EN field. */ 2587 #define RADIO_SUBSCRIBE_BCSTART_EN_Disabled (0UL) /*!< Disable subscription */ 2588 #define RADIO_SUBSCRIBE_BCSTART_EN_Enabled (1UL) /*!< Enable subscription */ 2589 2590 /* Bits 7..0 : DPPI channel that task BCSTART will subscribe to */ 2591 #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2592 #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2593 2594 /* Register: RADIO_SUBSCRIBE_BCSTOP */ 2595 /* Description: Subscribe configuration for task BCSTOP */ 2596 2597 /* Bit 31 : */ 2598 #define RADIO_SUBSCRIBE_BCSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 2599 #define RADIO_SUBSCRIBE_BCSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTOP_EN_Pos) /*!< Bit mask of EN field. */ 2600 #define RADIO_SUBSCRIBE_BCSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 2601 #define RADIO_SUBSCRIBE_BCSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 2602 2603 /* Bits 7..0 : DPPI channel that task BCSTOP will subscribe to */ 2604 #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2605 #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2606 2607 /* Register: RADIO_SUBSCRIBE_EDSTART */ 2608 /* Description: Subscribe configuration for task EDSTART */ 2609 2610 /* Bit 31 : */ 2611 #define RADIO_SUBSCRIBE_EDSTART_EN_Pos (31UL) /*!< Position of EN field. */ 2612 #define RADIO_SUBSCRIBE_EDSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTART_EN_Pos) /*!< Bit mask of EN field. */ 2613 #define RADIO_SUBSCRIBE_EDSTART_EN_Disabled (0UL) /*!< Disable subscription */ 2614 #define RADIO_SUBSCRIBE_EDSTART_EN_Enabled (1UL) /*!< Enable subscription */ 2615 2616 /* Bits 7..0 : DPPI channel that task EDSTART will subscribe to */ 2617 #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2618 #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2619 2620 /* Register: RADIO_SUBSCRIBE_EDSTOP */ 2621 /* Description: Subscribe configuration for task EDSTOP */ 2622 2623 /* Bit 31 : */ 2624 #define RADIO_SUBSCRIBE_EDSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 2625 #define RADIO_SUBSCRIBE_EDSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTOP_EN_Pos) /*!< Bit mask of EN field. */ 2626 #define RADIO_SUBSCRIBE_EDSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 2627 #define RADIO_SUBSCRIBE_EDSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 2628 2629 /* Bits 7..0 : DPPI channel that task EDSTOP will subscribe to */ 2630 #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2631 #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2632 2633 /* Register: RADIO_SUBSCRIBE_CCASTART */ 2634 /* Description: Subscribe configuration for task CCASTART */ 2635 2636 /* Bit 31 : */ 2637 #define RADIO_SUBSCRIBE_CCASTART_EN_Pos (31UL) /*!< Position of EN field. */ 2638 #define RADIO_SUBSCRIBE_CCASTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTART_EN_Pos) /*!< Bit mask of EN field. */ 2639 #define RADIO_SUBSCRIBE_CCASTART_EN_Disabled (0UL) /*!< Disable subscription */ 2640 #define RADIO_SUBSCRIBE_CCASTART_EN_Enabled (1UL) /*!< Enable subscription */ 2641 2642 /* Bits 7..0 : DPPI channel that task CCASTART will subscribe to */ 2643 #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2644 #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2645 2646 /* Register: RADIO_SUBSCRIBE_CCASTOP */ 2647 /* Description: Subscribe configuration for task CCASTOP */ 2648 2649 /* Bit 31 : */ 2650 #define RADIO_SUBSCRIBE_CCASTOP_EN_Pos (31UL) /*!< Position of EN field. */ 2651 #define RADIO_SUBSCRIBE_CCASTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTOP_EN_Pos) /*!< Bit mask of EN field. */ 2652 #define RADIO_SUBSCRIBE_CCASTOP_EN_Disabled (0UL) /*!< Disable subscription */ 2653 #define RADIO_SUBSCRIBE_CCASTOP_EN_Enabled (1UL) /*!< Enable subscription */ 2654 2655 /* Bits 7..0 : DPPI channel that task CCASTOP will subscribe to */ 2656 #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2657 #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2658 2659 /* Register: RADIO_EVENTS_READY */ 2660 /* Description: RADIO has ramped up and is ready to be started */ 2661 2662 /* Bit 0 : RADIO has ramped up and is ready to be started */ 2663 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ 2664 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ 2665 #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ 2666 #define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ 2667 2668 /* Register: RADIO_EVENTS_ADDRESS */ 2669 /* Description: Address sent or received */ 2670 2671 /* Bit 0 : Address sent or received */ 2672 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ 2673 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ 2674 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */ 2675 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */ 2676 2677 /* Register: RADIO_EVENTS_PAYLOAD */ 2678 /* Description: Packet payload sent or received */ 2679 2680 /* Bit 0 : Packet payload sent or received */ 2681 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ 2682 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ 2683 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */ 2684 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */ 2685 2686 /* Register: RADIO_EVENTS_END */ 2687 /* Description: Packet sent or received */ 2688 2689 /* Bit 0 : Packet sent or received */ 2690 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 2691 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 2692 #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 2693 #define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 2694 2695 /* Register: RADIO_EVENTS_DISABLED */ 2696 /* Description: RADIO has been disabled */ 2697 2698 /* Bit 0 : RADIO has been disabled */ 2699 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ 2700 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ 2701 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */ 2702 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */ 2703 2704 /* Register: RADIO_EVENTS_DEVMATCH */ 2705 /* Description: A device address match occurred on the last received packet */ 2706 2707 /* Bit 0 : A device address match occurred on the last received packet */ 2708 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ 2709 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ 2710 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */ 2711 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */ 2712 2713 /* Register: RADIO_EVENTS_DEVMISS */ 2714 /* Description: No device address match occurred on the last received packet */ 2715 2716 /* Bit 0 : No device address match occurred on the last received packet */ 2717 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ 2718 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ 2719 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */ 2720 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */ 2721 2722 /* Register: RADIO_EVENTS_RSSIEND */ 2723 /* Description: Sampling of receive signal strength complete */ 2724 2725 /* Bit 0 : Sampling of receive signal strength complete */ 2726 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ 2727 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ 2728 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */ 2729 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */ 2730 2731 /* Register: RADIO_EVENTS_BCMATCH */ 2732 /* Description: Bit counter reached bit count value */ 2733 2734 /* Bit 0 : Bit counter reached bit count value */ 2735 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ 2736 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ 2737 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */ 2738 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */ 2739 2740 /* Register: RADIO_EVENTS_CRCOK */ 2741 /* Description: Packet received with CRC ok */ 2742 2743 /* Bit 0 : Packet received with CRC ok */ 2744 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ 2745 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ 2746 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */ 2747 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */ 2748 2749 /* Register: RADIO_EVENTS_CRCERROR */ 2750 /* Description: Packet received with CRC error */ 2751 2752 /* Bit 0 : Packet received with CRC error */ 2753 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ 2754 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ 2755 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */ 2756 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */ 2757 2758 /* Register: RADIO_EVENTS_FRAMESTART */ 2759 /* Description: IEEE 802.15.4 length field received */ 2760 2761 /* Bit 0 : IEEE 802.15.4 length field received */ 2762 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ 2763 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */ 2764 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */ 2765 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ 2766 2767 /* Register: RADIO_EVENTS_EDEND */ 2768 /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ 2769 2770 /* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ 2771 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ 2772 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ 2773 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ 2774 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */ 2775 2776 /* Register: RADIO_EVENTS_EDSTOPPED */ 2777 /* Description: The sampling of energy detection has stopped */ 2778 2779 /* Bit 0 : The sampling of energy detection has stopped */ 2780 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ 2781 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */ 2782 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */ 2783 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */ 2784 2785 /* Register: RADIO_EVENTS_CCAIDLE */ 2786 /* Description: Wireless medium in idle - clear to send */ 2787 2788 /* Bit 0 : Wireless medium in idle - clear to send */ 2789 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ 2790 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */ 2791 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */ 2792 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */ 2793 2794 /* Register: RADIO_EVENTS_CCABUSY */ 2795 /* Description: Wireless medium busy - do not send */ 2796 2797 /* Bit 0 : Wireless medium busy - do not send */ 2798 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ 2799 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */ 2800 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */ 2801 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */ 2802 2803 /* Register: RADIO_EVENTS_CCASTOPPED */ 2804 /* Description: The CCA has stopped */ 2805 2806 /* Bit 0 : The CCA has stopped */ 2807 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ 2808 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */ 2809 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */ 2810 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */ 2811 2812 /* Register: RADIO_EVENTS_RATEBOOST */ 2813 /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ 2814 2815 /* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ 2816 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ 2817 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */ 2818 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */ 2819 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */ 2820 2821 /* Register: RADIO_EVENTS_TXREADY */ 2822 /* Description: RADIO has ramped up and is ready to be started TX path */ 2823 2824 /* Bit 0 : RADIO has ramped up and is ready to be started TX path */ 2825 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ 2826 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */ 2827 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */ 2828 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */ 2829 2830 /* Register: RADIO_EVENTS_RXREADY */ 2831 /* Description: RADIO has ramped up and is ready to be started RX path */ 2832 2833 /* Bit 0 : RADIO has ramped up and is ready to be started RX path */ 2834 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ 2835 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ 2836 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */ 2837 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */ 2838 2839 /* Register: RADIO_EVENTS_MHRMATCH */ 2840 /* Description: MAC header match found */ 2841 2842 /* Bit 0 : MAC header match found */ 2843 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ 2844 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */ 2845 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ 2846 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ 2847 2848 /* Register: RADIO_EVENTS_SYNC */ 2849 /* Description: Preamble indicator */ 2850 2851 /* Bit 0 : Preamble indicator */ 2852 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */ 2853 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */ 2854 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */ 2855 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */ 2856 2857 /* Register: RADIO_EVENTS_PHYEND */ 2858 /* Description: Generated when last bit is sent on air, or received from air */ 2859 2860 /* Bit 0 : Generated when last bit is sent on air, or received from air */ 2861 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ 2862 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ 2863 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ 2864 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */ 2865 2866 /* Register: RADIO_EVENTS_CTEPRESENT */ 2867 /* Description: CTE is present (early warning right after receiving CTEInfo byte) */ 2868 2869 /* Bit 0 : CTE is present (early warning right after receiving CTEInfo byte) */ 2870 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */ 2871 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask of EVENTS_CTEPRESENT field. */ 2872 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0UL) /*!< Event not generated */ 2873 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (1UL) /*!< Event generated */ 2874 2875 /* Register: RADIO_PUBLISH_READY */ 2876 /* Description: Publish configuration for event READY */ 2877 2878 /* Bit 31 : */ 2879 #define RADIO_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */ 2880 #define RADIO_PUBLISH_READY_EN_Msk (0x1UL << RADIO_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */ 2881 #define RADIO_PUBLISH_READY_EN_Disabled (0UL) /*!< Disable publishing */ 2882 #define RADIO_PUBLISH_READY_EN_Enabled (1UL) /*!< Enable publishing */ 2883 2884 /* Bits 7..0 : DPPI channel that event READY will publish to. */ 2885 #define RADIO_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2886 #define RADIO_PUBLISH_READY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2887 2888 /* Register: RADIO_PUBLISH_ADDRESS */ 2889 /* Description: Publish configuration for event ADDRESS */ 2890 2891 /* Bit 31 : */ 2892 #define RADIO_PUBLISH_ADDRESS_EN_Pos (31UL) /*!< Position of EN field. */ 2893 #define RADIO_PUBLISH_ADDRESS_EN_Msk (0x1UL << RADIO_PUBLISH_ADDRESS_EN_Pos) /*!< Bit mask of EN field. */ 2894 #define RADIO_PUBLISH_ADDRESS_EN_Disabled (0UL) /*!< Disable publishing */ 2895 #define RADIO_PUBLISH_ADDRESS_EN_Enabled (1UL) /*!< Enable publishing */ 2896 2897 /* Bits 7..0 : DPPI channel that event ADDRESS will publish to. */ 2898 #define RADIO_PUBLISH_ADDRESS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2899 #define RADIO_PUBLISH_ADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_ADDRESS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2900 2901 /* Register: RADIO_PUBLISH_PAYLOAD */ 2902 /* Description: Publish configuration for event PAYLOAD */ 2903 2904 /* Bit 31 : */ 2905 #define RADIO_PUBLISH_PAYLOAD_EN_Pos (31UL) /*!< Position of EN field. */ 2906 #define RADIO_PUBLISH_PAYLOAD_EN_Msk (0x1UL << RADIO_PUBLISH_PAYLOAD_EN_Pos) /*!< Bit mask of EN field. */ 2907 #define RADIO_PUBLISH_PAYLOAD_EN_Disabled (0UL) /*!< Disable publishing */ 2908 #define RADIO_PUBLISH_PAYLOAD_EN_Enabled (1UL) /*!< Enable publishing */ 2909 2910 /* Bits 7..0 : DPPI channel that event PAYLOAD will publish to. */ 2911 #define RADIO_PUBLISH_PAYLOAD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2912 #define RADIO_PUBLISH_PAYLOAD_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PAYLOAD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2913 2914 /* Register: RADIO_PUBLISH_END */ 2915 /* Description: Publish configuration for event END */ 2916 2917 /* Bit 31 : */ 2918 #define RADIO_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 2919 #define RADIO_PUBLISH_END_EN_Msk (0x1UL << RADIO_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 2920 #define RADIO_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ 2921 #define RADIO_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ 2922 2923 /* Bits 7..0 : DPPI channel that event END will publish to. */ 2924 #define RADIO_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2925 #define RADIO_PUBLISH_END_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2926 2927 /* Register: RADIO_PUBLISH_DISABLED */ 2928 /* Description: Publish configuration for event DISABLED */ 2929 2930 /* Bit 31 : */ 2931 #define RADIO_PUBLISH_DISABLED_EN_Pos (31UL) /*!< Position of EN field. */ 2932 #define RADIO_PUBLISH_DISABLED_EN_Msk (0x1UL << RADIO_PUBLISH_DISABLED_EN_Pos) /*!< Bit mask of EN field. */ 2933 #define RADIO_PUBLISH_DISABLED_EN_Disabled (0UL) /*!< Disable publishing */ 2934 #define RADIO_PUBLISH_DISABLED_EN_Enabled (1UL) /*!< Enable publishing */ 2935 2936 /* Bits 7..0 : DPPI channel that event DISABLED will publish to. */ 2937 #define RADIO_PUBLISH_DISABLED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2938 #define RADIO_PUBLISH_DISABLED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DISABLED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2939 2940 /* Register: RADIO_PUBLISH_DEVMATCH */ 2941 /* Description: Publish configuration for event DEVMATCH */ 2942 2943 /* Bit 31 : */ 2944 #define RADIO_PUBLISH_DEVMATCH_EN_Pos (31UL) /*!< Position of EN field. */ 2945 #define RADIO_PUBLISH_DEVMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMATCH_EN_Pos) /*!< Bit mask of EN field. */ 2946 #define RADIO_PUBLISH_DEVMATCH_EN_Disabled (0UL) /*!< Disable publishing */ 2947 #define RADIO_PUBLISH_DEVMATCH_EN_Enabled (1UL) /*!< Enable publishing */ 2948 2949 /* Bits 7..0 : DPPI channel that event DEVMATCH will publish to. */ 2950 #define RADIO_PUBLISH_DEVMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2951 #define RADIO_PUBLISH_DEVMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2952 2953 /* Register: RADIO_PUBLISH_DEVMISS */ 2954 /* Description: Publish configuration for event DEVMISS */ 2955 2956 /* Bit 31 : */ 2957 #define RADIO_PUBLISH_DEVMISS_EN_Pos (31UL) /*!< Position of EN field. */ 2958 #define RADIO_PUBLISH_DEVMISS_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMISS_EN_Pos) /*!< Bit mask of EN field. */ 2959 #define RADIO_PUBLISH_DEVMISS_EN_Disabled (0UL) /*!< Disable publishing */ 2960 #define RADIO_PUBLISH_DEVMISS_EN_Enabled (1UL) /*!< Enable publishing */ 2961 2962 /* Bits 7..0 : DPPI channel that event DEVMISS will publish to. */ 2963 #define RADIO_PUBLISH_DEVMISS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2964 #define RADIO_PUBLISH_DEVMISS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMISS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2965 2966 /* Register: RADIO_PUBLISH_RSSIEND */ 2967 /* Description: Publish configuration for event RSSIEND */ 2968 2969 /* Bit 31 : */ 2970 #define RADIO_PUBLISH_RSSIEND_EN_Pos (31UL) /*!< Position of EN field. */ 2971 #define RADIO_PUBLISH_RSSIEND_EN_Msk (0x1UL << RADIO_PUBLISH_RSSIEND_EN_Pos) /*!< Bit mask of EN field. */ 2972 #define RADIO_PUBLISH_RSSIEND_EN_Disabled (0UL) /*!< Disable publishing */ 2973 #define RADIO_PUBLISH_RSSIEND_EN_Enabled (1UL) /*!< Enable publishing */ 2974 2975 /* Bits 7..0 : DPPI channel that event RSSIEND will publish to. */ 2976 #define RADIO_PUBLISH_RSSIEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2977 #define RADIO_PUBLISH_RSSIEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RSSIEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2978 2979 /* Register: RADIO_PUBLISH_BCMATCH */ 2980 /* Description: Publish configuration for event BCMATCH */ 2981 2982 /* Bit 31 : */ 2983 #define RADIO_PUBLISH_BCMATCH_EN_Pos (31UL) /*!< Position of EN field. */ 2984 #define RADIO_PUBLISH_BCMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_BCMATCH_EN_Pos) /*!< Bit mask of EN field. */ 2985 #define RADIO_PUBLISH_BCMATCH_EN_Disabled (0UL) /*!< Disable publishing */ 2986 #define RADIO_PUBLISH_BCMATCH_EN_Enabled (1UL) /*!< Enable publishing */ 2987 2988 /* Bits 7..0 : DPPI channel that event BCMATCH will publish to. */ 2989 #define RADIO_PUBLISH_BCMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2990 #define RADIO_PUBLISH_BCMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_BCMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2991 2992 /* Register: RADIO_PUBLISH_CRCOK */ 2993 /* Description: Publish configuration for event CRCOK */ 2994 2995 /* Bit 31 : */ 2996 #define RADIO_PUBLISH_CRCOK_EN_Pos (31UL) /*!< Position of EN field. */ 2997 #define RADIO_PUBLISH_CRCOK_EN_Msk (0x1UL << RADIO_PUBLISH_CRCOK_EN_Pos) /*!< Bit mask of EN field. */ 2998 #define RADIO_PUBLISH_CRCOK_EN_Disabled (0UL) /*!< Disable publishing */ 2999 #define RADIO_PUBLISH_CRCOK_EN_Enabled (1UL) /*!< Enable publishing */ 3000 3001 /* Bits 7..0 : DPPI channel that event CRCOK will publish to. */ 3002 #define RADIO_PUBLISH_CRCOK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3003 #define RADIO_PUBLISH_CRCOK_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCOK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3004 3005 /* Register: RADIO_PUBLISH_CRCERROR */ 3006 /* Description: Publish configuration for event CRCERROR */ 3007 3008 /* Bit 31 : */ 3009 #define RADIO_PUBLISH_CRCERROR_EN_Pos (31UL) /*!< Position of EN field. */ 3010 #define RADIO_PUBLISH_CRCERROR_EN_Msk (0x1UL << RADIO_PUBLISH_CRCERROR_EN_Pos) /*!< Bit mask of EN field. */ 3011 #define RADIO_PUBLISH_CRCERROR_EN_Disabled (0UL) /*!< Disable publishing */ 3012 #define RADIO_PUBLISH_CRCERROR_EN_Enabled (1UL) /*!< Enable publishing */ 3013 3014 /* Bits 7..0 : DPPI channel that event CRCERROR will publish to. */ 3015 #define RADIO_PUBLISH_CRCERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3016 #define RADIO_PUBLISH_CRCERROR_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3017 3018 /* Register: RADIO_PUBLISH_FRAMESTART */ 3019 /* Description: Publish configuration for event FRAMESTART */ 3020 3021 /* Bit 31 : */ 3022 #define RADIO_PUBLISH_FRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */ 3023 #define RADIO_PUBLISH_FRAMESTART_EN_Msk (0x1UL << RADIO_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field. */ 3024 #define RADIO_PUBLISH_FRAMESTART_EN_Disabled (0UL) /*!< Disable publishing */ 3025 #define RADIO_PUBLISH_FRAMESTART_EN_Enabled (1UL) /*!< Enable publishing */ 3026 3027 /* Bits 7..0 : DPPI channel that event FRAMESTART will publish to. */ 3028 #define RADIO_PUBLISH_FRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3029 #define RADIO_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3030 3031 /* Register: RADIO_PUBLISH_EDEND */ 3032 /* Description: Publish configuration for event EDEND */ 3033 3034 /* Bit 31 : */ 3035 #define RADIO_PUBLISH_EDEND_EN_Pos (31UL) /*!< Position of EN field. */ 3036 #define RADIO_PUBLISH_EDEND_EN_Msk (0x1UL << RADIO_PUBLISH_EDEND_EN_Pos) /*!< Bit mask of EN field. */ 3037 #define RADIO_PUBLISH_EDEND_EN_Disabled (0UL) /*!< Disable publishing */ 3038 #define RADIO_PUBLISH_EDEND_EN_Enabled (1UL) /*!< Enable publishing */ 3039 3040 /* Bits 7..0 : DPPI channel that event EDEND will publish to. */ 3041 #define RADIO_PUBLISH_EDEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3042 #define RADIO_PUBLISH_EDEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3043 3044 /* Register: RADIO_PUBLISH_EDSTOPPED */ 3045 /* Description: Publish configuration for event EDSTOPPED */ 3046 3047 /* Bit 31 : */ 3048 #define RADIO_PUBLISH_EDSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 3049 #define RADIO_PUBLISH_EDSTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_EDSTOPPED_EN_Pos) /*!< Bit mask of EN field. */ 3050 #define RADIO_PUBLISH_EDSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 3051 #define RADIO_PUBLISH_EDSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 3052 3053 /* Bits 7..0 : DPPI channel that event EDSTOPPED will publish to. */ 3054 #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3055 #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3056 3057 /* Register: RADIO_PUBLISH_CCAIDLE */ 3058 /* Description: Publish configuration for event CCAIDLE */ 3059 3060 /* Bit 31 : */ 3061 #define RADIO_PUBLISH_CCAIDLE_EN_Pos (31UL) /*!< Position of EN field. */ 3062 #define RADIO_PUBLISH_CCAIDLE_EN_Msk (0x1UL << RADIO_PUBLISH_CCAIDLE_EN_Pos) /*!< Bit mask of EN field. */ 3063 #define RADIO_PUBLISH_CCAIDLE_EN_Disabled (0UL) /*!< Disable publishing */ 3064 #define RADIO_PUBLISH_CCAIDLE_EN_Enabled (1UL) /*!< Enable publishing */ 3065 3066 /* Bits 7..0 : DPPI channel that event CCAIDLE will publish to. */ 3067 #define RADIO_PUBLISH_CCAIDLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3068 #define RADIO_PUBLISH_CCAIDLE_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCAIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3069 3070 /* Register: RADIO_PUBLISH_CCABUSY */ 3071 /* Description: Publish configuration for event CCABUSY */ 3072 3073 /* Bit 31 : */ 3074 #define RADIO_PUBLISH_CCABUSY_EN_Pos (31UL) /*!< Position of EN field. */ 3075 #define RADIO_PUBLISH_CCABUSY_EN_Msk (0x1UL << RADIO_PUBLISH_CCABUSY_EN_Pos) /*!< Bit mask of EN field. */ 3076 #define RADIO_PUBLISH_CCABUSY_EN_Disabled (0UL) /*!< Disable publishing */ 3077 #define RADIO_PUBLISH_CCABUSY_EN_Enabled (1UL) /*!< Enable publishing */ 3078 3079 /* Bits 7..0 : DPPI channel that event CCABUSY will publish to. */ 3080 #define RADIO_PUBLISH_CCABUSY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3081 #define RADIO_PUBLISH_CCABUSY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCABUSY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3082 3083 /* Register: RADIO_PUBLISH_CCASTOPPED */ 3084 /* Description: Publish configuration for event CCASTOPPED */ 3085 3086 /* Bit 31 : */ 3087 #define RADIO_PUBLISH_CCASTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 3088 #define RADIO_PUBLISH_CCASTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_CCASTOPPED_EN_Pos) /*!< Bit mask of EN field. */ 3089 #define RADIO_PUBLISH_CCASTOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 3090 #define RADIO_PUBLISH_CCASTOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 3091 3092 /* Bits 7..0 : DPPI channel that event CCASTOPPED will publish to. */ 3093 #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3094 #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3095 3096 /* Register: RADIO_PUBLISH_RATEBOOST */ 3097 /* Description: Publish configuration for event RATEBOOST */ 3098 3099 /* Bit 31 : */ 3100 #define RADIO_PUBLISH_RATEBOOST_EN_Pos (31UL) /*!< Position of EN field. */ 3101 #define RADIO_PUBLISH_RATEBOOST_EN_Msk (0x1UL << RADIO_PUBLISH_RATEBOOST_EN_Pos) /*!< Bit mask of EN field. */ 3102 #define RADIO_PUBLISH_RATEBOOST_EN_Disabled (0UL) /*!< Disable publishing */ 3103 #define RADIO_PUBLISH_RATEBOOST_EN_Enabled (1UL) /*!< Enable publishing */ 3104 3105 /* Bits 7..0 : DPPI channel that event RATEBOOST will publish to. */ 3106 #define RADIO_PUBLISH_RATEBOOST_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3107 #define RADIO_PUBLISH_RATEBOOST_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RATEBOOST_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3108 3109 /* Register: RADIO_PUBLISH_TXREADY */ 3110 /* Description: Publish configuration for event TXREADY */ 3111 3112 /* Bit 31 : */ 3113 #define RADIO_PUBLISH_TXREADY_EN_Pos (31UL) /*!< Position of EN field. */ 3114 #define RADIO_PUBLISH_TXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_TXREADY_EN_Pos) /*!< Bit mask of EN field. */ 3115 #define RADIO_PUBLISH_TXREADY_EN_Disabled (0UL) /*!< Disable publishing */ 3116 #define RADIO_PUBLISH_TXREADY_EN_Enabled (1UL) /*!< Enable publishing */ 3117 3118 /* Bits 7..0 : DPPI channel that event TXREADY will publish to. */ 3119 #define RADIO_PUBLISH_TXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3120 #define RADIO_PUBLISH_TXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_TXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3121 3122 /* Register: RADIO_PUBLISH_RXREADY */ 3123 /* Description: Publish configuration for event RXREADY */ 3124 3125 /* Bit 31 : */ 3126 #define RADIO_PUBLISH_RXREADY_EN_Pos (31UL) /*!< Position of EN field. */ 3127 #define RADIO_PUBLISH_RXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_RXREADY_EN_Pos) /*!< Bit mask of EN field. */ 3128 #define RADIO_PUBLISH_RXREADY_EN_Disabled (0UL) /*!< Disable publishing */ 3129 #define RADIO_PUBLISH_RXREADY_EN_Enabled (1UL) /*!< Enable publishing */ 3130 3131 /* Bits 7..0 : DPPI channel that event RXREADY will publish to. */ 3132 #define RADIO_PUBLISH_RXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3133 #define RADIO_PUBLISH_RXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3134 3135 /* Register: RADIO_PUBLISH_MHRMATCH */ 3136 /* Description: Publish configuration for event MHRMATCH */ 3137 3138 /* Bit 31 : */ 3139 #define RADIO_PUBLISH_MHRMATCH_EN_Pos (31UL) /*!< Position of EN field. */ 3140 #define RADIO_PUBLISH_MHRMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_MHRMATCH_EN_Pos) /*!< Bit mask of EN field. */ 3141 #define RADIO_PUBLISH_MHRMATCH_EN_Disabled (0UL) /*!< Disable publishing */ 3142 #define RADIO_PUBLISH_MHRMATCH_EN_Enabled (1UL) /*!< Enable publishing */ 3143 3144 /* Bits 7..0 : DPPI channel that event MHRMATCH will publish to. */ 3145 #define RADIO_PUBLISH_MHRMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3146 #define RADIO_PUBLISH_MHRMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_MHRMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3147 3148 /* Register: RADIO_PUBLISH_SYNC */ 3149 /* Description: Publish configuration for event SYNC */ 3150 3151 /* Bit 31 : */ 3152 #define RADIO_PUBLISH_SYNC_EN_Pos (31UL) /*!< Position of EN field. */ 3153 #define RADIO_PUBLISH_SYNC_EN_Msk (0x1UL << RADIO_PUBLISH_SYNC_EN_Pos) /*!< Bit mask of EN field. */ 3154 #define RADIO_PUBLISH_SYNC_EN_Disabled (0UL) /*!< Disable publishing */ 3155 #define RADIO_PUBLISH_SYNC_EN_Enabled (1UL) /*!< Enable publishing */ 3156 3157 /* Bits 7..0 : DPPI channel that event SYNC will publish to. */ 3158 #define RADIO_PUBLISH_SYNC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3159 #define RADIO_PUBLISH_SYNC_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_SYNC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3160 3161 /* Register: RADIO_PUBLISH_PHYEND */ 3162 /* Description: Publish configuration for event PHYEND */ 3163 3164 /* Bit 31 : */ 3165 #define RADIO_PUBLISH_PHYEND_EN_Pos (31UL) /*!< Position of EN field. */ 3166 #define RADIO_PUBLISH_PHYEND_EN_Msk (0x1UL << RADIO_PUBLISH_PHYEND_EN_Pos) /*!< Bit mask of EN field. */ 3167 #define RADIO_PUBLISH_PHYEND_EN_Disabled (0UL) /*!< Disable publishing */ 3168 #define RADIO_PUBLISH_PHYEND_EN_Enabled (1UL) /*!< Enable publishing */ 3169 3170 /* Bits 7..0 : DPPI channel that event PHYEND will publish to. */ 3171 #define RADIO_PUBLISH_PHYEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3172 #define RADIO_PUBLISH_PHYEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PHYEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3173 3174 /* Register: RADIO_PUBLISH_CTEPRESENT */ 3175 /* Description: Publish configuration for event CTEPRESENT */ 3176 3177 /* Bit 31 : */ 3178 #define RADIO_PUBLISH_CTEPRESENT_EN_Pos (31UL) /*!< Position of EN field. */ 3179 #define RADIO_PUBLISH_CTEPRESENT_EN_Msk (0x1UL << RADIO_PUBLISH_CTEPRESENT_EN_Pos) /*!< Bit mask of EN field. */ 3180 #define RADIO_PUBLISH_CTEPRESENT_EN_Disabled (0UL) /*!< Disable publishing */ 3181 #define RADIO_PUBLISH_CTEPRESENT_EN_Enabled (1UL) /*!< Enable publishing */ 3182 3183 /* Bits 7..0 : DPPI channel that event CTEPRESENT will publish to. */ 3184 #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3185 #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3186 3187 /* Register: RADIO_SHORTS */ 3188 /* Description: Shortcuts between local events and tasks */ 3189 3190 /* Bit 21 : Shortcut between event PHYEND and task START */ 3191 #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */ 3192 #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ 3193 #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */ 3194 #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */ 3195 3196 /* Bit 20 : Shortcut between event PHYEND and task DISABLE */ 3197 #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */ 3198 #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ 3199 #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 3200 #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 3201 3202 /* Bit 19 : Shortcut between event RXREADY and task START */ 3203 #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ 3204 #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ 3205 #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ 3206 #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ 3207 3208 /* Bit 18 : Shortcut between event TXREADY and task START */ 3209 #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ 3210 #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ 3211 #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ 3212 #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ 3213 3214 /* Bit 17 : Shortcut between event CCAIDLE and task STOP */ 3215 #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */ 3216 #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ 3217 #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */ 3218 #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */ 3219 3220 /* Bit 16 : Shortcut between event EDEND and task DISABLE */ 3221 #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */ 3222 #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ 3223 #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 3224 #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 3225 3226 /* Bit 15 : Shortcut between event READY and task EDSTART */ 3227 #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */ 3228 #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ 3229 #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */ 3230 #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */ 3231 3232 /* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */ 3233 #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */ 3234 #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */ 3235 #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */ 3236 #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */ 3237 3238 /* Bit 13 : Shortcut between event CCABUSY and task DISABLE */ 3239 #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */ 3240 #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ 3241 #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 3242 #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 3243 3244 /* Bit 12 : Shortcut between event CCAIDLE and task TXEN */ 3245 #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */ 3246 #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ 3247 #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */ 3248 #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */ 3249 3250 /* Bit 11 : Shortcut between event RXREADY and task CCASTART */ 3251 #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */ 3252 #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */ 3253 #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */ 3254 #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */ 3255 3256 /* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */ 3257 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ 3258 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ 3259 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ 3260 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ 3261 3262 /* Bit 6 : Shortcut between event ADDRESS and task BCSTART */ 3263 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ 3264 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ 3265 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ 3266 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ 3267 3268 /* Bit 5 : Shortcut between event END and task START */ 3269 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ 3270 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 3271 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ 3272 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ 3273 3274 /* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ 3275 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ 3276 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ 3277 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ 3278 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ 3279 3280 /* Bit 3 : Shortcut between event DISABLED and task RXEN */ 3281 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ 3282 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ 3283 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ 3284 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ 3285 3286 /* Bit 2 : Shortcut between event DISABLED and task TXEN */ 3287 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ 3288 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ 3289 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ 3290 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ 3291 3292 /* Bit 1 : Shortcut between event END and task DISABLE */ 3293 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ 3294 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ 3295 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 3296 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 3297 3298 /* Bit 0 : Shortcut between event READY and task START */ 3299 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ 3300 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ 3301 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ 3302 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ 3303 3304 /* Register: RADIO_INTENSET */ 3305 /* Description: Enable interrupt */ 3306 3307 /* Bit 28 : Write '1' to enable interrupt for event CTEPRESENT */ 3308 #define RADIO_INTENSET_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */ 3309 #define RADIO_INTENSET_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ 3310 #define RADIO_INTENSET_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */ 3311 #define RADIO_INTENSET_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */ 3312 #define RADIO_INTENSET_CTEPRESENT_Set (1UL) /*!< Enable */ 3313 3314 /* Bit 27 : Write '1' to enable interrupt for event PHYEND */ 3315 #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ 3316 #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ 3317 #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ 3318 #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ 3319 #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ 3320 3321 /* Bit 26 : Write '1' to enable interrupt for event SYNC */ 3322 #define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */ 3323 #define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */ 3324 #define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */ 3325 #define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */ 3326 #define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */ 3327 3328 /* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ 3329 #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ 3330 #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ 3331 #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ 3332 #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ 3333 #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ 3334 3335 /* Bit 22 : Write '1' to enable interrupt for event RXREADY */ 3336 #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ 3337 #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ 3338 #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ 3339 #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ 3340 #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ 3341 3342 /* Bit 21 : Write '1' to enable interrupt for event TXREADY */ 3343 #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ 3344 #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ 3345 #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ 3346 #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ 3347 #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ 3348 3349 /* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ 3350 #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ 3351 #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ 3352 #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ 3353 #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ 3354 #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ 3355 3356 /* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ 3357 #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ 3358 #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ 3359 #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ 3360 #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ 3361 #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ 3362 3363 /* Bit 18 : Write '1' to enable interrupt for event CCABUSY */ 3364 #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ 3365 #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ 3366 #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ 3367 #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ 3368 #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ 3369 3370 /* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ 3371 #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ 3372 #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ 3373 #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ 3374 #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ 3375 #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ 3376 3377 /* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ 3378 #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ 3379 #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ 3380 #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 3381 #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 3382 #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ 3383 3384 /* Bit 15 : Write '1' to enable interrupt for event EDEND */ 3385 #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ 3386 #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ 3387 #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ 3388 #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ 3389 #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ 3390 3391 /* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */ 3392 #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ 3393 #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ 3394 #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ 3395 #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ 3396 #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ 3397 3398 /* Bit 13 : Write '1' to enable interrupt for event CRCERROR */ 3399 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ 3400 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ 3401 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ 3402 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ 3403 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ 3404 3405 /* Bit 12 : Write '1' to enable interrupt for event CRCOK */ 3406 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ 3407 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ 3408 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ 3409 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ 3410 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ 3411 3412 /* Bit 10 : Write '1' to enable interrupt for event BCMATCH */ 3413 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 3414 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 3415 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ 3416 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ 3417 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ 3418 3419 /* Bit 7 : Write '1' to enable interrupt for event RSSIEND */ 3420 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 3421 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 3422 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ 3423 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ 3424 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ 3425 3426 /* Bit 6 : Write '1' to enable interrupt for event DEVMISS */ 3427 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 3428 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 3429 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ 3430 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ 3431 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ 3432 3433 /* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */ 3434 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 3435 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 3436 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ 3437 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ 3438 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ 3439 3440 /* Bit 4 : Write '1' to enable interrupt for event DISABLED */ 3441 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 3442 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 3443 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ 3444 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ 3445 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ 3446 3447 /* Bit 3 : Write '1' to enable interrupt for event END */ 3448 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ 3449 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ 3450 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 3451 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 3452 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ 3453 3454 /* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */ 3455 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 3456 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 3457 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ 3458 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ 3459 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ 3460 3461 /* Bit 1 : Write '1' to enable interrupt for event ADDRESS */ 3462 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 3463 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 3464 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ 3465 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ 3466 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ 3467 3468 /* Bit 0 : Write '1' to enable interrupt for event READY */ 3469 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 3470 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 3471 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ 3472 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ 3473 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ 3474 3475 /* Register: RADIO_INTENCLR */ 3476 /* Description: Disable interrupt */ 3477 3478 /* Bit 28 : Write '1' to disable interrupt for event CTEPRESENT */ 3479 #define RADIO_INTENCLR_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */ 3480 #define RADIO_INTENCLR_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ 3481 #define RADIO_INTENCLR_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */ 3482 #define RADIO_INTENCLR_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */ 3483 #define RADIO_INTENCLR_CTEPRESENT_Clear (1UL) /*!< Disable */ 3484 3485 /* Bit 27 : Write '1' to disable interrupt for event PHYEND */ 3486 #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ 3487 #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ 3488 #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ 3489 #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ 3490 #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ 3491 3492 /* Bit 26 : Write '1' to disable interrupt for event SYNC */ 3493 #define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */ 3494 #define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */ 3495 #define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */ 3496 #define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */ 3497 #define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */ 3498 3499 /* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ 3500 #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ 3501 #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ 3502 #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ 3503 #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ 3504 #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ 3505 3506 /* Bit 22 : Write '1' to disable interrupt for event RXREADY */ 3507 #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ 3508 #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ 3509 #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ 3510 #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ 3511 #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ 3512 3513 /* Bit 21 : Write '1' to disable interrupt for event TXREADY */ 3514 #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ 3515 #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ 3516 #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ 3517 #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ 3518 #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ 3519 3520 /* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ 3521 #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ 3522 #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ 3523 #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ 3524 #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ 3525 #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ 3526 3527 /* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ 3528 #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ 3529 #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ 3530 #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ 3531 #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ 3532 #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ 3533 3534 /* Bit 18 : Write '1' to disable interrupt for event CCABUSY */ 3535 #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ 3536 #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ 3537 #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ 3538 #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ 3539 #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ 3540 3541 /* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ 3542 #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ 3543 #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ 3544 #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ 3545 #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ 3546 #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ 3547 3548 /* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ 3549 #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ 3550 #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ 3551 #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 3552 #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 3553 #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ 3554 3555 /* Bit 15 : Write '1' to disable interrupt for event EDEND */ 3556 #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ 3557 #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ 3558 #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ 3559 #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ 3560 #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ 3561 3562 /* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */ 3563 #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ 3564 #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ 3565 #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ 3566 #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ 3567 #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ 3568 3569 /* Bit 13 : Write '1' to disable interrupt for event CRCERROR */ 3570 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ 3571 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ 3572 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ 3573 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ 3574 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ 3575 3576 /* Bit 12 : Write '1' to disable interrupt for event CRCOK */ 3577 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ 3578 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ 3579 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ 3580 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ 3581 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ 3582 3583 /* Bit 10 : Write '1' to disable interrupt for event BCMATCH */ 3584 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 3585 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 3586 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ 3587 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ 3588 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ 3589 3590 /* Bit 7 : Write '1' to disable interrupt for event RSSIEND */ 3591 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 3592 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 3593 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ 3594 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ 3595 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ 3596 3597 /* Bit 6 : Write '1' to disable interrupt for event DEVMISS */ 3598 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 3599 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 3600 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ 3601 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ 3602 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ 3603 3604 /* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */ 3605 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 3606 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 3607 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ 3608 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ 3609 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ 3610 3611 /* Bit 4 : Write '1' to disable interrupt for event DISABLED */ 3612 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 3613 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 3614 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ 3615 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ 3616 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ 3617 3618 /* Bit 3 : Write '1' to disable interrupt for event END */ 3619 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ 3620 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 3621 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 3622 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 3623 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ 3624 3625 /* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */ 3626 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 3627 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 3628 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ 3629 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ 3630 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ 3631 3632 /* Bit 1 : Write '1' to disable interrupt for event ADDRESS */ 3633 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 3634 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 3635 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ 3636 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ 3637 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ 3638 3639 /* Bit 0 : Write '1' to disable interrupt for event READY */ 3640 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 3641 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 3642 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ 3643 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ 3644 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ 3645 3646 /* Register: RADIO_CRCSTATUS */ 3647 /* Description: CRC status */ 3648 3649 /* Bit 0 : CRC status of packet received */ 3650 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ 3651 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ 3652 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ 3653 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ 3654 3655 /* Register: RADIO_RXMATCH */ 3656 /* Description: Received address */ 3657 3658 /* Bits 2..0 : Received address */ 3659 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ 3660 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ 3661 3662 /* Register: RADIO_RXCRC */ 3663 /* Description: CRC field of previously received packet */ 3664 3665 /* Bits 23..0 : CRC field of previously received packet */ 3666 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ 3667 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ 3668 3669 /* Register: RADIO_DAI */ 3670 /* Description: Device address match index */ 3671 3672 /* Bits 2..0 : Device address match index */ 3673 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ 3674 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ 3675 3676 /* Register: RADIO_PDUSTAT */ 3677 /* Description: Payload status */ 3678 3679 /* Bits 2..1 : Status on what rate packet is received with in Long Range */ 3680 #define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */ 3681 #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */ 3682 #define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125 kbps */ 3683 #define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500 kbps */ 3684 3685 /* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */ 3686 #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */ 3687 #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */ 3688 #define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */ 3689 #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */ 3690 3691 /* Register: RADIO_CTESTATUS */ 3692 /* Description: CTEInfo parsed from received packet */ 3693 3694 /* Bits 7..6 : CTEType parsed from packet */ 3695 #define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */ 3696 #define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */ 3697 3698 /* Bit 5 : RFU parsed from packet */ 3699 #define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */ 3700 #define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */ 3701 3702 /* Bits 4..0 : CTETime parsed from packet */ 3703 #define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */ 3704 #define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */ 3705 3706 /* Register: RADIO_DFESTATUS */ 3707 /* Description: DFE status information */ 3708 3709 /* Bit 4 : Internal state of sampling state machine */ 3710 #define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */ 3711 #define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */ 3712 #define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0UL) /*!< Sampling state Idle */ 3713 #define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (1UL) /*!< Sampling state Sampling */ 3714 3715 /* Bits 2..0 : Internal state of switching state machine */ 3716 #define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */ 3717 #define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE field. */ 3718 #define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0UL) /*!< Switching state Idle */ 3719 #define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (1UL) /*!< Switching state Offset */ 3720 #define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (2UL) /*!< Switching state Guard */ 3721 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (3UL) /*!< Switching state Ref */ 3722 #define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (4UL) /*!< Switching state Switching */ 3723 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (5UL) /*!< Switching state Ending */ 3724 3725 /* Register: RADIO_PACKETPTR */ 3726 /* Description: Packet pointer */ 3727 3728 /* Bits 31..0 : Packet pointer */ 3729 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ 3730 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ 3731 3732 /* Register: RADIO_FREQUENCY */ 3733 /* Description: Frequency */ 3734 3735 /* Bit 8 : Channel map selection */ 3736 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ 3737 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ 3738 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHz and 2500 MHz */ 3739 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHz and 2460 MHz */ 3740 3741 /* Bits 6..0 : Radio channel frequency */ 3742 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 3743 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 3744 3745 /* Register: RADIO_TXPOWER */ 3746 /* Description: Output power */ 3747 3748 /* Bits 7..0 : RADIO output power */ 3749 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ 3750 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ 3751 #define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */ 3752 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ 3753 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */ 3754 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ 3755 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ 3756 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ 3757 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ 3758 #define RADIO_TXPOWER_TXPOWER_Neg7dBm (0xF9UL) /*!< -7 dBm */ 3759 #define RADIO_TXPOWER_TXPOWER_Neg6dBm (0xFAUL) /*!< -6 dBm */ 3760 #define RADIO_TXPOWER_TXPOWER_Neg5dBm (0xFBUL) /*!< -5 dBm */ 3761 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ 3762 #define RADIO_TXPOWER_TXPOWER_Neg3dBm (0xFDUL) /*!< -3 dBm */ 3763 #define RADIO_TXPOWER_TXPOWER_Neg2dBm (0xFEUL) /*!< -2 dBm */ 3764 #define RADIO_TXPOWER_TXPOWER_Neg1dBm (0xFFUL) /*!< -1 dBm */ 3765 3766 /* Register: RADIO_MODE */ 3767 /* Description: Data rate and modulation */ 3768 3769 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */ 3770 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 3771 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 3772 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbps Nordic proprietary radio mode */ 3773 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */ 3774 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */ 3775 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */ 3776 #define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long Range 125 kbps TX, 125 kbps and 500 kbps RX */ 3777 #define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long Range 500 kbps TX, 125 kbps and 500 kbps RX */ 3778 #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbps */ 3779 3780 /* Register: RADIO_PCNF0 */ 3781 /* Description: Packet configuration register 0 */ 3782 3783 /* Bits 30..29 : Length of TERM field in Long Range operation */ 3784 #define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */ 3785 #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */ 3786 3787 /* Bit 26 : Indicates if LENGTH field contains CRC or not */ 3788 #define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */ 3789 #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */ 3790 #define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */ 3791 #define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */ 3792 3793 /* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */ 3794 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ 3795 #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ 3796 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ 3797 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ 3798 #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ 3799 #define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for Bluetooth LE Long Range */ 3800 3801 /* Bits 23..22 : Length of code indicator - Long Range */ 3802 #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ 3803 #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ 3804 3805 /* Bit 20 : Include or exclude S1 field in RAM */ 3806 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ 3807 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ 3808 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ 3809 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ 3810 3811 /* Bits 19..16 : Length on air of S1 field in number of bits */ 3812 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ 3813 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ 3814 3815 /* Bit 8 : Length on air of S0 field in number of bytes */ 3816 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ 3817 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ 3818 3819 /* Bits 3..0 : Length on air of LENGTH field in number of bits */ 3820 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ 3821 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ 3822 3823 /* Register: RADIO_PCNF1 */ 3824 /* Description: Packet configuration register 1 */ 3825 3826 /* Bit 25 : Enable or disable packet whitening */ 3827 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ 3828 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ 3829 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ 3830 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ 3831 3832 /* Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */ 3833 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ 3834 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ 3835 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ 3836 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ 3837 3838 /* Bits 18..16 : Base address length in number of bytes */ 3839 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ 3840 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ 3841 3842 /* Bits 15..8 : Static length in number of bytes */ 3843 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ 3844 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ 3845 3846 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ 3847 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ 3848 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ 3849 3850 /* Register: RADIO_BASE0 */ 3851 /* Description: Base address 0 */ 3852 3853 /* Bits 31..0 : Base address 0 */ 3854 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ 3855 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ 3856 3857 /* Register: RADIO_BASE1 */ 3858 /* Description: Base address 1 */ 3859 3860 /* Bits 31..0 : Base address 1 */ 3861 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ 3862 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ 3863 3864 /* Register: RADIO_PREFIX0 */ 3865 /* Description: Prefixes bytes for logical addresses 0-3 */ 3866 3867 /* Bits 31..24 : Address prefix 3. */ 3868 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ 3869 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ 3870 3871 /* Bits 23..16 : Address prefix 2. */ 3872 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ 3873 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ 3874 3875 /* Bits 15..8 : Address prefix 1. */ 3876 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ 3877 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ 3878 3879 /* Bits 7..0 : Address prefix 0. */ 3880 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ 3881 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ 3882 3883 /* Register: RADIO_PREFIX1 */ 3884 /* Description: Prefixes bytes for logical addresses 4-7 */ 3885 3886 /* Bits 31..24 : Address prefix 7. */ 3887 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ 3888 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ 3889 3890 /* Bits 23..16 : Address prefix 6. */ 3891 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ 3892 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ 3893 3894 /* Bits 15..8 : Address prefix 5. */ 3895 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ 3896 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ 3897 3898 /* Bits 7..0 : Address prefix 4. */ 3899 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ 3900 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ 3901 3902 /* Register: RADIO_TXADDRESS */ 3903 /* Description: Transmit address select */ 3904 3905 /* Bits 2..0 : Transmit address select */ 3906 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ 3907 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ 3908 3909 /* Register: RADIO_RXADDRESSES */ 3910 /* Description: Receive address select */ 3911 3912 /* Bit 7 : Enable or disable reception on logical address 7. */ 3913 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ 3914 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ 3915 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ 3916 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ 3917 3918 /* Bit 6 : Enable or disable reception on logical address 6. */ 3919 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ 3920 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ 3921 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ 3922 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ 3923 3924 /* Bit 5 : Enable or disable reception on logical address 5. */ 3925 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ 3926 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ 3927 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ 3928 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ 3929 3930 /* Bit 4 : Enable or disable reception on logical address 4. */ 3931 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ 3932 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ 3933 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ 3934 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ 3935 3936 /* Bit 3 : Enable or disable reception on logical address 3. */ 3937 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ 3938 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ 3939 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ 3940 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ 3941 3942 /* Bit 2 : Enable or disable reception on logical address 2. */ 3943 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ 3944 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ 3945 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ 3946 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ 3947 3948 /* Bit 1 : Enable or disable reception on logical address 1. */ 3949 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ 3950 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ 3951 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ 3952 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ 3953 3954 /* Bit 0 : Enable or disable reception on logical address 0. */ 3955 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ 3956 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ 3957 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ 3958 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ 3959 3960 /* Register: RADIO_CRCCNF */ 3961 /* Description: CRC configuration */ 3962 3963 /* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */ 3964 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ 3965 #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ 3966 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ 3967 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ 3968 #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ 3969 3970 /* Bits 1..0 : CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported */ 3971 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ 3972 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ 3973 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ 3974 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ 3975 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ 3976 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ 3977 3978 /* Register: RADIO_CRCPOLY */ 3979 /* Description: CRC polynomial */ 3980 3981 /* Bits 23..0 : CRC polynomial */ 3982 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ 3983 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ 3984 3985 /* Register: RADIO_CRCINIT */ 3986 /* Description: CRC initial value */ 3987 3988 /* Bits 23..0 : CRC initial value */ 3989 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ 3990 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ 3991 3992 /* Register: RADIO_TIFS */ 3993 /* Description: Interframe spacing in us */ 3994 3995 /* Bits 9..0 : Interframe spacing in us. */ 3996 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ 3997 #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ 3998 3999 /* Register: RADIO_RSSISAMPLE */ 4000 /* Description: RSSI sample */ 4001 4002 /* Bits 6..0 : RSSI sample. */ 4003 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ 4004 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ 4005 4006 /* Register: RADIO_STATE */ 4007 /* Description: Current radio state */ 4008 4009 /* Bits 3..0 : Current radio state */ 4010 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ 4011 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ 4012 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ 4013 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ 4014 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ 4015 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ 4016 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ 4017 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ 4018 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ 4019 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ 4020 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ 4021 4022 /* Register: RADIO_DATAWHITEIV */ 4023 /* Description: Data whitening initial value */ 4024 4025 /* Bits 6..0 : Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ 4026 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ 4027 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ 4028 4029 /* Register: RADIO_BCC */ 4030 /* Description: Bit counter compare */ 4031 4032 /* Bits 31..0 : Bit counter compare */ 4033 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ 4034 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ 4035 4036 /* Register: RADIO_DAB */ 4037 /* Description: Description collection: Device address base segment n */ 4038 4039 /* Bits 31..0 : Device address base segment n */ 4040 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ 4041 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ 4042 4043 /* Register: RADIO_DAP */ 4044 /* Description: Description collection: Device address prefix n */ 4045 4046 /* Bits 15..0 : Device address prefix n */ 4047 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ 4048 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ 4049 4050 /* Register: RADIO_DACNF */ 4051 /* Description: Device address match configuration */ 4052 4053 /* Bit 15 : TxAdd for device address 7 */ 4054 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ 4055 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ 4056 4057 /* Bit 14 : TxAdd for device address 6 */ 4058 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ 4059 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ 4060 4061 /* Bit 13 : TxAdd for device address 5 */ 4062 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ 4063 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ 4064 4065 /* Bit 12 : TxAdd for device address 4 */ 4066 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ 4067 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ 4068 4069 /* Bit 11 : TxAdd for device address 3 */ 4070 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ 4071 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ 4072 4073 /* Bit 10 : TxAdd for device address 2 */ 4074 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ 4075 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ 4076 4077 /* Bit 9 : TxAdd for device address 1 */ 4078 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ 4079 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ 4080 4081 /* Bit 8 : TxAdd for device address 0 */ 4082 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ 4083 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ 4084 4085 /* Bit 7 : Enable or disable device address matching using device address 7 */ 4086 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ 4087 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ 4088 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ 4089 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ 4090 4091 /* Bit 6 : Enable or disable device address matching using device address 6 */ 4092 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ 4093 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ 4094 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ 4095 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ 4096 4097 /* Bit 5 : Enable or disable device address matching using device address 5 */ 4098 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ 4099 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ 4100 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ 4101 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ 4102 4103 /* Bit 4 : Enable or disable device address matching using device address 4 */ 4104 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ 4105 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ 4106 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ 4107 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ 4108 4109 /* Bit 3 : Enable or disable device address matching using device address 3 */ 4110 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ 4111 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ 4112 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ 4113 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ 4114 4115 /* Bit 2 : Enable or disable device address matching using device address 2 */ 4116 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ 4117 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ 4118 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ 4119 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ 4120 4121 /* Bit 1 : Enable or disable device address matching using device address 1 */ 4122 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ 4123 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ 4124 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ 4125 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ 4126 4127 /* Bit 0 : Enable or disable device address matching using device address 0 */ 4128 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ 4129 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ 4130 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ 4131 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ 4132 4133 /* Register: RADIO_MHRMATCHCONF */ 4134 /* Description: Search pattern configuration */ 4135 4136 /* Bits 31..0 : Search pattern configuration */ 4137 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */ 4138 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */ 4139 4140 /* Register: RADIO_MHRMATCHMAS */ 4141 /* Description: Pattern mask */ 4142 4143 /* Bits 31..0 : Pattern mask */ 4144 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */ 4145 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */ 4146 4147 /* Register: RADIO_MODECNF0 */ 4148 /* Description: Radio mode configuration register 0 */ 4149 4150 /* Bits 9..8 : Default TX value */ 4151 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ 4152 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ 4153 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ 4154 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ 4155 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ 4156 4157 /* Bit 0 : Radio ramp-up time */ 4158 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ 4159 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ 4160 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ 4161 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */ 4162 4163 /* Register: RADIO_SFD */ 4164 /* Description: IEEE 802.15.4 start of frame delimiter */ 4165 4166 /* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */ 4167 #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */ 4168 #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */ 4169 4170 /* Register: RADIO_EDCNT */ 4171 /* Description: IEEE 802.15.4 energy detect loop count */ 4172 4173 /* Bits 20..0 : IEEE 802.15.4 energy detect loop count */ 4174 #define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */ 4175 #define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */ 4176 4177 /* Register: RADIO_EDSAMPLE */ 4178 /* Description: IEEE 802.15.4 energy detect level */ 4179 4180 /* Bits 7..0 : IEEE 802.15.4 energy detect level */ 4181 #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */ 4182 #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */ 4183 4184 /* Register: RADIO_CCACTRL */ 4185 /* Description: IEEE 802.15.4 clear channel assessment control */ 4186 4187 /* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */ 4188 #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */ 4189 #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */ 4190 4191 /* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. */ 4192 #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */ 4193 #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */ 4194 4195 /* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */ 4196 #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */ 4197 #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */ 4198 4199 /* Bits 2..0 : CCA mode of operation */ 4200 #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */ 4201 #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */ 4202 #define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */ 4203 #define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */ 4204 #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */ 4205 #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */ 4206 #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ 4207 4208 /* Register: RADIO_DFEMODE */ 4209 /* Description: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */ 4210 4211 /* Bits 1..0 : Direction finding operation mode */ 4212 #define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */ 4213 #define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */ 4214 #define RADIO_DFEMODE_DFEOPMODE_Disabled (0UL) /*!< Direction finding mode disabled */ 4215 #define RADIO_DFEMODE_DFEOPMODE_AoD (2UL) /*!< Direction finding mode set to AoD */ 4216 #define RADIO_DFEMODE_DFEOPMODE_AoA (3UL) /*!< Direction finding mode set to AoA */ 4217 4218 /* Register: RADIO_CTEINLINECONF */ 4219 /* Description: Configuration for CTE inline mode */ 4220 4221 /* Bits 31..24 : S0 bit mask to set which bit to match */ 4222 #define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */ 4223 #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */ 4224 4225 /* Bits 23..16 : S0 bit pattern to match */ 4226 #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */ 4227 #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */ 4228 4229 /* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ 4230 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */ 4231 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */ 4232 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4 us */ 4233 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2 us */ 4234 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1 us */ 4235 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5 us */ 4236 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25 us */ 4237 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125 us */ 4238 4239 /* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ 4240 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */ 4241 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */ 4242 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4 us */ 4243 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2 us */ 4244 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1 us */ 4245 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5 us */ 4246 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25 us */ 4247 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125 us */ 4248 4249 /* Bits 7..6 : Max range of CTETime */ 4250 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */ 4251 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */ 4252 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 */ 4253 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8 us unit */ 4254 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8 us unit */ 4255 4256 /* Bit 4 : Sampling/switching if CRC is not OK */ 4257 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */ 4258 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of CTEERRORHANDLING field. */ 4259 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0UL) /*!< No sampling and antenna switching when CRC is not OK */ 4260 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (1UL) /*!< Sampling and antenna switching also when CRC is not OK */ 4261 4262 /* Bit 3 : CTEInfo is S1 byte or not */ 4263 #define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */ 4264 #define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 field. */ 4265 #define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */ 4266 #define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (1UL) /*!< CTEInfo is in S1 byte (data PDU) */ 4267 4268 /* Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */ 4269 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */ 4270 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of CTEINLINECTRLEN field. */ 4271 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0UL) /*!< Parsing of CTEInfo is disabled */ 4272 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (1UL) /*!< Parsing of CTEInfo is enabled */ 4273 4274 /* Register: RADIO_DFECTRL1 */ 4275 /* Description: Various configuration for Direction finding */ 4276 4277 /* Bits 27..24 : Gain will be lowered by the specified number of gain steps at the start of CTE */ 4278 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */ 4279 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field. */ 4280 4281 /* Bits 23..20 : Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. */ 4282 #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL) /*!< Position of REPEATPATTERN field. */ 4283 #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field. */ 4284 #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0UL) /*!< Do not repeat (1 time in total) */ 4285 4286 /* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */ 4287 #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */ 4288 #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */ 4289 #define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4 us */ 4290 #define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2 us */ 4291 #define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1 us */ 4292 #define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5 us */ 4293 #define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25 us */ 4294 #define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125 us */ 4295 4296 /* Bit 15 : Whether to sample I/Q or magnitude/phase */ 4297 #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */ 4298 #define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */ 4299 #define RADIO_DFECTRL1_SAMPLETYPE_IQ (0UL) /*!< Complex samples in I and Q */ 4300 #define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (1UL) /*!< Complex samples as magnitude and phase */ 4301 4302 /* Bits 14..12 : Interval between samples in the REFERENCE period */ 4303 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */ 4304 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */ 4305 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4 us */ 4306 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2 us */ 4307 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1 us */ 4308 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5 us */ 4309 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25 us */ 4310 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125 us */ 4311 4312 /* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */ 4313 #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */ 4314 #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */ 4315 #define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4 us */ 4316 #define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2 us */ 4317 #define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1 us */ 4318 4319 /* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */ 4320 #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */ 4321 #define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field. */ 4322 #define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0UL) /*!< Antenna switching/sampling is done in the packet payload */ 4323 #define RADIO_DFECTRL1_DFEINEXTENSION_CRC (1UL) /*!< AoA/AoD procedure triggered at end of CRC */ 4324 4325 /* Bits 5..0 : Length of the AoA/AoD procedure in number of 8 us units */ 4326 #define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */ 4327 #define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */ 4328 4329 /* Register: RADIO_DFECTRL2 */ 4330 /* Description: Start offset for Direction finding */ 4331 4332 /* Bits 27..16 : Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period */ 4333 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */ 4334 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */ 4335 4336 /* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles */ 4337 #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */ 4338 #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */ 4339 4340 /* Register: RADIO_SWITCHPATTERN */ 4341 /* Description: GPIO patterns to be used for each antenna */ 4342 4343 /* Bits 7..0 : Fill array of GPIO patterns for antenna control. */ 4344 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */ 4345 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */ 4346 4347 /* Register: RADIO_CLEARPATTERN */ 4348 /* Description: Clear the GPIO pattern array for antenna control */ 4349 4350 /* Bit 0 : Clears GPIO pattern array for antenna control */ 4351 #define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */ 4352 #define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN field. */ 4353 #define RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL) /*!< Clear the GPIO pattern */ 4354 4355 /* Register: RADIO_PSEL_DFEGPIO */ 4356 /* Description: Description collection: Pin select for DFE pin n */ 4357 4358 /* Bit 31 : Connection */ 4359 #define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 4360 #define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 4361 #define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0UL) /*!< Connect */ 4362 #define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (1UL) /*!< Disconnect */ 4363 4364 /* Bit 5 : Port number */ 4365 #define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL) /*!< Position of PORT field. */ 4366 #define RADIO_PSEL_DFEGPIO_PORT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field. */ 4367 4368 /* Bits 4..0 : Pin number */ 4369 #define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */ 4370 #define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */ 4371 4372 /* Register: RADIO_DFEPACKET_PTR */ 4373 /* Description: Data pointer */ 4374 4375 /* Bits 31..0 : Data pointer */ 4376 #define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 4377 #define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 4378 4379 /* Register: RADIO_DFEPACKET_MAXCNT */ 4380 /* Description: Maximum number of buffer words to transfer */ 4381 4382 /* Bits 13..0 : Maximum number of buffer words to transfer */ 4383 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 4384 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0x3FFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 4385 4386 /* Register: RADIO_DFEPACKET_AMOUNT */ 4387 /* Description: Number of samples transferred in the last transaction */ 4388 4389 /* Bits 15..0 : Number of samples transferred in the last transaction */ 4390 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 4391 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 4392 4393 /* Register: RADIO_POWER */ 4394 /* Description: Peripheral power control */ 4395 4396 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ 4397 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 4398 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 4399 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ 4400 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ 4401 4402 4403 4404 /* =========================================================================================================================== */ 4405 /* ================ RNG_NS ================ */ 4406 /* =========================================================================================================================== */ 4407 4408 4409 /** 4410 * @brief Random Number Generator (RNG_NS) 4411 */ 4412 4413 typedef struct { /*!< (@ 0x41009000) RNG_NS Structure */ 4414 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 4415 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 4416 __IM uint32_t RESERVED[30]; 4417 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 4418 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 4419 __IM uint32_t RESERVED1[30]; 4420 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 4421 written to the VALUE register */ 4422 __IM uint32_t RESERVED2[31]; 4423 __IOM uint32_t PUBLISH_VALRDY; /*!< (@ 0x00000180) Publish configuration for event VALRDY */ 4424 __IM uint32_t RESERVED3[31]; 4425 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 4426 __IM uint32_t RESERVED4[64]; 4427 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 4428 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 4429 __IM uint32_t RESERVED5[126]; 4430 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 4431 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 4432 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 4433 4434 4435 /* Peripheral: RNG */ 4436 /* Description: Random Number Generator */ 4437 4438 /* Register: RNG_TASKS_START */ 4439 /* Description: Task starting the random number generator */ 4440 4441 /* Bit 0 : Task starting the random number generator */ 4442 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 4443 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 4444 #define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 4445 4446 /* Register: RNG_TASKS_STOP */ 4447 /* Description: Task stopping the random number generator */ 4448 4449 /* Bit 0 : Task stopping the random number generator */ 4450 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 4451 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 4452 #define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 4453 4454 /* Register: RNG_SUBSCRIBE_START */ 4455 /* Description: Subscribe configuration for task START */ 4456 4457 /* Bit 31 : */ 4458 #define RNG_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 4459 #define RNG_SUBSCRIBE_START_EN_Msk (0x1UL << RNG_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 4460 #define RNG_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 4461 #define RNG_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 4462 4463 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 4464 #define RNG_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4465 #define RNG_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4466 4467 /* Register: RNG_SUBSCRIBE_STOP */ 4468 /* Description: Subscribe configuration for task STOP */ 4469 4470 /* Bit 31 : */ 4471 #define RNG_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 4472 #define RNG_SUBSCRIBE_STOP_EN_Msk (0x1UL << RNG_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 4473 #define RNG_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 4474 #define RNG_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 4475 4476 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 4477 #define RNG_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4478 #define RNG_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4479 4480 /* Register: RNG_EVENTS_VALRDY */ 4481 /* Description: Event being generated for every new random number written to the VALUE register */ 4482 4483 /* Bit 0 : Event being generated for every new random number written to the VALUE register */ 4484 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ 4485 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ 4486 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */ 4487 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */ 4488 4489 /* Register: RNG_PUBLISH_VALRDY */ 4490 /* Description: Publish configuration for event VALRDY */ 4491 4492 /* Bit 31 : */ 4493 #define RNG_PUBLISH_VALRDY_EN_Pos (31UL) /*!< Position of EN field. */ 4494 #define RNG_PUBLISH_VALRDY_EN_Msk (0x1UL << RNG_PUBLISH_VALRDY_EN_Pos) /*!< Bit mask of EN field. */ 4495 #define RNG_PUBLISH_VALRDY_EN_Disabled (0UL) /*!< Disable publishing */ 4496 #define RNG_PUBLISH_VALRDY_EN_Enabled (1UL) /*!< Enable publishing */ 4497 4498 /* Bits 7..0 : DPPI channel that event VALRDY will publish to. */ 4499 #define RNG_PUBLISH_VALRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4500 #define RNG_PUBLISH_VALRDY_CHIDX_Msk (0xFFUL << RNG_PUBLISH_VALRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4501 4502 /* Register: RNG_SHORTS */ 4503 /* Description: Shortcuts between local events and tasks */ 4504 4505 /* Bit 0 : Shortcut between event VALRDY and task STOP */ 4506 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ 4507 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ 4508 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 4509 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 4510 4511 /* Register: RNG_INTENSET */ 4512 /* Description: Enable interrupt */ 4513 4514 /* Bit 0 : Write '1' to enable interrupt for event VALRDY */ 4515 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 4516 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 4517 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ 4518 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ 4519 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ 4520 4521 /* Register: RNG_INTENCLR */ 4522 /* Description: Disable interrupt */ 4523 4524 /* Bit 0 : Write '1' to disable interrupt for event VALRDY */ 4525 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 4526 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 4527 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ 4528 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ 4529 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ 4530 4531 /* Register: RNG_CONFIG */ 4532 /* Description: Configuration register */ 4533 4534 /* Bit 0 : Bias correction */ 4535 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ 4536 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ 4537 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ 4538 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ 4539 4540 /* Register: RNG_VALUE */ 4541 /* Description: Output random number */ 4542 4543 /* Bits 7..0 : Generated random number */ 4544 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 4545 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ 4546 4547 /* =========================================================================================================================== */ 4548 /* ================ RTC ================ */ 4549 /* =========================================================================================================================== */ 4550 4551 4552 /** 4553 * @brief Real-time counter 0 (RTC0_NS) 4554 */ 4555 4556 typedef struct { /*!< (@ 0x41011000) RTC0_NS Structure */ 4557 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 4558 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 4559 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 4560 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 4561 __IM uint32_t RESERVED[12]; 4562 __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Description collection: Capture RTC counter to 4563 CC[n] register */ 4564 __IM uint32_t RESERVED1[12]; 4565 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 4566 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 4567 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 4568 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 4569 __IM uint32_t RESERVED2[12]; 4570 __IOM uint32_t SUBSCRIBE_CAPTURE[4]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 4571 for task CAPTURE[n] */ 4572 __IM uint32_t RESERVED3[12]; 4573 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 4574 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 4575 __IM uint32_t RESERVED4[14]; 4576 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 4577 match */ 4578 __IM uint32_t RESERVED5[12]; 4579 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 4580 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 4581 __IM uint32_t RESERVED6[14]; 4582 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 4583 for event COMPARE[n] */ 4584 __IM uint32_t RESERVED7[12]; 4585 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 4586 __IM uint32_t RESERVED8[64]; 4587 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 4588 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 4589 __IM uint32_t RESERVED9[13]; 4590 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 4591 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 4592 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 4593 __IM uint32_t RESERVED10[110]; 4594 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 4595 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768 4596 / (PRESCALER + 1)). Must be written when 4597 RTC is stopped. */ 4598 __IM uint32_t RESERVED11[13]; 4599 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 4600 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 4601 4602 4603 /* Peripheral: RTC */ 4604 /* Description: Real-time counter 0 */ 4605 4606 /* Register: RTC_TASKS_START */ 4607 /* Description: Start RTC counter */ 4608 4609 /* Bit 0 : Start RTC counter */ 4610 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 4611 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 4612 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 4613 4614 /* Register: RTC_TASKS_STOP */ 4615 /* Description: Stop RTC counter */ 4616 4617 /* Bit 0 : Stop RTC counter */ 4618 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 4619 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 4620 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 4621 4622 /* Register: RTC_TASKS_CLEAR */ 4623 /* Description: Clear RTC counter */ 4624 4625 /* Bit 0 : Clear RTC counter */ 4626 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 4627 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 4628 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ 4629 4630 /* Register: RTC_TASKS_TRIGOVRFLW */ 4631 /* Description: Set counter to 0xFFFFF0 */ 4632 4633 /* Bit 0 : Set counter to 0xFFFFF0 */ 4634 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ 4635 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ 4636 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ 4637 4638 /* Register: RTC_TASKS_CAPTURE */ 4639 /* Description: Description collection: Capture RTC counter to CC[n] register */ 4640 4641 /* Bit 0 : Capture RTC counter to CC[n] register */ 4642 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ 4643 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ 4644 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ 4645 4646 /* Register: RTC_SUBSCRIBE_START */ 4647 /* Description: Subscribe configuration for task START */ 4648 4649 /* Bit 31 : */ 4650 #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 4651 #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 4652 #define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 4653 #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 4654 4655 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 4656 #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4657 #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4658 4659 /* Register: RTC_SUBSCRIBE_STOP */ 4660 /* Description: Subscribe configuration for task STOP */ 4661 4662 /* Bit 31 : */ 4663 #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 4664 #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 4665 #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 4666 #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 4667 4668 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 4669 #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4670 #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4671 4672 /* Register: RTC_SUBSCRIBE_CLEAR */ 4673 /* Description: Subscribe configuration for task CLEAR */ 4674 4675 /* Bit 31 : */ 4676 #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ 4677 #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ 4678 #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ 4679 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ 4680 4681 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ 4682 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4683 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4684 4685 /* Register: RTC_SUBSCRIBE_TRIGOVRFLW */ 4686 /* Description: Subscribe configuration for task TRIGOVRFLW */ 4687 4688 /* Bit 31 : */ 4689 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ 4690 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */ 4691 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */ 4692 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */ 4693 4694 /* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */ 4695 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4696 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4697 4698 /* Register: RTC_SUBSCRIBE_CAPTURE */ 4699 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */ 4700 4701 /* Bit 31 : */ 4702 #define RTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ 4703 #define RTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << RTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ 4704 #define RTC_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */ 4705 #define RTC_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */ 4706 4707 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */ 4708 #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4709 #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4710 4711 /* Register: RTC_EVENTS_TICK */ 4712 /* Description: Event on counter increment */ 4713 4714 /* Bit 0 : Event on counter increment */ 4715 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ 4716 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ 4717 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ 4718 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ 4719 4720 /* Register: RTC_EVENTS_OVRFLW */ 4721 /* Description: Event on counter overflow */ 4722 4723 /* Bit 0 : Event on counter overflow */ 4724 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ 4725 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ 4726 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ 4727 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ 4728 4729 /* Register: RTC_EVENTS_COMPARE */ 4730 /* Description: Description collection: Compare event on CC[n] match */ 4731 4732 /* Bit 0 : Compare event on CC[n] match */ 4733 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 4734 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 4735 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ 4736 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ 4737 4738 /* Register: RTC_PUBLISH_TICK */ 4739 /* Description: Publish configuration for event TICK */ 4740 4741 /* Bit 31 : */ 4742 #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */ 4743 #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */ 4744 #define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */ 4745 #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */ 4746 4747 /* Bits 7..0 : DPPI channel that event TICK will publish to. */ 4748 #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4749 #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4750 4751 /* Register: RTC_PUBLISH_OVRFLW */ 4752 /* Description: Publish configuration for event OVRFLW */ 4753 4754 /* Bit 31 : */ 4755 #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ 4756 #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */ 4757 #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */ 4758 #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */ 4759 4760 /* Bits 7..0 : DPPI channel that event OVRFLW will publish to. */ 4761 #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4762 #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4763 4764 /* Register: RTC_PUBLISH_COMPARE */ 4765 /* Description: Description collection: Publish configuration for event COMPARE[n] */ 4766 4767 /* Bit 31 : */ 4768 #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ 4769 #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ 4770 #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ 4771 #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ 4772 4773 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */ 4774 #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4775 #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4776 4777 /* Register: RTC_SHORTS */ 4778 /* Description: Shortcuts between local events and tasks */ 4779 4780 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ 4781 #define RTC_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ 4782 #define RTC_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ 4783 #define RTC_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 4784 #define RTC_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 4785 4786 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ 4787 #define RTC_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 4788 #define RTC_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 4789 #define RTC_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 4790 #define RTC_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 4791 4792 /* Register: RTC_INTENSET */ 4793 /* Description: Enable interrupt */ 4794 4795 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ 4796 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4797 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4798 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 4799 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 4800 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ 4801 4802 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ 4803 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4804 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4805 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 4806 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 4807 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 4808 4809 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ 4810 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4811 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4812 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 4813 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 4814 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ 4815 4816 /* Bit 0 : Write '1' to enable interrupt for event TICK */ 4817 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 4818 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 4819 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 4820 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 4821 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ 4822 4823 /* Register: RTC_INTENCLR */ 4824 /* Description: Disable interrupt */ 4825 4826 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ 4827 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4828 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4829 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 4830 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 4831 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 4832 4833 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ 4834 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4835 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4836 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 4837 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 4838 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 4839 4840 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ 4841 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4842 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4843 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 4844 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 4845 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 4846 4847 /* Bit 0 : Write '1' to disable interrupt for event TICK */ 4848 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 4849 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 4850 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 4851 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 4852 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ 4853 4854 /* Register: RTC_EVTEN */ 4855 /* Description: Enable or disable event routing */ 4856 4857 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */ 4858 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4859 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4860 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ 4861 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ 4862 4863 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */ 4864 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4865 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4866 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ 4867 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ 4868 4869 /* Bit 1 : Enable or disable event routing for event OVRFLW */ 4870 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4871 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4872 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ 4873 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ 4874 4875 /* Bit 0 : Enable or disable event routing for event TICK */ 4876 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ 4877 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ 4878 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ 4879 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ 4880 4881 /* Register: RTC_EVTENSET */ 4882 /* Description: Enable event routing */ 4883 4884 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ 4885 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4886 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4887 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 4888 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 4889 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ 4890 4891 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ 4892 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4893 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4894 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 4895 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 4896 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ 4897 4898 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */ 4899 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4900 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4901 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 4902 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 4903 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ 4904 4905 /* Bit 0 : Write '1' to enable event routing for event TICK */ 4906 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 4907 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 4908 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 4909 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 4910 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ 4911 4912 /* Register: RTC_EVTENCLR */ 4913 /* Description: Disable event routing */ 4914 4915 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ 4916 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4917 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4918 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 4919 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 4920 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 4921 4922 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ 4923 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4924 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4925 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 4926 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 4927 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 4928 4929 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */ 4930 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4931 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4932 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 4933 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 4934 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 4935 4936 /* Bit 0 : Write '1' to disable event routing for event TICK */ 4937 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 4938 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 4939 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 4940 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 4941 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ 4942 4943 /* Register: RTC_COUNTER */ 4944 /* Description: Current counter value */ 4945 4946 /* Bits 23..0 : Counter value */ 4947 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ 4948 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ 4949 4950 /* Register: RTC_PRESCALER */ 4951 /* Description: 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. */ 4952 4953 /* Bits 11..0 : Prescaler value */ 4954 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 4955 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 4956 4957 /* Register: RTC_CC */ 4958 /* Description: Description collection: Compare register n */ 4959 4960 /* Bits 23..0 : Compare value */ 4961 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ 4962 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ 4963 4964 4965 /* =========================================================================================================================== */ 4966 /* ================ TEMP ================ */ 4967 /* =========================================================================================================================== */ 4968 4969 4970 /** 4971 * @brief Temperature Sensor (TEMP) 4972 */ 4973 4974 typedef struct { /*!< (@ 0x41010000) TEMP_NS Structure */ 4975 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 4976 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 4977 __IM uint32_t RESERVED[30]; 4978 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 4979 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 4980 __IM uint32_t RESERVED1[30]; 4981 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 4982 __IM uint32_t RESERVED2[31]; 4983 __IOM uint32_t PUBLISH_DATARDY; /*!< (@ 0x00000180) Publish configuration for event DATARDY */ 4984 __IM uint32_t RESERVED3[96]; 4985 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 4986 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 4987 __IM uint32_t RESERVED4[127]; 4988 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 4989 __IM uint32_t RESERVED5[5]; 4990 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ 4991 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ 4992 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ 4993 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ 4994 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ 4995 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ 4996 __IM uint32_t RESERVED6[2]; 4997 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ 4998 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ 4999 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ 5000 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ 5001 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ 5002 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ 5003 __IM uint32_t RESERVED7[2]; 5004 __IOM uint32_t T0; /*!< (@ 0x00000560) Endpoint of first piecewise linear function */ 5005 __IOM uint32_t T1; /*!< (@ 0x00000564) Endpoint of second piecewise linear function */ 5006 __IOM uint32_t T2; /*!< (@ 0x00000568) Endpoint of third piecewise linear function */ 5007 __IOM uint32_t T3; /*!< (@ 0x0000056C) Endpoint of fourth piecewise linear function */ 5008 __IOM uint32_t T4; /*!< (@ 0x00000570) Endpoint of fifth piecewise linear function */ 5009 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 5010 5011 5012 /* Peripheral: TEMP */ 5013 /* Description: Temperature Sensor */ 5014 5015 /* Register: TEMP_TASKS_START */ 5016 /* Description: Start temperature measurement */ 5017 5018 /* Bit 0 : Start temperature measurement */ 5019 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 5020 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 5021 #define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 5022 5023 /* Register: TEMP_TASKS_STOP */ 5024 /* Description: Stop temperature measurement */ 5025 5026 /* Bit 0 : Stop temperature measurement */ 5027 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 5028 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 5029 #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 5030 5031 /* Register: TEMP_SUBSCRIBE_START */ 5032 /* Description: Subscribe configuration for task START */ 5033 5034 /* Bit 31 : */ 5035 #define TEMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 5036 #define TEMP_SUBSCRIBE_START_EN_Msk (0x1UL << TEMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 5037 #define TEMP_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 5038 #define TEMP_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 5039 5040 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 5041 #define TEMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5042 #define TEMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5043 5044 /* Register: TEMP_SUBSCRIBE_STOP */ 5045 /* Description: Subscribe configuration for task STOP */ 5046 5047 /* Bit 31 : */ 5048 #define TEMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 5049 #define TEMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << TEMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 5050 #define TEMP_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 5051 #define TEMP_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 5052 5053 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 5054 #define TEMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5055 #define TEMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5056 5057 /* Register: TEMP_EVENTS_DATARDY */ 5058 /* Description: Temperature measurement complete, data ready */ 5059 5060 /* Bit 0 : Temperature measurement complete, data ready */ 5061 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ 5062 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ 5063 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */ 5064 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */ 5065 5066 /* Register: TEMP_PUBLISH_DATARDY */ 5067 /* Description: Publish configuration for event DATARDY */ 5068 5069 /* Bit 31 : */ 5070 #define TEMP_PUBLISH_DATARDY_EN_Pos (31UL) /*!< Position of EN field. */ 5071 #define TEMP_PUBLISH_DATARDY_EN_Msk (0x1UL << TEMP_PUBLISH_DATARDY_EN_Pos) /*!< Bit mask of EN field. */ 5072 #define TEMP_PUBLISH_DATARDY_EN_Disabled (0UL) /*!< Disable publishing */ 5073 #define TEMP_PUBLISH_DATARDY_EN_Enabled (1UL) /*!< Enable publishing */ 5074 5075 /* Bits 7..0 : DPPI channel that event DATARDY will publish to. */ 5076 #define TEMP_PUBLISH_DATARDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5077 #define TEMP_PUBLISH_DATARDY_CHIDX_Msk (0xFFUL << TEMP_PUBLISH_DATARDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5078 5079 /* Register: TEMP_INTENSET */ 5080 /* Description: Enable interrupt */ 5081 5082 /* Bit 0 : Write '1' to enable interrupt for event DATARDY */ 5083 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 5084 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 5085 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ 5086 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ 5087 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ 5088 5089 /* Register: TEMP_INTENCLR */ 5090 /* Description: Disable interrupt */ 5091 5092 /* Bit 0 : Write '1' to disable interrupt for event DATARDY */ 5093 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 5094 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 5095 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ 5096 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ 5097 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ 5098 5099 /* Register: TEMP_TEMP */ 5100 /* Description: Temperature in degC (0.25deg steps) */ 5101 5102 /* Bits 31..0 : Temperature in degC (0.25deg steps) */ 5103 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ 5104 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ 5105 5106 /* Register: TEMP_A0 */ 5107 /* Description: Slope of first piecewise linear function */ 5108 5109 /* Bits 11..0 : Slope of first piecewise linear function */ 5110 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ 5111 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ 5112 5113 /* Register: TEMP_A1 */ 5114 /* Description: Slope of second piecewise linear function */ 5115 5116 /* Bits 11..0 : Slope of second piecewise linear function */ 5117 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ 5118 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ 5119 5120 /* Register: TEMP_A2 */ 5121 /* Description: Slope of third piecewise linear function */ 5122 5123 /* Bits 11..0 : Slope of third piecewise linear function */ 5124 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ 5125 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ 5126 5127 /* Register: TEMP_A3 */ 5128 /* Description: Slope of fourth piecewise linear function */ 5129 5130 /* Bits 11..0 : Slope of fourth piecewise linear function */ 5131 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ 5132 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ 5133 5134 /* Register: TEMP_A4 */ 5135 /* Description: Slope of fifth piecewise linear function */ 5136 5137 /* Bits 11..0 : Slope of fifth piecewise linear function */ 5138 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ 5139 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ 5140 5141 /* Register: TEMP_A5 */ 5142 /* Description: Slope of sixth piecewise linear function */ 5143 5144 /* Bits 11..0 : Slope of sixth piecewise linear function */ 5145 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ 5146 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ 5147 5148 /* Register: TEMP_B0 */ 5149 /* Description: y-intercept of first piecewise linear function */ 5150 5151 /* Bits 11..0 : y-intercept of first piecewise linear function */ 5152 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ 5153 #define TEMP_B0_B0_Msk (0xFFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ 5154 5155 /* Register: TEMP_B1 */ 5156 /* Description: y-intercept of second piecewise linear function */ 5157 5158 /* Bits 11..0 : y-intercept of second piecewise linear function */ 5159 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ 5160 #define TEMP_B1_B1_Msk (0xFFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ 5161 5162 /* Register: TEMP_B2 */ 5163 /* Description: y-intercept of third piecewise linear function */ 5164 5165 /* Bits 11..0 : y-intercept of third piecewise linear function */ 5166 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ 5167 #define TEMP_B2_B2_Msk (0xFFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ 5168 5169 /* Register: TEMP_B3 */ 5170 /* Description: y-intercept of fourth piecewise linear function */ 5171 5172 /* Bits 11..0 : y-intercept of fourth piecewise linear function */ 5173 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ 5174 #define TEMP_B3_B3_Msk (0xFFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ 5175 5176 /* Register: TEMP_B4 */ 5177 /* Description: y-intercept of fifth piecewise linear function */ 5178 5179 /* Bits 11..0 : y-intercept of fifth piecewise linear function */ 5180 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ 5181 #define TEMP_B4_B4_Msk (0xFFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ 5182 5183 /* Register: TEMP_B5 */ 5184 /* Description: y-intercept of sixth piecewise linear function */ 5185 5186 /* Bits 11..0 : y-intercept of sixth piecewise linear function */ 5187 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ 5188 #define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ 5189 5190 /* Register: TEMP_T0 */ 5191 /* Description: Endpoint of first piecewise linear function */ 5192 5193 /* Bits 7..0 : Endpoint of first piecewise linear function */ 5194 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ 5195 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ 5196 5197 /* Register: TEMP_T1 */ 5198 /* Description: Endpoint of second piecewise linear function */ 5199 5200 /* Bits 7..0 : Endpoint of second piecewise linear function */ 5201 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ 5202 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ 5203 5204 /* Register: TEMP_T2 */ 5205 /* Description: Endpoint of third piecewise linear function */ 5206 5207 /* Bits 7..0 : Endpoint of third piecewise linear function */ 5208 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ 5209 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ 5210 5211 /* Register: TEMP_T3 */ 5212 /* Description: Endpoint of fourth piecewise linear function */ 5213 5214 /* Bits 7..0 : Endpoint of fourth piecewise linear function */ 5215 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ 5216 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ 5217 5218 /* Register: TEMP_T4 */ 5219 /* Description: Endpoint of fifth piecewise linear function */ 5220 5221 /* Bits 7..0 : Endpoint of fifth piecewise linear function */ 5222 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ 5223 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ 5224 5225 5226 5227 /* =========================================================================================================================== */ 5228 /* ================ TIMER ================ */ 5229 /* =========================================================================================================================== */ 5230 5231 5232 /** 5233 * @brief Timer/Counter 0 (TIMER0_NS) 5234 */ 5235 5236 typedef struct { /*!< (@ 0x4100C000) TIMER0_NS Structure */ 5237 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 5238 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 5239 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 5240 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 5241 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 5242 __IM uint32_t RESERVED[11]; 5243 __OM uint32_t TASKS_CAPTURE[8]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 5244 CC[n] register */ 5245 __IM uint32_t RESERVED1[8]; 5246 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 5247 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 5248 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 5249 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 5250 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 5251 for task SHUTDOWN */ 5252 __IM uint32_t RESERVED2[11]; 5253 __IOM uint32_t SUBSCRIBE_CAPTURE[8]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 5254 for task CAPTURE[n] */ 5255 __IM uint32_t RESERVED3[24]; 5256 __IOM uint32_t EVENTS_COMPARE[8]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 5257 match */ 5258 __IM uint32_t RESERVED4[24]; 5259 __IOM uint32_t PUBLISH_COMPARE[8]; /*!< (@ 0x000001C0) Description collection: Publish configuration 5260 for event COMPARE[n] */ 5261 __IM uint32_t RESERVED5[8]; 5262 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 5263 __IM uint32_t RESERVED6[63]; 5264 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 5265 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 5266 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 5267 __IM uint32_t RESERVED7[126]; 5268 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 5269 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 5270 __IM uint32_t RESERVED8; 5271 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 5272 __IM uint32_t RESERVED9[11]; 5273 __IOM uint32_t CC[8]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 5274 n */ 5275 __IM uint32_t RESERVED10[8]; 5276 __IOM uint32_t ONESHOTEN[8]; /*!< (@ 0x00000580) Description collection: Enable one-shot operation 5277 for Capture/Compare channel n */ 5278 } NRF_TIMER_Type; /*!< Size = 1440 (0x5a0) */ 5279 5280 5281 /* Peripheral: TIMER */ 5282 /* Description: Timer/Counter 0 */ 5283 5284 /* Register: TIMER_TASKS_START */ 5285 /* Description: Start Timer */ 5286 5287 /* Bit 0 : Start Timer */ 5288 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 5289 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 5290 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 5291 5292 /* Register: TIMER_TASKS_STOP */ 5293 /* Description: Stop Timer */ 5294 5295 /* Bit 0 : Stop Timer */ 5296 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 5297 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 5298 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 5299 5300 /* Register: TIMER_TASKS_COUNT */ 5301 /* Description: Increment Timer (Counter mode only) */ 5302 5303 /* Bit 0 : Increment Timer (Counter mode only) */ 5304 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ 5305 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ 5306 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ 5307 5308 /* Register: TIMER_TASKS_CLEAR */ 5309 /* Description: Clear time */ 5310 5311 /* Bit 0 : Clear time */ 5312 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 5313 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 5314 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ 5315 5316 /* Register: TIMER_TASKS_SHUTDOWN */ 5317 /* Description: Deprecated register - Shut down timer */ 5318 5319 /* Bit 0 : Deprecated field - Shut down timer */ 5320 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ 5321 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ 5322 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ 5323 5324 /* Register: TIMER_TASKS_CAPTURE */ 5325 /* Description: Description collection: Capture Timer value to CC[n] register */ 5326 5327 /* Bit 0 : Capture Timer value to CC[n] register */ 5328 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ 5329 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ 5330 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ 5331 5332 /* Register: TIMER_SUBSCRIBE_START */ 5333 /* Description: Subscribe configuration for task START */ 5334 5335 /* Bit 31 : */ 5336 #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 5337 #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 5338 #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 5339 #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 5340 5341 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 5342 #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5343 #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5344 5345 /* Register: TIMER_SUBSCRIBE_STOP */ 5346 /* Description: Subscribe configuration for task STOP */ 5347 5348 /* Bit 31 : */ 5349 #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 5350 #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 5351 #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 5352 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 5353 5354 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 5355 #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5356 #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5357 5358 /* Register: TIMER_SUBSCRIBE_COUNT */ 5359 /* Description: Subscribe configuration for task COUNT */ 5360 5361 /* Bit 31 : */ 5362 #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */ 5363 #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */ 5364 #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */ 5365 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */ 5366 5367 /* Bits 7..0 : DPPI channel that task COUNT will subscribe to */ 5368 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5369 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5370 5371 /* Register: TIMER_SUBSCRIBE_CLEAR */ 5372 /* Description: Subscribe configuration for task CLEAR */ 5373 5374 /* Bit 31 : */ 5375 #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ 5376 #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ 5377 #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ 5378 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ 5379 5380 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ 5381 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5382 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5383 5384 /* Register: TIMER_SUBSCRIBE_SHUTDOWN */ 5385 /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */ 5386 5387 /* Bit 31 : */ 5388 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */ 5389 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */ 5390 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */ 5391 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */ 5392 5393 /* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */ 5394 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5395 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5396 5397 /* Register: TIMER_SUBSCRIBE_CAPTURE */ 5398 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */ 5399 5400 /* Bit 31 : */ 5401 #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ 5402 #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ 5403 #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */ 5404 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */ 5405 5406 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */ 5407 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5408 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5409 5410 /* Register: TIMER_EVENTS_COMPARE */ 5411 /* Description: Description collection: Compare event on CC[n] match */ 5412 5413 /* Bit 0 : Compare event on CC[n] match */ 5414 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 5415 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 5416 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ 5417 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ 5418 5419 /* Register: TIMER_PUBLISH_COMPARE */ 5420 /* Description: Description collection: Publish configuration for event COMPARE[n] */ 5421 5422 /* Bit 31 : */ 5423 #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ 5424 #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ 5425 #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ 5426 #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ 5427 5428 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */ 5429 #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5430 #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5431 5432 /* Register: TIMER_SHORTS */ 5433 /* Description: Shortcuts between local events and tasks */ 5434 5435 /* Bit 23 : Shortcut between event COMPARE[7] and task STOP */ 5436 #define TIMER_SHORTS_COMPARE7_STOP_Pos (23UL) /*!< Position of COMPARE7_STOP field. */ 5437 #define TIMER_SHORTS_COMPARE7_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE7_STOP_Pos) /*!< Bit mask of COMPARE7_STOP field. */ 5438 #define TIMER_SHORTS_COMPARE7_STOP_Disabled (0UL) /*!< Disable shortcut */ 5439 #define TIMER_SHORTS_COMPARE7_STOP_Enabled (1UL) /*!< Enable shortcut */ 5440 5441 /* Bit 16 : Shortcut between event COMPARE[0] and task STOP */ 5442 #define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL) /*!< Position of COMPARE0_STOP field. */ 5443 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ 5444 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ 5445 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ 5446 5447 /* Bit 7 : Shortcut between event COMPARE[7] and task CLEAR */ 5448 #define TIMER_SHORTS_COMPARE7_CLEAR_Pos (7UL) /*!< Position of COMPARE7_CLEAR field. */ 5449 #define TIMER_SHORTS_COMPARE7_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE7_CLEAR_Pos) /*!< Bit mask of COMPARE7_CLEAR field. */ 5450 #define TIMER_SHORTS_COMPARE7_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 5451 #define TIMER_SHORTS_COMPARE7_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 5452 5453 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ 5454 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 5455 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 5456 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 5457 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 5458 5459 /* Register: TIMER_INTEN */ 5460 /* Description: Enable or disable interrupt */ 5461 5462 /* Bit 23 : Enable or disable interrupt for event COMPARE[7] */ 5463 #define TIMER_INTEN_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ 5464 #define TIMER_INTEN_COMPARE7_Msk (0x1UL << TIMER_INTEN_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ 5465 #define TIMER_INTEN_COMPARE7_Disabled (0UL) /*!< Disable */ 5466 #define TIMER_INTEN_COMPARE7_Enabled (1UL) /*!< Enable */ 5467 5468 /* Bit 16 : Enable or disable interrupt for event COMPARE[0] */ 5469 #define TIMER_INTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5470 #define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5471 #define TIMER_INTEN_COMPARE0_Disabled (0UL) /*!< Disable */ 5472 #define TIMER_INTEN_COMPARE0_Enabled (1UL) /*!< Enable */ 5473 5474 /* Register: TIMER_INTENSET */ 5475 /* Description: Enable interrupt */ 5476 5477 /* Bit 23 : Write '1' to enable interrupt for event COMPARE[7] */ 5478 #define TIMER_INTENSET_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ 5479 #define TIMER_INTENSET_COMPARE7_Msk (0x1UL << TIMER_INTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ 5480 #define TIMER_INTENSET_COMPARE7_Disabled (0UL) /*!< Read: Disabled */ 5481 #define TIMER_INTENSET_COMPARE7_Enabled (1UL) /*!< Read: Enabled */ 5482 #define TIMER_INTENSET_COMPARE7_Set (1UL) /*!< Enable */ 5483 5484 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ 5485 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5486 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5487 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 5488 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 5489 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 5490 5491 /* Register: TIMER_INTENCLR */ 5492 /* Description: Disable interrupt */ 5493 5494 /* Bit 23 : Write '1' to disable interrupt for event COMPARE[7] */ 5495 #define TIMER_INTENCLR_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ 5496 #define TIMER_INTENCLR_COMPARE7_Msk (0x1UL << TIMER_INTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ 5497 #define TIMER_INTENCLR_COMPARE7_Disabled (0UL) /*!< Read: Disabled */ 5498 #define TIMER_INTENCLR_COMPARE7_Enabled (1UL) /*!< Read: Enabled */ 5499 #define TIMER_INTENCLR_COMPARE7_Clear (1UL) /*!< Disable */ 5500 5501 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ 5502 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5503 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5504 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 5505 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 5506 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 5507 5508 /* Register: TIMER_MODE */ 5509 /* Description: Timer mode selection */ 5510 5511 /* Bits 1..0 : Timer mode */ 5512 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 5513 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 5514 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ 5515 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ 5516 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ 5517 5518 /* Register: TIMER_BITMODE */ 5519 /* Description: Configure the number of bits used by the TIMER */ 5520 5521 /* Bits 1..0 : Timer bit width */ 5522 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ 5523 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ 5524 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ 5525 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ 5526 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ 5527 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ 5528 5529 /* Register: TIMER_PRESCALER */ 5530 /* Description: Timer prescaler register */ 5531 5532 /* Bits 3..0 : Prescaler value */ 5533 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 5534 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 5535 5536 /* Register: TIMER_CC */ 5537 /* Description: Description collection: Capture/Compare register n */ 5538 5539 /* Bits 31..0 : Capture/Compare value */ 5540 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ 5541 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ 5542 5543 /* Register: TIMER_ONESHOTEN */ 5544 /* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */ 5545 5546 /* Bit 0 : Enable one-shot operation */ 5547 #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */ 5548 #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */ 5549 #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL) /*!< Disable one-shot operation */ 5550 #define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL) /*!< Enable one-shot operation */ 5551 5552 5553 /* =========================================================================================================================== */ 5554 /* ================ UART0 ================ */ 5555 /* =========================================================================================================================== */ 5556 5557 /** 5558 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 5559 */ 5560 5561 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 5562 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 5563 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 5564 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 5565 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 5566 __IM uint32_t RESERVED[3]; 5567 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 5568 __IM uint32_t RESERVED1[56]; 5569 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 5570 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 5571 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 5572 __IM uint32_t RESERVED2[4]; 5573 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 5574 __IM uint32_t RESERVED3; 5575 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 5576 __IM uint32_t RESERVED4[7]; 5577 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 5578 __IM uint32_t RESERVED5[46]; 5579 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 5580 __IM uint32_t RESERVED6[64]; 5581 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 5582 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 5583 __IM uint32_t RESERVED7[93]; 5584 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 5585 __IM uint32_t RESERVED8[31]; 5586 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 5587 __IM uint32_t RESERVED9; 5588 __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 5589 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 5590 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 5591 __IM uint32_t RESERVED10; 5592 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 5593 selected. */ 5594 __IM uint32_t RESERVED11[17]; 5595 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 5596 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 5597 5598 5599 /* Peripheral: UART */ 5600 /* Description: Universal Asynchronous Receiver/Transmitter */ 5601 5602 /* Register: UART_SHORTS */ 5603 /* Description: Shortcuts between local events and tasks */ 5604 5605 /* Bit 4 : Shortcut between event NCTS and task STOPRX */ 5606 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ 5607 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ 5608 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ 5609 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ 5610 5611 /* Bit 3 : Shortcut between event CTS and task STARTRX */ 5612 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ 5613 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ 5614 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 5615 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 5616 5617 /* Register: UART_ERRORSRC */ 5618 /* Description: Error source */ 5619 5620 /* Bit 3 : Break condition */ 5621 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 5622 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 5623 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ 5624 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ 5625 5626 /* Bit 2 : Framing error occurred */ 5627 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 5628 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 5629 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ 5630 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ 5631 5632 /* Bit 1 : Parity error */ 5633 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 5634 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 5635 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ 5636 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ 5637 5638 /* Bit 0 : Overrun error */ 5639 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 5640 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 5641 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ 5642 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ 5643 5644 /* Register: UART_ENABLE */ 5645 /* Description: Enable UART */ 5646 5647 /* Bits 3..0 : Enable or disable UART */ 5648 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 5649 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 5650 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ 5651 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ 5652 5653 /* Register: UART_PSEL_RTS */ 5654 /* Description: Pin select for RTS */ 5655 5656 /* Bit 31 : Connection */ 5657 #define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 5658 #define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 5659 #define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ 5660 #define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 5661 5662 /* Bit 5 : Port number */ 5663 #define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ 5664 #define UART_PSEL_RTS_PORT_Msk (0x1UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ 5665 5666 /* Bits 4..0 : Pin number */ 5667 #define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 5668 #define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ 5669 5670 /* Register: UART_PSEL_TXD */ 5671 /* Description: Pin select for TXD */ 5672 5673 /* Bit 31 : Connection */ 5674 #define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 5675 #define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 5676 #define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ 5677 #define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 5678 5679 /* Bit 5 : Port number */ 5680 #define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ 5681 #define UART_PSEL_TXD_PORT_Msk (0x1UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ 5682 5683 /* Bits 4..0 : Pin number */ 5684 #define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 5685 #define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ 5686 5687 /* Register: UART_PSEL_CTS */ 5688 /* Description: Pin select for CTS */ 5689 5690 /* Bit 31 : Connection */ 5691 #define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 5692 #define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 5693 #define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ 5694 #define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 5695 5696 /* Bit 5 : Port number */ 5697 #define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ 5698 #define UART_PSEL_CTS_PORT_Msk (0x1UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ 5699 5700 /* Bits 4..0 : Pin number */ 5701 #define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 5702 #define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ 5703 5704 /* Register: UART_PSEL_RXD */ 5705 /* Description: Pin select for RXD */ 5706 5707 /* Bit 31 : Connection */ 5708 #define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 5709 #define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 5710 #define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ 5711 #define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 5712 5713 /* Bit 5 : Port number */ 5714 #define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ 5715 #define UART_PSEL_RXD_PORT_Msk (0x1UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ 5716 5717 /* Bits 4..0 : Pin number */ 5718 #define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 5719 #define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ 5720 5721 /* Register: UART_RXD */ 5722 /* Description: RXD register */ 5723 5724 /* Bits 7..0 : RX data received in previous transfers, double buffered */ 5725 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 5726 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 5727 5728 /* Register: UART_TXD */ 5729 /* Description: TXD register */ 5730 5731 /* Bits 7..0 : TX data to be transferred */ 5732 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 5733 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 5734 5735 /* Register: UART_BAUDRATE */ 5736 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ 5737 5738 /* Bits 31..0 : Baud rate */ 5739 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 5740 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 5741 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ 5742 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ 5743 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ 5744 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ 5745 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ 5746 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ 5747 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ 5748 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ 5749 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ 5750 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ 5751 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ 5752 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ 5753 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ 5754 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ 5755 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ 5756 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ 5757 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ 5758 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ 5759 5760 /* Register: UART_CONFIG */ 5761 /* Description: Configuration of parity and hardware flow control */ 5762 5763 /* Bit 8 : Even or odd parity type */ 5764 #define UART_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */ 5765 #define UART_CONFIG_PARITYTYPE_Msk (0x1UL << UART_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */ 5766 #define UART_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */ 5767 #define UART_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */ 5768 5769 /* Bit 4 : Stop bits */ 5770 #define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ 5771 #define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ 5772 #define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */ 5773 #define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ 5774 5775 /* Bits 3..1 : Parity */ 5776 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 5777 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 5778 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ 5779 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ 5780 5781 /* Bit 0 : Hardware flow control */ 5782 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 5783 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 5784 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ 5785 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ 5786 5787 5788 /* =========================================================================================================================== */ 5789 /* ================ UARTE0_NS ================ */ 5790 /* =========================================================================================================================== */ 5791 5792 5793 /** 5794 * @brief UART with EasyDMA 0 (UARTE0_NS) 5795 */ 5796 5797 typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */ 5798 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 5799 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 5800 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 5801 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 5802 __IM uint32_t RESERVED[7]; 5803 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 5804 __IM uint32_t RESERVED1[20]; 5805 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 5806 __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 5807 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 5808 __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 5809 __IM uint32_t RESERVED2[7]; 5810 __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 5811 __IM uint32_t RESERVED3[20]; 5812 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 5813 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 5814 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 5815 transferred to Data RAM) */ 5816 __IM uint32_t RESERVED4; 5817 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 5818 __IM uint32_t RESERVED5[2]; 5819 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 5820 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 5821 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 5822 __IM uint32_t RESERVED6[7]; 5823 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 5824 __IM uint32_t RESERVED7; 5825 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 5826 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 5827 __IM uint32_t RESERVED8; 5828 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 5829 __IM uint32_t RESERVED9[9]; 5830 __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 5831 __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 5832 __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 5833 __IM uint32_t RESERVED10; 5834 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 5835 __IM uint32_t RESERVED11[2]; 5836 __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 5837 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 5838 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 5839 __IM uint32_t RESERVED12[7]; 5840 __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 5841 __IM uint32_t RESERVED13; 5842 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 5843 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 5844 __IM uint32_t RESERVED14; 5845 __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 5846 __IM uint32_t RESERVED15[9]; 5847 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 5848 __IM uint32_t RESERVED16[63]; 5849 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 5850 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 5851 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 5852 __IM uint32_t RESERVED17[93]; 5853 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 5854 __IM uint32_t RESERVED18[31]; 5855 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 5856 __IM uint32_t RESERVED19; 5857 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 5858 __IM uint32_t RESERVED20[3]; 5859 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 5860 selected. */ 5861 __IM uint32_t RESERVED21[3]; 5862 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 5863 __IM uint32_t RESERVED22; 5864 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 5865 __IM uint32_t RESERVED23[7]; 5866 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 5867 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 5868 5869 5870 /* Peripheral: UARTE */ 5871 /* Description: UART with EasyDMA 0 */ 5872 5873 /* Register: UARTE_SHORTS */ 5874 /* Description: Shortcuts between local events and tasks */ 5875 5876 /* Bit 6 : Shortcut between event ENDRX and task STOPRX */ 5877 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ 5878 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ 5879 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ 5880 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ 5881 5882 /* Bit 5 : Shortcut between event ENDRX and task STARTRX */ 5883 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ 5884 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ 5885 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 5886 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 5887 5888 /* Register: UARTE_INTENSET */ 5889 /* Description: Enable interrupt */ 5890 5891 /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ 5892 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 5893 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 5894 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 5895 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 5896 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ 5897 5898 /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ 5899 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 5900 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 5901 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 5902 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 5903 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 5904 5905 /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ 5906 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 5907 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 5908 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 5909 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 5910 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 5911 5912 /* Bit 17 : Write '1' to enable interrupt for event RXTO */ 5913 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 5914 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ 5915 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ 5916 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ 5917 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ 5918 5919 /* Bit 9 : Write '1' to enable interrupt for event ERROR */ 5920 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 5921 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 5922 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 5923 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 5924 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ 5925 5926 /* Bit 8 : Write '1' to enable interrupt for event ENDTX */ 5927 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 5928 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 5929 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 5930 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 5931 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ 5932 5933 /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ 5934 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 5935 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 5936 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ 5937 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ 5938 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ 5939 5940 /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ 5941 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 5942 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 5943 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 5944 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 5945 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 5946 5947 /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ 5948 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 5949 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 5950 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ 5951 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ 5952 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ 5953 5954 /* Bit 1 : Write '1' to enable interrupt for event NCTS */ 5955 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 5956 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ 5957 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ 5958 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ 5959 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ 5960 5961 /* Bit 0 : Write '1' to enable interrupt for event CTS */ 5962 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ 5963 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ 5964 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ 5965 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ 5966 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ 5967 5968 5969 /* Register: UARTE_ERRORSRC */ 5970 /* Description: Error source This register is read/write one to clear. */ 5971 5972 /* Bit 3 : Break condition */ 5973 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 5974 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 5975 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ 5976 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ 5977 5978 /* Bit 2 : Framing error occurred */ 5979 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 5980 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 5981 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ 5982 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ 5983 5984 /* Bit 1 : Parity error */ 5985 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 5986 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 5987 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ 5988 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ 5989 5990 /* Bit 0 : Overrun error */ 5991 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 5992 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 5993 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ 5994 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ 5995 5996 /* Register: UARTE_ENABLE */ 5997 /* Description: Enable UART */ 5998 5999 /* Bits 3..0 : Enable or disable UARTE */ 6000 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 6001 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 6002 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ 6003 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ 6004 6005 /* Register: UARTE_PSEL_RTS */ 6006 /* Description: Pin select for RTS signal */ 6007 6008 /* Bit 31 : Connection */ 6009 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 6010 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 6011 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ 6012 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 6013 6014 /* Bit 5 : Port number */ 6015 #define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ 6016 #define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ 6017 6018 /* Bits 4..0 : Pin number */ 6019 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 6020 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ 6021 6022 /* Register: UARTE_PSEL_TXD */ 6023 /* Description: Pin select for TXD signal */ 6024 6025 /* Bit 31 : Connection */ 6026 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 6027 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 6028 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ 6029 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 6030 6031 /* Bit 5 : Port number */ 6032 #define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ 6033 #define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ 6034 6035 /* Bits 4..0 : Pin number */ 6036 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 6037 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ 6038 6039 /* Register: UARTE_PSEL_CTS */ 6040 /* Description: Pin select for CTS signal */ 6041 6042 /* Bit 31 : Connection */ 6043 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 6044 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 6045 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ 6046 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 6047 6048 /* Bit 5 : Port number */ 6049 #define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ 6050 #define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ 6051 6052 /* Bits 4..0 : Pin number */ 6053 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 6054 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ 6055 6056 /* Register: UARTE_PSEL_RXD */ 6057 /* Description: Pin select for RXD signal */ 6058 6059 /* Bit 31 : Connection */ 6060 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 6061 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 6062 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ 6063 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 6064 6065 /* Bit 5 : Port number */ 6066 #define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ 6067 #define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ 6068 6069 /* Bits 4..0 : Pin number */ 6070 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 6071 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ 6072 6073 /* Register: UARTE_BAUDRATE */ 6074 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ 6075 6076 /* Bits 31..0 : Baud rate */ 6077 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 6078 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 6079 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ 6080 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ 6081 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ 6082 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ 6083 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ 6084 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ 6085 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ 6086 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ 6087 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ 6088 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ 6089 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ 6090 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ 6091 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ 6092 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ 6093 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ 6094 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ 6095 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ 6096 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ 6097 6098 /* Register: UARTE_RXD_PTR */ 6099 /* Description: Data pointer */ 6100 6101 /* Bits 31..0 : Data pointer */ 6102 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 6103 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 6104 6105 /* Register: UARTE_RXD_MAXCNT */ 6106 /* Description: Maximum number of bytes in receive buffer */ 6107 6108 /* Bits 15..0 : Maximum number of bytes in receive buffer */ 6109 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 6110 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 6111 6112 /* Register: UARTE_RXD_AMOUNT */ 6113 /* Description: Number of bytes transferred in the last transaction */ 6114 6115 /* Bits 15..0 : Number of bytes transferred in the last transaction */ 6116 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 6117 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 6118 6119 /* Register: UARTE_TXD_PTR */ 6120 /* Description: Data pointer */ 6121 6122 /* Bits 31..0 : Data pointer */ 6123 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 6124 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 6125 6126 /* Register: UARTE_TXD_MAXCNT */ 6127 /* Description: Maximum number of bytes in transmit buffer */ 6128 6129 /* Bits 15..0 : Maximum number of bytes in transmit buffer */ 6130 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 6131 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 6132 6133 /* Register: UARTE_TXD_AMOUNT */ 6134 /* Description: Number of bytes transferred in the last transaction */ 6135 6136 /* Bits 15..0 : Number of bytes transferred in the last transaction */ 6137 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 6138 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 6139 6140 /* Register: UARTE_CONFIG */ 6141 /* Description: Configuration of parity and hardware flow control */ 6142 6143 /* Bit 8 : Even or odd parity type */ 6144 #define UARTE_CONFIG_PARITYTYPE_Pos (8UL) /*!< Position of PARITYTYPE field. */ 6145 #define UARTE_CONFIG_PARITYTYPE_Msk (0x1UL << UARTE_CONFIG_PARITYTYPE_Pos) /*!< Bit mask of PARITYTYPE field. */ 6146 #define UARTE_CONFIG_PARITYTYPE_Even (0UL) /*!< Even parity */ 6147 #define UARTE_CONFIG_PARITYTYPE_Odd (1UL) /*!< Odd parity */ 6148 6149 /* Bit 4 : Stop bits */ 6150 #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ 6151 #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ 6152 #define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ 6153 #define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ 6154 6155 /* Bits 3..1 : Parity */ 6156 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 6157 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 6158 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ 6159 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ 6160 6161 /* Bit 0 : Hardware flow control */ 6162 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 6163 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 6164 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ 6165 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ 6166 6167 6168 /* =========================================================================================================================== */ 6169 /* ================ UICR ================ */ 6170 /* =========================================================================================================================== */ 6171 6172 6173 /** 6174 * @brief User Information Configuration Registers (UICR) 6175 * At this point just a chunk of reserved space of 2KiB 6176 */ 6177 6178 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 6179 __IM uint32_t RESERVED[1024]; 6180 } NRF_UICR_Type; /*!< Size = 4096 */ 6181 6182 6183 6184 /* =========================================================================================================================== */ 6185 /* ================ VREQCTRL ================ */ 6186 /* =========================================================================================================================== */ 6187 6188 6189 /** 6190 * @brief Voltage request control (VREQCTRL) 6191 */ 6192 6193 typedef struct { /*!< (@ 0x41004000) VREQCTRL_NS Structure */ 6194 __IM uint32_t RESERVED[320]; 6195 __IOM VREQCTRL_VREGRADIO_Type VREGRADIO; /*!< (@ 0x00000500) Unspecified */ 6196 } NRF_VREQCTRL_Type; /*!< Size = 1292 (0x50c) */ 6197 6198 6199 6200 #ifdef __cplusplus 6201 } 6202 #endif 6203 6204 #endif /* _NRF5340_PERI_TYPES_H */ 6205
