1 /* 2 * Copyright (c) 2023 Nordic Semiconductor ASA 3 * 4 * Note: Most of these file content is taken directly or with minor 5 * modifications from the Nordic nrfx MDK files, which are 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 * 9 * Therefore this file overall has that same license. 10 * 11 * HW peripherals SW regiters interface definitions 12 * For an nRF5340 SOC 13 * 14 */ 15 16 #ifndef _NRF5340_PERI_TYPES_H 17 #define _NRF5340_PERI_TYPES_H 18 19 #include <stdint.h> 20 21 #ifndef __IM 22 #define __IM 23 #endif 24 #ifndef __OM 25 #define __OM 26 #endif 27 #ifndef __IOM 28 #define __IOM 29 #endif 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /** 36 * @brief FICR_INFO [INFO] (Device info) 37 */ 38 typedef struct { 39 __IM uint32_t CONFIGID; /*!< (@ 0x00000000) Configuration identifier */ 40 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 41 __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 42 __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 43 configuration */ 44 __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 45 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 46 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 47 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size in bytes */ 48 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 49 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 50 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 51 52 53 /** 54 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 55 */ 56 typedef struct { 57 __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address */ 58 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 59 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 60 61 62 /** 63 * @brief FICR_NFC [NFC] (Unspecified) 64 */ 65 typedef struct { 66 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read 67 these values to populate NFCID1_3RD_LAST, 68 NFCID1_2ND_LAST and NFCID1_LAST. */ 69 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read 70 these values to populate NFCID1_3RD_LAST, 71 NFCID1_2ND_LAST and NFCID1_LAST. */ 72 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read 73 these values to populate NFCID1_3RD_LAST, 74 NFCID1_2ND_LAST and NFCID1_LAST. */ 75 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read 76 these values to populate NFCID1_3RD_LAST, 77 NFCID1_2ND_LAST and NFCID1_LAST. */ 78 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 79 80 81 /** 82 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 83 */ 84 typedef struct { 85 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 86 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 87 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 88 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 89 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 90 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 91 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 92 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 93 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 94 95 96 /** 97 * @brief RADIO_PSEL [PSEL] (Unspecified) 98 */ 99 typedef struct { 100 __IOM uint32_t DFEGPIO[8]; /*!< (@ 0x00000000) Description collection: Pin select for DFE pin 101 n */ 102 } RADIO_PSEL_Type; /*!< Size = 32 (0x20) */ 103 104 105 /** 106 * @brief RADIO_DFEPACKET [DFEPACKET] (DFE packet EasyDMA channel) 107 */ 108 typedef struct { 109 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 110 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 111 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of samples transferred in the last transaction */ 112 } RADIO_DFEPACKET_Type; /*!< Size = 12 (0xc) */ 113 114 /** 115 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 116 */ 117 typedef struct { 118 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 119 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 120 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 121 122 123 /** 124 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 125 */ 126 typedef struct { 127 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 128 for task CHG[n].EN */ 129 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 130 for task CHG[n].DIS */ 131 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 132 133 134 /** 135 * @brief CLOCK_HFCLKAUDIO [HFCLKAUDIO] (Unspecified) 136 */ 137 typedef struct { 138 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000000) Audio PLL frequency in 11.176 MHz - 11.402 MHz 139 or 12.165 MHz - 12.411 MHz frequency bands */ 140 } CLOCK_HFCLKAUDIO_Type; /*!< Size = 4 (0x4) */ 141 142 143 /** 144 * @brief RESET_NETWORK [NETWORK] (ULP network core control) 145 */ 146 typedef struct { 147 __IM uint32_t RESERVED; 148 __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force network core off */ 149 } RESET_NETWORK_Type; /*!< Size = 8 (0x8) */ 150 151 152 /** 153 * @brief VREQCTRL_VREGRADIO [VREGRADIO] (Unspecified) 154 */ 155 typedef struct { 156 __IOM uint32_t VREQH; /*!< (@ 0x00000000) Request high voltage on RADIO After requesting 157 high voltage, the user must wait until VREQHREADY 158 is set to Ready */ 159 __IM uint32_t RESERVED; 160 __IM uint32_t VREQHREADY; /*!< (@ 0x00000008) High voltage on RADIO is ready */ 161 } VREQCTRL_VREGRADIO_Type; /*!< Size = 12 (0xc) */ 162 163 /* =========================================================================================================================== */ 164 /* ================ AAR ================ */ 165 /* =========================================================================================================================== */ 166 167 168 /** 169 * @brief Accelerated Address Resolver (AAR) 170 */ 171 172 typedef struct { /*!< (@ 0x4100E000) AAR_NS Structure */ 173 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 174 in the IRK data structure */ 175 __IM uint32_t RESERVED; 176 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 177 __IM uint32_t RESERVED1[29]; 178 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 179 __IM uint32_t RESERVED2; 180 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 181 __IM uint32_t RESERVED3[29]; 182 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 183 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 184 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 185 __IM uint32_t RESERVED4[29]; 186 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000180) Publish configuration for event END */ 187 __IOM uint32_t PUBLISH_RESOLVED; /*!< (@ 0x00000184) Publish configuration for event RESOLVED */ 188 __IOM uint32_t PUBLISH_NOTRESOLVED; /*!< (@ 0x00000188) Publish configuration for event NOTRESOLVED */ 189 __IM uint32_t RESERVED5[94]; 190 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 191 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 192 __IM uint32_t RESERVED6[61]; 193 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 194 __IM uint32_t RESERVED7[63]; 195 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 196 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 197 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 198 __IM uint32_t RESERVED8; 199 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 200 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 201 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 202 203 /* Peripheral: AAR */ 204 /* Description: Accelerated Address Resolver */ 205 206 /* Register: AAR_TASKS_START */ 207 /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ 208 209 /* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ 210 #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 211 #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 212 #define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 213 214 /* Register: AAR_TASKS_STOP */ 215 /* Description: Stop resolving addresses */ 216 217 /* Bit 0 : Stop resolving addresses */ 218 #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 219 #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 220 #define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 221 222 /* Register: AAR_SUBSCRIBE_START */ 223 /* Description: Subscribe configuration for task START */ 224 225 /* Bit 31 : */ 226 #define AAR_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 227 #define AAR_SUBSCRIBE_START_EN_Msk (0x1UL << AAR_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 228 #define AAR_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 229 #define AAR_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 230 231 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 232 #define AAR_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 233 #define AAR_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 234 235 /* Register: AAR_SUBSCRIBE_STOP */ 236 /* Description: Subscribe configuration for task STOP */ 237 238 /* Bit 31 : */ 239 #define AAR_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 240 #define AAR_SUBSCRIBE_STOP_EN_Msk (0x1UL << AAR_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 241 #define AAR_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 242 #define AAR_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 243 244 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 245 #define AAR_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 246 #define AAR_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 247 248 /* Register: AAR_EVENTS_END */ 249 /* Description: Address resolution procedure complete */ 250 251 /* Bit 0 : Address resolution procedure complete */ 252 #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 253 #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 254 #define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 255 #define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 256 257 /* Register: AAR_EVENTS_RESOLVED */ 258 /* Description: Address resolved */ 259 260 /* Bit 0 : Address resolved */ 261 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ 262 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ 263 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */ 264 #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */ 265 266 /* Register: AAR_EVENTS_NOTRESOLVED */ 267 /* Description: Address not resolved */ 268 269 /* Bit 0 : Address not resolved */ 270 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ 271 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ 272 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */ 273 #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */ 274 275 /* Register: AAR_PUBLISH_END */ 276 /* Description: Publish configuration for event END */ 277 278 /* Bit 31 : */ 279 #define AAR_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 280 #define AAR_PUBLISH_END_EN_Msk (0x1UL << AAR_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 281 #define AAR_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ 282 #define AAR_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ 283 284 /* Bits 7..0 : DPPI channel that event END will publish to. */ 285 #define AAR_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 286 #define AAR_PUBLISH_END_CHIDX_Msk (0xFFUL << AAR_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 287 288 /* Register: AAR_PUBLISH_RESOLVED */ 289 /* Description: Publish configuration for event RESOLVED */ 290 291 /* Bit 31 : */ 292 #define AAR_PUBLISH_RESOLVED_EN_Pos (31UL) /*!< Position of EN field. */ 293 #define AAR_PUBLISH_RESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_RESOLVED_EN_Pos) /*!< Bit mask of EN field. */ 294 #define AAR_PUBLISH_RESOLVED_EN_Disabled (0UL) /*!< Disable publishing */ 295 #define AAR_PUBLISH_RESOLVED_EN_Enabled (1UL) /*!< Enable publishing */ 296 297 /* Bits 7..0 : DPPI channel that event RESOLVED will publish to. */ 298 #define AAR_PUBLISH_RESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 299 #define AAR_PUBLISH_RESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_RESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 300 301 /* Register: AAR_PUBLISH_NOTRESOLVED */ 302 /* Description: Publish configuration for event NOTRESOLVED */ 303 304 /* Bit 31 : */ 305 #define AAR_PUBLISH_NOTRESOLVED_EN_Pos (31UL) /*!< Position of EN field. */ 306 #define AAR_PUBLISH_NOTRESOLVED_EN_Msk (0x1UL << AAR_PUBLISH_NOTRESOLVED_EN_Pos) /*!< Bit mask of EN field. */ 307 #define AAR_PUBLISH_NOTRESOLVED_EN_Disabled (0UL) /*!< Disable publishing */ 308 #define AAR_PUBLISH_NOTRESOLVED_EN_Enabled (1UL) /*!< Enable publishing */ 309 310 /* Bits 7..0 : DPPI channel that event NOTRESOLVED will publish to. */ 311 #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 312 #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 313 314 /* Register: AAR_INTENSET */ 315 /* Description: Enable interrupt */ 316 317 /* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ 318 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 319 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 320 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ 321 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ 322 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ 323 324 /* Bit 1 : Write '1' to enable interrupt for event RESOLVED */ 325 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 326 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 327 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ 328 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ 329 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ 330 331 /* Bit 0 : Write '1' to enable interrupt for event END */ 332 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ 333 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ 334 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 335 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 336 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */ 337 338 /* Register: AAR_INTENCLR */ 339 /* Description: Disable interrupt */ 340 341 /* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ 342 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 343 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 344 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ 345 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ 346 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ 347 348 /* Bit 1 : Write '1' to disable interrupt for event RESOLVED */ 349 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 350 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 351 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ 352 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ 353 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ 354 355 /* Bit 0 : Write '1' to disable interrupt for event END */ 356 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ 357 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 358 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 359 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 360 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ 361 362 /* Register: AAR_STATUS */ 363 /* Description: Resolution status */ 364 365 /* Bits 3..0 : The IRK that was used last time an address was resolved */ 366 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 367 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 368 369 /* Register: AAR_ENABLE */ 370 /* Description: Enable AAR */ 371 372 /* Bits 1..0 : Enable or disable AAR */ 373 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 374 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 375 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 376 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ 377 378 /* Register: AAR_NIRK */ 379 /* Description: Number of IRKs */ 380 381 /* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */ 382 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ 383 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ 384 385 /* Register: AAR_IRKPTR */ 386 /* Description: Pointer to IRK data structure */ 387 388 /* Bits 31..0 : Pointer to the IRK data structure */ 389 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ 390 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ 391 392 /* Register: AAR_ADDRPTR */ 393 /* Description: Pointer to the resolvable address */ 394 395 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ 396 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ 397 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ 398 399 /* Register: AAR_SCRATCHPTR */ 400 /* Description: Pointer to data area used for temporary storage */ 401 402 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */ 403 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ 404 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ 405 406 407 408 /* =========================================================================================================================== */ 409 /* ================ CCM ================ */ 410 /* =========================================================================================================================== */ 411 412 413 /** 414 * @brief AES CCM mode encryption (CCM) 415 */ 416 417 typedef struct { /*!< (@ 0x4100E000) CCM_NS Structure */ 418 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation 419 will stop by itself when completed. */ 420 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 421 stop by itself when completed. */ 422 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 423 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 424 the contents of the RATEOVERRIDE register 425 for any ongoing encryption/decryption */ 426 __IM uint32_t RESERVED[28]; 427 __IOM uint32_t SUBSCRIBE_KSGEN; /*!< (@ 0x00000080) Subscribe configuration for task KSGEN */ 428 __IOM uint32_t SUBSCRIBE_CRYPT; /*!< (@ 0x00000084) Subscribe configuration for task CRYPT */ 429 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 430 __IOM uint32_t SUBSCRIBE_RATEOVERRIDE; /*!< (@ 0x0000008C) Subscribe configuration for task RATEOVERRIDE */ 431 __IM uint32_t RESERVED1[28]; 432 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ 433 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 434 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 435 __IM uint32_t RESERVED2[29]; 436 __IOM uint32_t PUBLISH_ENDKSGEN; /*!< (@ 0x00000180) Publish configuration for event ENDKSGEN */ 437 __IOM uint32_t PUBLISH_ENDCRYPT; /*!< (@ 0x00000184) Publish configuration for event ENDCRYPT */ 438 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x00000188) Deprecated register - Publish configuration for 439 event ERROR */ 440 __IM uint32_t RESERVED3[29]; 441 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 442 __IM uint32_t RESERVED4[64]; 443 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 444 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 445 __IM uint32_t RESERVED5[61]; 446 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 447 __IM uint32_t RESERVED6[63]; 448 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 449 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 450 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding the AES key 451 and the NONCE vector */ 452 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 453 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 454 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 455 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH 456 = Extended */ 457 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 458 __IOM uint32_t HEADERMASK; /*!< (@ 0x00000520) Header (S0) mask. */ 459 } NRF_CCM_Type; /*!< Size = 1316 (0x524) */ 460 461 462 /* Peripheral: CCM */ 463 /* Description: AES CCM mode encryption */ 464 465 /* Register: CCM_TASKS_KSGEN */ 466 /* Description: Start generation of keystream. This operation will stop by itself when completed. */ 467 468 /* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */ 469 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ 470 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ 471 #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ 472 473 /* Register: CCM_TASKS_CRYPT */ 474 /* Description: Start encryption/decryption. This operation will stop by itself when completed. */ 475 476 /* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ 477 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ 478 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ 479 #define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */ 480 481 /* Register: CCM_TASKS_STOP */ 482 /* Description: Stop encryption/decryption */ 483 484 /* Bit 0 : Stop encryption/decryption */ 485 #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 486 #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 487 #define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 488 489 /* Register: CCM_TASKS_RATEOVERRIDE */ 490 /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ 491 492 /* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ 493 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ 494 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ 495 #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ 496 497 /* Register: CCM_SUBSCRIBE_KSGEN */ 498 /* Description: Subscribe configuration for task KSGEN */ 499 500 /* Bit 31 : */ 501 #define CCM_SUBSCRIBE_KSGEN_EN_Pos (31UL) /*!< Position of EN field. */ 502 #define CCM_SUBSCRIBE_KSGEN_EN_Msk (0x1UL << CCM_SUBSCRIBE_KSGEN_EN_Pos) /*!< Bit mask of EN field. */ 503 #define CCM_SUBSCRIBE_KSGEN_EN_Disabled (0UL) /*!< Disable subscription */ 504 #define CCM_SUBSCRIBE_KSGEN_EN_Enabled (1UL) /*!< Enable subscription */ 505 506 /* Bits 7..0 : DPPI channel that task KSGEN will subscribe to */ 507 #define CCM_SUBSCRIBE_KSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 508 #define CCM_SUBSCRIBE_KSGEN_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_KSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 509 510 /* Register: CCM_SUBSCRIBE_CRYPT */ 511 /* Description: Subscribe configuration for task CRYPT */ 512 513 /* Bit 31 : */ 514 #define CCM_SUBSCRIBE_CRYPT_EN_Pos (31UL) /*!< Position of EN field. */ 515 #define CCM_SUBSCRIBE_CRYPT_EN_Msk (0x1UL << CCM_SUBSCRIBE_CRYPT_EN_Pos) /*!< Bit mask of EN field. */ 516 #define CCM_SUBSCRIBE_CRYPT_EN_Disabled (0UL) /*!< Disable subscription */ 517 #define CCM_SUBSCRIBE_CRYPT_EN_Enabled (1UL) /*!< Enable subscription */ 518 519 /* Bits 7..0 : DPPI channel that task CRYPT will subscribe to */ 520 #define CCM_SUBSCRIBE_CRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 521 #define CCM_SUBSCRIBE_CRYPT_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_CRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 522 523 /* Register: CCM_SUBSCRIBE_STOP */ 524 /* Description: Subscribe configuration for task STOP */ 525 526 /* Bit 31 : */ 527 #define CCM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 528 #define CCM_SUBSCRIBE_STOP_EN_Msk (0x1UL << CCM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 529 #define CCM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 530 #define CCM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 531 532 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 533 #define CCM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 534 #define CCM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 535 536 /* Register: CCM_SUBSCRIBE_RATEOVERRIDE */ 537 /* Description: Subscribe configuration for task RATEOVERRIDE */ 538 539 /* Bit 31 : */ 540 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos (31UL) /*!< Position of EN field. */ 541 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Msk (0x1UL << CCM_SUBSCRIBE_RATEOVERRIDE_EN_Pos) /*!< Bit mask of EN field. */ 542 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Disabled (0UL) /*!< Disable subscription */ 543 #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (1UL) /*!< Enable subscription */ 544 545 /* Bits 7..0 : DPPI channel that task RATEOVERRIDE will subscribe to */ 546 #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 547 #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 548 549 /* Register: CCM_EVENTS_ENDKSGEN */ 550 /* Description: Keystream generation complete */ 551 552 /* Bit 0 : Keystream generation complete */ 553 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ 554 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ 555 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ 556 #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */ 557 558 /* Register: CCM_EVENTS_ENDCRYPT */ 559 /* Description: Encrypt/decrypt complete */ 560 561 /* Bit 0 : Encrypt/decrypt complete */ 562 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ 563 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ 564 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */ 565 #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */ 566 567 /* Register: CCM_EVENTS_ERROR */ 568 /* Description: Deprecated register - CCM error event */ 569 570 /* Bit 0 : Deprecated field - CCM error event */ 571 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ 572 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ 573 #define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ 574 #define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ 575 576 /* Register: CCM_PUBLISH_ENDKSGEN */ 577 /* Description: Publish configuration for event ENDKSGEN */ 578 579 /* Bit 31 : */ 580 #define CCM_PUBLISH_ENDKSGEN_EN_Pos (31UL) /*!< Position of EN field. */ 581 #define CCM_PUBLISH_ENDKSGEN_EN_Msk (0x1UL << CCM_PUBLISH_ENDKSGEN_EN_Pos) /*!< Bit mask of EN field. */ 582 #define CCM_PUBLISH_ENDKSGEN_EN_Disabled (0UL) /*!< Disable publishing */ 583 #define CCM_PUBLISH_ENDKSGEN_EN_Enabled (1UL) /*!< Enable publishing */ 584 585 /* Bits 7..0 : DPPI channel that event ENDKSGEN will publish to. */ 586 #define CCM_PUBLISH_ENDKSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 587 #define CCM_PUBLISH_ENDKSGEN_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDKSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 588 589 /* Register: CCM_PUBLISH_ENDCRYPT */ 590 /* Description: Publish configuration for event ENDCRYPT */ 591 592 /* Bit 31 : */ 593 #define CCM_PUBLISH_ENDCRYPT_EN_Pos (31UL) /*!< Position of EN field. */ 594 #define CCM_PUBLISH_ENDCRYPT_EN_Msk (0x1UL << CCM_PUBLISH_ENDCRYPT_EN_Pos) /*!< Bit mask of EN field. */ 595 #define CCM_PUBLISH_ENDCRYPT_EN_Disabled (0UL) /*!< Disable publishing */ 596 #define CCM_PUBLISH_ENDCRYPT_EN_Enabled (1UL) /*!< Enable publishing */ 597 598 /* Bits 7..0 : DPPI channel that event ENDCRYPT will publish to. */ 599 #define CCM_PUBLISH_ENDCRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 600 #define CCM_PUBLISH_ENDCRYPT_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDCRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 601 602 /* Register: CCM_PUBLISH_ERROR */ 603 /* Description: Deprecated register - Publish configuration for event ERROR */ 604 605 /* Bit 31 : */ 606 #define CCM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ 607 #define CCM_PUBLISH_ERROR_EN_Msk (0x1UL << CCM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ 608 #define CCM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ 609 #define CCM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ 610 611 /* Bits 7..0 : DPPI channel that event ERROR will publish to. */ 612 #define CCM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 613 #define CCM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 614 615 /* Register: CCM_SHORTS */ 616 /* Description: Shortcuts between local events and tasks */ 617 618 /* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */ 619 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ 620 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ 621 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ 622 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ 623 624 /* Register: CCM_INTENSET */ 625 /* Description: Enable interrupt */ 626 627 /* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */ 628 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 629 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 630 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 631 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 632 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ 633 634 /* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */ 635 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 636 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 637 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ 638 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ 639 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ 640 641 /* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */ 642 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 643 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 644 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ 645 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ 646 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ 647 648 /* Register: CCM_INTENCLR */ 649 /* Description: Disable interrupt */ 650 651 /* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */ 652 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 653 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 654 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 655 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 656 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 657 658 /* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */ 659 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 660 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 661 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ 662 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ 663 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ 664 665 /* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */ 666 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 667 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 668 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ 669 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ 670 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ 671 672 /* Register: CCM_MICSTATUS */ 673 /* Description: MIC check result */ 674 675 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */ 676 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ 677 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ 678 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ 679 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ 680 681 /* Register: CCM_ENABLE */ 682 /* Description: Enable */ 683 684 /* Bits 1..0 : Enable or disable CCM */ 685 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 686 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 687 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 688 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ 689 690 /* Register: CCM_MODE */ 691 /* Description: Operation mode */ 692 693 /* Bit 24 : Packet length configuration */ 694 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ 695 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ 696 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */ 697 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ 698 699 /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ 700 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ 701 #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ 702 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ 703 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ 704 #define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */ 705 #define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */ 706 707 /* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */ 708 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 709 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 710 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ 711 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ 712 713 /* Register: CCM_CNFPTR */ 714 /* Description: Pointer to data structure holding the AES key and the NONCE vector */ 715 716 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see table CCM data structure overview) */ 717 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ 718 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ 719 720 /* Register: CCM_INPTR */ 721 /* Description: Input pointer */ 722 723 /* Bits 31..0 : Input pointer */ 724 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ 725 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ 726 727 /* Register: CCM_OUTPTR */ 728 /* Description: Output pointer */ 729 730 /* Bits 31..0 : Output pointer */ 731 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ 732 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ 733 734 /* Register: CCM_SCRATCHPTR */ 735 /* Description: Pointer to data area used for temporary storage */ 736 737 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation, 738 MIC generation and encryption/decryption. */ 739 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ 740 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ 741 742 /* Register: CCM_MAXPACKETSIZE */ 743 /* Description: Length of keystream generated when MODE.LENGTH = Extended */ 744 745 /* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater than or equal to the subsequent packet payload to be encrypted/decrypted. */ 746 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ 747 #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ 748 749 /* Register: CCM_RATEOVERRIDE */ 750 /* Description: Data rate override setting. */ 751 752 /* Bits 1..0 : Data rate override setting */ 753 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ 754 #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ 755 #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ 756 #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ 757 #define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */ 758 #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */ 759 760 /* Register: CCM_HEADERMASK */ 761 /* Description: Header (S0) mask. */ 762 763 /* Bits 7..0 : Header (S0) mask */ 764 #define CCM_HEADERMASK_HEADERMASK_Pos (0UL) /*!< Position of HEADERMASK field. */ 765 #define CCM_HEADERMASK_HEADERMASK_Msk (0xFFUL << CCM_HEADERMASK_HEADERMASK_Pos) /*!< Bit mask of HEADERMASK field. */ 766 767 768 769 /* =========================================================================================================================== */ 770 /* ================ CLOCK ================ */ 771 /* =========================================================================================================================== */ 772 773 774 /** 775 * @brief Clock management (CLOCK) 776 */ 777 778 typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ 779 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK128M/HFCLK64M source as selected in 780 HFCLKSRC */ 781 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK128M/HFCLK64M source */ 782 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source as selected in LFCLKSRC */ 783 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 784 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 785 __IM uint32_t RESERVED; 786 __OM uint32_t TASKS_HFCLKAUDIOSTART; /*!< (@ 0x00000018) Start HFCLKAUDIO source */ 787 __OM uint32_t TASKS_HFCLKAUDIOSTOP; /*!< (@ 0x0000001C) Stop HFCLKAUDIO source */ 788 __OM uint32_t TASKS_HFCLK192MSTART; /*!< (@ 0x00000020) Start HFCLK192M source as selected in HFCLK192MSRC */ 789 __OM uint32_t TASKS_HFCLK192MSTOP; /*!< (@ 0x00000024) Stop HFCLK192M source */ 790 __IM uint32_t RESERVED1[22]; 791 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 792 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 793 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 794 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 795 __IOM uint32_t SUBSCRIBE_CAL; /*!< (@ 0x00000090) Subscribe configuration for task CAL */ 796 __IM uint32_t RESERVED2; 797 __IOM uint32_t SUBSCRIBE_HFCLKAUDIOSTART; /*!< (@ 0x00000098) Subscribe configuration for task HFCLKAUDIOSTART */ 798 __IOM uint32_t SUBSCRIBE_HFCLKAUDIOSTOP; /*!< (@ 0x0000009C) Subscribe configuration for task HFCLKAUDIOSTOP */ 799 __IOM uint32_t SUBSCRIBE_HFCLK192MSTART; /*!< (@ 0x000000A0) Subscribe configuration for task HFCLK192MSTART */ 800 __IOM uint32_t SUBSCRIBE_HFCLK192MSTOP; /*!< (@ 0x000000A4) Subscribe configuration for task HFCLK192MSTOP */ 801 __IM uint32_t RESERVED3[22]; 802 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK128M/HFCLK64M source started */ 803 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK source started */ 804 __IM uint32_t RESERVED4[5]; 805 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000011C) Calibration of LFRC oscillator complete event */ 806 __IOM uint32_t EVENTS_HFCLKAUDIOSTARTED; /*!< (@ 0x00000120) HFCLKAUDIO source started */ 807 __IOM uint32_t EVENTS_HFCLK192MSTARTED; /*!< (@ 0x00000124) HFCLK192M source started */ 808 __IM uint32_t RESERVED5[22]; 809 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 810 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 811 __IM uint32_t RESERVED6[5]; 812 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x0000019C) Publish configuration for event DONE */ 813 __IOM uint32_t PUBLISH_HFCLKAUDIOSTARTED; /*!< (@ 0x000001A0) Publish configuration for event HFCLKAUDIOSTARTED */ 814 __IOM uint32_t PUBLISH_HFCLK192MSTARTED; /*!< (@ 0x000001A4) Publish configuration for event HFCLK192MSTARTED */ 815 __IM uint32_t RESERVED7[86]; 816 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 817 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 818 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 819 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 820 __IM uint32_t RESERVED8[62]; 821 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 822 triggered */ 823 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) Status indicating which HFCLK128M/HFCLK64M source 824 is running This register value in any CLOCK 825 instance reflects status only due to configurations/action 826 in that CLOCK instance. */ 827 __IM uint32_t RESERVED9; 828 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 829 triggered */ 830 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Status indicating which LFCLK source is running 831 This register value in any CLOCK instance 832 reflects status only due to configurations/actions 833 in that CLOCK instance. */ 834 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 835 task was triggered */ 836 __IM uint32_t RESERVED10[12]; 837 __IM uint32_t HFCLKAUDIORUN; /*!< (@ 0x00000450) Status indicating that HFCLKAUDIOSTART task has 838 been triggered */ 839 __IM uint32_t HFCLKAUDIOSTAT; /*!< (@ 0x00000454) Status indicating which HFCLKAUDIO source is 840 running */ 841 __IM uint32_t HFCLK192MRUN; /*!< (@ 0x00000458) Status indicating that HFCLK192MSTART task has 842 been triggered */ 843 __IM uint32_t HFCLK192MSTAT; /*!< (@ 0x0000045C) Status indicating which HFCLK192M source is running */ 844 __IM uint32_t RESERVED11[45]; 845 __IOM uint32_t HFCLKSRC; /*!< (@ 0x00000514) Clock source for HFCLK128M/HFCLK64M */ 846 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for LFCLK */ 847 __IM uint32_t RESERVED12[15]; 848 __IOM uint32_t HFCLKCTRL; /*!< (@ 0x00000558) HFCLK128M frequency configuration */ 849 __IOM CLOCK_HFCLKAUDIO_Type HFCLKAUDIO; /*!< (@ 0x0000055C) Unspecified */ 850 __IM uint32_t RESERVED13[4]; 851 __IOM uint32_t HFCLKALWAYSRUN; /*!< (@ 0x00000570) Automatic or manual control of HFCLK128M/HFCLK64M */ 852 __IOM uint32_t LFCLKALWAYSRUN; /*!< (@ 0x00000574) Automatic or manual control of LFCLK */ 853 __IM uint32_t RESERVED14; 854 __IOM uint32_t HFCLKAUDIOALWAYSRUN; /*!< (@ 0x0000057C) Automatic or manual control of HFCLKAUDIO */ 855 __IOM uint32_t HFCLK192MSRC; /*!< (@ 0x00000580) Clock source for HFCLK192M */ 856 __IOM uint32_t HFCLK192MALWAYSRUN; /*!< (@ 0x00000584) Automatic or manual control of HFCLK192M */ 857 __IM uint32_t RESERVED15[12]; 858 __IOM uint32_t HFCLK192MCTRL; /*!< (@ 0x000005B8) HFCLK192M frequency configuration */ 859 } NRF_CLOCK_Type; /*!< Size = 1468 (0x5bc) */ 860 861 862 /* Peripheral: CLOCK */ 863 /* Description: Clock management 0 */ 864 865 /* Register: CLOCK_TASKS_HFCLKSTART */ 866 /* Description: Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */ 867 868 /* Bit 0 : Start HFCLK128M/HFCLK64M source as selected in HFCLKSRC */ 869 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ 870 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ 871 #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ 872 873 /* Register: CLOCK_TASKS_HFCLKSTOP */ 874 /* Description: Stop HFCLK128M/HFCLK64M source */ 875 876 /* Bit 0 : Stop HFCLK128M/HFCLK64M source */ 877 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ 878 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ 879 #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ 880 881 /* Register: CLOCK_TASKS_LFCLKSTART */ 882 /* Description: Start LFCLK source as selected in LFCLKSRC */ 883 884 /* Bit 0 : Start LFCLK source as selected in LFCLKSRC */ 885 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ 886 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ 887 #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ 888 889 /* Register: CLOCK_TASKS_LFCLKSTOP */ 890 /* Description: Stop LFCLK source */ 891 892 /* Bit 0 : Stop LFCLK source */ 893 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ 894 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ 895 #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ 896 897 /* Register: CLOCK_TASKS_CAL */ 898 /* Description: Start calibration of LFRC oscillator */ 899 900 /* Bit 0 : Start calibration of LFRC oscillator */ 901 #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ 902 #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ 903 #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ 904 905 /* Register: CLOCK_TASKS_HFCLKAUDIOSTART */ 906 /* Description: Start HFCLKAUDIO source */ 907 908 /* Bit 0 : Start HFCLKAUDIO source */ 909 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTART field. */ 910 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTART field. */ 911 #define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Trigger (1UL) /*!< Trigger task */ 912 913 /* Register: CLOCK_TASKS_HFCLKAUDIOSTOP */ 914 /* Description: Stop HFCLKAUDIO source */ 915 916 /* Bit 0 : Stop HFCLKAUDIO source */ 917 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTOP field. */ 918 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTOP field. */ 919 #define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Trigger (1UL) /*!< Trigger task */ 920 921 /* Register: CLOCK_TASKS_HFCLK192MSTART */ 922 /* Description: Start HFCLK192M source as selected in HFCLK192MSRC */ 923 924 /* Bit 0 : Start HFCLK192M source as selected in HFCLK192MSRC */ 925 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTART field. */ 926 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos) /*!< Bit mask of TASKS_HFCLK192MSTART field. */ 927 #define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Trigger (1UL) /*!< Trigger task */ 928 929 /* Register: CLOCK_TASKS_HFCLK192MSTOP */ 930 /* Description: Stop HFCLK192M source */ 931 932 /* Bit 0 : Stop HFCLK192M source */ 933 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTOP field. */ 934 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos) /*!< Bit mask of TASKS_HFCLK192MSTOP field. */ 935 #define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Trigger (1UL) /*!< Trigger task */ 936 937 /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */ 938 /* Description: Subscribe configuration for task HFCLKSTART */ 939 940 /* Bit 31 : */ 941 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ 942 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ 943 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ 944 #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ 945 946 /* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */ 947 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 948 #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 949 950 /* Register: CLOCK_SUBSCRIBE_HFCLKSTOP */ 951 /* Description: Subscribe configuration for task HFCLKSTOP */ 952 953 /* Bit 31 : */ 954 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 955 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ 956 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 957 #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 958 959 /* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */ 960 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 961 #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 962 963 /* Register: CLOCK_SUBSCRIBE_LFCLKSTART */ 964 /* Description: Subscribe configuration for task LFCLKSTART */ 965 966 /* Bit 31 : */ 967 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ 968 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ 969 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ 970 #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ 971 972 /* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */ 973 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 974 #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 975 976 /* Register: CLOCK_SUBSCRIBE_LFCLKSTOP */ 977 /* Description: Subscribe configuration for task LFCLKSTOP */ 978 979 /* Bit 31 : */ 980 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 981 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ 982 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 983 #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 984 985 /* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */ 986 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 987 #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 988 989 /* Register: CLOCK_SUBSCRIBE_CAL */ 990 /* Description: Subscribe configuration for task CAL */ 991 992 /* Bit 31 : */ 993 #define CLOCK_SUBSCRIBE_CAL_EN_Pos (31UL) /*!< Position of EN field. */ 994 #define CLOCK_SUBSCRIBE_CAL_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_CAL_EN_Pos) /*!< Bit mask of EN field. */ 995 #define CLOCK_SUBSCRIBE_CAL_EN_Disabled (0UL) /*!< Disable subscription */ 996 #define CLOCK_SUBSCRIBE_CAL_EN_Enabled (1UL) /*!< Enable subscription */ 997 998 /* Bits 7..0 : DPPI channel that task CAL will subscribe to */ 999 #define CLOCK_SUBSCRIBE_CAL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1000 #define CLOCK_SUBSCRIBE_CAL_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_CAL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1001 1002 /* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTART */ 1003 /* Description: Subscribe configuration for task HFCLKAUDIOSTART */ 1004 1005 /* Bit 31 : */ 1006 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos (31UL) /*!< Position of EN field. */ 1007 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos) /*!< Bit mask of EN field. */ 1008 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Disabled (0UL) /*!< Disable subscription */ 1009 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Enabled (1UL) /*!< Enable subscription */ 1010 1011 /* Bits 7..0 : DPPI channel that task HFCLKAUDIOSTART will subscribe to */ 1012 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1013 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1014 1015 /* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP */ 1016 /* Description: Subscribe configuration for task HFCLKAUDIOSTOP */ 1017 1018 /* Bit 31 : */ 1019 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 1020 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos) /*!< Bit mask of EN field. */ 1021 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 1022 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 1023 1024 /* Bits 7..0 : DPPI channel that task HFCLKAUDIOSTOP will subscribe to */ 1025 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1026 #define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1027 1028 /* Register: CLOCK_SUBSCRIBE_HFCLK192MSTART */ 1029 /* Description: Subscribe configuration for task HFCLK192MSTART */ 1030 1031 /* Bit 31 : */ 1032 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos (31UL) /*!< Position of EN field. */ 1033 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos) /*!< Bit mask of EN field. */ 1034 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Disabled (0UL) /*!< Disable subscription */ 1035 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Enabled (1UL) /*!< Enable subscription */ 1036 1037 /* Bits 7..0 : DPPI channel that task HFCLK192MSTART will subscribe to */ 1038 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1039 #define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1040 1041 /* Register: CLOCK_SUBSCRIBE_HFCLK192MSTOP */ 1042 /* Description: Subscribe configuration for task HFCLK192MSTOP */ 1043 1044 /* Bit 31 : */ 1045 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 1046 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos) /*!< Bit mask of EN field. */ 1047 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 1048 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 1049 1050 /* Bits 7..0 : DPPI channel that task HFCLK192MSTOP will subscribe to */ 1051 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1052 #define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1053 1054 /* Register: CLOCK_EVENTS_HFCLKSTARTED */ 1055 /* Description: HFCLK128M/HFCLK64M source started */ 1056 1057 /* Bit 0 : HFCLK128M/HFCLK64M source started */ 1058 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ 1059 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ 1060 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ 1061 #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ 1062 1063 /* Register: CLOCK_EVENTS_LFCLKSTARTED */ 1064 /* Description: LFCLK source started */ 1065 1066 /* Bit 0 : LFCLK source started */ 1067 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ 1068 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ 1069 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ 1070 #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ 1071 1072 /* Register: CLOCK_EVENTS_DONE */ 1073 /* Description: Calibration of LFRC oscillator complete event */ 1074 1075 /* Bit 0 : Calibration of LFRC oscillator complete event */ 1076 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ 1077 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ 1078 #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ 1079 #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ 1080 1081 /* Register: CLOCK_EVENTS_HFCLKAUDIOSTARTED */ 1082 /* Description: HFCLKAUDIO source started */ 1083 1084 /* Bit 0 : HFCLKAUDIO source started */ 1085 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKAUDIOSTARTED field. */ 1086 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKAUDIOSTARTED field. */ 1087 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_NotGenerated (0UL) /*!< Event not generated */ 1088 #define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Generated (1UL) /*!< Event generated */ 1089 1090 /* Register: CLOCK_EVENTS_HFCLK192MSTARTED */ 1091 /* Description: HFCLK192M source started */ 1092 1093 /* Bit 0 : HFCLK192M source started */ 1094 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLK192MSTARTED field. */ 1095 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLK192MSTARTED field. */ 1096 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_NotGenerated (0UL) /*!< Event not generated */ 1097 #define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Generated (1UL) /*!< Event generated */ 1098 1099 /* Register: CLOCK_PUBLISH_HFCLKSTARTED */ 1100 /* Description: Publish configuration for event HFCLKSTARTED */ 1101 1102 /* Bit 31 : */ 1103 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 1104 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 1105 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 1106 #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 1107 1108 /* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to. */ 1109 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1110 #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1111 1112 /* Register: CLOCK_PUBLISH_LFCLKSTARTED */ 1113 /* Description: Publish configuration for event LFCLKSTARTED */ 1114 1115 /* Bit 31 : */ 1116 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 1117 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 1118 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 1119 #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 1120 1121 /* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to. */ 1122 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1123 #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1124 1125 /* Register: CLOCK_PUBLISH_DONE */ 1126 /* Description: Publish configuration for event DONE */ 1127 1128 /* Bit 31 : */ 1129 #define CLOCK_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */ 1130 #define CLOCK_PUBLISH_DONE_EN_Msk (0x1UL << CLOCK_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */ 1131 #define CLOCK_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */ 1132 #define CLOCK_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */ 1133 1134 /* Bits 7..0 : DPPI channel that event DONE will publish to. */ 1135 #define CLOCK_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1136 #define CLOCK_PUBLISH_DONE_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1137 1138 /* Register: CLOCK_PUBLISH_HFCLKAUDIOSTARTED */ 1139 /* Description: Publish configuration for event HFCLKAUDIOSTARTED */ 1140 1141 /* Bit 31 : */ 1142 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 1143 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 1144 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 1145 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 1146 1147 /* Bits 7..0 : DPPI channel that event HFCLKAUDIOSTARTED will publish to. */ 1148 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1149 #define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1150 1151 /* Register: CLOCK_PUBLISH_HFCLK192MSTARTED */ 1152 /* Description: Publish configuration for event HFCLK192MSTARTED */ 1153 1154 /* Bit 31 : */ 1155 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ 1156 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos) /*!< Bit mask of EN field. */ 1157 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ 1158 #define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ 1159 1160 /* Bits 7..0 : DPPI channel that event HFCLK192MSTARTED will publish to. */ 1161 #define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1162 #define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1163 1164 /* Register: CLOCK_INTEN */ 1165 /* Description: Enable or disable interrupt */ 1166 1167 /* Bit 9 : Enable or disable interrupt for event HFCLK192MSTARTED */ 1168 #define CLOCK_INTEN_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ 1169 #define CLOCK_INTEN_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ 1170 #define CLOCK_INTEN_HFCLK192MSTARTED_Disabled (0UL) /*!< Disable */ 1171 #define CLOCK_INTEN_HFCLK192MSTARTED_Enabled (1UL) /*!< Enable */ 1172 1173 /* Bit 8 : Enable or disable interrupt for event HFCLKAUDIOSTARTED */ 1174 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ 1175 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ 1176 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Disable */ 1177 #define CLOCK_INTEN_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Enable */ 1178 1179 /* Bit 7 : Enable or disable interrupt for event DONE */ 1180 #define CLOCK_INTEN_DONE_Pos (7UL) /*!< Position of DONE field. */ 1181 #define CLOCK_INTEN_DONE_Msk (0x1UL << CLOCK_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ 1182 #define CLOCK_INTEN_DONE_Disabled (0UL) /*!< Disable */ 1183 #define CLOCK_INTEN_DONE_Enabled (1UL) /*!< Enable */ 1184 1185 /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */ 1186 #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 1187 #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 1188 #define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */ 1189 #define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */ 1190 1191 /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */ 1192 #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 1193 #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 1194 #define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */ 1195 #define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */ 1196 1197 /* Register: CLOCK_INTENSET */ 1198 /* Description: Enable interrupt */ 1199 1200 /* Bit 9 : Write '1' to enable interrupt for event HFCLK192MSTARTED */ 1201 #define CLOCK_INTENSET_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ 1202 #define CLOCK_INTENSET_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ 1203 #define CLOCK_INTENSET_HFCLK192MSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1204 #define CLOCK_INTENSET_HFCLK192MSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1205 #define CLOCK_INTENSET_HFCLK192MSTARTED_Set (1UL) /*!< Enable */ 1206 1207 /* Bit 8 : Write '1' to enable interrupt for event HFCLKAUDIOSTARTED */ 1208 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ 1209 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ 1210 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1211 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1212 #define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Set (1UL) /*!< Enable */ 1213 1214 /* Bit 7 : Write '1' to enable interrupt for event DONE */ 1215 #define CLOCK_INTENSET_DONE_Pos (7UL) /*!< Position of DONE field. */ 1216 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 1217 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ 1218 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ 1219 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ 1220 1221 /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ 1222 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 1223 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 1224 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1225 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1226 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ 1227 1228 /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ 1229 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 1230 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 1231 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1232 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1233 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ 1234 1235 /* Register: CLOCK_INTENCLR */ 1236 /* Description: Disable interrupt */ 1237 1238 /* Bit 9 : Write '1' to disable interrupt for event HFCLK192MSTARTED */ 1239 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ 1240 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ 1241 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1242 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1243 #define CLOCK_INTENCLR_HFCLK192MSTARTED_Clear (1UL) /*!< Disable */ 1244 1245 /* Bit 8 : Write '1' to disable interrupt for event HFCLKAUDIOSTARTED */ 1246 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ 1247 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ 1248 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1249 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1250 #define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Clear (1UL) /*!< Disable */ 1251 1252 /* Bit 7 : Write '1' to disable interrupt for event DONE */ 1253 #define CLOCK_INTENCLR_DONE_Pos (7UL) /*!< Position of DONE field. */ 1254 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 1255 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ 1256 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ 1257 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ 1258 1259 /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ 1260 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 1261 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 1262 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1263 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1264 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ 1265 1266 /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ 1267 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 1268 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 1269 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 1270 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 1271 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ 1272 1273 /* Register: CLOCK_INTPEND */ 1274 /* Description: Pending interrupts */ 1275 1276 /* Bit 9 : Read pending status of interrupt for event HFCLK192MSTARTED */ 1277 #define CLOCK_INTPEND_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ 1278 #define CLOCK_INTPEND_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ 1279 #define CLOCK_INTPEND_HFCLK192MSTARTED_NotPending (0UL) /*!< Read: Not pending */ 1280 #define CLOCK_INTPEND_HFCLK192MSTARTED_Pending (1UL) /*!< Read: Pending */ 1281 1282 /* Bit 8 : Read pending status of interrupt for event HFCLKAUDIOSTARTED */ 1283 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ 1284 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ 1285 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_NotPending (0UL) /*!< Read: Not pending */ 1286 #define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pending (1UL) /*!< Read: Pending */ 1287 1288 /* Bit 7 : Read pending status of interrupt for event DONE */ 1289 #define CLOCK_INTPEND_DONE_Pos (7UL) /*!< Position of DONE field. */ 1290 #define CLOCK_INTPEND_DONE_Msk (0x1UL << CLOCK_INTPEND_DONE_Pos) /*!< Bit mask of DONE field. */ 1291 #define CLOCK_INTPEND_DONE_NotPending (0UL) /*!< Read: Not pending */ 1292 #define CLOCK_INTPEND_DONE_Pending (1UL) /*!< Read: Pending */ 1293 1294 /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */ 1295 #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 1296 #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 1297 #define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */ 1298 #define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */ 1299 1300 /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */ 1301 #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 1302 #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 1303 #define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */ 1304 #define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */ 1305 1306 /* Register: CLOCK_HFCLKRUN */ 1307 /* Description: Status indicating that HFCLKSTART task has been triggered */ 1308 1309 /* Bit 0 : HFCLKSTART task triggered or not */ 1310 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1311 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1312 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 1313 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 1314 1315 /* Register: CLOCK_HFCLKSTAT */ 1316 /* Description: Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ 1317 1318 /* Bit 16 : HFCLK state */ 1319 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 1320 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 1321 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ 1322 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ 1323 1324 /* Bit 4 : ALWAYSRUN activated */ 1325 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */ 1326 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */ 1327 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */ 1328 #define CLOCK_HFCLKSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */ 1329 1330 /* Bit 0 : Active clock source */ 1331 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 1332 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 1333 #define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< Clock source: HFINT - 128 MHz on-chip oscillator */ 1334 #define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< Clock source: HFXO - 128 MHz clock derived from external 32 MHz crystal oscillator */ 1335 1336 /* Register: CLOCK_LFCLKRUN */ 1337 /* Description: Status indicating that LFCLKSTART task has been triggered */ 1338 1339 /* Bit 0 : LFCLKSTART task triggered or not */ 1340 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1341 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1342 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 1343 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 1344 1345 /* Register: CLOCK_LFCLKSTAT */ 1346 /* Description: Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ 1347 1348 /* Bit 16 : LFCLK state */ 1349 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 1350 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 1351 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ 1352 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ 1353 1354 /* Bit 4 : ALWAYSRUN activated */ 1355 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */ 1356 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */ 1357 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */ 1358 #define CLOCK_LFCLKSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */ 1359 1360 /* Bits 1..0 : Active clock source */ 1361 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 1362 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 1363 #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ 1364 #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ 1365 #define CLOCK_LFCLKSTAT_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ 1366 1367 /* Register: CLOCK_LFCLKSRCCOPY */ 1368 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ 1369 1370 /* Bits 1..0 : Clock source */ 1371 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ 1372 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ 1373 #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ 1374 #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ 1375 #define CLOCK_LFCLKSRCCOPY_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ 1376 1377 /* Register: CLOCK_HFCLKAUDIORUN */ 1378 /* Description: Status indicating that HFCLKAUDIOSTART task has been triggered */ 1379 1380 /* Bit 0 : HFCLKAUDIOSTART task triggered or not */ 1381 #define CLOCK_HFCLKAUDIORUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1382 #define CLOCK_HFCLKAUDIORUN_STATUS_Msk (0x1UL << CLOCK_HFCLKAUDIORUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1383 #define CLOCK_HFCLKAUDIORUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 1384 #define CLOCK_HFCLKAUDIORUN_STATUS_Triggered (1UL) /*!< Task triggered */ 1385 1386 /* Register: CLOCK_HFCLKAUDIOSTAT */ 1387 /* Description: Status indicating which HFCLKAUDIO source is running */ 1388 1389 /* Bit 16 : HFCLKAUDIO state */ 1390 #define CLOCK_HFCLKAUDIOSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 1391 #define CLOCK_HFCLKAUDIOSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 1392 #define CLOCK_HFCLKAUDIOSTAT_STATE_NotRunning (0UL) /*!< HFCLKAUDIO not running */ 1393 #define CLOCK_HFCLKAUDIOSTAT_STATE_Running (1UL) /*!< HFCLKAUDIO running */ 1394 1395 /* Bit 4 : ALWAYSRUN activated */ 1396 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */ 1397 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */ 1398 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */ 1399 #define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */ 1400 1401 /* Register: CLOCK_HFCLK192MRUN */ 1402 /* Description: Status indicating that HFCLK192MSTART task has been triggered */ 1403 1404 /* Bit 0 : HFCLK192MSTART task triggered or not */ 1405 #define CLOCK_HFCLK192MRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1406 #define CLOCK_HFCLK192MRUN_STATUS_Msk (0x1UL << CLOCK_HFCLK192MRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1407 #define CLOCK_HFCLK192MRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 1408 #define CLOCK_HFCLK192MRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 1409 1410 /* Register: CLOCK_HFCLK192MSTAT */ 1411 /* Description: Status indicating which HFCLK192M source is running */ 1412 1413 /* Bit 16 : HFCLK192M state */ 1414 #define CLOCK_HFCLK192MSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 1415 #define CLOCK_HFCLK192MSTAT_STATE_Msk (0x1UL << CLOCK_HFCLK192MSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 1416 #define CLOCK_HFCLK192MSTAT_STATE_NotRunning (0UL) /*!< HFCLK192M not running */ 1417 #define CLOCK_HFCLK192MSTAT_STATE_Running (1UL) /*!< HFCLK192M running */ 1418 1419 /* Bit 4 : ALWAYSRUN activated */ 1420 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */ 1421 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */ 1422 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */ 1423 #define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */ 1424 1425 /* Bit 0 : Active clock source */ 1426 #define CLOCK_HFCLK192MSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 1427 #define CLOCK_HFCLK192MSTAT_SRC_Msk (0x1UL << CLOCK_HFCLK192MSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 1428 #define CLOCK_HFCLK192MSTAT_SRC_HFINT (0UL) /*!< Clock source: HFINT - on-chip oscillator */ 1429 #define CLOCK_HFCLK192MSTAT_SRC_HFXO (1UL) /*!< Clock source: HFXO - derived from external 32 MHz crystal oscillator */ 1430 1431 /* Register: CLOCK_HFCLKSRC */ 1432 /* Description: Clock source for HFCLK128M/HFCLK64M */ 1433 1434 /* Bit 0 : Select which HFCLK source is started by the HFCLKSTART task */ 1435 #define CLOCK_HFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 1436 #define CLOCK_HFCLKSRC_SRC_Msk (0x1UL << CLOCK_HFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 1437 #define CLOCK_HFCLKSRC_SRC_HFINT (0UL) /*!< HFCLKSTART task starts HFINT oscillator */ 1438 #define CLOCK_HFCLKSRC_SRC_HFXO (1UL) /*!< HFCLKSTART task starts HFXO oscillator */ 1439 1440 /* Register: CLOCK_LFCLKSRC */ 1441 /* Description: Clock source for LFCLK */ 1442 1443 /* Bits 1..0 : Select which LFCLK source is started by the LFCLKSTART task */ 1444 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 1445 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 1446 #define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ 1447 #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ 1448 #define CLOCK_LFCLKSRC_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ 1449 1450 /* Register: CLOCK_HFCLKCTRL */ 1451 /* Description: HFCLK128M frequency configuration */ 1452 1453 /* Bits 1..0 : High frequency clock HCLK */ 1454 #define CLOCK_HFCLKCTRL_HCLK_Pos (0UL) /*!< Position of HCLK field. */ 1455 #define CLOCK_HFCLKCTRL_HCLK_Msk (0x3UL << CLOCK_HFCLKCTRL_HCLK_Pos) /*!< Bit mask of HCLK field. */ 1456 #define CLOCK_HFCLKCTRL_HCLK_Div1 (0UL) /*!< Divide HFCLK by 1 */ 1457 #define CLOCK_HFCLKCTRL_HCLK_Div2 (1UL) /*!< Divide HFCLK by 2 */ 1458 1459 /* Register: CLOCK_HFCLKAUDIO_FREQUENCY */ 1460 /* Description: Audio PLL frequency in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands */ 1461 1462 /* Bits 15..0 : Frequency 0: 10.666 MHz 65535: 13.333 MHz */ 1463 #define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 1464 #define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Msk (0xFFFFUL << CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 1465 1466 /* Register: CLOCK_HFCLKALWAYSRUN */ 1467 /* Description: Automatic or manual control of HFCLK128M/HFCLK64M */ 1468 1469 /* Bit 0 : Ensure clock is always running */ 1470 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */ 1471 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */ 1472 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */ 1473 #define CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */ 1474 1475 /* Register: CLOCK_LFCLKALWAYSRUN */ 1476 /* Description: Automatic or manual control of LFCLK */ 1477 1478 /* Bit 0 : Ensure clock is always running */ 1479 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */ 1480 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */ 1481 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */ 1482 #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */ 1483 1484 /* Register: CLOCK_HFCLKAUDIOALWAYSRUN */ 1485 /* Description: Automatic or manual control of HFCLKAUDIO */ 1486 1487 /* Bit 0 : Ensure clock is always running */ 1488 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */ 1489 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */ 1490 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */ 1491 #define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */ 1492 1493 /* Register: CLOCK_HFCLK192MSRC */ 1494 /* Description: Clock source for HFCLK192M */ 1495 1496 /* Bit 0 : Select which HFCLK192M source is started by the HFCLK192MSTART task */ 1497 #define CLOCK_HFCLK192MSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 1498 #define CLOCK_HFCLK192MSRC_SRC_Msk (0x1UL << CLOCK_HFCLK192MSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 1499 #define CLOCK_HFCLK192MSRC_SRC_HFINT (0UL) /*!< HFCLK192MSTART task starts HFINT oscillator */ 1500 #define CLOCK_HFCLK192MSRC_SRC_HFXO (1UL) /*!< HFCLK192MSTART task starts HFXO oscillator */ 1501 1502 /* Register: CLOCK_HFCLK192MALWAYSRUN */ 1503 /* Description: Automatic or manual control of HFCLK192M */ 1504 1505 /* Bit 0 : Ensure clock is always running */ 1506 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */ 1507 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */ 1508 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */ 1509 #define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */ 1510 1511 /* Register: CLOCK_HFCLK192MCTRL */ 1512 /* Description: HFCLK192M frequency configuration */ 1513 1514 /* Bits 1..0 : High frequency clock HCLK192M */ 1515 #define CLOCK_HFCLK192MCTRL_HCLK192M_Pos (0UL) /*!< Position of HCLK192M field. */ 1516 #define CLOCK_HFCLK192MCTRL_HCLK192M_Msk (0x3UL << CLOCK_HFCLK192MCTRL_HCLK192M_Pos) /*!< Bit mask of HCLK192M field. */ 1517 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div1 (0UL) /*!< Divide HFCLK192M by 1 */ 1518 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div2 (1UL) /*!< Divide HFCLK192M by 2 */ 1519 #define CLOCK_HFCLK192MCTRL_HCLK192M_Div4 (2UL) /*!< Divide HFCLK192M by 4 */ 1520 1521 /* =========================================================================================================================== */ 1522 /* ================ ECB_NS ================ */ 1523 /* =========================================================================================================================== */ 1524 1525 1526 /** 1527 * @brief AES ECB Mode Encryption (ECB_NS) 1528 */ 1529 1530 typedef struct { /*!< (@ 0x4100D000) ECB_NS Structure */ 1531 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1532 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1533 __IM uint32_t RESERVED[30]; 1534 __IOM uint32_t SUBSCRIBE_STARTECB; /*!< (@ 0x00000080) Subscribe configuration for task STARTECB */ 1535 __IOM uint32_t SUBSCRIBE_STOPECB; /*!< (@ 0x00000084) Subscribe configuration for task STOPECB */ 1536 __IM uint32_t RESERVED1[30]; 1537 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1538 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1539 task or due to an error */ 1540 __IM uint32_t RESERVED2[30]; 1541 __IOM uint32_t PUBLISH_ENDECB; /*!< (@ 0x00000180) Publish configuration for event ENDECB */ 1542 __IOM uint32_t PUBLISH_ERRORECB; /*!< (@ 0x00000184) Publish configuration for event ERRORECB */ 1543 __IM uint32_t RESERVED3[95]; 1544 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1545 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1546 __IM uint32_t RESERVED4[126]; 1547 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1548 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1549 1550 1551 /* Peripheral: ECB */ 1552 /* Description: AES ECB Mode Encryption */ 1553 1554 /* Register: ECB_TASKS_STARTECB */ 1555 /* Description: Start ECB block encrypt */ 1556 1557 /* Bit 0 : Start ECB block encrypt */ 1558 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ 1559 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ 1560 #define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */ 1561 1562 /* Register: ECB_TASKS_STOPECB */ 1563 /* Description: Abort a possible executing ECB operation */ 1564 1565 /* Bit 0 : Abort a possible executing ECB operation */ 1566 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ 1567 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ 1568 #define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */ 1569 1570 /* Register: ECB_SUBSCRIBE_STARTECB */ 1571 /* Description: Subscribe configuration for task STARTECB */ 1572 1573 /* Bit 31 : */ 1574 #define ECB_SUBSCRIBE_STARTECB_EN_Pos (31UL) /*!< Position of EN field. */ 1575 #define ECB_SUBSCRIBE_STARTECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STARTECB_EN_Pos) /*!< Bit mask of EN field. */ 1576 #define ECB_SUBSCRIBE_STARTECB_EN_Disabled (0UL) /*!< Disable subscription */ 1577 #define ECB_SUBSCRIBE_STARTECB_EN_Enabled (1UL) /*!< Enable subscription */ 1578 1579 /* Bits 7..0 : DPPI channel that task STARTECB will subscribe to */ 1580 #define ECB_SUBSCRIBE_STARTECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1581 #define ECB_SUBSCRIBE_STARTECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STARTECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1582 1583 /* Register: ECB_SUBSCRIBE_STOPECB */ 1584 /* Description: Subscribe configuration for task STOPECB */ 1585 1586 /* Bit 31 : */ 1587 #define ECB_SUBSCRIBE_STOPECB_EN_Pos (31UL) /*!< Position of EN field. */ 1588 #define ECB_SUBSCRIBE_STOPECB_EN_Msk (0x1UL << ECB_SUBSCRIBE_STOPECB_EN_Pos) /*!< Bit mask of EN field. */ 1589 #define ECB_SUBSCRIBE_STOPECB_EN_Disabled (0UL) /*!< Disable subscription */ 1590 #define ECB_SUBSCRIBE_STOPECB_EN_Enabled (1UL) /*!< Enable subscription */ 1591 1592 /* Bits 7..0 : DPPI channel that task STOPECB will subscribe to */ 1593 #define ECB_SUBSCRIBE_STOPECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1594 #define ECB_SUBSCRIBE_STOPECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STOPECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1595 1596 /* Register: ECB_EVENTS_ENDECB */ 1597 /* Description: ECB block encrypt complete */ 1598 1599 /* Bit 0 : ECB block encrypt complete */ 1600 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ 1601 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ 1602 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */ 1603 #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */ 1604 1605 /* Register: ECB_EVENTS_ERRORECB */ 1606 /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ 1607 1608 /* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */ 1609 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ 1610 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ 1611 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */ 1612 #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */ 1613 1614 /* Register: ECB_PUBLISH_ENDECB */ 1615 /* Description: Publish configuration for event ENDECB */ 1616 1617 /* Bit 31 : */ 1618 #define ECB_PUBLISH_ENDECB_EN_Pos (31UL) /*!< Position of EN field. */ 1619 #define ECB_PUBLISH_ENDECB_EN_Msk (0x1UL << ECB_PUBLISH_ENDECB_EN_Pos) /*!< Bit mask of EN field. */ 1620 #define ECB_PUBLISH_ENDECB_EN_Disabled (0UL) /*!< Disable publishing */ 1621 #define ECB_PUBLISH_ENDECB_EN_Enabled (1UL) /*!< Enable publishing */ 1622 1623 /* Bits 7..0 : DPPI channel that event ENDECB will publish to. */ 1624 #define ECB_PUBLISH_ENDECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1625 #define ECB_PUBLISH_ENDECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ENDECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1626 1627 /* Register: ECB_PUBLISH_ERRORECB */ 1628 /* Description: Publish configuration for event ERRORECB */ 1629 1630 /* Bit 31 : */ 1631 #define ECB_PUBLISH_ERRORECB_EN_Pos (31UL) /*!< Position of EN field. */ 1632 #define ECB_PUBLISH_ERRORECB_EN_Msk (0x1UL << ECB_PUBLISH_ERRORECB_EN_Pos) /*!< Bit mask of EN field. */ 1633 #define ECB_PUBLISH_ERRORECB_EN_Disabled (0UL) /*!< Disable publishing */ 1634 #define ECB_PUBLISH_ERRORECB_EN_Enabled (1UL) /*!< Enable publishing */ 1635 1636 /* Bits 7..0 : DPPI channel that event ERRORECB will publish to. */ 1637 #define ECB_PUBLISH_ERRORECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1638 #define ECB_PUBLISH_ERRORECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ERRORECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1639 1640 /* Register: ECB_INTENSET */ 1641 /* Description: Enable interrupt */ 1642 1643 /* Bit 1 : Write '1' to enable interrupt for event ERRORECB */ 1644 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 1645 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 1646 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ 1647 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ 1648 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ 1649 1650 /* Bit 0 : Write '1' to enable interrupt for event ENDECB */ 1651 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 1652 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 1653 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ 1654 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ 1655 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ 1656 1657 /* Register: ECB_INTENCLR */ 1658 /* Description: Disable interrupt */ 1659 1660 /* Bit 1 : Write '1' to disable interrupt for event ERRORECB */ 1661 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 1662 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 1663 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ 1664 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ 1665 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ 1666 1667 /* Bit 0 : Write '1' to disable interrupt for event ENDECB */ 1668 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 1669 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 1670 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ 1671 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ 1672 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ 1673 1674 /* Register: ECB_ECBDATAPTR */ 1675 /* Description: ECB block encrypt memory pointers */ 1676 1677 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ 1678 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ 1679 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ 1680 1681 1682 /* =========================================================================================================================== */ 1683 /* ================ EGU ================ */ 1684 /* =========================================================================================================================== */ 1685 1686 1687 /** 1688 * @brief Event generator unit 0 (EGU0_NS) 1689 */ 1690 1691 typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ 1692 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1693 the corresponding TRIGGERED[n] event */ 1694 __IM uint32_t RESERVED[16]; 1695 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1696 for task TRIGGER[n] */ 1697 __IM uint32_t RESERVED1[16]; 1698 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1699 by triggering the corresponding TRIGGER[n] 1700 task */ 1701 __IM uint32_t RESERVED2[16]; 1702 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 1703 for event TRIGGERED[n] */ 1704 __IM uint32_t RESERVED3[80]; 1705 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1706 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1707 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1708 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1709 1710 /* Peripheral: EGU */ 1711 /* Description: Event generator unit */ 1712 1713 /* Register: EGU_TASKS_TRIGGER */ 1714 /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ 1715 1716 /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ 1717 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ 1718 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ 1719 #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ 1720 1721 /* Register: EGU_SUBSCRIBE_TRIGGER */ 1722 /* Description: Description collection: Subscribe configuration for task TRIGGER[n] */ 1723 1724 /* Bit 31 : */ 1725 #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ 1726 #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */ 1727 #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */ 1728 #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */ 1729 1730 /* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */ 1731 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1732 #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1733 1734 /* Register: EGU_EVENTS_TRIGGERED */ 1735 /* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ 1736 1737 /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ 1738 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ 1739 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ 1740 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ 1741 #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ 1742 1743 /* Register: EGU_PUBLISH_TRIGGERED */ 1744 /* Description: Description collection: Publish configuration for event TRIGGERED[n] */ 1745 1746 /* Bit 31 : */ 1747 #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ 1748 #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */ 1749 #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */ 1750 #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */ 1751 1752 /* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to. */ 1753 #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1754 #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1755 1756 /* Register: EGU_INTEN */ 1757 /* Description: Enable or disable interrupt */ 1758 1759 /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ 1760 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1761 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1762 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ 1763 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ 1764 1765 /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ 1766 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1767 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1768 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ 1769 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ 1770 1771 /* Register: EGU_INTENSET */ 1772 /* Description: Enable interrupt */ 1773 1774 /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ 1775 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1776 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1777 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 1778 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 1779 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ 1780 1781 /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ 1782 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1783 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1784 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 1785 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 1786 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ 1787 1788 /* Register: EGU_INTENCLR */ 1789 /* Description: Disable interrupt */ 1790 1791 /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ 1792 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 1793 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 1794 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 1795 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 1796 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ 1797 1798 /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ 1799 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 1800 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 1801 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 1802 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 1803 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ 1804 1805 1806 1807 1808 /* =========================================================================================================================== */ 1809 /* ================ DPPIC_NS ================ */ 1810 /* =========================================================================================================================== */ 1811 1812 1813 /** 1814 * @brief Distributed programmable peripheral interconnect controller (DPPIC_NS) 1815 */ 1816 1817 typedef struct { /*!< (@ 0x4100F000) DPPIC_NS Structure */ 1818 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1819 __IM uint32_t RESERVED[20]; 1820 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 1821 __IM uint32_t RESERVED1[276]; 1822 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1823 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1824 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1825 __IM uint32_t RESERVED2[189]; 1826 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 1827 Writes to this register are ignored if either 1828 SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS 1829 is enabled */ 1830 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 1831 1832 1833 1834 /* Peripheral: DPPIC */ 1835 /* Description: Distributed programmable peripheral interconnect controller */ 1836 1837 /* Register: DPPIC_TASKS_CHG_EN */ 1838 /* Description: Description cluster: Enable channel group n */ 1839 1840 /* Bit 0 : Enable channel group n */ 1841 #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ 1842 #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ 1843 #define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ 1844 1845 /* Register: DPPIC_TASKS_CHG_DIS */ 1846 /* Description: Description cluster: Disable channel group n */ 1847 1848 /* Bit 0 : Disable channel group n */ 1849 #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ 1850 #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ 1851 #define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ 1852 1853 /* Register: DPPIC_SUBSCRIBE_CHG_EN */ 1854 /* Description: Description cluster: Subscribe configuration for task CHG[n].EN */ 1855 1856 /* Bit 31 : */ 1857 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */ 1858 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ 1859 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */ 1860 #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */ 1861 1862 /* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */ 1863 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1864 #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1865 1866 /* Register: DPPIC_SUBSCRIBE_CHG_DIS */ 1867 /* Description: Description cluster: Subscribe configuration for task CHG[n].DIS */ 1868 1869 /* Bit 31 : */ 1870 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */ 1871 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */ 1872 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */ 1873 #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */ 1874 1875 /* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */ 1876 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 1877 #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 1878 1879 /* Register: DPPIC_CHEN */ 1880 /* Description: Channel enable register */ 1881 1882 /* Bit 31 : Enable or disable channel 31 */ 1883 #define DPPIC_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ 1884 #define DPPIC_CHEN_CH31_Msk (0x1UL << DPPIC_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ 1885 #define DPPIC_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ 1886 #define DPPIC_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ 1887 1888 /* Bit 0 : Enable or disable channel 0 */ 1889 #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ 1890 #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ 1891 #define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ 1892 #define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ 1893 1894 /* Register: DPPIC_CHENSET */ 1895 /* Description: Channel enable set register */ 1896 1897 /* Bit 31 : Channel 31 enable set register. Writing 0 has no effect. */ 1898 #define DPPIC_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ 1899 #define DPPIC_CHENSET_CH31_Msk (0x1UL << DPPIC_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ 1900 #define DPPIC_CHENSET_CH31_Disabled (0UL) /*!< Read: Channel disabled */ 1901 #define DPPIC_CHENSET_CH31_Enabled (1UL) /*!< Read: Channel enabled */ 1902 #define DPPIC_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ 1903 1904 /* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */ 1905 #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ 1906 #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ 1907 #define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */ 1908 #define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */ 1909 #define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ 1910 1911 /* Register: DPPIC_CHENCLR */ 1912 /* Description: Channel enable clear register */ 1913 1914 /* Bit 31 : Channel 31 enable clear register. Writing 0 has no effect. */ 1915 #define DPPIC_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ 1916 #define DPPIC_CHENCLR_CH31_Msk (0x1UL << DPPIC_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ 1917 #define DPPIC_CHENCLR_CH31_Disabled (0UL) /*!< Read: Channel disabled */ 1918 #define DPPIC_CHENCLR_CH31_Enabled (1UL) /*!< Read: Channel enabled */ 1919 #define DPPIC_CHENCLR_CH31_Clear (1UL) /*!< Write: Disable channel */ 1920 1921 /* Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */ 1922 #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ 1923 #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ 1924 #define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */ 1925 #define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */ 1926 #define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */ 1927 1928 /* Register: DPPIC_CHG */ 1929 /* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */ 1930 1931 /* Bit 31 : Include or exclude channel 31 */ 1932 #define DPPIC_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ 1933 #define DPPIC_CHG_CH31_Msk (0x1UL << DPPIC_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ 1934 #define DPPIC_CHG_CH31_Excluded (0UL) /*!< Exclude */ 1935 #define DPPIC_CHG_CH31_Included (1UL) /*!< Include */ 1936 1937 /* Bit 0 : Include or exclude channel 0 */ 1938 #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ 1939 #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ 1940 #define DPPIC_CHG_CH0_Excluded (0UL) /*!< Exclude */ 1941 #define DPPIC_CHG_CH0_Included (1UL) /*!< Include */ 1942 1943 /* =========================================================================================================================== */ 1944 /* ================ FICR ================ */ 1945 /* =========================================================================================================================== */ 1946 1947 1948 /** 1949 * @brief Factory Information Configuration Registers (FICR) 1950 */ 1951 1952 typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ 1953 __IM uint32_t RESERVED[128]; 1954 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 1955 __IM uint32_t RESERVED1[53]; 1956 __IOM FICR_TRIMCNF_Type TRIMCNF[32]; /*!< (@ 0x00000300) Unspecified */ 1957 __IM uint32_t RESERVED2[20]; 1958 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 1959 __IM uint32_t RESERVED3[488]; 1960 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 1961 __IM uint32_t XOSC32MTRIM; /*!< (@ 0x00000C20) XOSC32M capacitor selection trim values */ 1962 } NRF_FICR_APP_Type; /*!< Size = 3108 (0xc24) */ 1963 1964 typedef struct { /*!< (@ 0x01FF0000) FICR_NS Structure */ 1965 __IM uint32_t RESERVED[128]; 1966 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 1967 __IM uint32_t RESERVED1[21]; 1968 __IM uint32_t ER[4]; /*!< (@ 0x00000280) Description collection: Encryption Root, word 1969 n */ 1970 __IM uint32_t IR[4]; /*!< (@ 0x00000290) Description collection: Identity Root, word n */ 1971 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000002A0) Device address type */ 1972 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000002A4) Description collection: Device address n */ 1973 __IM uint32_t RESERVED2[21]; 1974 __IOM FICR_TRIMCNF_Type TRIMCNF[32]; /*!< (@ 0x00000300) Unspecified */ 1975 } NRF_FICR_NET_Type; /*!< Size = 1024 (0x400) */ 1976 1977 1978 /* =========================================================================================================================== */ 1979 /* ================ NVMC ================ */ 1980 /* =========================================================================================================================== */ 1981 1982 1983 /** 1984 * @brief Non-volatile memory controller (NVMC) 1985 * 1986 * Note: This is the app core register layouts 1987 * as by now the icache registers are just ignored 1988 */ 1989 1990 typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ 1991 __IM uint32_t RESERVED[256]; 1992 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1993 __IM uint32_t RESERVED1; 1994 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 1995 __IM uint32_t RESERVED2[62]; 1996 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1997 __IM uint32_t RESERVED3; 1998 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1999 __IM uint32_t RESERVED4[3]; 2000 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 2001 __IM uint32_t RESERVED5[25]; 2002 __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Non-secure configuration register */ 2003 __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ 2004 } NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ 2005 2006 2007 /* Peripheral: NVMC */ 2008 /* Description: Non-volatile memory controller */ 2009 2010 /* Register: NVMC_READY */ 2011 /* Description: Ready flag */ 2012 2013 /* Bit 0 : NVMC is ready or busy */ 2014 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ 2015 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ 2016 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */ 2017 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ 2018 2019 /* Register: NVMC_READYNEXT */ 2020 /* Description: Ready flag */ 2021 2022 /* Bit 0 : NVMC can accept a new write operation */ 2023 #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */ 2024 #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ 2025 #define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */ 2026 #define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */ 2027 2028 /* Register: NVMC_CONFIG */ 2029 /* Description: Configuration register */ 2030 2031 /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ 2032 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ 2033 #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ 2034 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ 2035 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ 2036 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ 2037 #define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */ 2038 2039 /* Register: NVMC_ERASEALL */ 2040 /* Description: Register for erasing all non-volatile user memory */ 2041 2042 /* Bit 0 : Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. */ 2043 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ 2044 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ 2045 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ 2046 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ 2047 2048 /* Register: NVMC_ERASEPAGEPARTIALCFG */ 2049 /* Description: Register for partial erase configuration */ 2050 2051 /* Bits 6..0 : Duration of the partial erase in milliseconds */ 2052 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ 2053 #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ 2054 2055 2056 /* =========================================================================================================================== */ 2057 /* ================ POWER_NS ================ */ 2058 /* =========================================================================================================================== */ 2059 2060 2061 /** 2062 * @brief Power control 0 (POWER_NS) 2063 */ 2064 2065 typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ 2066 __IM uint32_t RESERVED[30]; 2067 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 2068 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-Power mode (variable latency) */ 2069 __IM uint32_t RESERVED1[30]; 2070 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 2071 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 2072 __IM uint32_t RESERVED2[2]; 2073 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 2074 __IM uint32_t RESERVED3[2]; 2075 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 2076 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 2077 __IM uint32_t RESERVED4[27]; 2078 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 2079 __IM uint32_t RESERVED5[2]; 2080 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 2081 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 2082 __IM uint32_t RESERVED6[89]; 2083 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2084 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2085 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2086 __IM uint32_t RESERVED7[132]; 2087 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 2088 register */ 2089 } NRF_POWER_Type; /*!< Size = 1316 (0x524) */ 2090 2091 2092 /* =========================================================================================================================== */ 2093 /* ================ RESET ================ */ 2094 /* =========================================================================================================================== */ 2095 2096 2097 /** 2098 * @brief Reset control (RESET) 2099 */ 2100 2101 typedef struct { /*!< (@ 0x40005000) RESET_NS Structure */ 2102 __IM uint32_t RESERVED[256]; 2103 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 2104 __IM uint32_t RESERVED1[131]; 2105 __IOM RESET_NETWORK_Type NETWORK; /*!< (@ 0x00000610) ULP network core control */ 2106 } NRF_RESET_Type; /*!< Size = 1560 (0x618) */ 2107 2108 2109 2110 /* =========================================================================================================================== */ 2111 /* ================ RADIO_NS ================ */ 2112 /* =========================================================================================================================== */ 2113 2114 2115 /** 2116 * @brief 2.4 GHz radio (RADIO_NS) 2117 */ 2118 2119 typedef struct { /*!< (@ 0x41008000) RADIO_NS Structure */ 2120 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 2121 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 2122 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 2123 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 2124 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 2125 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 2126 the receive signal strength */ 2127 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 2128 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 2129 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 2130 __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 2131 802.15.4 mode */ 2132 __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 2133 __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 2134 802.15.4 mode */ 2135 __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 2136 __IM uint32_t RESERVED[19]; 2137 __IOM uint32_t SUBSCRIBE_TXEN; /*!< (@ 0x00000080) Subscribe configuration for task TXEN */ 2138 __IOM uint32_t SUBSCRIBE_RXEN; /*!< (@ 0x00000084) Subscribe configuration for task RXEN */ 2139 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000088) Subscribe configuration for task START */ 2140 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x0000008C) Subscribe configuration for task STOP */ 2141 __IOM uint32_t SUBSCRIBE_DISABLE; /*!< (@ 0x00000090) Subscribe configuration for task DISABLE */ 2142 __IOM uint32_t SUBSCRIBE_RSSISTART; /*!< (@ 0x00000094) Subscribe configuration for task RSSISTART */ 2143 __IOM uint32_t SUBSCRIBE_RSSISTOP; /*!< (@ 0x00000098) Subscribe configuration for task RSSISTOP */ 2144 __IOM uint32_t SUBSCRIBE_BCSTART; /*!< (@ 0x0000009C) Subscribe configuration for task BCSTART */ 2145 __IOM uint32_t SUBSCRIBE_BCSTOP; /*!< (@ 0x000000A0) Subscribe configuration for task BCSTOP */ 2146 __IOM uint32_t SUBSCRIBE_EDSTART; /*!< (@ 0x000000A4) Subscribe configuration for task EDSTART */ 2147 __IOM uint32_t SUBSCRIBE_EDSTOP; /*!< (@ 0x000000A8) Subscribe configuration for task EDSTOP */ 2148 __IOM uint32_t SUBSCRIBE_CCASTART; /*!< (@ 0x000000AC) Subscribe configuration for task CCASTART */ 2149 __IOM uint32_t SUBSCRIBE_CCASTOP; /*!< (@ 0x000000B0) Subscribe configuration for task CCASTOP */ 2150 __IM uint32_t RESERVED1[19]; 2151 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 2152 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 2153 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 2154 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 2155 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 2156 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 2157 packet */ 2158 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 2159 received packet */ 2160 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 2161 __IM uint32_t RESERVED2[2]; 2162 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 2163 __IM uint32_t RESERVED3; 2164 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 2165 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 2166 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 2167 __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 2168 ED sample is ready for readout from the 2169 RADIO.EDSAMPLE register. */ 2170 __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 2171 __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 2172 __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 2173 __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 2174 __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 2175 from Ble_LR125Kbit to Ble_LR500Kbit. */ 2176 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 2177 TX path */ 2178 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 2179 RX path */ 2180 __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 2181 __IM uint32_t RESERVED4[2]; 2182 __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator */ 2183 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received 2184 from air */ 2185 __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving 2186 CTEInfo byte) */ 2187 __IM uint32_t RESERVED5[3]; 2188 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 2189 __IOM uint32_t PUBLISH_ADDRESS; /*!< (@ 0x00000184) Publish configuration for event ADDRESS */ 2190 __IOM uint32_t PUBLISH_PAYLOAD; /*!< (@ 0x00000188) Publish configuration for event PAYLOAD */ 2191 __IOM uint32_t PUBLISH_END; /*!< (@ 0x0000018C) Publish configuration for event END */ 2192 __IOM uint32_t PUBLISH_DISABLED; /*!< (@ 0x00000190) Publish configuration for event DISABLED */ 2193 __IOM uint32_t PUBLISH_DEVMATCH; /*!< (@ 0x00000194) Publish configuration for event DEVMATCH */ 2194 __IOM uint32_t PUBLISH_DEVMISS; /*!< (@ 0x00000198) Publish configuration for event DEVMISS */ 2195 __IOM uint32_t PUBLISH_RSSIEND; /*!< (@ 0x0000019C) Publish configuration for event RSSIEND */ 2196 __IM uint32_t RESERVED6[2]; 2197 __IOM uint32_t PUBLISH_BCMATCH; /*!< (@ 0x000001A8) Publish configuration for event BCMATCH */ 2198 __IM uint32_t RESERVED7; 2199 __IOM uint32_t PUBLISH_CRCOK; /*!< (@ 0x000001B0) Publish configuration for event CRCOK */ 2200 __IOM uint32_t PUBLISH_CRCERROR; /*!< (@ 0x000001B4) Publish configuration for event CRCERROR */ 2201 __IOM uint32_t PUBLISH_FRAMESTART; /*!< (@ 0x000001B8) Publish configuration for event FRAMESTART */ 2202 __IOM uint32_t PUBLISH_EDEND; /*!< (@ 0x000001BC) Publish configuration for event EDEND */ 2203 __IOM uint32_t PUBLISH_EDSTOPPED; /*!< (@ 0x000001C0) Publish configuration for event EDSTOPPED */ 2204 __IOM uint32_t PUBLISH_CCAIDLE; /*!< (@ 0x000001C4) Publish configuration for event CCAIDLE */ 2205 __IOM uint32_t PUBLISH_CCABUSY; /*!< (@ 0x000001C8) Publish configuration for event CCABUSY */ 2206 __IOM uint32_t PUBLISH_CCASTOPPED; /*!< (@ 0x000001CC) Publish configuration for event CCASTOPPED */ 2207 __IOM uint32_t PUBLISH_RATEBOOST; /*!< (@ 0x000001D0) Publish configuration for event RATEBOOST */ 2208 __IOM uint32_t PUBLISH_TXREADY; /*!< (@ 0x000001D4) Publish configuration for event TXREADY */ 2209 __IOM uint32_t PUBLISH_RXREADY; /*!< (@ 0x000001D8) Publish configuration for event RXREADY */ 2210 __IOM uint32_t PUBLISH_MHRMATCH; /*!< (@ 0x000001DC) Publish configuration for event MHRMATCH */ 2211 __IM uint32_t RESERVED8[2]; 2212 __IOM uint32_t PUBLISH_SYNC; /*!< (@ 0x000001E8) Publish configuration for event SYNC */ 2213 __IOM uint32_t PUBLISH_PHYEND; /*!< (@ 0x000001EC) Publish configuration for event PHYEND */ 2214 __IOM uint32_t PUBLISH_CTEPRESENT; /*!< (@ 0x000001F0) Publish configuration for event CTEPRESENT */ 2215 __IM uint32_t RESERVED9[3]; 2216 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2217 __IM uint32_t RESERVED10[64]; 2218 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2219 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2220 __IM uint32_t RESERVED11[61]; 2221 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 2222 __IM uint32_t RESERVED12; 2223 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 2224 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 2225 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 2226 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 2227 __IM uint32_t RESERVED13[13]; 2228 __IM uint32_t CTESTATUS; /*!< (@ 0x0000044C) CTEInfo parsed from received packet */ 2229 __IM uint32_t RESERVED14[2]; 2230 __IM uint32_t DFESTATUS; /*!< (@ 0x00000458) DFE status information */ 2231 __IM uint32_t RESERVED15[42]; 2232 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 2233 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 2234 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 2235 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 2236 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 2237 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 2238 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 2239 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 2240 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 2241 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 2242 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 2243 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 2244 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 2245 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 2246 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 2247 __IM uint32_t RESERVED16; 2248 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 2249 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 2250 __IM uint32_t RESERVED17; 2251 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 2252 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 2253 __IM uint32_t RESERVED18[2]; 2254 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 2255 __IM uint32_t RESERVED19[39]; 2256 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 2257 n */ 2258 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 2259 n */ 2260 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 2261 __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 2262 __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 2263 __IM uint32_t RESERVED20; 2264 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 2265 __IM uint32_t RESERVED21[3]; 2266 __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 2267 __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 2268 __IM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 2269 __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 2270 __IM uint32_t RESERVED22[164]; 2271 __IOM uint32_t DFEMODE; /*!< (@ 0x00000900) Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure 2272 (AOD) */ 2273 __IOM uint32_t CTEINLINECONF; /*!< (@ 0x00000904) Configuration for CTE inline mode */ 2274 __IM uint32_t RESERVED23[2]; 2275 __IOM uint32_t DFECTRL1; /*!< (@ 0x00000910) Various configuration for Direction finding */ 2276 __IOM uint32_t DFECTRL2; /*!< (@ 0x00000914) Start offset for Direction finding */ 2277 __IM uint32_t RESERVED24[4]; 2278 __IOM uint32_t SWITCHPATTERN; /*!< (@ 0x00000928) GPIO patterns to be used for each antenna */ 2279 __IOM uint32_t CLEARPATTERN; /*!< (@ 0x0000092C) Clear the GPIO pattern array for antenna control */ 2280 __IOM RADIO_PSEL_Type PSEL; /*!< (@ 0x00000930) Unspecified */ 2281 __IOM RADIO_DFEPACKET_Type DFEPACKET; /*!< (@ 0x00000950) DFE packet EasyDMA channel */ 2282 __IM uint32_t RESERVED25[424]; 2283 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 2284 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 2285 2286 2287 /* Peripheral: RADIO */ 2288 /* Description: 2.4 GHz radio */ 2289 2290 /* Register: RADIO_TASKS_TXEN */ 2291 /* Description: Enable RADIO in TX mode */ 2292 2293 /* Bit 0 : Enable RADIO in TX mode */ 2294 #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ 2295 #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ 2296 #define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */ 2297 2298 /* Register: RADIO_TASKS_RXEN */ 2299 /* Description: Enable RADIO in RX mode */ 2300 2301 /* Bit 0 : Enable RADIO in RX mode */ 2302 #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ 2303 #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ 2304 #define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */ 2305 2306 /* Register: RADIO_TASKS_START */ 2307 /* Description: Start RADIO */ 2308 2309 /* Bit 0 : Start RADIO */ 2310 #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 2311 #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 2312 #define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 2313 2314 /* Register: RADIO_TASKS_STOP */ 2315 /* Description: Stop RADIO */ 2316 2317 /* Bit 0 : Stop RADIO */ 2318 #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 2319 #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 2320 #define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 2321 2322 /* Register: RADIO_TASKS_DISABLE */ 2323 /* Description: Disable RADIO */ 2324 2325 /* Bit 0 : Disable RADIO */ 2326 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ 2327 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ 2328 #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ 2329 2330 /* Register: RADIO_TASKS_RSSISTART */ 2331 /* Description: Start the RSSI and take one single sample of the receive signal strength */ 2332 2333 /* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ 2334 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ 2335 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ 2336 #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */ 2337 2338 /* Register: RADIO_TASKS_RSSISTOP */ 2339 /* Description: Stop the RSSI measurement */ 2340 2341 /* Bit 0 : Stop the RSSI measurement */ 2342 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ 2343 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ 2344 #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */ 2345 2346 /* Register: RADIO_TASKS_BCSTART */ 2347 /* Description: Start the bit counter */ 2348 2349 /* Bit 0 : Start the bit counter */ 2350 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ 2351 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ 2352 #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */ 2353 2354 /* Register: RADIO_TASKS_BCSTOP */ 2355 /* Description: Stop the bit counter */ 2356 2357 /* Bit 0 : Stop the bit counter */ 2358 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ 2359 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ 2360 #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */ 2361 2362 /* Register: RADIO_TASKS_EDSTART */ 2363 /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */ 2364 2365 /* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */ 2366 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ 2367 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */ 2368 #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */ 2369 2370 /* Register: RADIO_TASKS_EDSTOP */ 2371 /* Description: Stop the energy detect measurement */ 2372 2373 /* Bit 0 : Stop the energy detect measurement */ 2374 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ 2375 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */ 2376 #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */ 2377 2378 /* Register: RADIO_TASKS_CCASTART */ 2379 /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */ 2380 2381 /* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */ 2382 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ 2383 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */ 2384 #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */ 2385 2386 /* Register: RADIO_TASKS_CCASTOP */ 2387 /* Description: Stop the clear channel assessment */ 2388 2389 /* Bit 0 : Stop the clear channel assessment */ 2390 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ 2391 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */ 2392 #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */ 2393 2394 /* Register: RADIO_SUBSCRIBE_TXEN */ 2395 /* Description: Subscribe configuration for task TXEN */ 2396 2397 /* Bit 31 : */ 2398 #define RADIO_SUBSCRIBE_TXEN_EN_Pos (31UL) /*!< Position of EN field. */ 2399 #define RADIO_SUBSCRIBE_TXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_TXEN_EN_Pos) /*!< Bit mask of EN field. */ 2400 #define RADIO_SUBSCRIBE_TXEN_EN_Disabled (0UL) /*!< Disable subscription */ 2401 #define RADIO_SUBSCRIBE_TXEN_EN_Enabled (1UL) /*!< Enable subscription */ 2402 2403 /* Bits 7..0 : DPPI channel that task TXEN will subscribe to */ 2404 #define RADIO_SUBSCRIBE_TXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2405 #define RADIO_SUBSCRIBE_TXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_TXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2406 2407 /* Register: RADIO_SUBSCRIBE_RXEN */ 2408 /* Description: Subscribe configuration for task RXEN */ 2409 2410 /* Bit 31 : */ 2411 #define RADIO_SUBSCRIBE_RXEN_EN_Pos (31UL) /*!< Position of EN field. */ 2412 #define RADIO_SUBSCRIBE_RXEN_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RXEN_EN_Pos) /*!< Bit mask of EN field. */ 2413 #define RADIO_SUBSCRIBE_RXEN_EN_Disabled (0UL) /*!< Disable subscription */ 2414 #define RADIO_SUBSCRIBE_RXEN_EN_Enabled (1UL) /*!< Enable subscription */ 2415 2416 /* Bits 7..0 : DPPI channel that task RXEN will subscribe to */ 2417 #define RADIO_SUBSCRIBE_RXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2418 #define RADIO_SUBSCRIBE_RXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2419 2420 /* Register: RADIO_SUBSCRIBE_START */ 2421 /* Description: Subscribe configuration for task START */ 2422 2423 /* Bit 31 : */ 2424 #define RADIO_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 2425 #define RADIO_SUBSCRIBE_START_EN_Msk (0x1UL << RADIO_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 2426 #define RADIO_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 2427 #define RADIO_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 2428 2429 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 2430 #define RADIO_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2431 #define RADIO_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2432 2433 /* Register: RADIO_SUBSCRIBE_STOP */ 2434 /* Description: Subscribe configuration for task STOP */ 2435 2436 /* Bit 31 : */ 2437 #define RADIO_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 2438 #define RADIO_SUBSCRIBE_STOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 2439 #define RADIO_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 2440 #define RADIO_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 2441 2442 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 2443 #define RADIO_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2444 #define RADIO_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2445 2446 /* Register: RADIO_SUBSCRIBE_DISABLE */ 2447 /* Description: Subscribe configuration for task DISABLE */ 2448 2449 /* Bit 31 : */ 2450 #define RADIO_SUBSCRIBE_DISABLE_EN_Pos (31UL) /*!< Position of EN field. */ 2451 #define RADIO_SUBSCRIBE_DISABLE_EN_Msk (0x1UL << RADIO_SUBSCRIBE_DISABLE_EN_Pos) /*!< Bit mask of EN field. */ 2452 #define RADIO_SUBSCRIBE_DISABLE_EN_Disabled (0UL) /*!< Disable subscription */ 2453 #define RADIO_SUBSCRIBE_DISABLE_EN_Enabled (1UL) /*!< Enable subscription */ 2454 2455 /* Bits 7..0 : DPPI channel that task DISABLE will subscribe to */ 2456 #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2457 #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2458 2459 /* Register: RADIO_SUBSCRIBE_RSSISTART */ 2460 /* Description: Subscribe configuration for task RSSISTART */ 2461 2462 /* Bit 31 : */ 2463 #define RADIO_SUBSCRIBE_RSSISTART_EN_Pos (31UL) /*!< Position of EN field. */ 2464 #define RADIO_SUBSCRIBE_RSSISTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTART_EN_Pos) /*!< Bit mask of EN field. */ 2465 #define RADIO_SUBSCRIBE_RSSISTART_EN_Disabled (0UL) /*!< Disable subscription */ 2466 #define RADIO_SUBSCRIBE_RSSISTART_EN_Enabled (1UL) /*!< Enable subscription */ 2467 2468 /* Bits 7..0 : DPPI channel that task RSSISTART will subscribe to */ 2469 #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2470 #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2471 2472 /* Register: RADIO_SUBSCRIBE_RSSISTOP */ 2473 /* Description: Subscribe configuration for task RSSISTOP */ 2474 2475 /* Bit 31 : */ 2476 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Pos (31UL) /*!< Position of EN field. */ 2477 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_RSSISTOP_EN_Pos) /*!< Bit mask of EN field. */ 2478 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Disabled (0UL) /*!< Disable subscription */ 2479 #define RADIO_SUBSCRIBE_RSSISTOP_EN_Enabled (1UL) /*!< Enable subscription */ 2480 2481 /* Bits 7..0 : DPPI channel that task RSSISTOP will subscribe to */ 2482 #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2483 #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2484 2485 /* Register: RADIO_SUBSCRIBE_BCSTART */ 2486 /* Description: Subscribe configuration for task BCSTART */ 2487 2488 /* Bit 31 : */ 2489 #define RADIO_SUBSCRIBE_BCSTART_EN_Pos (31UL) /*!< Position of EN field. */ 2490 #define RADIO_SUBSCRIBE_BCSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTART_EN_Pos) /*!< Bit mask of EN field. */ 2491 #define RADIO_SUBSCRIBE_BCSTART_EN_Disabled (0UL) /*!< Disable subscription */ 2492 #define RADIO_SUBSCRIBE_BCSTART_EN_Enabled (1UL) /*!< Enable subscription */ 2493 2494 /* Bits 7..0 : DPPI channel that task BCSTART will subscribe to */ 2495 #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2496 #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2497 2498 /* Register: RADIO_SUBSCRIBE_BCSTOP */ 2499 /* Description: Subscribe configuration for task BCSTOP */ 2500 2501 /* Bit 31 : */ 2502 #define RADIO_SUBSCRIBE_BCSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 2503 #define RADIO_SUBSCRIBE_BCSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_BCSTOP_EN_Pos) /*!< Bit mask of EN field. */ 2504 #define RADIO_SUBSCRIBE_BCSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 2505 #define RADIO_SUBSCRIBE_BCSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 2506 2507 /* Bits 7..0 : DPPI channel that task BCSTOP will subscribe to */ 2508 #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2509 #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2510 2511 /* Register: RADIO_SUBSCRIBE_EDSTART */ 2512 /* Description: Subscribe configuration for task EDSTART */ 2513 2514 /* Bit 31 : */ 2515 #define RADIO_SUBSCRIBE_EDSTART_EN_Pos (31UL) /*!< Position of EN field. */ 2516 #define RADIO_SUBSCRIBE_EDSTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTART_EN_Pos) /*!< Bit mask of EN field. */ 2517 #define RADIO_SUBSCRIBE_EDSTART_EN_Disabled (0UL) /*!< Disable subscription */ 2518 #define RADIO_SUBSCRIBE_EDSTART_EN_Enabled (1UL) /*!< Enable subscription */ 2519 2520 /* Bits 7..0 : DPPI channel that task EDSTART will subscribe to */ 2521 #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2522 #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2523 2524 /* Register: RADIO_SUBSCRIBE_EDSTOP */ 2525 /* Description: Subscribe configuration for task EDSTOP */ 2526 2527 /* Bit 31 : */ 2528 #define RADIO_SUBSCRIBE_EDSTOP_EN_Pos (31UL) /*!< Position of EN field. */ 2529 #define RADIO_SUBSCRIBE_EDSTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_EDSTOP_EN_Pos) /*!< Bit mask of EN field. */ 2530 #define RADIO_SUBSCRIBE_EDSTOP_EN_Disabled (0UL) /*!< Disable subscription */ 2531 #define RADIO_SUBSCRIBE_EDSTOP_EN_Enabled (1UL) /*!< Enable subscription */ 2532 2533 /* Bits 7..0 : DPPI channel that task EDSTOP will subscribe to */ 2534 #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2535 #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2536 2537 /* Register: RADIO_SUBSCRIBE_CCASTART */ 2538 /* Description: Subscribe configuration for task CCASTART */ 2539 2540 /* Bit 31 : */ 2541 #define RADIO_SUBSCRIBE_CCASTART_EN_Pos (31UL) /*!< Position of EN field. */ 2542 #define RADIO_SUBSCRIBE_CCASTART_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTART_EN_Pos) /*!< Bit mask of EN field. */ 2543 #define RADIO_SUBSCRIBE_CCASTART_EN_Disabled (0UL) /*!< Disable subscription */ 2544 #define RADIO_SUBSCRIBE_CCASTART_EN_Enabled (1UL) /*!< Enable subscription */ 2545 2546 /* Bits 7..0 : DPPI channel that task CCASTART will subscribe to */ 2547 #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2548 #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2549 2550 /* Register: RADIO_SUBSCRIBE_CCASTOP */ 2551 /* Description: Subscribe configuration for task CCASTOP */ 2552 2553 /* Bit 31 : */ 2554 #define RADIO_SUBSCRIBE_CCASTOP_EN_Pos (31UL) /*!< Position of EN field. */ 2555 #define RADIO_SUBSCRIBE_CCASTOP_EN_Msk (0x1UL << RADIO_SUBSCRIBE_CCASTOP_EN_Pos) /*!< Bit mask of EN field. */ 2556 #define RADIO_SUBSCRIBE_CCASTOP_EN_Disabled (0UL) /*!< Disable subscription */ 2557 #define RADIO_SUBSCRIBE_CCASTOP_EN_Enabled (1UL) /*!< Enable subscription */ 2558 2559 /* Bits 7..0 : DPPI channel that task CCASTOP will subscribe to */ 2560 #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2561 #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2562 2563 /* Register: RADIO_EVENTS_READY */ 2564 /* Description: RADIO has ramped up and is ready to be started */ 2565 2566 /* Bit 0 : RADIO has ramped up and is ready to be started */ 2567 #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ 2568 #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ 2569 #define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ 2570 #define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ 2571 2572 /* Register: RADIO_EVENTS_ADDRESS */ 2573 /* Description: Address sent or received */ 2574 2575 /* Bit 0 : Address sent or received */ 2576 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ 2577 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ 2578 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */ 2579 #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */ 2580 2581 /* Register: RADIO_EVENTS_PAYLOAD */ 2582 /* Description: Packet payload sent or received */ 2583 2584 /* Bit 0 : Packet payload sent or received */ 2585 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ 2586 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ 2587 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */ 2588 #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */ 2589 2590 /* Register: RADIO_EVENTS_END */ 2591 /* Description: Packet sent or received */ 2592 2593 /* Bit 0 : Packet sent or received */ 2594 #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ 2595 #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ 2596 #define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ 2597 #define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ 2598 2599 /* Register: RADIO_EVENTS_DISABLED */ 2600 /* Description: RADIO has been disabled */ 2601 2602 /* Bit 0 : RADIO has been disabled */ 2603 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ 2604 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ 2605 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */ 2606 #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */ 2607 2608 /* Register: RADIO_EVENTS_DEVMATCH */ 2609 /* Description: A device address match occurred on the last received packet */ 2610 2611 /* Bit 0 : A device address match occurred on the last received packet */ 2612 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ 2613 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ 2614 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */ 2615 #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */ 2616 2617 /* Register: RADIO_EVENTS_DEVMISS */ 2618 /* Description: No device address match occurred on the last received packet */ 2619 2620 /* Bit 0 : No device address match occurred on the last received packet */ 2621 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ 2622 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ 2623 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */ 2624 #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */ 2625 2626 /* Register: RADIO_EVENTS_RSSIEND */ 2627 /* Description: Sampling of receive signal strength complete */ 2628 2629 /* Bit 0 : Sampling of receive signal strength complete */ 2630 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ 2631 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ 2632 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */ 2633 #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */ 2634 2635 /* Register: RADIO_EVENTS_BCMATCH */ 2636 /* Description: Bit counter reached bit count value */ 2637 2638 /* Bit 0 : Bit counter reached bit count value */ 2639 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ 2640 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ 2641 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */ 2642 #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */ 2643 2644 /* Register: RADIO_EVENTS_CRCOK */ 2645 /* Description: Packet received with CRC ok */ 2646 2647 /* Bit 0 : Packet received with CRC ok */ 2648 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ 2649 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ 2650 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */ 2651 #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */ 2652 2653 /* Register: RADIO_EVENTS_CRCERROR */ 2654 /* Description: Packet received with CRC error */ 2655 2656 /* Bit 0 : Packet received with CRC error */ 2657 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ 2658 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ 2659 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */ 2660 #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */ 2661 2662 /* Register: RADIO_EVENTS_FRAMESTART */ 2663 /* Description: IEEE 802.15.4 length field received */ 2664 2665 /* Bit 0 : IEEE 802.15.4 length field received */ 2666 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ 2667 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */ 2668 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */ 2669 #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ 2670 2671 /* Register: RADIO_EVENTS_EDEND */ 2672 /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ 2673 2674 /* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ 2675 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ 2676 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ 2677 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ 2678 #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */ 2679 2680 /* Register: RADIO_EVENTS_EDSTOPPED */ 2681 /* Description: The sampling of energy detection has stopped */ 2682 2683 /* Bit 0 : The sampling of energy detection has stopped */ 2684 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ 2685 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */ 2686 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */ 2687 #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */ 2688 2689 /* Register: RADIO_EVENTS_CCAIDLE */ 2690 /* Description: Wireless medium in idle - clear to send */ 2691 2692 /* Bit 0 : Wireless medium in idle - clear to send */ 2693 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ 2694 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */ 2695 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */ 2696 #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */ 2697 2698 /* Register: RADIO_EVENTS_CCABUSY */ 2699 /* Description: Wireless medium busy - do not send */ 2700 2701 /* Bit 0 : Wireless medium busy - do not send */ 2702 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ 2703 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */ 2704 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */ 2705 #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */ 2706 2707 /* Register: RADIO_EVENTS_CCASTOPPED */ 2708 /* Description: The CCA has stopped */ 2709 2710 /* Bit 0 : The CCA has stopped */ 2711 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ 2712 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */ 2713 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */ 2714 #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */ 2715 2716 /* Register: RADIO_EVENTS_RATEBOOST */ 2717 /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ 2718 2719 /* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ 2720 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ 2721 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */ 2722 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */ 2723 #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */ 2724 2725 /* Register: RADIO_EVENTS_TXREADY */ 2726 /* Description: RADIO has ramped up and is ready to be started TX path */ 2727 2728 /* Bit 0 : RADIO has ramped up and is ready to be started TX path */ 2729 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ 2730 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */ 2731 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */ 2732 #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */ 2733 2734 /* Register: RADIO_EVENTS_RXREADY */ 2735 /* Description: RADIO has ramped up and is ready to be started RX path */ 2736 2737 /* Bit 0 : RADIO has ramped up and is ready to be started RX path */ 2738 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ 2739 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ 2740 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */ 2741 #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */ 2742 2743 /* Register: RADIO_EVENTS_MHRMATCH */ 2744 /* Description: MAC header match found */ 2745 2746 /* Bit 0 : MAC header match found */ 2747 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ 2748 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */ 2749 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ 2750 #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ 2751 2752 /* Register: RADIO_EVENTS_SYNC */ 2753 /* Description: Preamble indicator */ 2754 2755 /* Bit 0 : Preamble indicator */ 2756 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */ 2757 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */ 2758 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */ 2759 #define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */ 2760 2761 /* Register: RADIO_EVENTS_PHYEND */ 2762 /* Description: Generated when last bit is sent on air, or received from air */ 2763 2764 /* Bit 0 : Generated when last bit is sent on air, or received from air */ 2765 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ 2766 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ 2767 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ 2768 #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */ 2769 2770 /* Register: RADIO_EVENTS_CTEPRESENT */ 2771 /* Description: CTE is present (early warning right after receiving CTEInfo byte) */ 2772 2773 /* Bit 0 : CTE is present (early warning right after receiving CTEInfo byte) */ 2774 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos (0UL) /*!< Position of EVENTS_CTEPRESENT field. */ 2775 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Msk (0x1UL << RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Pos) /*!< Bit mask of EVENTS_CTEPRESENT field. */ 2776 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_NotGenerated (0UL) /*!< Event not generated */ 2777 #define RADIO_EVENTS_CTEPRESENT_EVENTS_CTEPRESENT_Generated (1UL) /*!< Event generated */ 2778 2779 /* Register: RADIO_PUBLISH_READY */ 2780 /* Description: Publish configuration for event READY */ 2781 2782 /* Bit 31 : */ 2783 #define RADIO_PUBLISH_READY_EN_Pos (31UL) /*!< Position of EN field. */ 2784 #define RADIO_PUBLISH_READY_EN_Msk (0x1UL << RADIO_PUBLISH_READY_EN_Pos) /*!< Bit mask of EN field. */ 2785 #define RADIO_PUBLISH_READY_EN_Disabled (0UL) /*!< Disable publishing */ 2786 #define RADIO_PUBLISH_READY_EN_Enabled (1UL) /*!< Enable publishing */ 2787 2788 /* Bits 7..0 : DPPI channel that event READY will publish to. */ 2789 #define RADIO_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2790 #define RADIO_PUBLISH_READY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2791 2792 /* Register: RADIO_PUBLISH_ADDRESS */ 2793 /* Description: Publish configuration for event ADDRESS */ 2794 2795 /* Bit 31 : */ 2796 #define RADIO_PUBLISH_ADDRESS_EN_Pos (31UL) /*!< Position of EN field. */ 2797 #define RADIO_PUBLISH_ADDRESS_EN_Msk (0x1UL << RADIO_PUBLISH_ADDRESS_EN_Pos) /*!< Bit mask of EN field. */ 2798 #define RADIO_PUBLISH_ADDRESS_EN_Disabled (0UL) /*!< Disable publishing */ 2799 #define RADIO_PUBLISH_ADDRESS_EN_Enabled (1UL) /*!< Enable publishing */ 2800 2801 /* Bits 7..0 : DPPI channel that event ADDRESS will publish to. */ 2802 #define RADIO_PUBLISH_ADDRESS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2803 #define RADIO_PUBLISH_ADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_ADDRESS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2804 2805 /* Register: RADIO_PUBLISH_PAYLOAD */ 2806 /* Description: Publish configuration for event PAYLOAD */ 2807 2808 /* Bit 31 : */ 2809 #define RADIO_PUBLISH_PAYLOAD_EN_Pos (31UL) /*!< Position of EN field. */ 2810 #define RADIO_PUBLISH_PAYLOAD_EN_Msk (0x1UL << RADIO_PUBLISH_PAYLOAD_EN_Pos) /*!< Bit mask of EN field. */ 2811 #define RADIO_PUBLISH_PAYLOAD_EN_Disabled (0UL) /*!< Disable publishing */ 2812 #define RADIO_PUBLISH_PAYLOAD_EN_Enabled (1UL) /*!< Enable publishing */ 2813 2814 /* Bits 7..0 : DPPI channel that event PAYLOAD will publish to. */ 2815 #define RADIO_PUBLISH_PAYLOAD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2816 #define RADIO_PUBLISH_PAYLOAD_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PAYLOAD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2817 2818 /* Register: RADIO_PUBLISH_END */ 2819 /* Description: Publish configuration for event END */ 2820 2821 /* Bit 31 : */ 2822 #define RADIO_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ 2823 #define RADIO_PUBLISH_END_EN_Msk (0x1UL << RADIO_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ 2824 #define RADIO_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ 2825 #define RADIO_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ 2826 2827 /* Bits 7..0 : DPPI channel that event END will publish to. */ 2828 #define RADIO_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2829 #define RADIO_PUBLISH_END_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2830 2831 /* Register: RADIO_PUBLISH_DISABLED */ 2832 /* Description: Publish configuration for event DISABLED */ 2833 2834 /* Bit 31 : */ 2835 #define RADIO_PUBLISH_DISABLED_EN_Pos (31UL) /*!< Position of EN field. */ 2836 #define RADIO_PUBLISH_DISABLED_EN_Msk (0x1UL << RADIO_PUBLISH_DISABLED_EN_Pos) /*!< Bit mask of EN field. */ 2837 #define RADIO_PUBLISH_DISABLED_EN_Disabled (0UL) /*!< Disable publishing */ 2838 #define RADIO_PUBLISH_DISABLED_EN_Enabled (1UL) /*!< Enable publishing */ 2839 2840 /* Bits 7..0 : DPPI channel that event DISABLED will publish to. */ 2841 #define RADIO_PUBLISH_DISABLED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2842 #define RADIO_PUBLISH_DISABLED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DISABLED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2843 2844 /* Register: RADIO_PUBLISH_DEVMATCH */ 2845 /* Description: Publish configuration for event DEVMATCH */ 2846 2847 /* Bit 31 : */ 2848 #define RADIO_PUBLISH_DEVMATCH_EN_Pos (31UL) /*!< Position of EN field. */ 2849 #define RADIO_PUBLISH_DEVMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMATCH_EN_Pos) /*!< Bit mask of EN field. */ 2850 #define RADIO_PUBLISH_DEVMATCH_EN_Disabled (0UL) /*!< Disable publishing */ 2851 #define RADIO_PUBLISH_DEVMATCH_EN_Enabled (1UL) /*!< Enable publishing */ 2852 2853 /* Bits 7..0 : DPPI channel that event DEVMATCH will publish to. */ 2854 #define RADIO_PUBLISH_DEVMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2855 #define RADIO_PUBLISH_DEVMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2856 2857 /* Register: RADIO_PUBLISH_DEVMISS */ 2858 /* Description: Publish configuration for event DEVMISS */ 2859 2860 /* Bit 31 : */ 2861 #define RADIO_PUBLISH_DEVMISS_EN_Pos (31UL) /*!< Position of EN field. */ 2862 #define RADIO_PUBLISH_DEVMISS_EN_Msk (0x1UL << RADIO_PUBLISH_DEVMISS_EN_Pos) /*!< Bit mask of EN field. */ 2863 #define RADIO_PUBLISH_DEVMISS_EN_Disabled (0UL) /*!< Disable publishing */ 2864 #define RADIO_PUBLISH_DEVMISS_EN_Enabled (1UL) /*!< Enable publishing */ 2865 2866 /* Bits 7..0 : DPPI channel that event DEVMISS will publish to. */ 2867 #define RADIO_PUBLISH_DEVMISS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2868 #define RADIO_PUBLISH_DEVMISS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMISS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2869 2870 /* Register: RADIO_PUBLISH_RSSIEND */ 2871 /* Description: Publish configuration for event RSSIEND */ 2872 2873 /* Bit 31 : */ 2874 #define RADIO_PUBLISH_RSSIEND_EN_Pos (31UL) /*!< Position of EN field. */ 2875 #define RADIO_PUBLISH_RSSIEND_EN_Msk (0x1UL << RADIO_PUBLISH_RSSIEND_EN_Pos) /*!< Bit mask of EN field. */ 2876 #define RADIO_PUBLISH_RSSIEND_EN_Disabled (0UL) /*!< Disable publishing */ 2877 #define RADIO_PUBLISH_RSSIEND_EN_Enabled (1UL) /*!< Enable publishing */ 2878 2879 /* Bits 7..0 : DPPI channel that event RSSIEND will publish to. */ 2880 #define RADIO_PUBLISH_RSSIEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2881 #define RADIO_PUBLISH_RSSIEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RSSIEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2882 2883 /* Register: RADIO_PUBLISH_BCMATCH */ 2884 /* Description: Publish configuration for event BCMATCH */ 2885 2886 /* Bit 31 : */ 2887 #define RADIO_PUBLISH_BCMATCH_EN_Pos (31UL) /*!< Position of EN field. */ 2888 #define RADIO_PUBLISH_BCMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_BCMATCH_EN_Pos) /*!< Bit mask of EN field. */ 2889 #define RADIO_PUBLISH_BCMATCH_EN_Disabled (0UL) /*!< Disable publishing */ 2890 #define RADIO_PUBLISH_BCMATCH_EN_Enabled (1UL) /*!< Enable publishing */ 2891 2892 /* Bits 7..0 : DPPI channel that event BCMATCH will publish to. */ 2893 #define RADIO_PUBLISH_BCMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2894 #define RADIO_PUBLISH_BCMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_BCMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2895 2896 /* Register: RADIO_PUBLISH_CRCOK */ 2897 /* Description: Publish configuration for event CRCOK */ 2898 2899 /* Bit 31 : */ 2900 #define RADIO_PUBLISH_CRCOK_EN_Pos (31UL) /*!< Position of EN field. */ 2901 #define RADIO_PUBLISH_CRCOK_EN_Msk (0x1UL << RADIO_PUBLISH_CRCOK_EN_Pos) /*!< Bit mask of EN field. */ 2902 #define RADIO_PUBLISH_CRCOK_EN_Disabled (0UL) /*!< Disable publishing */ 2903 #define RADIO_PUBLISH_CRCOK_EN_Enabled (1UL) /*!< Enable publishing */ 2904 2905 /* Bits 7..0 : DPPI channel that event CRCOK will publish to. */ 2906 #define RADIO_PUBLISH_CRCOK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2907 #define RADIO_PUBLISH_CRCOK_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCOK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2908 2909 /* Register: RADIO_PUBLISH_CRCERROR */ 2910 /* Description: Publish configuration for event CRCERROR */ 2911 2912 /* Bit 31 : */ 2913 #define RADIO_PUBLISH_CRCERROR_EN_Pos (31UL) /*!< Position of EN field. */ 2914 #define RADIO_PUBLISH_CRCERROR_EN_Msk (0x1UL << RADIO_PUBLISH_CRCERROR_EN_Pos) /*!< Bit mask of EN field. */ 2915 #define RADIO_PUBLISH_CRCERROR_EN_Disabled (0UL) /*!< Disable publishing */ 2916 #define RADIO_PUBLISH_CRCERROR_EN_Enabled (1UL) /*!< Enable publishing */ 2917 2918 /* Bits 7..0 : DPPI channel that event CRCERROR will publish to. */ 2919 #define RADIO_PUBLISH_CRCERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2920 #define RADIO_PUBLISH_CRCERROR_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2921 2922 /* Register: RADIO_PUBLISH_FRAMESTART */ 2923 /* Description: Publish configuration for event FRAMESTART */ 2924 2925 /* Bit 31 : */ 2926 #define RADIO_PUBLISH_FRAMESTART_EN_Pos (31UL) /*!< Position of EN field. */ 2927 #define RADIO_PUBLISH_FRAMESTART_EN_Msk (0x1UL << RADIO_PUBLISH_FRAMESTART_EN_Pos) /*!< Bit mask of EN field. */ 2928 #define RADIO_PUBLISH_FRAMESTART_EN_Disabled (0UL) /*!< Disable publishing */ 2929 #define RADIO_PUBLISH_FRAMESTART_EN_Enabled (1UL) /*!< Enable publishing */ 2930 2931 /* Bits 7..0 : DPPI channel that event FRAMESTART will publish to. */ 2932 #define RADIO_PUBLISH_FRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2933 #define RADIO_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2934 2935 /* Register: RADIO_PUBLISH_EDEND */ 2936 /* Description: Publish configuration for event EDEND */ 2937 2938 /* Bit 31 : */ 2939 #define RADIO_PUBLISH_EDEND_EN_Pos (31UL) /*!< Position of EN field. */ 2940 #define RADIO_PUBLISH_EDEND_EN_Msk (0x1UL << RADIO_PUBLISH_EDEND_EN_Pos) /*!< Bit mask of EN field. */ 2941 #define RADIO_PUBLISH_EDEND_EN_Disabled (0UL) /*!< Disable publishing */ 2942 #define RADIO_PUBLISH_EDEND_EN_Enabled (1UL) /*!< Enable publishing */ 2943 2944 /* Bits 7..0 : DPPI channel that event EDEND will publish to. */ 2945 #define RADIO_PUBLISH_EDEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2946 #define RADIO_PUBLISH_EDEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2947 2948 /* Register: RADIO_PUBLISH_EDSTOPPED */ 2949 /* Description: Publish configuration for event EDSTOPPED */ 2950 2951 /* Bit 31 : */ 2952 #define RADIO_PUBLISH_EDSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 2953 #define RADIO_PUBLISH_EDSTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_EDSTOPPED_EN_Pos) /*!< Bit mask of EN field. */ 2954 #define RADIO_PUBLISH_EDSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 2955 #define RADIO_PUBLISH_EDSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 2956 2957 /* Bits 7..0 : DPPI channel that event EDSTOPPED will publish to. */ 2958 #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2959 #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2960 2961 /* Register: RADIO_PUBLISH_CCAIDLE */ 2962 /* Description: Publish configuration for event CCAIDLE */ 2963 2964 /* Bit 31 : */ 2965 #define RADIO_PUBLISH_CCAIDLE_EN_Pos (31UL) /*!< Position of EN field. */ 2966 #define RADIO_PUBLISH_CCAIDLE_EN_Msk (0x1UL << RADIO_PUBLISH_CCAIDLE_EN_Pos) /*!< Bit mask of EN field. */ 2967 #define RADIO_PUBLISH_CCAIDLE_EN_Disabled (0UL) /*!< Disable publishing */ 2968 #define RADIO_PUBLISH_CCAIDLE_EN_Enabled (1UL) /*!< Enable publishing */ 2969 2970 /* Bits 7..0 : DPPI channel that event CCAIDLE will publish to. */ 2971 #define RADIO_PUBLISH_CCAIDLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2972 #define RADIO_PUBLISH_CCAIDLE_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCAIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2973 2974 /* Register: RADIO_PUBLISH_CCABUSY */ 2975 /* Description: Publish configuration for event CCABUSY */ 2976 2977 /* Bit 31 : */ 2978 #define RADIO_PUBLISH_CCABUSY_EN_Pos (31UL) /*!< Position of EN field. */ 2979 #define RADIO_PUBLISH_CCABUSY_EN_Msk (0x1UL << RADIO_PUBLISH_CCABUSY_EN_Pos) /*!< Bit mask of EN field. */ 2980 #define RADIO_PUBLISH_CCABUSY_EN_Disabled (0UL) /*!< Disable publishing */ 2981 #define RADIO_PUBLISH_CCABUSY_EN_Enabled (1UL) /*!< Enable publishing */ 2982 2983 /* Bits 7..0 : DPPI channel that event CCABUSY will publish to. */ 2984 #define RADIO_PUBLISH_CCABUSY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2985 #define RADIO_PUBLISH_CCABUSY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCABUSY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2986 2987 /* Register: RADIO_PUBLISH_CCASTOPPED */ 2988 /* Description: Publish configuration for event CCASTOPPED */ 2989 2990 /* Bit 31 : */ 2991 #define RADIO_PUBLISH_CCASTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ 2992 #define RADIO_PUBLISH_CCASTOPPED_EN_Msk (0x1UL << RADIO_PUBLISH_CCASTOPPED_EN_Pos) /*!< Bit mask of EN field. */ 2993 #define RADIO_PUBLISH_CCASTOPPED_EN_Disabled (0UL) /*!< Disable publishing */ 2994 #define RADIO_PUBLISH_CCASTOPPED_EN_Enabled (1UL) /*!< Enable publishing */ 2995 2996 /* Bits 7..0 : DPPI channel that event CCASTOPPED will publish to. */ 2997 #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 2998 #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 2999 3000 /* Register: RADIO_PUBLISH_RATEBOOST */ 3001 /* Description: Publish configuration for event RATEBOOST */ 3002 3003 /* Bit 31 : */ 3004 #define RADIO_PUBLISH_RATEBOOST_EN_Pos (31UL) /*!< Position of EN field. */ 3005 #define RADIO_PUBLISH_RATEBOOST_EN_Msk (0x1UL << RADIO_PUBLISH_RATEBOOST_EN_Pos) /*!< Bit mask of EN field. */ 3006 #define RADIO_PUBLISH_RATEBOOST_EN_Disabled (0UL) /*!< Disable publishing */ 3007 #define RADIO_PUBLISH_RATEBOOST_EN_Enabled (1UL) /*!< Enable publishing */ 3008 3009 /* Bits 7..0 : DPPI channel that event RATEBOOST will publish to. */ 3010 #define RADIO_PUBLISH_RATEBOOST_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3011 #define RADIO_PUBLISH_RATEBOOST_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RATEBOOST_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3012 3013 /* Register: RADIO_PUBLISH_TXREADY */ 3014 /* Description: Publish configuration for event TXREADY */ 3015 3016 /* Bit 31 : */ 3017 #define RADIO_PUBLISH_TXREADY_EN_Pos (31UL) /*!< Position of EN field. */ 3018 #define RADIO_PUBLISH_TXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_TXREADY_EN_Pos) /*!< Bit mask of EN field. */ 3019 #define RADIO_PUBLISH_TXREADY_EN_Disabled (0UL) /*!< Disable publishing */ 3020 #define RADIO_PUBLISH_TXREADY_EN_Enabled (1UL) /*!< Enable publishing */ 3021 3022 /* Bits 7..0 : DPPI channel that event TXREADY will publish to. */ 3023 #define RADIO_PUBLISH_TXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3024 #define RADIO_PUBLISH_TXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_TXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3025 3026 /* Register: RADIO_PUBLISH_RXREADY */ 3027 /* Description: Publish configuration for event RXREADY */ 3028 3029 /* Bit 31 : */ 3030 #define RADIO_PUBLISH_RXREADY_EN_Pos (31UL) /*!< Position of EN field. */ 3031 #define RADIO_PUBLISH_RXREADY_EN_Msk (0x1UL << RADIO_PUBLISH_RXREADY_EN_Pos) /*!< Bit mask of EN field. */ 3032 #define RADIO_PUBLISH_RXREADY_EN_Disabled (0UL) /*!< Disable publishing */ 3033 #define RADIO_PUBLISH_RXREADY_EN_Enabled (1UL) /*!< Enable publishing */ 3034 3035 /* Bits 7..0 : DPPI channel that event RXREADY will publish to. */ 3036 #define RADIO_PUBLISH_RXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3037 #define RADIO_PUBLISH_RXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3038 3039 /* Register: RADIO_PUBLISH_MHRMATCH */ 3040 /* Description: Publish configuration for event MHRMATCH */ 3041 3042 /* Bit 31 : */ 3043 #define RADIO_PUBLISH_MHRMATCH_EN_Pos (31UL) /*!< Position of EN field. */ 3044 #define RADIO_PUBLISH_MHRMATCH_EN_Msk (0x1UL << RADIO_PUBLISH_MHRMATCH_EN_Pos) /*!< Bit mask of EN field. */ 3045 #define RADIO_PUBLISH_MHRMATCH_EN_Disabled (0UL) /*!< Disable publishing */ 3046 #define RADIO_PUBLISH_MHRMATCH_EN_Enabled (1UL) /*!< Enable publishing */ 3047 3048 /* Bits 7..0 : DPPI channel that event MHRMATCH will publish to. */ 3049 #define RADIO_PUBLISH_MHRMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3050 #define RADIO_PUBLISH_MHRMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_MHRMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3051 3052 /* Register: RADIO_PUBLISH_SYNC */ 3053 /* Description: Publish configuration for event SYNC */ 3054 3055 /* Bit 31 : */ 3056 #define RADIO_PUBLISH_SYNC_EN_Pos (31UL) /*!< Position of EN field. */ 3057 #define RADIO_PUBLISH_SYNC_EN_Msk (0x1UL << RADIO_PUBLISH_SYNC_EN_Pos) /*!< Bit mask of EN field. */ 3058 #define RADIO_PUBLISH_SYNC_EN_Disabled (0UL) /*!< Disable publishing */ 3059 #define RADIO_PUBLISH_SYNC_EN_Enabled (1UL) /*!< Enable publishing */ 3060 3061 /* Bits 7..0 : DPPI channel that event SYNC will publish to. */ 3062 #define RADIO_PUBLISH_SYNC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3063 #define RADIO_PUBLISH_SYNC_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_SYNC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3064 3065 /* Register: RADIO_PUBLISH_PHYEND */ 3066 /* Description: Publish configuration for event PHYEND */ 3067 3068 /* Bit 31 : */ 3069 #define RADIO_PUBLISH_PHYEND_EN_Pos (31UL) /*!< Position of EN field. */ 3070 #define RADIO_PUBLISH_PHYEND_EN_Msk (0x1UL << RADIO_PUBLISH_PHYEND_EN_Pos) /*!< Bit mask of EN field. */ 3071 #define RADIO_PUBLISH_PHYEND_EN_Disabled (0UL) /*!< Disable publishing */ 3072 #define RADIO_PUBLISH_PHYEND_EN_Enabled (1UL) /*!< Enable publishing */ 3073 3074 /* Bits 7..0 : DPPI channel that event PHYEND will publish to. */ 3075 #define RADIO_PUBLISH_PHYEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3076 #define RADIO_PUBLISH_PHYEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PHYEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3077 3078 /* Register: RADIO_PUBLISH_CTEPRESENT */ 3079 /* Description: Publish configuration for event CTEPRESENT */ 3080 3081 /* Bit 31 : */ 3082 #define RADIO_PUBLISH_CTEPRESENT_EN_Pos (31UL) /*!< Position of EN field. */ 3083 #define RADIO_PUBLISH_CTEPRESENT_EN_Msk (0x1UL << RADIO_PUBLISH_CTEPRESENT_EN_Pos) /*!< Bit mask of EN field. */ 3084 #define RADIO_PUBLISH_CTEPRESENT_EN_Disabled (0UL) /*!< Disable publishing */ 3085 #define RADIO_PUBLISH_CTEPRESENT_EN_Enabled (1UL) /*!< Enable publishing */ 3086 3087 /* Bits 7..0 : DPPI channel that event CTEPRESENT will publish to. */ 3088 #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 3089 #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 3090 3091 /* Register: RADIO_SHORTS */ 3092 /* Description: Shortcuts between local events and tasks */ 3093 3094 /* Bit 21 : Shortcut between event PHYEND and task START */ 3095 #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */ 3096 #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ 3097 #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */ 3098 #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */ 3099 3100 /* Bit 20 : Shortcut between event PHYEND and task DISABLE */ 3101 #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */ 3102 #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ 3103 #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 3104 #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 3105 3106 /* Bit 19 : Shortcut between event RXREADY and task START */ 3107 #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ 3108 #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ 3109 #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ 3110 #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ 3111 3112 /* Bit 18 : Shortcut between event TXREADY and task START */ 3113 #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ 3114 #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ 3115 #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ 3116 #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ 3117 3118 /* Bit 17 : Shortcut between event CCAIDLE and task STOP */ 3119 #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */ 3120 #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ 3121 #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */ 3122 #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */ 3123 3124 /* Bit 16 : Shortcut between event EDEND and task DISABLE */ 3125 #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */ 3126 #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ 3127 #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 3128 #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 3129 3130 /* Bit 15 : Shortcut between event READY and task EDSTART */ 3131 #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */ 3132 #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ 3133 #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */ 3134 #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */ 3135 3136 /* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */ 3137 #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */ 3138 #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */ 3139 #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */ 3140 #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */ 3141 3142 /* Bit 13 : Shortcut between event CCABUSY and task DISABLE */ 3143 #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */ 3144 #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ 3145 #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 3146 #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 3147 3148 /* Bit 12 : Shortcut between event CCAIDLE and task TXEN */ 3149 #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */ 3150 #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ 3151 #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */ 3152 #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */ 3153 3154 /* Bit 11 : Shortcut between event RXREADY and task CCASTART */ 3155 #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */ 3156 #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */ 3157 #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */ 3158 #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */ 3159 3160 /* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */ 3161 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ 3162 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ 3163 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ 3164 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ 3165 3166 /* Bit 6 : Shortcut between event ADDRESS and task BCSTART */ 3167 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ 3168 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ 3169 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ 3170 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ 3171 3172 /* Bit 5 : Shortcut between event END and task START */ 3173 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ 3174 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 3175 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ 3176 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ 3177 3178 /* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ 3179 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ 3180 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ 3181 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ 3182 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ 3183 3184 /* Bit 3 : Shortcut between event DISABLED and task RXEN */ 3185 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ 3186 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ 3187 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ 3188 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ 3189 3190 /* Bit 2 : Shortcut between event DISABLED and task TXEN */ 3191 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ 3192 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ 3193 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ 3194 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ 3195 3196 /* Bit 1 : Shortcut between event END and task DISABLE */ 3197 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ 3198 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ 3199 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 3200 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 3201 3202 /* Bit 0 : Shortcut between event READY and task START */ 3203 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ 3204 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ 3205 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ 3206 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ 3207 3208 /* Register: RADIO_INTENSET */ 3209 /* Description: Enable interrupt */ 3210 3211 /* Bit 28 : Write '1' to enable interrupt for event CTEPRESENT */ 3212 #define RADIO_INTENSET_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */ 3213 #define RADIO_INTENSET_CTEPRESENT_Msk (0x1UL << RADIO_INTENSET_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ 3214 #define RADIO_INTENSET_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */ 3215 #define RADIO_INTENSET_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */ 3216 #define RADIO_INTENSET_CTEPRESENT_Set (1UL) /*!< Enable */ 3217 3218 /* Bit 27 : Write '1' to enable interrupt for event PHYEND */ 3219 #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ 3220 #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ 3221 #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ 3222 #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ 3223 #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ 3224 3225 /* Bit 26 : Write '1' to enable interrupt for event SYNC */ 3226 #define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */ 3227 #define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */ 3228 #define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */ 3229 #define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */ 3230 #define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */ 3231 3232 /* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ 3233 #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ 3234 #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ 3235 #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ 3236 #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ 3237 #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ 3238 3239 /* Bit 22 : Write '1' to enable interrupt for event RXREADY */ 3240 #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ 3241 #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ 3242 #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ 3243 #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ 3244 #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ 3245 3246 /* Bit 21 : Write '1' to enable interrupt for event TXREADY */ 3247 #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ 3248 #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ 3249 #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ 3250 #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ 3251 #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ 3252 3253 /* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ 3254 #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ 3255 #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ 3256 #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ 3257 #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ 3258 #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ 3259 3260 /* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ 3261 #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ 3262 #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ 3263 #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ 3264 #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ 3265 #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ 3266 3267 /* Bit 18 : Write '1' to enable interrupt for event CCABUSY */ 3268 #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ 3269 #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ 3270 #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ 3271 #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ 3272 #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ 3273 3274 /* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ 3275 #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ 3276 #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ 3277 #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ 3278 #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ 3279 #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ 3280 3281 /* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ 3282 #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ 3283 #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ 3284 #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 3285 #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 3286 #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ 3287 3288 /* Bit 15 : Write '1' to enable interrupt for event EDEND */ 3289 #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ 3290 #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ 3291 #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ 3292 #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ 3293 #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ 3294 3295 /* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */ 3296 #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ 3297 #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ 3298 #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ 3299 #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ 3300 #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ 3301 3302 /* Bit 13 : Write '1' to enable interrupt for event CRCERROR */ 3303 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ 3304 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ 3305 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ 3306 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ 3307 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ 3308 3309 /* Bit 12 : Write '1' to enable interrupt for event CRCOK */ 3310 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ 3311 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ 3312 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ 3313 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ 3314 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ 3315 3316 /* Bit 10 : Write '1' to enable interrupt for event BCMATCH */ 3317 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 3318 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 3319 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ 3320 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ 3321 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ 3322 3323 /* Bit 7 : Write '1' to enable interrupt for event RSSIEND */ 3324 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 3325 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 3326 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ 3327 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ 3328 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ 3329 3330 /* Bit 6 : Write '1' to enable interrupt for event DEVMISS */ 3331 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 3332 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 3333 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ 3334 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ 3335 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ 3336 3337 /* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */ 3338 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 3339 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 3340 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ 3341 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ 3342 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ 3343 3344 /* Bit 4 : Write '1' to enable interrupt for event DISABLED */ 3345 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 3346 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 3347 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ 3348 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ 3349 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ 3350 3351 /* Bit 3 : Write '1' to enable interrupt for event END */ 3352 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ 3353 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ 3354 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 3355 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 3356 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ 3357 3358 /* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */ 3359 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 3360 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 3361 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ 3362 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ 3363 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ 3364 3365 /* Bit 1 : Write '1' to enable interrupt for event ADDRESS */ 3366 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 3367 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 3368 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ 3369 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ 3370 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ 3371 3372 /* Bit 0 : Write '1' to enable interrupt for event READY */ 3373 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 3374 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 3375 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ 3376 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ 3377 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ 3378 3379 /* Register: RADIO_INTENCLR */ 3380 /* Description: Disable interrupt */ 3381 3382 /* Bit 28 : Write '1' to disable interrupt for event CTEPRESENT */ 3383 #define RADIO_INTENCLR_CTEPRESENT_Pos (28UL) /*!< Position of CTEPRESENT field. */ 3384 #define RADIO_INTENCLR_CTEPRESENT_Msk (0x1UL << RADIO_INTENCLR_CTEPRESENT_Pos) /*!< Bit mask of CTEPRESENT field. */ 3385 #define RADIO_INTENCLR_CTEPRESENT_Disabled (0UL) /*!< Read: Disabled */ 3386 #define RADIO_INTENCLR_CTEPRESENT_Enabled (1UL) /*!< Read: Enabled */ 3387 #define RADIO_INTENCLR_CTEPRESENT_Clear (1UL) /*!< Disable */ 3388 3389 /* Bit 27 : Write '1' to disable interrupt for event PHYEND */ 3390 #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ 3391 #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ 3392 #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ 3393 #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ 3394 #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ 3395 3396 /* Bit 26 : Write '1' to disable interrupt for event SYNC */ 3397 #define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */ 3398 #define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */ 3399 #define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */ 3400 #define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */ 3401 #define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */ 3402 3403 /* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ 3404 #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ 3405 #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ 3406 #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ 3407 #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ 3408 #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ 3409 3410 /* Bit 22 : Write '1' to disable interrupt for event RXREADY */ 3411 #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ 3412 #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ 3413 #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ 3414 #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ 3415 #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ 3416 3417 /* Bit 21 : Write '1' to disable interrupt for event TXREADY */ 3418 #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ 3419 #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ 3420 #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ 3421 #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ 3422 #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ 3423 3424 /* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ 3425 #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ 3426 #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ 3427 #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ 3428 #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ 3429 #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ 3430 3431 /* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ 3432 #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ 3433 #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ 3434 #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ 3435 #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ 3436 #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ 3437 3438 /* Bit 18 : Write '1' to disable interrupt for event CCABUSY */ 3439 #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ 3440 #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ 3441 #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ 3442 #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ 3443 #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ 3444 3445 /* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ 3446 #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ 3447 #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ 3448 #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ 3449 #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ 3450 #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ 3451 3452 /* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ 3453 #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ 3454 #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ 3455 #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 3456 #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 3457 #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ 3458 3459 /* Bit 15 : Write '1' to disable interrupt for event EDEND */ 3460 #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ 3461 #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ 3462 #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ 3463 #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ 3464 #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ 3465 3466 /* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */ 3467 #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ 3468 #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ 3469 #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ 3470 #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ 3471 #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ 3472 3473 /* Bit 13 : Write '1' to disable interrupt for event CRCERROR */ 3474 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ 3475 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ 3476 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ 3477 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ 3478 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ 3479 3480 /* Bit 12 : Write '1' to disable interrupt for event CRCOK */ 3481 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ 3482 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ 3483 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ 3484 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ 3485 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ 3486 3487 /* Bit 10 : Write '1' to disable interrupt for event BCMATCH */ 3488 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 3489 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 3490 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ 3491 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ 3492 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ 3493 3494 /* Bit 7 : Write '1' to disable interrupt for event RSSIEND */ 3495 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 3496 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 3497 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ 3498 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ 3499 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ 3500 3501 /* Bit 6 : Write '1' to disable interrupt for event DEVMISS */ 3502 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 3503 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 3504 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ 3505 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ 3506 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ 3507 3508 /* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */ 3509 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 3510 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 3511 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ 3512 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ 3513 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ 3514 3515 /* Bit 4 : Write '1' to disable interrupt for event DISABLED */ 3516 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 3517 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 3518 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ 3519 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ 3520 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ 3521 3522 /* Bit 3 : Write '1' to disable interrupt for event END */ 3523 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ 3524 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 3525 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 3526 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 3527 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ 3528 3529 /* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */ 3530 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 3531 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 3532 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ 3533 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ 3534 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ 3535 3536 /* Bit 1 : Write '1' to disable interrupt for event ADDRESS */ 3537 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 3538 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 3539 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ 3540 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ 3541 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ 3542 3543 /* Bit 0 : Write '1' to disable interrupt for event READY */ 3544 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 3545 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 3546 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ 3547 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ 3548 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ 3549 3550 /* Register: RADIO_CRCSTATUS */ 3551 /* Description: CRC status */ 3552 3553 /* Bit 0 : CRC status of packet received */ 3554 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ 3555 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ 3556 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ 3557 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ 3558 3559 /* Register: RADIO_RXMATCH */ 3560 /* Description: Received address */ 3561 3562 /* Bits 2..0 : Received address */ 3563 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ 3564 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ 3565 3566 /* Register: RADIO_RXCRC */ 3567 /* Description: CRC field of previously received packet */ 3568 3569 /* Bits 23..0 : CRC field of previously received packet */ 3570 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ 3571 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ 3572 3573 /* Register: RADIO_DAI */ 3574 /* Description: Device address match index */ 3575 3576 /* Bits 2..0 : Device address match index */ 3577 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ 3578 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ 3579 3580 /* Register: RADIO_PDUSTAT */ 3581 /* Description: Payload status */ 3582 3583 /* Bits 2..1 : Status on what rate packet is received with in Long Range */ 3584 #define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */ 3585 #define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */ 3586 #define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125 kbps */ 3587 #define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500 kbps */ 3588 3589 /* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */ 3590 #define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */ 3591 #define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */ 3592 #define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */ 3593 #define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */ 3594 3595 /* Register: RADIO_CTESTATUS */ 3596 /* Description: CTEInfo parsed from received packet */ 3597 3598 /* Bits 7..6 : CTEType parsed from packet */ 3599 #define RADIO_CTESTATUS_CTETYPE_Pos (6UL) /*!< Position of CTETYPE field. */ 3600 #define RADIO_CTESTATUS_CTETYPE_Msk (0x3UL << RADIO_CTESTATUS_CTETYPE_Pos) /*!< Bit mask of CTETYPE field. */ 3601 3602 /* Bit 5 : RFU parsed from packet */ 3603 #define RADIO_CTESTATUS_RFU_Pos (5UL) /*!< Position of RFU field. */ 3604 #define RADIO_CTESTATUS_RFU_Msk (0x1UL << RADIO_CTESTATUS_RFU_Pos) /*!< Bit mask of RFU field. */ 3605 3606 /* Bits 4..0 : CTETime parsed from packet */ 3607 #define RADIO_CTESTATUS_CTETIME_Pos (0UL) /*!< Position of CTETIME field. */ 3608 #define RADIO_CTESTATUS_CTETIME_Msk (0x1FUL << RADIO_CTESTATUS_CTETIME_Pos) /*!< Bit mask of CTETIME field. */ 3609 3610 /* Register: RADIO_DFESTATUS */ 3611 /* Description: DFE status information */ 3612 3613 /* Bit 4 : Internal state of sampling state machine */ 3614 #define RADIO_DFESTATUS_SAMPLINGSTATE_Pos (4UL) /*!< Position of SAMPLINGSTATE field. */ 3615 #define RADIO_DFESTATUS_SAMPLINGSTATE_Msk (0x1UL << RADIO_DFESTATUS_SAMPLINGSTATE_Pos) /*!< Bit mask of SAMPLINGSTATE field. */ 3616 #define RADIO_DFESTATUS_SAMPLINGSTATE_Idle (0UL) /*!< Sampling state Idle */ 3617 #define RADIO_DFESTATUS_SAMPLINGSTATE_Sampling (1UL) /*!< Sampling state Sampling */ 3618 3619 /* Bits 2..0 : Internal state of switching state machine */ 3620 #define RADIO_DFESTATUS_SWITCHINGSTATE_Pos (0UL) /*!< Position of SWITCHINGSTATE field. */ 3621 #define RADIO_DFESTATUS_SWITCHINGSTATE_Msk (0x7UL << RADIO_DFESTATUS_SWITCHINGSTATE_Pos) /*!< Bit mask of SWITCHINGSTATE field. */ 3622 #define RADIO_DFESTATUS_SWITCHINGSTATE_Idle (0UL) /*!< Switching state Idle */ 3623 #define RADIO_DFESTATUS_SWITCHINGSTATE_Offset (1UL) /*!< Switching state Offset */ 3624 #define RADIO_DFESTATUS_SWITCHINGSTATE_Guard (2UL) /*!< Switching state Guard */ 3625 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ref (3UL) /*!< Switching state Ref */ 3626 #define RADIO_DFESTATUS_SWITCHINGSTATE_Switching (4UL) /*!< Switching state Switching */ 3627 #define RADIO_DFESTATUS_SWITCHINGSTATE_Ending (5UL) /*!< Switching state Ending */ 3628 3629 /* Register: RADIO_PACKETPTR */ 3630 /* Description: Packet pointer */ 3631 3632 /* Bits 31..0 : Packet pointer */ 3633 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ 3634 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ 3635 3636 /* Register: RADIO_FREQUENCY */ 3637 /* Description: Frequency */ 3638 3639 /* Bit 8 : Channel map selection */ 3640 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ 3641 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ 3642 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHz and 2500 MHz */ 3643 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHz and 2460 MHz */ 3644 3645 /* Bits 6..0 : Radio channel frequency */ 3646 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 3647 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 3648 3649 /* Register: RADIO_TXPOWER */ 3650 /* Description: Output power */ 3651 3652 /* Bits 7..0 : RADIO output power */ 3653 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ 3654 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ 3655 #define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */ 3656 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ 3657 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */ 3658 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ 3659 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ 3660 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ 3661 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ 3662 #define RADIO_TXPOWER_TXPOWER_Neg7dBm (0xF9UL) /*!< -7 dBm */ 3663 #define RADIO_TXPOWER_TXPOWER_Neg6dBm (0xFAUL) /*!< -6 dBm */ 3664 #define RADIO_TXPOWER_TXPOWER_Neg5dBm (0xFBUL) /*!< -5 dBm */ 3665 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ 3666 #define RADIO_TXPOWER_TXPOWER_Neg3dBm (0xFDUL) /*!< -3 dBm */ 3667 #define RADIO_TXPOWER_TXPOWER_Neg2dBm (0xFEUL) /*!< -2 dBm */ 3668 #define RADIO_TXPOWER_TXPOWER_Neg1dBm (0xFFUL) /*!< -1 dBm */ 3669 3670 /* Register: RADIO_MODE */ 3671 /* Description: Data rate and modulation */ 3672 3673 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */ 3674 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 3675 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 3676 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbps Nordic proprietary radio mode */ 3677 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */ 3678 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */ 3679 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */ 3680 #define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long Range 125 kbps TX, 125 kbps and 500 kbps RX */ 3681 #define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long Range 500 kbps TX, 125 kbps and 500 kbps RX */ 3682 #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbps */ 3683 3684 /* Register: RADIO_PCNF0 */ 3685 /* Description: Packet configuration register 0 */ 3686 3687 /* Bits 30..29 : Length of TERM field in Long Range operation */ 3688 #define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */ 3689 #define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */ 3690 3691 /* Bit 26 : Indicates if LENGTH field contains CRC or not */ 3692 #define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */ 3693 #define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */ 3694 #define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */ 3695 #define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */ 3696 3697 /* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */ 3698 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ 3699 #define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ 3700 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ 3701 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ 3702 #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ 3703 #define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for Bluetooth LE Long Range */ 3704 3705 /* Bits 23..22 : Length of code indicator - Long Range */ 3706 #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ 3707 #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ 3708 3709 /* Bit 20 : Include or exclude S1 field in RAM */ 3710 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ 3711 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ 3712 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ 3713 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ 3714 3715 /* Bits 19..16 : Length on air of S1 field in number of bits */ 3716 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ 3717 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ 3718 3719 /* Bit 8 : Length on air of S0 field in number of bytes */ 3720 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ 3721 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ 3722 3723 /* Bits 3..0 : Length on air of LENGTH field in number of bits */ 3724 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ 3725 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ 3726 3727 /* Register: RADIO_PCNF1 */ 3728 /* Description: Packet configuration register 1 */ 3729 3730 /* Bit 25 : Enable or disable packet whitening */ 3731 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ 3732 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ 3733 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ 3734 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ 3735 3736 /* Bit 24 : On-air endianness of packet, this applies to the S0, LENGTH, S1, and the PAYLOAD fields. */ 3737 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ 3738 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ 3739 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ 3740 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ 3741 3742 /* Bits 18..16 : Base address length in number of bytes */ 3743 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ 3744 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ 3745 3746 /* Bits 15..8 : Static length in number of bytes */ 3747 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ 3748 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ 3749 3750 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ 3751 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ 3752 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ 3753 3754 /* Register: RADIO_BASE0 */ 3755 /* Description: Base address 0 */ 3756 3757 /* Bits 31..0 : Base address 0 */ 3758 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ 3759 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ 3760 3761 /* Register: RADIO_BASE1 */ 3762 /* Description: Base address 1 */ 3763 3764 /* Bits 31..0 : Base address 1 */ 3765 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ 3766 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ 3767 3768 /* Register: RADIO_PREFIX0 */ 3769 /* Description: Prefixes bytes for logical addresses 0-3 */ 3770 3771 /* Bits 31..24 : Address prefix 3. */ 3772 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ 3773 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ 3774 3775 /* Bits 23..16 : Address prefix 2. */ 3776 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ 3777 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ 3778 3779 /* Bits 15..8 : Address prefix 1. */ 3780 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ 3781 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ 3782 3783 /* Bits 7..0 : Address prefix 0. */ 3784 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ 3785 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ 3786 3787 /* Register: RADIO_PREFIX1 */ 3788 /* Description: Prefixes bytes for logical addresses 4-7 */ 3789 3790 /* Bits 31..24 : Address prefix 7. */ 3791 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ 3792 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ 3793 3794 /* Bits 23..16 : Address prefix 6. */ 3795 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ 3796 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ 3797 3798 /* Bits 15..8 : Address prefix 5. */ 3799 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ 3800 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ 3801 3802 /* Bits 7..0 : Address prefix 4. */ 3803 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ 3804 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ 3805 3806 /* Register: RADIO_TXADDRESS */ 3807 /* Description: Transmit address select */ 3808 3809 /* Bits 2..0 : Transmit address select */ 3810 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ 3811 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ 3812 3813 /* Register: RADIO_RXADDRESSES */ 3814 /* Description: Receive address select */ 3815 3816 /* Bit 7 : Enable or disable reception on logical address 7. */ 3817 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ 3818 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ 3819 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ 3820 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ 3821 3822 /* Bit 6 : Enable or disable reception on logical address 6. */ 3823 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ 3824 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ 3825 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ 3826 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ 3827 3828 /* Bit 5 : Enable or disable reception on logical address 5. */ 3829 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ 3830 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ 3831 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ 3832 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ 3833 3834 /* Bit 4 : Enable or disable reception on logical address 4. */ 3835 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ 3836 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ 3837 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ 3838 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ 3839 3840 /* Bit 3 : Enable or disable reception on logical address 3. */ 3841 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ 3842 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ 3843 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ 3844 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ 3845 3846 /* Bit 2 : Enable or disable reception on logical address 2. */ 3847 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ 3848 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ 3849 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ 3850 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ 3851 3852 /* Bit 1 : Enable or disable reception on logical address 1. */ 3853 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ 3854 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ 3855 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ 3856 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ 3857 3858 /* Bit 0 : Enable or disable reception on logical address 0. */ 3859 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ 3860 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ 3861 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ 3862 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ 3863 3864 /* Register: RADIO_CRCCNF */ 3865 /* Description: CRC configuration */ 3866 3867 /* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */ 3868 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ 3869 #define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ 3870 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ 3871 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ 3872 #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ 3873 3874 /* Bits 1..0 : CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported */ 3875 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ 3876 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ 3877 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ 3878 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ 3879 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ 3880 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ 3881 3882 /* Register: RADIO_CRCPOLY */ 3883 /* Description: CRC polynomial */ 3884 3885 /* Bits 23..0 : CRC polynomial */ 3886 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ 3887 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ 3888 3889 /* Register: RADIO_CRCINIT */ 3890 /* Description: CRC initial value */ 3891 3892 /* Bits 23..0 : CRC initial value */ 3893 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ 3894 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ 3895 3896 /* Register: RADIO_TIFS */ 3897 /* Description: Interframe spacing in us */ 3898 3899 /* Bits 9..0 : Interframe spacing in us. */ 3900 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ 3901 #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ 3902 3903 /* Register: RADIO_RSSISAMPLE */ 3904 /* Description: RSSI sample */ 3905 3906 /* Bits 6..0 : RSSI sample. */ 3907 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ 3908 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ 3909 3910 /* Register: RADIO_STATE */ 3911 /* Description: Current radio state */ 3912 3913 /* Bits 3..0 : Current radio state */ 3914 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ 3915 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ 3916 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ 3917 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ 3918 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ 3919 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ 3920 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ 3921 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ 3922 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ 3923 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ 3924 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ 3925 3926 /* Register: RADIO_DATAWHITEIV */ 3927 /* Description: Data whitening initial value */ 3928 3929 /* Bits 6..0 : Data whitening initial value. Bit 6 is hardwired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ 3930 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ 3931 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ 3932 3933 /* Register: RADIO_BCC */ 3934 /* Description: Bit counter compare */ 3935 3936 /* Bits 31..0 : Bit counter compare */ 3937 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ 3938 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ 3939 3940 /* Register: RADIO_DAB */ 3941 /* Description: Description collection: Device address base segment n */ 3942 3943 /* Bits 31..0 : Device address base segment n */ 3944 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ 3945 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ 3946 3947 /* Register: RADIO_DAP */ 3948 /* Description: Description collection: Device address prefix n */ 3949 3950 /* Bits 15..0 : Device address prefix n */ 3951 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ 3952 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ 3953 3954 /* Register: RADIO_DACNF */ 3955 /* Description: Device address match configuration */ 3956 3957 /* Bit 15 : TxAdd for device address 7 */ 3958 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ 3959 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ 3960 3961 /* Bit 14 : TxAdd for device address 6 */ 3962 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ 3963 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ 3964 3965 /* Bit 13 : TxAdd for device address 5 */ 3966 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ 3967 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ 3968 3969 /* Bit 12 : TxAdd for device address 4 */ 3970 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ 3971 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ 3972 3973 /* Bit 11 : TxAdd for device address 3 */ 3974 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ 3975 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ 3976 3977 /* Bit 10 : TxAdd for device address 2 */ 3978 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ 3979 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ 3980 3981 /* Bit 9 : TxAdd for device address 1 */ 3982 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ 3983 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ 3984 3985 /* Bit 8 : TxAdd for device address 0 */ 3986 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ 3987 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ 3988 3989 /* Bit 7 : Enable or disable device address matching using device address 7 */ 3990 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ 3991 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ 3992 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ 3993 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ 3994 3995 /* Bit 6 : Enable or disable device address matching using device address 6 */ 3996 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ 3997 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ 3998 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ 3999 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ 4000 4001 /* Bit 5 : Enable or disable device address matching using device address 5 */ 4002 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ 4003 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ 4004 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ 4005 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ 4006 4007 /* Bit 4 : Enable or disable device address matching using device address 4 */ 4008 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ 4009 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ 4010 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ 4011 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ 4012 4013 /* Bit 3 : Enable or disable device address matching using device address 3 */ 4014 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ 4015 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ 4016 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ 4017 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ 4018 4019 /* Bit 2 : Enable or disable device address matching using device address 2 */ 4020 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ 4021 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ 4022 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ 4023 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ 4024 4025 /* Bit 1 : Enable or disable device address matching using device address 1 */ 4026 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ 4027 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ 4028 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ 4029 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ 4030 4031 /* Bit 0 : Enable or disable device address matching using device address 0 */ 4032 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ 4033 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ 4034 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ 4035 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ 4036 4037 /* Register: RADIO_MHRMATCHCONF */ 4038 /* Description: Search pattern configuration */ 4039 4040 /* Bits 31..0 : Search pattern configuration */ 4041 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */ 4042 #define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */ 4043 4044 /* Register: RADIO_MHRMATCHMAS */ 4045 /* Description: Pattern mask */ 4046 4047 /* Bits 31..0 : Pattern mask */ 4048 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */ 4049 #define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */ 4050 4051 /* Register: RADIO_MODECNF0 */ 4052 /* Description: Radio mode configuration register 0 */ 4053 4054 /* Bits 9..8 : Default TX value */ 4055 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ 4056 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ 4057 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ 4058 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ 4059 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ 4060 4061 /* Bit 0 : Radio ramp-up time */ 4062 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ 4063 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ 4064 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ 4065 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */ 4066 4067 /* Register: RADIO_SFD */ 4068 /* Description: IEEE 802.15.4 start of frame delimiter */ 4069 4070 /* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */ 4071 #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */ 4072 #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */ 4073 4074 /* Register: RADIO_EDCNT */ 4075 /* Description: IEEE 802.15.4 energy detect loop count */ 4076 4077 /* Bits 20..0 : IEEE 802.15.4 energy detect loop count */ 4078 #define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */ 4079 #define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */ 4080 4081 /* Register: RADIO_EDSAMPLE */ 4082 /* Description: IEEE 802.15.4 energy detect level */ 4083 4084 /* Bits 7..0 : IEEE 802.15.4 energy detect level */ 4085 #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */ 4086 #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */ 4087 4088 /* Register: RADIO_CCACTRL */ 4089 /* Description: IEEE 802.15.4 clear channel assessment control */ 4090 4091 /* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */ 4092 #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */ 4093 #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */ 4094 4095 /* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode, and CarrierOrEdMode. */ 4096 #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */ 4097 #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */ 4098 4099 /* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */ 4100 #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */ 4101 #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */ 4102 4103 /* Bits 2..0 : CCA mode of operation */ 4104 #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */ 4105 #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */ 4106 #define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */ 4107 #define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */ 4108 #define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */ 4109 #define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */ 4110 #define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ 4111 4112 /* Register: RADIO_DFEMODE */ 4113 /* Description: Whether to use Angle-of-Arrival (AOA) or Angle-of-Departure (AOD) */ 4114 4115 /* Bits 1..0 : Direction finding operation mode */ 4116 #define RADIO_DFEMODE_DFEOPMODE_Pos (0UL) /*!< Position of DFEOPMODE field. */ 4117 #define RADIO_DFEMODE_DFEOPMODE_Msk (0x3UL << RADIO_DFEMODE_DFEOPMODE_Pos) /*!< Bit mask of DFEOPMODE field. */ 4118 #define RADIO_DFEMODE_DFEOPMODE_Disabled (0UL) /*!< Direction finding mode disabled */ 4119 #define RADIO_DFEMODE_DFEOPMODE_AoD (2UL) /*!< Direction finding mode set to AoD */ 4120 #define RADIO_DFEMODE_DFEOPMODE_AoA (3UL) /*!< Direction finding mode set to AoA */ 4121 4122 /* Register: RADIO_CTEINLINECONF */ 4123 /* Description: Configuration for CTE inline mode */ 4124 4125 /* Bits 31..24 : S0 bit mask to set which bit to match */ 4126 #define RADIO_CTEINLINECONF_S0MASK_Pos (24UL) /*!< Position of S0MASK field. */ 4127 #define RADIO_CTEINLINECONF_S0MASK_Msk (0xFFUL << RADIO_CTEINLINECONF_S0MASK_Pos) /*!< Bit mask of S0MASK field. */ 4128 4129 /* Bits 23..16 : S0 bit pattern to match */ 4130 #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */ 4131 #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */ 4132 4133 /* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ 4134 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */ 4135 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */ 4136 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4 us */ 4137 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2 us */ 4138 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1 us */ 4139 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5 us */ 4140 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25 us */ 4141 #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125 us */ 4142 4143 /* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ 4144 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */ 4145 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */ 4146 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4 us */ 4147 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2 us */ 4148 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1 us */ 4149 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5 us */ 4150 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25 us */ 4151 #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125 us */ 4152 4153 /* Bits 7..6 : Max range of CTETime */ 4154 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */ 4155 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */ 4156 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 */ 4157 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8 us unit */ 4158 #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8 us unit */ 4159 4160 /* Bit 4 : Sampling/switching if CRC is not OK */ 4161 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */ 4162 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Msk (0x1UL << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos) /*!< Bit mask of CTEERRORHANDLING field. */ 4163 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_No (0UL) /*!< No sampling and antenna switching when CRC is not OK */ 4164 #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Yes (1UL) /*!< Sampling and antenna switching also when CRC is not OK */ 4165 4166 /* Bit 3 : CTEInfo is S1 byte or not */ 4167 #define RADIO_CTEINLINECONF_CTEINFOINS1_Pos (3UL) /*!< Position of CTEINFOINS1 field. */ 4168 #define RADIO_CTEINLINECONF_CTEINFOINS1_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINFOINS1_Pos) /*!< Bit mask of CTEINFOINS1 field. */ 4169 #define RADIO_CTEINLINECONF_CTEINFOINS1_NotInS1 (0UL) /*!< CTEInfo is NOT in S1 byte (advertising PDU) */ 4170 #define RADIO_CTEINLINECONF_CTEINFOINS1_InS1 (1UL) /*!< CTEInfo is in S1 byte (data PDU) */ 4171 4172 /* Bit 0 : Enable parsing of CTEInfo from received packet in BLE modes */ 4173 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos (0UL) /*!< Position of CTEINLINECTRLEN field. */ 4174 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Msk (0x1UL << RADIO_CTEINLINECONF_CTEINLINECTRLEN_Pos) /*!< Bit mask of CTEINLINECTRLEN field. */ 4175 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Disabled (0UL) /*!< Parsing of CTEInfo is disabled */ 4176 #define RADIO_CTEINLINECONF_CTEINLINECTRLEN_Enabled (1UL) /*!< Parsing of CTEInfo is enabled */ 4177 4178 /* Register: RADIO_DFECTRL1 */ 4179 /* Description: Various configuration for Direction finding */ 4180 4181 /* Bits 27..24 : Gain will be lowered by the specified number of gain steps at the start of CTE */ 4182 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */ 4183 #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field. */ 4184 4185 /* Bits 23..20 : Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. */ 4186 #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL) /*!< Position of REPEATPATTERN field. */ 4187 #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field. */ 4188 #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0UL) /*!< Do not repeat (1 time in total) */ 4189 4190 /* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */ 4191 #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */ 4192 #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */ 4193 #define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4 us */ 4194 #define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2 us */ 4195 #define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1 us */ 4196 #define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5 us */ 4197 #define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25 us */ 4198 #define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125 us */ 4199 4200 /* Bit 15 : Whether to sample I/Q or magnitude/phase */ 4201 #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */ 4202 #define RADIO_DFECTRL1_SAMPLETYPE_Msk (0x1UL << RADIO_DFECTRL1_SAMPLETYPE_Pos) /*!< Bit mask of SAMPLETYPE field. */ 4203 #define RADIO_DFECTRL1_SAMPLETYPE_IQ (0UL) /*!< Complex samples in I and Q */ 4204 #define RADIO_DFECTRL1_SAMPLETYPE_MagPhase (1UL) /*!< Complex samples as magnitude and phase */ 4205 4206 /* Bits 14..12 : Interval between samples in the REFERENCE period */ 4207 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */ 4208 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */ 4209 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4 us */ 4210 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2 us */ 4211 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1 us */ 4212 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5 us */ 4213 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25 us */ 4214 #define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125 us */ 4215 4216 /* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */ 4217 #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */ 4218 #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */ 4219 #define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4 us */ 4220 #define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2 us */ 4221 #define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1 us */ 4222 4223 /* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */ 4224 #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */ 4225 #define RADIO_DFECTRL1_DFEINEXTENSION_Msk (0x1UL << RADIO_DFECTRL1_DFEINEXTENSION_Pos) /*!< Bit mask of DFEINEXTENSION field. */ 4226 #define RADIO_DFECTRL1_DFEINEXTENSION_Payload (0UL) /*!< Antenna switching/sampling is done in the packet payload */ 4227 #define RADIO_DFECTRL1_DFEINEXTENSION_CRC (1UL) /*!< AoA/AoD procedure triggered at end of CRC */ 4228 4229 /* Bits 5..0 : Length of the AoA/AoD procedure in number of 8 us units */ 4230 #define RADIO_DFECTRL1_NUMBEROF8US_Pos (0UL) /*!< Position of NUMBEROF8US field. */ 4231 #define RADIO_DFECTRL1_NUMBEROF8US_Msk (0x3FUL << RADIO_DFECTRL1_NUMBEROF8US_Pos) /*!< Bit mask of NUMBEROF8US field. */ 4232 4233 /* Register: RADIO_DFECTRL2 */ 4234 /* Description: Start offset for Direction finding */ 4235 4236 /* Bits 27..16 : Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period */ 4237 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */ 4238 #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */ 4239 4240 /* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles */ 4241 #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */ 4242 #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */ 4243 4244 /* Register: RADIO_SWITCHPATTERN */ 4245 /* Description: GPIO patterns to be used for each antenna */ 4246 4247 /* Bits 7..0 : Fill array of GPIO patterns for antenna control. */ 4248 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */ 4249 #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */ 4250 4251 /* Register: RADIO_CLEARPATTERN */ 4252 /* Description: Clear the GPIO pattern array for antenna control */ 4253 4254 /* Bit 0 : Clears GPIO pattern array for antenna control */ 4255 #define RADIO_CLEARPATTERN_CLEARPATTERN_Pos (0UL) /*!< Position of CLEARPATTERN field. */ 4256 #define RADIO_CLEARPATTERN_CLEARPATTERN_Msk (0x1UL << RADIO_CLEARPATTERN_CLEARPATTERN_Pos) /*!< Bit mask of CLEARPATTERN field. */ 4257 #define RADIO_CLEARPATTERN_CLEARPATTERN_Clear (1UL) /*!< Clear the GPIO pattern */ 4258 4259 /* Register: RADIO_PSEL_DFEGPIO */ 4260 /* Description: Description collection: Pin select for DFE pin n */ 4261 4262 /* Bit 31 : Connection */ 4263 #define RADIO_PSEL_DFEGPIO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 4264 #define RADIO_PSEL_DFEGPIO_CONNECT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 4265 #define RADIO_PSEL_DFEGPIO_CONNECT_Connected (0UL) /*!< Connect */ 4266 #define RADIO_PSEL_DFEGPIO_CONNECT_Disconnected (1UL) /*!< Disconnect */ 4267 4268 /* Bit 5 : Port number */ 4269 #define RADIO_PSEL_DFEGPIO_PORT_Pos (5UL) /*!< Position of PORT field. */ 4270 #define RADIO_PSEL_DFEGPIO_PORT_Msk (0x1UL << RADIO_PSEL_DFEGPIO_PORT_Pos) /*!< Bit mask of PORT field. */ 4271 4272 /* Bits 4..0 : Pin number */ 4273 #define RADIO_PSEL_DFEGPIO_PIN_Pos (0UL) /*!< Position of PIN field. */ 4274 #define RADIO_PSEL_DFEGPIO_PIN_Msk (0x1FUL << RADIO_PSEL_DFEGPIO_PIN_Pos) /*!< Bit mask of PIN field. */ 4275 4276 /* Register: RADIO_DFEPACKET_PTR */ 4277 /* Description: Data pointer */ 4278 4279 /* Bits 31..0 : Data pointer */ 4280 #define RADIO_DFEPACKET_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 4281 #define RADIO_DFEPACKET_PTR_PTR_Msk (0xFFFFFFFFUL << RADIO_DFEPACKET_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 4282 4283 /* Register: RADIO_DFEPACKET_MAXCNT */ 4284 /* Description: Maximum number of buffer words to transfer */ 4285 4286 /* Bits 13..0 : Maximum number of buffer words to transfer */ 4287 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 4288 #define RADIO_DFEPACKET_MAXCNT_MAXCNT_Msk (0x3FFFUL << RADIO_DFEPACKET_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 4289 4290 /* Register: RADIO_DFEPACKET_AMOUNT */ 4291 /* Description: Number of samples transferred in the last transaction */ 4292 4293 /* Bits 15..0 : Number of samples transferred in the last transaction */ 4294 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 4295 #define RADIO_DFEPACKET_AMOUNT_AMOUNT_Msk (0xFFFFUL << RADIO_DFEPACKET_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 4296 4297 /* Register: RADIO_POWER */ 4298 /* Description: Peripheral power control */ 4299 4300 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ 4301 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 4302 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 4303 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ 4304 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ 4305 4306 4307 4308 /* =========================================================================================================================== */ 4309 /* ================ RNG_NS ================ */ 4310 /* =========================================================================================================================== */ 4311 4312 4313 /** 4314 * @brief Random Number Generator (RNG_NS) 4315 */ 4316 4317 typedef struct { /*!< (@ 0x41009000) RNG_NS Structure */ 4318 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 4319 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 4320 __IM uint32_t RESERVED[30]; 4321 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 4322 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 4323 __IM uint32_t RESERVED1[30]; 4324 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 4325 written to the VALUE register */ 4326 __IM uint32_t RESERVED2[31]; 4327 __IOM uint32_t PUBLISH_VALRDY; /*!< (@ 0x00000180) Publish configuration for event VALRDY */ 4328 __IM uint32_t RESERVED3[31]; 4329 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 4330 __IM uint32_t RESERVED4[64]; 4331 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 4332 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 4333 __IM uint32_t RESERVED5[126]; 4334 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 4335 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 4336 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 4337 4338 4339 /* Peripheral: RNG */ 4340 /* Description: Random Number Generator */ 4341 4342 /* Register: RNG_TASKS_START */ 4343 /* Description: Task starting the random number generator */ 4344 4345 /* Bit 0 : Task starting the random number generator */ 4346 #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 4347 #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 4348 #define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 4349 4350 /* Register: RNG_TASKS_STOP */ 4351 /* Description: Task stopping the random number generator */ 4352 4353 /* Bit 0 : Task stopping the random number generator */ 4354 #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 4355 #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 4356 #define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 4357 4358 /* Register: RNG_SUBSCRIBE_START */ 4359 /* Description: Subscribe configuration for task START */ 4360 4361 /* Bit 31 : */ 4362 #define RNG_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 4363 #define RNG_SUBSCRIBE_START_EN_Msk (0x1UL << RNG_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 4364 #define RNG_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 4365 #define RNG_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 4366 4367 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 4368 #define RNG_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4369 #define RNG_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4370 4371 /* Register: RNG_SUBSCRIBE_STOP */ 4372 /* Description: Subscribe configuration for task STOP */ 4373 4374 /* Bit 31 : */ 4375 #define RNG_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 4376 #define RNG_SUBSCRIBE_STOP_EN_Msk (0x1UL << RNG_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 4377 #define RNG_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 4378 #define RNG_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 4379 4380 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 4381 #define RNG_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4382 #define RNG_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4383 4384 /* Register: RNG_EVENTS_VALRDY */ 4385 /* Description: Event being generated for every new random number written to the VALUE register */ 4386 4387 /* Bit 0 : Event being generated for every new random number written to the VALUE register */ 4388 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ 4389 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ 4390 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */ 4391 #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */ 4392 4393 /* Register: RNG_PUBLISH_VALRDY */ 4394 /* Description: Publish configuration for event VALRDY */ 4395 4396 /* Bit 31 : */ 4397 #define RNG_PUBLISH_VALRDY_EN_Pos (31UL) /*!< Position of EN field. */ 4398 #define RNG_PUBLISH_VALRDY_EN_Msk (0x1UL << RNG_PUBLISH_VALRDY_EN_Pos) /*!< Bit mask of EN field. */ 4399 #define RNG_PUBLISH_VALRDY_EN_Disabled (0UL) /*!< Disable publishing */ 4400 #define RNG_PUBLISH_VALRDY_EN_Enabled (1UL) /*!< Enable publishing */ 4401 4402 /* Bits 7..0 : DPPI channel that event VALRDY will publish to. */ 4403 #define RNG_PUBLISH_VALRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4404 #define RNG_PUBLISH_VALRDY_CHIDX_Msk (0xFFUL << RNG_PUBLISH_VALRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4405 4406 /* Register: RNG_SHORTS */ 4407 /* Description: Shortcuts between local events and tasks */ 4408 4409 /* Bit 0 : Shortcut between event VALRDY and task STOP */ 4410 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ 4411 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ 4412 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 4413 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 4414 4415 /* Register: RNG_INTENSET */ 4416 /* Description: Enable interrupt */ 4417 4418 /* Bit 0 : Write '1' to enable interrupt for event VALRDY */ 4419 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 4420 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 4421 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ 4422 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ 4423 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ 4424 4425 /* Register: RNG_INTENCLR */ 4426 /* Description: Disable interrupt */ 4427 4428 /* Bit 0 : Write '1' to disable interrupt for event VALRDY */ 4429 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 4430 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 4431 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ 4432 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ 4433 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ 4434 4435 /* Register: RNG_CONFIG */ 4436 /* Description: Configuration register */ 4437 4438 /* Bit 0 : Bias correction */ 4439 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ 4440 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ 4441 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ 4442 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ 4443 4444 /* Register: RNG_VALUE */ 4445 /* Description: Output random number */ 4446 4447 /* Bits 7..0 : Generated random number */ 4448 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 4449 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ 4450 4451 /* =========================================================================================================================== */ 4452 /* ================ RTC ================ */ 4453 /* =========================================================================================================================== */ 4454 4455 4456 /** 4457 * @brief Real-time counter 0 (RTC0_NS) 4458 */ 4459 4460 typedef struct { /*!< (@ 0x41011000) RTC0_NS Structure */ 4461 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 4462 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 4463 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 4464 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 4465 __IM uint32_t RESERVED[12]; 4466 __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Description collection: Capture RTC counter to 4467 CC[n] register */ 4468 __IM uint32_t RESERVED1[12]; 4469 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 4470 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 4471 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 4472 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 4473 __IM uint32_t RESERVED2[12]; 4474 __IOM uint32_t SUBSCRIBE_CAPTURE[4]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 4475 for task CAPTURE[n] */ 4476 __IM uint32_t RESERVED3[12]; 4477 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 4478 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 4479 __IM uint32_t RESERVED4[14]; 4480 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 4481 match */ 4482 __IM uint32_t RESERVED5[12]; 4483 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 4484 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 4485 __IM uint32_t RESERVED6[14]; 4486 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 4487 for event COMPARE[n] */ 4488 __IM uint32_t RESERVED7[12]; 4489 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 4490 __IM uint32_t RESERVED8[64]; 4491 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 4492 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 4493 __IM uint32_t RESERVED9[13]; 4494 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 4495 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 4496 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 4497 __IM uint32_t RESERVED10[110]; 4498 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 4499 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768 4500 / (PRESCALER + 1)). Must be written when 4501 RTC is stopped. */ 4502 __IM uint32_t RESERVED11[13]; 4503 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 4504 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 4505 4506 4507 /* Peripheral: RTC */ 4508 /* Description: Real-time counter 0 */ 4509 4510 /* Register: RTC_TASKS_START */ 4511 /* Description: Start RTC counter */ 4512 4513 /* Bit 0 : Start RTC counter */ 4514 #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 4515 #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 4516 #define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 4517 4518 /* Register: RTC_TASKS_STOP */ 4519 /* Description: Stop RTC counter */ 4520 4521 /* Bit 0 : Stop RTC counter */ 4522 #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 4523 #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 4524 #define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 4525 4526 /* Register: RTC_TASKS_CLEAR */ 4527 /* Description: Clear RTC counter */ 4528 4529 /* Bit 0 : Clear RTC counter */ 4530 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 4531 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 4532 #define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ 4533 4534 /* Register: RTC_TASKS_TRIGOVRFLW */ 4535 /* Description: Set counter to 0xFFFFF0 */ 4536 4537 /* Bit 0 : Set counter to 0xFFFFF0 */ 4538 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ 4539 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ 4540 #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ 4541 4542 /* Register: RTC_TASKS_CAPTURE */ 4543 /* Description: Description collection: Capture RTC counter to CC[n] register */ 4544 4545 /* Bit 0 : Capture RTC counter to CC[n] register */ 4546 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ 4547 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << RTC_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ 4548 #define RTC_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ 4549 4550 /* Register: RTC_SUBSCRIBE_START */ 4551 /* Description: Subscribe configuration for task START */ 4552 4553 /* Bit 31 : */ 4554 #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 4555 #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 4556 #define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 4557 #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 4558 4559 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 4560 #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4561 #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4562 4563 /* Register: RTC_SUBSCRIBE_STOP */ 4564 /* Description: Subscribe configuration for task STOP */ 4565 4566 /* Bit 31 : */ 4567 #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 4568 #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 4569 #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 4570 #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 4571 4572 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 4573 #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4574 #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4575 4576 /* Register: RTC_SUBSCRIBE_CLEAR */ 4577 /* Description: Subscribe configuration for task CLEAR */ 4578 4579 /* Bit 31 : */ 4580 #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ 4581 #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ 4582 #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ 4583 #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ 4584 4585 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ 4586 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4587 #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4588 4589 /* Register: RTC_SUBSCRIBE_TRIGOVRFLW */ 4590 /* Description: Subscribe configuration for task TRIGOVRFLW */ 4591 4592 /* Bit 31 : */ 4593 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ 4594 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */ 4595 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */ 4596 #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */ 4597 4598 /* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */ 4599 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4600 #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4601 4602 /* Register: RTC_SUBSCRIBE_CAPTURE */ 4603 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */ 4604 4605 /* Bit 31 : */ 4606 #define RTC_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ 4607 #define RTC_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << RTC_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ 4608 #define RTC_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */ 4609 #define RTC_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */ 4610 4611 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */ 4612 #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4613 #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4614 4615 /* Register: RTC_EVENTS_TICK */ 4616 /* Description: Event on counter increment */ 4617 4618 /* Bit 0 : Event on counter increment */ 4619 #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ 4620 #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ 4621 #define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ 4622 #define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ 4623 4624 /* Register: RTC_EVENTS_OVRFLW */ 4625 /* Description: Event on counter overflow */ 4626 4627 /* Bit 0 : Event on counter overflow */ 4628 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ 4629 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ 4630 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ 4631 #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ 4632 4633 /* Register: RTC_EVENTS_COMPARE */ 4634 /* Description: Description collection: Compare event on CC[n] match */ 4635 4636 /* Bit 0 : Compare event on CC[n] match */ 4637 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 4638 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 4639 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ 4640 #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ 4641 4642 /* Register: RTC_PUBLISH_TICK */ 4643 /* Description: Publish configuration for event TICK */ 4644 4645 /* Bit 31 : */ 4646 #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */ 4647 #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */ 4648 #define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */ 4649 #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */ 4650 4651 /* Bits 7..0 : DPPI channel that event TICK will publish to. */ 4652 #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4653 #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4654 4655 /* Register: RTC_PUBLISH_OVRFLW */ 4656 /* Description: Publish configuration for event OVRFLW */ 4657 4658 /* Bit 31 : */ 4659 #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ 4660 #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */ 4661 #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */ 4662 #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */ 4663 4664 /* Bits 7..0 : DPPI channel that event OVRFLW will publish to. */ 4665 #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4666 #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4667 4668 /* Register: RTC_PUBLISH_COMPARE */ 4669 /* Description: Description collection: Publish configuration for event COMPARE[n] */ 4670 4671 /* Bit 31 : */ 4672 #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ 4673 #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ 4674 #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ 4675 #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ 4676 4677 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */ 4678 #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4679 #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4680 4681 /* Register: RTC_SHORTS */ 4682 /* Description: Shortcuts between local events and tasks */ 4683 4684 /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ 4685 #define RTC_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ 4686 #define RTC_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ 4687 #define RTC_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 4688 #define RTC_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 4689 4690 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ 4691 #define RTC_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 4692 #define RTC_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << RTC_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 4693 #define RTC_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 4694 #define RTC_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 4695 4696 /* Register: RTC_INTENSET */ 4697 /* Description: Enable interrupt */ 4698 4699 /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ 4700 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4701 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4702 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 4703 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 4704 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ 4705 4706 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ 4707 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4708 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4709 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 4710 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 4711 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 4712 4713 /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ 4714 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4715 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4716 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 4717 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 4718 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ 4719 4720 /* Bit 0 : Write '1' to enable interrupt for event TICK */ 4721 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 4722 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 4723 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 4724 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 4725 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ 4726 4727 /* Register: RTC_INTENCLR */ 4728 /* Description: Disable interrupt */ 4729 4730 /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ 4731 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4732 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4733 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 4734 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 4735 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 4736 4737 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ 4738 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4739 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4740 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 4741 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 4742 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 4743 4744 /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ 4745 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4746 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4747 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 4748 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 4749 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 4750 4751 /* Bit 0 : Write '1' to disable interrupt for event TICK */ 4752 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 4753 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 4754 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 4755 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 4756 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ 4757 4758 /* Register: RTC_EVTEN */ 4759 /* Description: Enable or disable event routing */ 4760 4761 /* Bit 19 : Enable or disable event routing for event COMPARE[3] */ 4762 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4763 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4764 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ 4765 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ 4766 4767 /* Bit 16 : Enable or disable event routing for event COMPARE[0] */ 4768 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4769 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4770 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ 4771 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ 4772 4773 /* Bit 1 : Enable or disable event routing for event OVRFLW */ 4774 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4775 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4776 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ 4777 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ 4778 4779 /* Bit 0 : Enable or disable event routing for event TICK */ 4780 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ 4781 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ 4782 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ 4783 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ 4784 4785 /* Register: RTC_EVTENSET */ 4786 /* Description: Enable event routing */ 4787 4788 /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ 4789 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4790 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4791 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 4792 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 4793 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ 4794 4795 /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ 4796 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4797 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4798 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 4799 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 4800 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ 4801 4802 /* Bit 1 : Write '1' to enable event routing for event OVRFLW */ 4803 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4804 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4805 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 4806 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 4807 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ 4808 4809 /* Bit 0 : Write '1' to enable event routing for event TICK */ 4810 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 4811 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 4812 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 4813 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 4814 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ 4815 4816 /* Register: RTC_EVTENCLR */ 4817 /* Description: Disable event routing */ 4818 4819 /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ 4820 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 4821 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 4822 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 4823 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 4824 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 4825 4826 /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ 4827 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 4828 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 4829 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 4830 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 4831 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 4832 4833 /* Bit 1 : Write '1' to disable event routing for event OVRFLW */ 4834 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 4835 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 4836 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 4837 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 4838 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 4839 4840 /* Bit 0 : Write '1' to disable event routing for event TICK */ 4841 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 4842 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 4843 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 4844 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 4845 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ 4846 4847 /* Register: RTC_COUNTER */ 4848 /* Description: Current counter value */ 4849 4850 /* Bits 23..0 : Counter value */ 4851 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ 4852 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ 4853 4854 /* Register: RTC_PRESCALER */ 4855 /* Description: 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. */ 4856 4857 /* Bits 11..0 : Prescaler value */ 4858 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 4859 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 4860 4861 /* Register: RTC_CC */ 4862 /* Description: Description collection: Compare register n */ 4863 4864 /* Bits 23..0 : Compare value */ 4865 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ 4866 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ 4867 4868 4869 /* =========================================================================================================================== */ 4870 /* ================ TEMP ================ */ 4871 /* =========================================================================================================================== */ 4872 4873 4874 /** 4875 * @brief Temperature Sensor (TEMP) 4876 */ 4877 4878 typedef struct { /*!< (@ 0x41010000) TEMP_NS Structure */ 4879 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 4880 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 4881 __IM uint32_t RESERVED[30]; 4882 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 4883 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 4884 __IM uint32_t RESERVED1[30]; 4885 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 4886 __IM uint32_t RESERVED2[31]; 4887 __IOM uint32_t PUBLISH_DATARDY; /*!< (@ 0x00000180) Publish configuration for event DATARDY */ 4888 __IM uint32_t RESERVED3[96]; 4889 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 4890 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 4891 __IM uint32_t RESERVED4[127]; 4892 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 4893 __IM uint32_t RESERVED5[5]; 4894 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ 4895 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ 4896 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ 4897 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ 4898 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ 4899 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ 4900 __IM uint32_t RESERVED6[2]; 4901 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ 4902 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ 4903 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ 4904 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ 4905 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ 4906 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ 4907 __IM uint32_t RESERVED7[2]; 4908 __IOM uint32_t T0; /*!< (@ 0x00000560) Endpoint of first piecewise linear function */ 4909 __IOM uint32_t T1; /*!< (@ 0x00000564) Endpoint of second piecewise linear function */ 4910 __IOM uint32_t T2; /*!< (@ 0x00000568) Endpoint of third piecewise linear function */ 4911 __IOM uint32_t T3; /*!< (@ 0x0000056C) Endpoint of fourth piecewise linear function */ 4912 __IOM uint32_t T4; /*!< (@ 0x00000570) Endpoint of fifth piecewise linear function */ 4913 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 4914 4915 4916 /* Peripheral: TEMP */ 4917 /* Description: Temperature Sensor */ 4918 4919 /* Register: TEMP_TASKS_START */ 4920 /* Description: Start temperature measurement */ 4921 4922 /* Bit 0 : Start temperature measurement */ 4923 #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 4924 #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 4925 #define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 4926 4927 /* Register: TEMP_TASKS_STOP */ 4928 /* Description: Stop temperature measurement */ 4929 4930 /* Bit 0 : Stop temperature measurement */ 4931 #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 4932 #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 4933 #define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 4934 4935 /* Register: TEMP_SUBSCRIBE_START */ 4936 /* Description: Subscribe configuration for task START */ 4937 4938 /* Bit 31 : */ 4939 #define TEMP_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 4940 #define TEMP_SUBSCRIBE_START_EN_Msk (0x1UL << TEMP_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 4941 #define TEMP_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 4942 #define TEMP_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 4943 4944 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 4945 #define TEMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4946 #define TEMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4947 4948 /* Register: TEMP_SUBSCRIBE_STOP */ 4949 /* Description: Subscribe configuration for task STOP */ 4950 4951 /* Bit 31 : */ 4952 #define TEMP_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 4953 #define TEMP_SUBSCRIBE_STOP_EN_Msk (0x1UL << TEMP_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 4954 #define TEMP_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 4955 #define TEMP_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 4956 4957 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 4958 #define TEMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4959 #define TEMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4960 4961 /* Register: TEMP_EVENTS_DATARDY */ 4962 /* Description: Temperature measurement complete, data ready */ 4963 4964 /* Bit 0 : Temperature measurement complete, data ready */ 4965 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ 4966 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ 4967 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */ 4968 #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */ 4969 4970 /* Register: TEMP_PUBLISH_DATARDY */ 4971 /* Description: Publish configuration for event DATARDY */ 4972 4973 /* Bit 31 : */ 4974 #define TEMP_PUBLISH_DATARDY_EN_Pos (31UL) /*!< Position of EN field. */ 4975 #define TEMP_PUBLISH_DATARDY_EN_Msk (0x1UL << TEMP_PUBLISH_DATARDY_EN_Pos) /*!< Bit mask of EN field. */ 4976 #define TEMP_PUBLISH_DATARDY_EN_Disabled (0UL) /*!< Disable publishing */ 4977 #define TEMP_PUBLISH_DATARDY_EN_Enabled (1UL) /*!< Enable publishing */ 4978 4979 /* Bits 7..0 : DPPI channel that event DATARDY will publish to. */ 4980 #define TEMP_PUBLISH_DATARDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 4981 #define TEMP_PUBLISH_DATARDY_CHIDX_Msk (0xFFUL << TEMP_PUBLISH_DATARDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 4982 4983 /* Register: TEMP_INTENSET */ 4984 /* Description: Enable interrupt */ 4985 4986 /* Bit 0 : Write '1' to enable interrupt for event DATARDY */ 4987 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 4988 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 4989 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ 4990 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ 4991 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ 4992 4993 /* Register: TEMP_INTENCLR */ 4994 /* Description: Disable interrupt */ 4995 4996 /* Bit 0 : Write '1' to disable interrupt for event DATARDY */ 4997 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 4998 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 4999 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ 5000 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ 5001 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ 5002 5003 /* Register: TEMP_TEMP */ 5004 /* Description: Temperature in degC (0.25deg steps) */ 5005 5006 /* Bits 31..0 : Temperature in degC (0.25deg steps) */ 5007 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ 5008 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ 5009 5010 /* Register: TEMP_A0 */ 5011 /* Description: Slope of first piecewise linear function */ 5012 5013 /* Bits 11..0 : Slope of first piecewise linear function */ 5014 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ 5015 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ 5016 5017 /* Register: TEMP_A1 */ 5018 /* Description: Slope of second piecewise linear function */ 5019 5020 /* Bits 11..0 : Slope of second piecewise linear function */ 5021 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ 5022 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ 5023 5024 /* Register: TEMP_A2 */ 5025 /* Description: Slope of third piecewise linear function */ 5026 5027 /* Bits 11..0 : Slope of third piecewise linear function */ 5028 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ 5029 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ 5030 5031 /* Register: TEMP_A3 */ 5032 /* Description: Slope of fourth piecewise linear function */ 5033 5034 /* Bits 11..0 : Slope of fourth piecewise linear function */ 5035 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ 5036 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ 5037 5038 /* Register: TEMP_A4 */ 5039 /* Description: Slope of fifth piecewise linear function */ 5040 5041 /* Bits 11..0 : Slope of fifth piecewise linear function */ 5042 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ 5043 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ 5044 5045 /* Register: TEMP_A5 */ 5046 /* Description: Slope of sixth piecewise linear function */ 5047 5048 /* Bits 11..0 : Slope of sixth piecewise linear function */ 5049 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ 5050 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ 5051 5052 /* Register: TEMP_B0 */ 5053 /* Description: y-intercept of first piecewise linear function */ 5054 5055 /* Bits 11..0 : y-intercept of first piecewise linear function */ 5056 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ 5057 #define TEMP_B0_B0_Msk (0xFFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ 5058 5059 /* Register: TEMP_B1 */ 5060 /* Description: y-intercept of second piecewise linear function */ 5061 5062 /* Bits 11..0 : y-intercept of second piecewise linear function */ 5063 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ 5064 #define TEMP_B1_B1_Msk (0xFFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ 5065 5066 /* Register: TEMP_B2 */ 5067 /* Description: y-intercept of third piecewise linear function */ 5068 5069 /* Bits 11..0 : y-intercept of third piecewise linear function */ 5070 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ 5071 #define TEMP_B2_B2_Msk (0xFFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ 5072 5073 /* Register: TEMP_B3 */ 5074 /* Description: y-intercept of fourth piecewise linear function */ 5075 5076 /* Bits 11..0 : y-intercept of fourth piecewise linear function */ 5077 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ 5078 #define TEMP_B3_B3_Msk (0xFFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ 5079 5080 /* Register: TEMP_B4 */ 5081 /* Description: y-intercept of fifth piecewise linear function */ 5082 5083 /* Bits 11..0 : y-intercept of fifth piecewise linear function */ 5084 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ 5085 #define TEMP_B4_B4_Msk (0xFFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ 5086 5087 /* Register: TEMP_B5 */ 5088 /* Description: y-intercept of sixth piecewise linear function */ 5089 5090 /* Bits 11..0 : y-intercept of sixth piecewise linear function */ 5091 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ 5092 #define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ 5093 5094 /* Register: TEMP_T0 */ 5095 /* Description: Endpoint of first piecewise linear function */ 5096 5097 /* Bits 7..0 : Endpoint of first piecewise linear function */ 5098 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ 5099 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ 5100 5101 /* Register: TEMP_T1 */ 5102 /* Description: Endpoint of second piecewise linear function */ 5103 5104 /* Bits 7..0 : Endpoint of second piecewise linear function */ 5105 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ 5106 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ 5107 5108 /* Register: TEMP_T2 */ 5109 /* Description: Endpoint of third piecewise linear function */ 5110 5111 /* Bits 7..0 : Endpoint of third piecewise linear function */ 5112 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ 5113 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ 5114 5115 /* Register: TEMP_T3 */ 5116 /* Description: Endpoint of fourth piecewise linear function */ 5117 5118 /* Bits 7..0 : Endpoint of fourth piecewise linear function */ 5119 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ 5120 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ 5121 5122 /* Register: TEMP_T4 */ 5123 /* Description: Endpoint of fifth piecewise linear function */ 5124 5125 /* Bits 7..0 : Endpoint of fifth piecewise linear function */ 5126 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ 5127 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ 5128 5129 5130 5131 /* =========================================================================================================================== */ 5132 /* ================ TIMER ================ */ 5133 /* =========================================================================================================================== */ 5134 5135 5136 /** 5137 * @brief Timer/Counter 0 (TIMER0_NS) 5138 */ 5139 5140 typedef struct { /*!< (@ 0x4100C000) TIMER0_NS Structure */ 5141 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 5142 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 5143 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 5144 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 5145 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 5146 __IM uint32_t RESERVED[11]; 5147 __OM uint32_t TASKS_CAPTURE[8]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 5148 CC[n] register */ 5149 __IM uint32_t RESERVED1[8]; 5150 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 5151 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 5152 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 5153 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 5154 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 5155 for task SHUTDOWN */ 5156 __IM uint32_t RESERVED2[11]; 5157 __IOM uint32_t SUBSCRIBE_CAPTURE[8]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 5158 for task CAPTURE[n] */ 5159 __IM uint32_t RESERVED3[24]; 5160 __IOM uint32_t EVENTS_COMPARE[8]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 5161 match */ 5162 __IM uint32_t RESERVED4[24]; 5163 __IOM uint32_t PUBLISH_COMPARE[8]; /*!< (@ 0x000001C0) Description collection: Publish configuration 5164 for event COMPARE[n] */ 5165 __IM uint32_t RESERVED5[8]; 5166 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 5167 __IM uint32_t RESERVED6[63]; 5168 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 5169 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 5170 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 5171 __IM uint32_t RESERVED7[126]; 5172 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 5173 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 5174 __IM uint32_t RESERVED8; 5175 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 5176 __IM uint32_t RESERVED9[11]; 5177 __IOM uint32_t CC[8]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 5178 n */ 5179 __IM uint32_t RESERVED10[8]; 5180 __IOM uint32_t ONESHOTEN[8]; /*!< (@ 0x00000580) Description collection: Enable one-shot operation 5181 for Capture/Compare channel n */ 5182 } NRF_TIMER_Type; /*!< Size = 1440 (0x5a0) */ 5183 5184 5185 /* Peripheral: TIMER */ 5186 /* Description: Timer/Counter 0 */ 5187 5188 /* Register: TIMER_TASKS_START */ 5189 /* Description: Start Timer */ 5190 5191 /* Bit 0 : Start Timer */ 5192 #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ 5193 #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ 5194 #define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ 5195 5196 /* Register: TIMER_TASKS_STOP */ 5197 /* Description: Stop Timer */ 5198 5199 /* Bit 0 : Stop Timer */ 5200 #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ 5201 #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ 5202 #define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ 5203 5204 /* Register: TIMER_TASKS_COUNT */ 5205 /* Description: Increment Timer (Counter mode only) */ 5206 5207 /* Bit 0 : Increment Timer (Counter mode only) */ 5208 #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ 5209 #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ 5210 #define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ 5211 5212 /* Register: TIMER_TASKS_CLEAR */ 5213 /* Description: Clear time */ 5214 5215 /* Bit 0 : Clear time */ 5216 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ 5217 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ 5218 #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ 5219 5220 /* Register: TIMER_TASKS_SHUTDOWN */ 5221 /* Description: Deprecated register - Shut down timer */ 5222 5223 /* Bit 0 : Deprecated field - Shut down timer */ 5224 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ 5225 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ 5226 #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ 5227 5228 /* Register: TIMER_TASKS_CAPTURE */ 5229 /* Description: Description collection: Capture Timer value to CC[n] register */ 5230 5231 /* Bit 0 : Capture Timer value to CC[n] register */ 5232 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ 5233 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ 5234 #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ 5235 5236 /* Register: TIMER_SUBSCRIBE_START */ 5237 /* Description: Subscribe configuration for task START */ 5238 5239 /* Bit 31 : */ 5240 #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ 5241 #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ 5242 #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ 5243 #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ 5244 5245 /* Bits 7..0 : DPPI channel that task START will subscribe to */ 5246 #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5247 #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5248 5249 /* Register: TIMER_SUBSCRIBE_STOP */ 5250 /* Description: Subscribe configuration for task STOP */ 5251 5252 /* Bit 31 : */ 5253 #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ 5254 #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ 5255 #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ 5256 #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ 5257 5258 /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ 5259 #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5260 #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5261 5262 /* Register: TIMER_SUBSCRIBE_COUNT */ 5263 /* Description: Subscribe configuration for task COUNT */ 5264 5265 /* Bit 31 : */ 5266 #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */ 5267 #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */ 5268 #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */ 5269 #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */ 5270 5271 /* Bits 7..0 : DPPI channel that task COUNT will subscribe to */ 5272 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5273 #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5274 5275 /* Register: TIMER_SUBSCRIBE_CLEAR */ 5276 /* Description: Subscribe configuration for task CLEAR */ 5277 5278 /* Bit 31 : */ 5279 #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ 5280 #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ 5281 #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ 5282 #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ 5283 5284 /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ 5285 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5286 #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5287 5288 /* Register: TIMER_SUBSCRIBE_SHUTDOWN */ 5289 /* Description: Deprecated register - Subscribe configuration for task SHUTDOWN */ 5290 5291 /* Bit 31 : */ 5292 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */ 5293 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */ 5294 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */ 5295 #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */ 5296 5297 /* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */ 5298 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5299 #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5300 5301 /* Register: TIMER_SUBSCRIBE_CAPTURE */ 5302 /* Description: Description collection: Subscribe configuration for task CAPTURE[n] */ 5303 5304 /* Bit 31 : */ 5305 #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ 5306 #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ 5307 #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */ 5308 #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */ 5309 5310 /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */ 5311 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5312 #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5313 5314 /* Register: TIMER_EVENTS_COMPARE */ 5315 /* Description: Description collection: Compare event on CC[n] match */ 5316 5317 /* Bit 0 : Compare event on CC[n] match */ 5318 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ 5319 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ 5320 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ 5321 #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ 5322 5323 /* Register: TIMER_PUBLISH_COMPARE */ 5324 /* Description: Description collection: Publish configuration for event COMPARE[n] */ 5325 5326 /* Bit 31 : */ 5327 #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ 5328 #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ 5329 #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ 5330 #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ 5331 5332 /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */ 5333 #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ 5334 #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ 5335 5336 /* Register: TIMER_SHORTS */ 5337 /* Description: Shortcuts between local events and tasks */ 5338 5339 /* Bit 23 : Shortcut between event COMPARE[7] and task STOP */ 5340 #define TIMER_SHORTS_COMPARE7_STOP_Pos (23UL) /*!< Position of COMPARE7_STOP field. */ 5341 #define TIMER_SHORTS_COMPARE7_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE7_STOP_Pos) /*!< Bit mask of COMPARE7_STOP field. */ 5342 #define TIMER_SHORTS_COMPARE7_STOP_Disabled (0UL) /*!< Disable shortcut */ 5343 #define TIMER_SHORTS_COMPARE7_STOP_Enabled (1UL) /*!< Enable shortcut */ 5344 5345 /* Bit 16 : Shortcut between event COMPARE[0] and task STOP */ 5346 #define TIMER_SHORTS_COMPARE0_STOP_Pos (16UL) /*!< Position of COMPARE0_STOP field. */ 5347 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ 5348 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ 5349 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ 5350 5351 /* Bit 7 : Shortcut between event COMPARE[7] and task CLEAR */ 5352 #define TIMER_SHORTS_COMPARE7_CLEAR_Pos (7UL) /*!< Position of COMPARE7_CLEAR field. */ 5353 #define TIMER_SHORTS_COMPARE7_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE7_CLEAR_Pos) /*!< Bit mask of COMPARE7_CLEAR field. */ 5354 #define TIMER_SHORTS_COMPARE7_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 5355 #define TIMER_SHORTS_COMPARE7_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 5356 5357 /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ 5358 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 5359 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 5360 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 5361 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 5362 5363 /* Register: TIMER_INTEN */ 5364 /* Description: Enable or disable interrupt */ 5365 5366 /* Bit 23 : Enable or disable interrupt for event COMPARE[7] */ 5367 #define TIMER_INTEN_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ 5368 #define TIMER_INTEN_COMPARE7_Msk (0x1UL << TIMER_INTEN_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ 5369 #define TIMER_INTEN_COMPARE7_Disabled (0UL) /*!< Disable */ 5370 #define TIMER_INTEN_COMPARE7_Enabled (1UL) /*!< Enable */ 5371 5372 /* Bit 16 : Enable or disable interrupt for event COMPARE[0] */ 5373 #define TIMER_INTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5374 #define TIMER_INTEN_COMPARE0_Msk (0x1UL << TIMER_INTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5375 #define TIMER_INTEN_COMPARE0_Disabled (0UL) /*!< Disable */ 5376 #define TIMER_INTEN_COMPARE0_Enabled (1UL) /*!< Enable */ 5377 5378 /* Register: TIMER_INTENSET */ 5379 /* Description: Enable interrupt */ 5380 5381 /* Bit 23 : Write '1' to enable interrupt for event COMPARE[7] */ 5382 #define TIMER_INTENSET_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ 5383 #define TIMER_INTENSET_COMPARE7_Msk (0x1UL << TIMER_INTENSET_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ 5384 #define TIMER_INTENSET_COMPARE7_Disabled (0UL) /*!< Read: Disabled */ 5385 #define TIMER_INTENSET_COMPARE7_Enabled (1UL) /*!< Read: Enabled */ 5386 #define TIMER_INTENSET_COMPARE7_Set (1UL) /*!< Enable */ 5387 5388 /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ 5389 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5390 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5391 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 5392 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 5393 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 5394 5395 /* Register: TIMER_INTENCLR */ 5396 /* Description: Disable interrupt */ 5397 5398 /* Bit 23 : Write '1' to disable interrupt for event COMPARE[7] */ 5399 #define TIMER_INTENCLR_COMPARE7_Pos (23UL) /*!< Position of COMPARE7 field. */ 5400 #define TIMER_INTENCLR_COMPARE7_Msk (0x1UL << TIMER_INTENCLR_COMPARE7_Pos) /*!< Bit mask of COMPARE7 field. */ 5401 #define TIMER_INTENCLR_COMPARE7_Disabled (0UL) /*!< Read: Disabled */ 5402 #define TIMER_INTENCLR_COMPARE7_Enabled (1UL) /*!< Read: Enabled */ 5403 #define TIMER_INTENCLR_COMPARE7_Clear (1UL) /*!< Disable */ 5404 5405 /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ 5406 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5407 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5408 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 5409 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 5410 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 5411 5412 /* Register: TIMER_MODE */ 5413 /* Description: Timer mode selection */ 5414 5415 /* Bits 1..0 : Timer mode */ 5416 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 5417 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 5418 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ 5419 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ 5420 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ 5421 5422 /* Register: TIMER_BITMODE */ 5423 /* Description: Configure the number of bits used by the TIMER */ 5424 5425 /* Bits 1..0 : Timer bit width */ 5426 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ 5427 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ 5428 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ 5429 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ 5430 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ 5431 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ 5432 5433 /* Register: TIMER_PRESCALER */ 5434 /* Description: Timer prescaler register */ 5435 5436 /* Bits 3..0 : Prescaler value */ 5437 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 5438 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 5439 5440 /* Register: TIMER_CC */ 5441 /* Description: Description collection: Capture/Compare register n */ 5442 5443 /* Bits 31..0 : Capture/Compare value */ 5444 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ 5445 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ 5446 5447 /* Register: TIMER_ONESHOTEN */ 5448 /* Description: Description collection: Enable one-shot operation for Capture/Compare channel n */ 5449 5450 /* Bit 0 : Enable one-shot operation */ 5451 #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */ 5452 #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */ 5453 #define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL) /*!< Disable one-shot operation */ 5454 #define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL) /*!< Enable one-shot operation */ 5455 5456 /* =========================================================================================================================== */ 5457 /* ================ UICR ================ */ 5458 /* =========================================================================================================================== */ 5459 5460 5461 /** 5462 * @brief User Information Configuration Registers (UICR) 5463 * At this point just a chunk of reserved space of 2KiB 5464 */ 5465 5466 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 5467 __IM uint32_t RESERVED[1024]; 5468 } NRF_UICR_Type; /*!< Size = 4096 */ 5469 5470 5471 5472 /* =========================================================================================================================== */ 5473 /* ================ VREQCTRL ================ */ 5474 /* =========================================================================================================================== */ 5475 5476 5477 /** 5478 * @brief Voltage request control (VREQCTRL) 5479 */ 5480 5481 typedef struct { /*!< (@ 0x41004000) VREQCTRL_NS Structure */ 5482 __IM uint32_t RESERVED[320]; 5483 __IOM VREQCTRL_VREGRADIO_Type VREGRADIO; /*!< (@ 0x00000500) Unspecified */ 5484 } NRF_VREQCTRL_Type; /*!< Size = 1292 (0x50c) */ 5485 5486 5487 5488 #ifdef __cplusplus 5489 } 5490 #endif 5491 5492 #endif /* _NRF5340_PERI_TYPES_H */ 5493
