1 /*
2 * Copyright (c) 2018 - 2020 Nordic Semiconductor ASA
3 * Copyright (c) 2018 Ioannis Glaropoulos
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #if defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
9 #define NRF_DPPIC NRF_DPPIC10
10 #endif /* CONFIG_SOC_COMPATIBLE_NRF54LX */
11
hal_radio_nrf_ppi_channels_enable(uint32_t mask)12 static inline void hal_radio_nrf_ppi_channels_enable(uint32_t mask)
13 {
14 nrf_dppi_channels_enable(NRF_DPPIC, mask);
15 }
16
hal_radio_nrf_ppi_channels_disable(uint32_t mask)17 static inline void hal_radio_nrf_ppi_channels_disable(uint32_t mask)
18 {
19 nrf_dppi_channels_disable(NRF_DPPIC, mask);
20 }
21
22 /*******************************************************************************
23 * Enable Radio on Event Timer tick:
24 * wire the EVENT_TIMER EVENTS_COMPARE[0] event to RADIO TASKS_TXEN/RXEN task.
25 */
hal_radio_enable_on_tick_ppi_config_and_enable(uint8_t trx)26 static inline void hal_radio_enable_on_tick_ppi_config_and_enable(uint8_t trx)
27 {
28 if (trx) {
29 nrf_timer_publish_set(EVENT_TIMER, HAL_EVENT_TIMER_TRX_EVENT,
30 HAL_RADIO_ENABLE_TX_ON_TICK_PPI);
31 nrf_radio_subscribe_set(NRF_RADIO, NRF_RADIO_TASK_TXEN,
32 HAL_RADIO_ENABLE_TX_ON_TICK_PPI);
33
34 /* Address nRF5340 Engineering A Errata 16 */
35 if (IS_ENABLED(CONFIG_BT_CTLR_TIFS_HW)) {
36 nrf_radio_subscribe_clear(NRF_RADIO,
37 NRF_RADIO_TASK_RXEN);
38 }
39
40 nrf_dppi_channels_enable(NRF_DPPIC,
41 BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI));
42 } else {
43 nrf_timer_publish_set(EVENT_TIMER, HAL_EVENT_TIMER_TRX_EVENT,
44 HAL_RADIO_ENABLE_RX_ON_TICK_PPI);
45 nrf_radio_subscribe_set(NRF_RADIO, NRF_RADIO_TASK_RXEN,
46 HAL_RADIO_ENABLE_RX_ON_TICK_PPI);
47
48 /* Address nRF5340 Engineering A Errata 16 */
49 if (IS_ENABLED(CONFIG_BT_CTLR_TIFS_HW)) {
50 nrf_radio_subscribe_clear(NRF_RADIO,
51 NRF_RADIO_TASK_TXEN);
52 }
53
54 nrf_dppi_channels_enable(NRF_DPPIC,
55 BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI));
56 }
57 }
58
59 /*******************************************************************************
60 * Capture event timer on Address reception:
61 * wire the RADIO EVENTS_ADDRESS event to the
62 * EVENT_TIMER TASKS_CAPTURE[<address timer>] task.
63 */
hal_radio_recv_timeout_cancel_ppi_config(void)64 static inline void hal_radio_recv_timeout_cancel_ppi_config(void)
65 {
66 nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_ADDRESS,
67 HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI);
68 nrf_timer_subscribe_set(EVENT_TIMER, HAL_EVENT_TIMER_ADDRESS_TASK,
69 HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI);
70 }
71
72 /*******************************************************************************
73 * Disable Radio on HCTO:
74 * wire the EVENT_TIMER EVENTS_COMPARE[<HCTO timer>] event
75 * to the RADIO TASKS_DISABLE task.
76 */
hal_radio_disable_on_hcto_ppi_config(void)77 static inline void hal_radio_disable_on_hcto_ppi_config(void)
78 {
79 nrf_timer_publish_set(EVENT_TIMER, HAL_EVENT_TIMER_HCTO_EVENT,
80 HAL_RADIO_DISABLE_ON_HCTO_PPI);
81 nrf_radio_subscribe_set(NRF_RADIO, NRF_RADIO_TASK_DISABLE,
82 HAL_RADIO_DISABLE_ON_HCTO_PPI);
83 }
84
85 /*******************************************************************************
86 * Capture event timer on Radio end:
87 * wire the RADIO EVENTS_END event to the
88 * EVENT_TIMER TASKS_CAPTURE[<radio end timer>] task.
89 */
hal_radio_end_time_capture_ppi_config(void)90 static inline void hal_radio_end_time_capture_ppi_config(void)
91 {
92 nrf_radio_publish_set(NRF_RADIO, HAL_NRF_RADIO_EVENT_END,
93 HAL_RADIO_END_TIME_CAPTURE_PPI);
94 nrf_timer_subscribe_set(EVENT_TIMER, HAL_EVENT_TIMER_TRX_END_TASK,
95 HAL_RADIO_END_TIME_CAPTURE_PPI);
96 }
97
98 /*******************************************************************************
99 * Start event timer on RTC tick:
100 * wire the RTC0 EVENTS_COMPARE[2] event to EVENT_TIMER TASKS_START task.
101 */
hal_event_timer_start_ppi_config(void)102 static inline void hal_event_timer_start_ppi_config(void)
103 {
104 #if defined(CONFIG_BT_CTLR_NRF_GRTC)
105 /* Publish GRTC compare */
106 nrf_grtc_publish_set(NRF_GRTC, HAL_CNTR_GRTC_EVENT_COMPARE_RADIO,
107 HAL_EVENT_TIMER_START_PPI);
108
109 /* Enable same DPPI in Peripheral domain */
110 nrf_dppi_channels_enable(NRF_DPPIC20,
111 BIT(HAL_EVENT_TIMER_START_PPI));
112
113 /* Setup PPIB send subscribe */
114 nrf_ppib_subscribe_set(NRF_PPIB21, HAL_PPIB_SEND_EVENT_TIMER_START_PPI,
115 HAL_EVENT_TIMER_START_PPI);
116
117 /* Setup PPIB receive publish */
118 nrf_ppib_publish_set(NRF_PPIB11, HAL_PPIB_RECEIVE_EVENT_TIMER_START_PPI,
119 HAL_EVENT_TIMER_START_PPI);
120
121 #else /* !CONFIG_BT_CTLR_NRF_GRTC */
122 nrf_rtc_publish_set(NRF_RTC, NRF_RTC_EVENT_COMPARE_2, HAL_EVENT_TIMER_START_PPI);
123 #endif /* !CONFIG_BT_CTLR_NRF_GRTC */
124
125 nrf_timer_subscribe_set(EVENT_TIMER, NRF_TIMER_TASK_START, HAL_EVENT_TIMER_START_PPI);
126 }
127
128 /*******************************************************************************
129 * Capture event timer on Radio ready:
130 * wire the RADIO EVENTS_READY event to the
131 * EVENT_TIMER TASKS_CAPTURE[<radio ready timer>] task.
132 */
hal_radio_ready_time_capture_ppi_config(void)133 static inline void hal_radio_ready_time_capture_ppi_config(void)
134 {
135 nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_READY,
136 HAL_RADIO_READY_TIME_CAPTURE_PPI);
137 nrf_timer_subscribe_set(EVENT_TIMER, HAL_EVENT_TIMER_READY_TASK,
138 HAL_RADIO_READY_TIME_CAPTURE_PPI);
139 }
140
141 #if defined(CONFIG_BT_CTLR_LE_ENC) || defined(CONFIG_BT_CTLR_BROADCAST_ISO_ENC)
142 /*******************************************************************************
143 * Trigger encryption task upon address reception:
144 * wire the RADIO EVENTS_ADDRESS event to the CCM TASKS_CRYPT task.
145 *
146 * Note: we do not need an additional PPI, since we have already set up
147 * a PPI to publish RADIO ADDRESS event.
148 */
hal_trigger_crypt_ppi_config(void)149 static inline void hal_trigger_crypt_ppi_config(void)
150 {
151 nrf_ccm_subscribe_set(NRF_CCM, NRF_CCM_TASK_START, HAL_TRIGGER_CRYPT_PPI);
152
153 #if !defined(CONFIG_SOC_COMPATIBLE_NRF54LX)
154 nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_ADDRESS, HAL_TRIGGER_CRYPT_PPI);
155
156 #else /* !CONFIG_SOC_COMPATIBLE_NRF54LX */
157 nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_PAYLOAD, HAL_TRIGGER_CRYPT_PPI);
158
159 /* Enable same DPPI in MCU domain */
160 nrf_dppi_channels_enable(NRF_DPPIC00, BIT(HAL_TRIGGER_CRYPT_PPI));
161
162 /* Setup PPIB send subscribe */
163 nrf_ppib_subscribe_set(NRF_PPIB10, HAL_PPIB_SEND_TRIGGER_CRYPT_PPI, HAL_TRIGGER_CRYPT_PPI);
164
165 /* Setup PPIB receive publish */
166 nrf_ppib_publish_set(NRF_PPIB00, HAL_PPIB_RECEIVE_TRIGGER_CRYPT_PPI, HAL_TRIGGER_CRYPT_PPI);
167 #endif /* !CONFIG_SOC_COMPATIBLE_NRF54LX */
168 }
169
170 /*******************************************************************************
171 * Disable trigger encryption task
172 */
hal_trigger_crypt_ppi_disable(void)173 static inline void hal_trigger_crypt_ppi_disable(void)
174 {
175 nrf_ccm_subscribe_clear(NRF_CCM, NRF_CCM_TASK_START);
176 }
177
178 #if defined(CONFIG_BT_CTLR_PRIVACY)
179 /*******************************************************************************
180 * Trigger automatic address resolution on Bit counter match:
181 * wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task.
182 */
hal_trigger_aar_ppi_config(void)183 static inline void hal_trigger_aar_ppi_config(void)
184 {
185 nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_BCMATCH, HAL_TRIGGER_AAR_PPI);
186 nrf_aar_subscribe_set(NRF_AAR, NRF_AAR_TASK_START, HAL_TRIGGER_AAR_PPI);
187 }
188 #endif /* CONFIG_BT_CTLR_PRIVACY */
189
190 /* When hardware does not support Coded PHY we still allow the Controller
191 * implementation to accept Coded PHY flags, but the Controller will use 1M
192 * PHY on air. This is implementation specific feature.
193 */
194 #if defined(CONFIG_BT_CTLR_PHY_CODED) && defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
195 /*******************************************************************************
196 * Trigger Radio Rate override upon Rateboost event.
197 */
hal_trigger_rateoverride_ppi_config(void)198 static inline void hal_trigger_rateoverride_ppi_config(void)
199 {
200 nrf_radio_publish_set(NRF_RADIO, NRF_RADIO_EVENT_RATEBOOST, HAL_TRIGGER_RATEOVERRIDE_PPI);
201 nrf_ccm_subscribe_set(NRF_CCM, NRF_CCM_TASK_RATEOVERRIDE, HAL_TRIGGER_RATEOVERRIDE_PPI);
202 }
203 #endif /* CONFIG_BT_CTLR_PHY_CODED && CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
204
205 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
206 /*******************************************************************************
207 * Trigger encryption task on Bit counter match:
208 * wire the RADIO EVENTS_BCMATCH event to the CCM TASKS_CRYPT task.
209 *
210 * PPI channel HAL_TRIGGER_CRYPT_DELAY_PPI is also used for HAL_TRIGGER-
211 * _RATEOVERRIDE_PPI.
212 * Make sure the same PPI is not configured for both events at once.
213 *
214 * EEP: RADIO->EVENTS_BCMATCH
215 * TEP: CCM->TASKS_CRYPT
216 */
hal_trigger_crypt_by_bcmatch_ppi_config(void)217 static inline void hal_trigger_crypt_by_bcmatch_ppi_config(void)
218 {
219 /* Configure Bit counter to trigger EVENTS_BCMATCH for CCM_TASKS_CRYPT-
220 * _DELAY_BITS bit. This is a time required for Radio to store
221 * received data in memory before the CCM TASKS_CRYPT starts. This
222 * makes CCM to do not read the memory before Radio stores received
223 * data.
224 */
225 nrf_radio_publish_set(NRF_RADIO,
226 NRF_RADIO_EVENT_BCMATCH, HAL_TRIGGER_CRYPT_DELAY_PPI);
227 nrf_ccm_subscribe_set(NRF_CCM, NRF_CCM_TASK_START, HAL_TRIGGER_CRYPT_DELAY_PPI);
228 }
229 #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
230 #endif /* CONFIG_BT_CTLR_LE_ENC || CONFIG_BT_CTLR_BROADCAST_ISO_ENC */
231
232 /******************************************************************************/
233 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
234 /* DPPI setup used for SW-based auto-switching during TIFS. */
235
236 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER) && !defined(CONFIG_BT_CTLR_DF)
237 #define HAL_NRF_RADIO_TIMER_CLEAR_EVENT_END HAL_NRF_RADIO_EVENT_END
238 #define HAL_RADIO_GROUP_TASK_ENABLE_PUBLISH_END HAL_RADIO_PUBLISH_END
239 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER || CONFIG_BT_CTLR_DF */
240 #define HAL_NRF_RADIO_TIMER_CLEAR_EVENT_END HAL_NRF_RADIO_EVENT_PHYEND
241 #define HAL_RADIO_GROUP_TASK_ENABLE_PUBLISH_END HAL_RADIO_PUBLISH_PHYEND
242 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER || CONFIG_BT_CTLR_DF */
243
244 /* Clear SW-switch timer on packet end:
245 * wire the RADIO EVENTS_END event to SW_SWITCH_TIMER TASKS_CLEAR task.
246 *
247 * Note: In case of HW TIFS support or single timer configuration we do not need
248 * an additional PPI, since we have already set up a PPI to publish RADIO END
249 * event. In other case separate PPI is used because packet end is marked by
250 * PHYEND event while last bit or CRC is marked by END event.
251 */
hal_sw_switch_timer_clear_ppi_config(void)252 static inline void hal_sw_switch_timer_clear_ppi_config(void)
253 {
254 nrf_radio_publish_set(NRF_RADIO, HAL_NRF_RADIO_TIMER_CLEAR_EVENT_END,
255 HAL_SW_SWITCH_TIMER_CLEAR_PPI);
256 nrf_timer_subscribe_set(SW_SWITCH_TIMER,
257 NRF_TIMER_TASK_CLEAR, HAL_SW_SWITCH_TIMER_CLEAR_PPI);
258
259 /* NOTE: nRF5340 may share the DPPI channel being triggered by Radio End,
260 * for End time capture and sw_switch DPPI channel toggling.
261 * The channel must be always enabled when software switch is used.
262 */
263 nrf_dppi_channels_enable(NRF_DPPIC, BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI));
264 }
265
266 /* The 2 adjacent PPI groups used for implementing SW_SWITCH_TIMER-based
267 * auto-switch for TIFS. 'index' must be 0 or 1.
268 */
269 #define SW_SWITCH_TIMER_TASK_GROUP(index) \
270 (SW_SWITCH_TIMER_TASK_GROUP_BASE + (index))
271
272 /* The 2 adjacent TIMER EVENTS_COMPARE event offsets used for implementing
273 * SW_SWITCH_TIMER-based auto-switch for TIFS. 'index' must be 0 or 1.
274 */
275 #define SW_SWITCH_TIMER_EVTS_COMP(index) \
276 (SW_SWITCH_TIMER_EVTS_COMP_BASE + (index))
277
278 /* The 2 adjacent TIMER EVENTS_COMPARE event offsets used for implementing
279 * SW_SWITCH_TIMER-based auto-switch for TIFS, when receiving on LE Coded
280 * PHY. 'index' must be 0 or 1.
281 */
282 #define SW_SWITCH_TIMER_S2_EVTS_COMP(index) \
283 (SW_SWITCH_TIMER_EVTS_COMP_S2_BASE + (index))
284
285 /*
286 * Convert a dppi channel group number into the *enable* task enumerate value
287 * the nrfx hal accepts
288 */
289 #define HAL_SW_DPPI_TASK_EN_FROM_IDX(index) \
290 (NRF_DPPI_TASK_CHG0_EN + ((index) * (NRF_DPPI_TASK_CHG1_EN - NRF_DPPI_TASK_CHG0_EN)))
291
292 /*
293 * Convert a dppi channel group number into the *disable* task enumerate value
294 * the nrfx hal accepts
295 */
296 #define HAL_SW_DPPI_TASK_DIS_FROM_IDX(index) \
297 (NRF_DPPI_TASK_CHG0_DIS + ((index) * (NRF_DPPI_TASK_CHG1_EN - NRF_DPPI_TASK_CHG0_EN)))
298
299 /* Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
300 * to a PPI GROUP TASK DISABLE task (PPI group with index <index>).
301 * 2 adjacent PPIs (14 & 15) and 2 adjacent PPI groups are used for this wiring;
302 * <index> must be 0 or 1. <offset> must be a valid TIMER CC register offset.
303 */
304 #define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(index) \
305 (HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE + (index))
306
307 #define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT(cc_offset) \
308 SW_SWITCH_TIMER->PUBLISH_COMPARE[cc_offset]
309 #define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(chan) \
310 (((chan << TIMER_PUBLISH_COMPARE_CHIDX_Pos) \
311 & TIMER_PUBLISH_COMPARE_CHIDX_Msk) | \
312 ((TIMER_PUBLISH_COMPARE_EN_Enabled << TIMER_PUBLISH_COMPARE_EN_Pos) \
313 & TIMER_PUBLISH_COMPARE_EN_Msk))
314 #define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK(index, channel) \
315 nrf_dppi_subscribe_set(NRF_DPPIC, \
316 HAL_SW_DPPI_TASK_DIS_FROM_IDX(SW_SWITCH_TIMER_TASK_GROUP(index)), \
317 channel);
318
319 /* Enable the SW Switch PPI Group on RADIO END Event.
320 *
321 * Note: we do not need an additional PPI, since we have already set up
322 * a PPI to publish RADIO END event.
323 */
324 #define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_REGISTER_EVT \
325 (NRF_RADIO->HAL_RADIO_GROUP_TASK_ENABLE_PUBLISH_END)
326 #define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_EVT \
327 (((HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI << \
328 RADIO_PUBLISH_END_CHIDX_Pos) \
329 & RADIO_PUBLISH_END_CHIDX_Msk) | \
330 ((RADIO_PUBLISH_END_EN_Enabled << RADIO_PUBLISH_END_EN_Pos) \
331 & RADIO_PUBLISH_END_EN_Msk))
332
333 /* Enable Radio on SW Switch timer event.
334 * Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
335 * to a RADIO Enable task (TX or RX).
336 *
337 * Note:
338 * We use the same PPI as for disabling the SW Switch PPI groups,
339 * since we need to listen for the same event (SW Switch event).
340 *
341 * We use the same PPI for the alternative SW Switch Timer compare
342 * event.
343 */
344 #define HAL_SW_SWITCH_RADIO_ENABLE_PPI(index) \
345 (HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE + (index))
346
347 #define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(index) \
348 (HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE + (index))
349
350 #define HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(cc_offset) \
351 SW_SWITCH_TIMER->PUBLISH_COMPARE[cc_offset]
352 #define HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(chan) \
353 (((chan << TIMER_PUBLISH_COMPARE_CHIDX_Pos) \
354 & TIMER_PUBLISH_COMPARE_CHIDX_Msk) | \
355 ((TIMER_PUBLISH_COMPARE_EN_Enabled << TIMER_PUBLISH_COMPARE_EN_Pos) \
356 & TIMER_PUBLISH_COMPARE_EN_Msk))
357
358 /* Cancel the SW switch timer running considering S8 timing:
359 * wire the RADIO EVENTS_RATEBOOST event to SW_SWITCH_TIMER TASKS_CAPTURE task.
360 *
361 * Note: We already have a PPI where we publish the RATEBOOST event.
362 */
363 #define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_EVT \
364 NRF_RADIO->PUBLISH_RATEBOOST
365 #define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_EVT \
366 (((HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI << \
367 RADIO_PUBLISH_RATEBOOST_CHIDX_Pos) \
368 & RADIO_PUBLISH_RATEBOOST_CHIDX_Msk) | \
369 ((RADIO_PUBLISH_RATEBOOST_EN_Enabled << \
370 RADIO_PUBLISH_RATEBOOST_EN_Pos) \
371 & RADIO_PUBLISH_RATEBOOST_EN_Msk))
372 #define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_TASK(cc_reg) \
373 SW_SWITCH_TIMER->SUBSCRIBE_CAPTURE[cc_reg]
374
375 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
376 /* The 2 adjacent TIMER EVENTS_COMPARE event offsets used for implementing PHYEND delay compensation
377 * for SW_SWITCH_TIMER-based TIFS auto-switch. 'index' must be 0 or 1.
378 */
379 #define SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_EVTS_COMP(index) \
380 (SW_SWITCH_TIMER_EVTS_COMP_PHYEND_DELAY_COMPENSATION_BASE + (index))
381 #define HAL_SW_SWITCH_RADIO_ENABLE_PHYEND_DELAY_COMPENSATION_PPI(index) \
382 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(index)
383
384 /* Cancel the SW switch timer running considering PHYEND delay compensation timing:
385 * wire the RADIO EVENTS_CTEPRESENT event to SW_SWITCH_TIMER TASKS_CAPTURE task.
386 */
387 #define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_REGISTER_EVT \
388 NRF_RADIO->PUBLISH_CTEPRESENT
389
390 #define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_EVT \
391 (((HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI \
392 << RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos) & \
393 RADIO_PUBLISH_CTEPRESENT_CHIDX_Msk) | \
394 ((RADIO_PUBLISH_CTEPRESENT_EN_Enabled << RADIO_PUBLISH_CTEPRESENT_EN_Pos) & \
395 RADIO_PUBLISH_CTEPRESENT_EN_Msk))
396
397 #define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_TASK \
398 (((HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI \
399 << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) & \
400 TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk) | \
401 ((TIMER_SUBSCRIBE_CAPTURE_EN_Enabled << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) & \
402 TIMER_SUBSCRIBE_CAPTURE_EN_Msk))
403
404 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
405
hal_radio_sw_switch_setup(uint8_t ppi_group_index)406 static inline void hal_radio_sw_switch_setup(uint8_t ppi_group_index)
407 {
408 /* Set up software switch mechanism for next Radio switch. */
409
410 /* Wire RADIO END event to PPI Group[<index>] enable task,
411 * over PPI[<HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI>]
412 */
413 HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_REGISTER_EVT =
414 HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_EVT;
415 nrf_dppi_subscribe_set(NRF_DPPIC,
416 HAL_SW_DPPI_TASK_EN_FROM_IDX(SW_SWITCH_TIMER_TASK_GROUP(ppi_group_index)),
417 HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI);
418
419 /* We need to un-subscribe the other group from the PPI channel. */
420 uint8_t other_grp = (ppi_group_index + 1) & 0x01;
421
422 nrf_dppi_subscribe_clear(NRF_DPPIC,
423 HAL_SW_DPPI_TASK_EN_FROM_IDX(SW_SWITCH_TIMER_TASK_GROUP(other_grp)));
424 }
425
hal_radio_txen_on_sw_switch(uint8_t compare_reg_index,uint8_t radio_enable_ppi)426 static inline void hal_radio_txen_on_sw_switch(uint8_t compare_reg_index, uint8_t radio_enable_ppi)
427 {
428 /* Wire SW Switch timer event <compare_reg> to the
429 * PPI[<radio_enable_ppi>] for enabling Radio. Do
430 * not wire the task; it is done by the caller of
431 * the function depending on the desired direction
432 * (TX/RX).
433 */
434 HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(compare_reg_index) =
435 HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(radio_enable_ppi);
436
437 nrf_radio_subscribe_set(NRF_RADIO, NRF_RADIO_TASK_TXEN, radio_enable_ppi);
438 }
439
hal_radio_b2b_txen_on_sw_switch(uint8_t compare_reg_index,uint8_t radio_enable_ppi)440 static inline void hal_radio_b2b_txen_on_sw_switch(uint8_t compare_reg_index,
441 uint8_t radio_enable_ppi)
442 {
443 /* Wire SW Switch timer event <compare_reg> to the
444 * PPI[<radio_enable_ppi>] for enabling Radio. Do
445 * not wire the task; it is done by the caller of
446 * the function depending on the desired direction
447 * (TX/RX).
448 */
449 HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(compare_reg_index) =
450 HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(radio_enable_ppi);
451
452 uint8_t prev_ppi_idx = (compare_reg_index + 0x01 - SW_SWITCH_TIMER_EVTS_COMP_BASE) & 0x01;
453
454 radio_enable_ppi = HAL_SW_SWITCH_RADIO_ENABLE_PPI(prev_ppi_idx);
455 nrf_radio_subscribe_set(NRF_RADIO, NRF_RADIO_TASK_TXEN, radio_enable_ppi);
456 }
457
hal_radio_rxen_on_sw_switch(uint8_t compare_reg_index,uint8_t radio_enable_ppi)458 static inline void hal_radio_rxen_on_sw_switch(uint8_t compare_reg_index, uint8_t radio_enable_ppi)
459 {
460 /* Wire SW Switch timer event <compare_reg> to the
461 * PPI[<radio_enable_ppi>] for enabling Radio. Do
462 * not wire the task; it is done by the caller of
463 * the function depending on the desired direction
464 * (TX/RX).
465 */
466 HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(compare_reg_index) =
467 HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(radio_enable_ppi);
468
469 nrf_radio_subscribe_set(NRF_RADIO, NRF_RADIO_TASK_RXEN, radio_enable_ppi);
470 }
471
hal_radio_b2b_rxen_on_sw_switch(uint8_t compare_reg_index,uint8_t radio_enable_ppi)472 static inline void hal_radio_b2b_rxen_on_sw_switch(uint8_t compare_reg_index,
473 uint8_t radio_enable_ppi)
474 {
475 /* Wire SW Switch timer event <compare_reg> to the
476 * PPI[<radio_enable_ppi>] for enabling Radio. Do
477 * not wire the task; it is done by the caller of
478 * the function depending on the desired direction
479 * (TX/RX).
480 */
481 HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(compare_reg_index) =
482 HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(radio_enable_ppi);
483
484 uint8_t prev_ppi_idx = (compare_reg_index + 0x01 - SW_SWITCH_TIMER_EVTS_COMP_BASE) & 0x01;
485
486 radio_enable_ppi = HAL_SW_SWITCH_RADIO_ENABLE_PPI(prev_ppi_idx);
487 nrf_radio_subscribe_set(NRF_RADIO, NRF_RADIO_TASK_RXEN, radio_enable_ppi);
488 }
489
hal_radio_sw_switch_disable(void)490 static inline void hal_radio_sw_switch_disable(void)
491 {
492 /* We cannot deactivate the PPI channels, as other tasks
493 * are subscribed to RADIO_END event, i.e on the same channel.
494 * So we simply cancel the task subscription.
495 */
496 nrf_timer_subscribe_clear(SW_SWITCH_TIMER, NRF_TIMER_TASK_CLEAR);
497 nrf_dppi_subscribe_clear(NRF_DPPIC,
498 HAL_SW_DPPI_TASK_EN_FROM_IDX(SW_SWITCH_TIMER_TASK_GROUP(0)));
499 nrf_dppi_subscribe_clear(NRF_DPPIC,
500 HAL_SW_DPPI_TASK_EN_FROM_IDX(SW_SWITCH_TIMER_TASK_GROUP(1)));
501
502 /* Invalidation of subscription of S2 timer Compare used when
503 * RXing on LE Coded PHY is not needed, as other DPPI subscription
504 * is disable on each sw_switch call already.
505 */
506 }
507
hal_radio_sw_switch_b2b_tx_disable(uint8_t compare_reg_index)508 static inline void hal_radio_sw_switch_b2b_tx_disable(uint8_t compare_reg_index)
509 {
510 hal_radio_sw_switch_disable();
511
512 uint8_t prev_ppi_idx = (compare_reg_index + 0x01 - SW_SWITCH_TIMER_EVTS_COMP_BASE) & 0x01;
513 uint8_t radio_enable_ppi = HAL_SW_SWITCH_RADIO_ENABLE_PPI(prev_ppi_idx);
514
515 nrf_radio_subscribe_set(NRF_RADIO, NRF_RADIO_TASK_TXEN, radio_enable_ppi);
516 }
517
hal_radio_sw_switch_b2b_rx_disable(uint8_t compare_reg_index)518 static inline void hal_radio_sw_switch_b2b_rx_disable(uint8_t compare_reg_index)
519 {
520 hal_radio_sw_switch_disable();
521
522 uint8_t prev_ppi_idx = (compare_reg_index + 0x01 - SW_SWITCH_TIMER_EVTS_COMP_BASE) & 0x01;
523 uint8_t radio_enable_ppi = HAL_SW_SWITCH_RADIO_ENABLE_PPI(prev_ppi_idx);
524
525 nrf_radio_subscribe_set(NRF_RADIO, NRF_RADIO_TASK_RXEN, radio_enable_ppi);
526 }
527
hal_radio_sw_switch_cleanup(void)528 static inline void hal_radio_sw_switch_cleanup(void)
529 {
530 hal_radio_sw_switch_disable();
531 nrf_dppi_channels_disable(NRF_DPPIC,
532 #if !defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
533 BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
534 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
535 BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI));
536 nrf_dppi_group_disable(NRF_DPPIC, SW_SWITCH_TIMER_TASK_GROUP(0));
537 nrf_dppi_group_disable(NRF_DPPIC, SW_SWITCH_TIMER_TASK_GROUP(1));
538 }
539
540 #if defined(CONFIG_BT_CTLR_PHY_CODED)
hal_radio_sw_switch_coded_tx_config_set(uint8_t ppi_en,uint8_t ppi_dis,uint8_t cc_s2,uint8_t group_index)541 static inline void hal_radio_sw_switch_coded_tx_config_set(uint8_t ppi_en,
542 uint8_t ppi_dis, uint8_t cc_s2, uint8_t group_index)
543 {
544 /* Publish the SW Switch Timer Compare event for S2 timing
545 * to the PPI that will be used to trigger Radio enable.
546 */
547 HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(cc_s2) =
548 HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(ppi_en);
549
550 /* The Radio Enable Task is already subscribed to the channel. */
551
552 /* Wire the Group task disable to the S2 EVENTS_COMPARE. */
553 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT(cc_s2) =
554 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(ppi_dis);
555
556 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK(group_index,
557 ppi_dis);
558
559 /* Capture CC to cancel the timer that has assumed
560 * S8 reception, if packet will be received in S2.
561 */
562 HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_REGISTER_EVT =
563 HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_EVT;
564 nrf_timer_subscribe_set(SW_SWITCH_TIMER,
565 nrf_timer_capture_task_get(SW_SWITCH_TIMER_EVTS_COMP(group_index)),
566 HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI);
567
568 nrf_dppi_channels_enable(NRF_DPPIC,
569 BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI));
570 }
571
572 /* When hardware does not support Coded PHY we still allow the Controller
573 * implementation to accept Coded PHY flags, but the Controller will use 1M
574 * PHY on air. This is implementation specific feature.
575 */
576 #if defined(CONFIG_BT_CTLR_PHY_CODED) && defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
hal_radio_sw_switch_coded_config_clear(uint8_t ppi_en,uint8_t ppi_dis,uint8_t cc_s2,uint8_t group_index)577 static inline void hal_radio_sw_switch_coded_config_clear(uint8_t ppi_en,
578 uint8_t ppi_dis, uint8_t cc_s2, uint8_t group_index)
579 {
580 /* Invalidate subscription of S2 timer Compare used when
581 * RXing on LE Coded PHY.
582 *
583 * Note: we do not un-subscribe the Radio enable task because
584 * we use the same PPI for both SW Switch Timer compare events.
585 */
586 HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(cc_s2) = 0U;
587 }
588 #endif /* CONFIG_BT_CTLR_PHY_CODED && CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
589
hal_radio_sw_switch_disable_group_clear(uint8_t ppi_dis,uint8_t cc_reg,uint8_t group_index)590 static inline void hal_radio_sw_switch_disable_group_clear(uint8_t ppi_dis, uint8_t cc_reg,
591 uint8_t group_index)
592 {
593 /* Wire the Group[group_index] task disable to the default
594 * SW Switch Timer EVENTS_COMPARE.
595 */
596 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT(
597 cc_reg) =
598 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(
599 ppi_dis);
600 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK(
601 group_index, ppi_dis);
602 }
603 #endif /* defined(CONFIG_BT_CTLR_PHY_CODED) */
604
hal_radio_sw_switch_ppi_group_setup(void)605 static inline void hal_radio_sw_switch_ppi_group_setup(void)
606 {
607 /* Include the appropriate PPI channels in the two PPI Groups, used for
608 * SW-based TIFS.
609 *
610 * Note that this needs to be done before any SUBSCRIBE task
611 * registers are written, therefore, we clear the task registers
612 * here.
613 */
614 nrf_dppi_subscribe_clear(NRF_DPPIC,
615 HAL_SW_DPPI_TASK_EN_FROM_IDX(SW_SWITCH_TIMER_TASK_GROUP(0)));
616 nrf_dppi_subscribe_clear(NRF_DPPIC,
617 HAL_SW_DPPI_TASK_DIS_FROM_IDX(SW_SWITCH_TIMER_TASK_GROUP(0)));
618 nrf_dppi_subscribe_clear(NRF_DPPIC,
619 HAL_SW_DPPI_TASK_EN_FROM_IDX(SW_SWITCH_TIMER_TASK_GROUP(1)));
620 nrf_dppi_subscribe_clear(NRF_DPPIC,
621 HAL_SW_DPPI_TASK_DIS_FROM_IDX(SW_SWITCH_TIMER_TASK_GROUP(1)));
622
623 nrf_dppi_task_trigger(NRF_DPPIC,
624 HAL_SW_DPPI_TASK_DIS_FROM_IDX(SW_SWITCH_TIMER_TASK_GROUP(0)));
625 nrf_dppi_task_trigger(NRF_DPPIC,
626 HAL_SW_DPPI_TASK_DIS_FROM_IDX(SW_SWITCH_TIMER_TASK_GROUP(1)));
627
628 /* Include the appropriate PPI channels in the two PPI Groups. */
629 #if defined(CONFIG_BT_CTLR_PHY_CODED)
630 nrf_dppi_group_clear(NRF_DPPIC,
631 SW_SWITCH_TIMER_TASK_GROUP(0));
632 nrf_dppi_channels_include_in_group(NRF_DPPIC,
633 BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(0)) |
634 BIT(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(0)) |
635 BIT(HAL_SW_SWITCH_RADIO_ENABLE_PPI(0)),
636 SW_SWITCH_TIMER_TASK_GROUP(0));
637 nrf_dppi_group_clear(NRF_DPPIC,
638 SW_SWITCH_TIMER_TASK_GROUP(1));
639 nrf_dppi_channels_include_in_group(NRF_DPPIC,
640 BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(1)) |
641 BIT(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(1)) |
642 BIT(HAL_SW_SWITCH_RADIO_ENABLE_PPI(1)),
643 SW_SWITCH_TIMER_TASK_GROUP(1));
644
645 /* NOTE: HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE is equal to
646 * HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE.
647 */
648 BUILD_ASSERT(
649 !IS_ENABLED(CONFIG_BT_CTLR_PHY_CODED) ||
650 (HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE ==
651 HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE),
652 "Radio enable and Group disable not on the same PPI channels.");
653
654 #else /* !CONFIG_BT_CTLR_PHY_CODED */
655 nrf_dppi_group_clear(NRF_DPPIC,
656 SW_SWITCH_TIMER_TASK_GROUP(0));
657 nrf_dppi_channels_include_in_group(NRF_DPPIC,
658 BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(0)) |
659 BIT(HAL_SW_SWITCH_RADIO_ENABLE_PPI(0)),
660 SW_SWITCH_TIMER_TASK_GROUP(0));
661 nrf_dppi_group_clear(NRF_DPPIC,
662 SW_SWITCH_TIMER_TASK_GROUP(1));
663 nrf_dppi_channels_include_in_group(NRF_DPPIC,
664 BIT(HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(1)) |
665 BIT(HAL_SW_SWITCH_RADIO_ENABLE_PPI(1)),
666 SW_SWITCH_TIMER_TASK_GROUP(1));
667 #endif /* !CONFIG_BT_CTLR_PHY_CODED */
668
669 /* Sanity build-time check that RADIO Enable and Group Disable
670 * tasks are going to be subscribed on the same PPIs.
671 */
672 BUILD_ASSERT(
673 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE ==
674 HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE,
675 "Radio enable and Group disable not on the same PPI channels.");
676
677 /* Address nRF5340 Engineering A Errata 16 */
678 nrf_radio_subscribe_clear(NRF_RADIO, NRF_RADIO_TASK_TXEN);
679 nrf_radio_subscribe_clear(NRF_RADIO, NRF_RADIO_TASK_RXEN);
680 }
681
hal_radio_group_task_disable_ppi_setup(void)682 static inline void hal_radio_group_task_disable_ppi_setup(void)
683 {
684
685 /* Wire SW SWITCH TIMER EVENTS COMPARE event <cc index-0> to
686 * PPI Group TASK [<index-0>] DISABLE task, over PPI<index-0>.
687 */
688 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT(
689 SW_SWITCH_TIMER_EVTS_COMP(0)) =
690 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(
691 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(0));
692 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK(0,
693 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(0));
694
695 /* Wire SW SWITCH TIMER event <compare index-1> to
696 * PPI Group[<index-1>] Disable Task, over PPI<index-1>.
697 */
698 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT(
699 SW_SWITCH_TIMER_EVTS_COMP(1)) =
700 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(
701 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(1));
702 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK(1,
703 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(1));
704 }
705
706 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
707 /**
708 * @brief Setup additional EVENTS_COMPARE to compensate EVENTS_PHYEND delay.
709 *
710 * When EVENTS_PHYEND event is used to mark actual end of PDU, CTEINLINE is enabled but received
711 * PDU does not include CTE after CRC, the EVENTS_PHYEND will be generated with a short delay.
712 * That influences maintenance of TISF by software switch. To compensate the delay additional
713 * EVENTS_COMPARE events is set with TIFS value subtracted by the delay. This EVENT_COMPARE
714 * event will timeout before regular EVENTS_COMPARE and start radio switching procedure.
715 * In case there is a CTEInfo in the received PDU, an EVENTS_CTEPRESENT will be generated by
716 * Radio peripheral. The EVENTS_CTEPRESENT event is wired to cancel EVENTS_COMPARE setup for
717 * handling delayed EVENTS_PHYEND.
718 *
719 * Disable of the group of PPIs responsible for handling of software based switch is done by
720 * timeout of regular EVENTS_PHYEND event. The EVENTS_PHYEND delay is short enough (16 us) that
721 * the same EVENT COMPARE may be used to trigger disable task for the software switch group.
722 * In case the EVENTS_COMPARE for delayed EVENTS_PHYEND event timeouts, the group will be disabled
723 * within the Radio TX rampup period.
724 *
725 * CTEINLINE is enabled only for reception of PDUs that may include Constant Tone Extension.
726 * Delayed PHYEND event may occur only at end of received PDU, hence next task that is
727 * triggered by compensated EVENTS_COMPARE is Radio TASKS_TXEN.
728 *
729 * @param phyend_delay_cc Index of EVENTS_COMPARE event to be set for delayed EVENTS_PHYEND event
730 * @param radio_enable_ppi Index of PPI to wire EVENTS_PHYEND event to Radio enable TX task.
731 */
732 static inline void
hal_radio_sw_switch_phyend_delay_compensation_config_set(uint8_t radio_enable_ppi,uint8_t phyend_delay_cc)733 hal_radio_sw_switch_phyend_delay_compensation_config_set(uint8_t radio_enable_ppi,
734 uint8_t phyend_delay_cc)
735 {
736 /* Wire EVENTS_COMPARE[<phyend_delay_cc_offs>] event to Radio TASKS_TXEN */
737 HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(phyend_delay_cc) =
738 HAL_SW_SWITCH_RADIO_ENABLE_PPI_EVT(radio_enable_ppi);
739
740 /* The Radio Enable Task is already subscribed to the channel.
741 * There is no need to call channel enable again here.
742 */
743
744 /* Wire Radio CTEPRESENT event to cancel EVENTS_COMPARE[<cc_offs>] timer */
745 HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_REGISTER_EVT =
746 HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI_EVT;
747 nrf_timer_subscribe_set(SW_SWITCH_TIMER,
748 nrf_timer_capture_task_get(phyend_delay_cc),
749 HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI);
750
751 /* Enable CTEPRESENT event to disable EVENTS_COMPARE[<cc_offs>] PPI channel */
752 nrf_dppi_channels_enable(NRF_DPPIC,
753 BIT(HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI));
754 }
755
756 /**
757 * @brief Clear additional EVENTS_COMAPRE responsible for compensation EVENTS_PHYEND delay.
758 *
759 * Disables PPI responsible for cancel of EVENTS_COMPARE set for delayed EVENTS_PHYEND.
760 * Removes wiring of delayed EVENTS_COMPARE event to enable Radio TX task.
761 *
762 * @param phyend_delay_cc Index of EVENTS_COMPARE event to be cleared
763 * @param radio_enable_ppi Index of PPI to wire EVENTS_PHYEND event to Radio enable TX task.
764 */
765 static inline void
hal_radio_sw_switch_phyend_delay_compensation_config_clear(uint8_t radio_enable_ppi,uint8_t phyend_delay_cc)766 hal_radio_sw_switch_phyend_delay_compensation_config_clear(uint8_t radio_enable_ppi,
767 uint8_t phyend_delay_cc)
768 {
769 /* Invalidate PPI used for compensation of delayed EVETNS_PHYEND.
770 *
771 * Note: we do not un-subscribe the Radio enable task because
772 * we use the same PPI for both SW Switch Timer compare events.
773 */
774 HAL_SW_SWITCH_RADIO_ENABLE_PPI_REGISTER_EVT(phyend_delay_cc) = NRF_PPI_NONE;
775
776 nrf_timer_subscribe_clear(SW_SWITCH_TIMER,
777 nrf_timer_capture_task_get(phyend_delay_cc));
778
779 /* Disable CTEPRESENT event to disable EVENTS_COMPARE[<phyend_delay_cc_offs>] PPI channel */
780 nrf_dppi_channels_disable(NRF_DPPIC,
781 BIT(HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI));
782 }
783 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
784
785 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
786
