1# Nordic Semiconductor nRF53 MCU line
2
3# Copyright (c) 2019 Nordic Semiconductor ASA
4# SPDX-License-Identifier: Apache-2.0
5
6config SOC_SERIES_NRF53X
7	bool
8	select ARM
9	select SOC_COMPATIBLE_NRF53X
10	select CPU_CORTEX_M33
11	select CPU_CORTEX_M_HAS_DWT
12	select CPU_HAS_ARM_MPU
13	imply XIP
14	select HAS_NRFX
15	select HAS_NORDIC_DRIVERS
16	select HAS_NORDIC_RAM_CTRL
17	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
18	select HAS_SWO
19	help
20	 Enable support for NRF53 MCU series
21
22config SOC_NRF5340_CPUAPP
23	select CPU_HAS_NRF_IDAU
24	select CPU_HAS_FPU
25	select ARMV8_M_DSP
26	select HAS_POWEROFF
27	select SOC_COMPATIBLE_NRF5340_CPUAPP
28	select SOC_NRF53_CPUNET_MGMT
29	imply SOC_NRF53_RTC_PRETICK
30	imply SOC_NRF53_ANOMALY_168_WORKAROUND
31
32config SOC_NRF5340_CPUNET
33	select ARM_ON_EXIT_CPU_IDLE
34	select SOC_COMPATIBLE_NRF5340_CPUNET
35	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
36	imply SOC_NRF53_RTC_PRETICK if !WDT_NRFX
37	imply SOC_NRF53_ANOMALY_168_WORKAROUND
38
39if SOC_SERIES_NRF53X
40
41VREGMAIN_PATH := $(dt_nodelabel_path,vregmain)
42VREGRADIO_PATH := $(dt_nodelabel_path,vregradio)
43
44config SOC_NRF53_ANOMALY_47_WORKAROUND
45	bool "Anomaly 47 workaround"
46	depends on NRFX_TWIM
47	help
48	  Due to Anomaly 47 the low period of SCL clock is too short to meet
49	  the I2C specification at 400 kHz. This workaround configures the I2C
50	  frequency to 390 kHz instead of 400 kHz.
51
52config SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
53	bool "Workaround for nRF5340 anomaly 160"
54	imply SOC_NRF53_ANOMALY_160_WORKAROUND
55	default y if "$(dt_node_int_prop_int,$(VREGMAIN_PATH),regulator-initial-mode)" = 1
56	default y if "$(dt_node_int_prop_int,$(VREGRADIO_PATH),regulator-initial-mode)" = 1
57	help
58	  Indicates that the workaround for the anomaly 160 that affects
59	  the nRF5340 SoC should be applied.
60	  This option is enabled by default for the Application MCU when
61	  DC/DC mode is enabled for the VREGMAIN or VREGRADIO regulator
62	  and always for the Network MCU.
63	  If this option is enabled, but the workaround cannot be applied,
64	  because the system clock is disabled, a related cmake warning is
65	  issued.
66
67config SOC_NRF53_ANOMALY_160_WORKAROUND
68	bool
69	depends on SYS_CLOCK_EXISTS
70	select ARM_ON_ENTER_CPU_IDLE_HOOK
71
72config SOC_NRF53_ANOMALY_168_WORKAROUND
73	bool "Workaround for nRF5340 anomaly 168"
74	select ARM_ON_EXIT_CPU_IDLE
75	help
76	  Indicates that the workaround for the anomaly 168 that affects
77	  the nRF5340 SoC should be applied.
78	  The workaround involves execution of 8 NOP instructions when the CPU
79	  exist its idle state (when the WFI/WFE instruction returns) and it is
80	  enabled by default for both the application and network core.
81
82config SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM
83	bool "Extend the workaround to execution at 128 MHz from RAM"
84	depends on SOC_NRF53_ANOMALY_168_WORKAROUND && SOC_NRF5340_CPUAPP
85	help
86	  Indicates that the anomaly 168 workaround is to be extended to cover
87	  also a specific case when the WFI/WFE instruction is executed at 128
88	  MHz from RAM. Then, 26 instead of 8 NOP instructions needs to be
89	  executed after WFI/WFE. This extension is not enabled by default.
90
91config SOC_NRF53_RTC_PRETICK
92	bool "Pre-tick workaround for nRF5340 anomaly 165"
93	depends on (SYS_CLOCK_EXISTS && SOC_NRF5340_CPUNET) || SOC_NRF5340_CPUAPP
94	select NRFX_GPPI
95	select ARM_ON_ENTER_CPU_IDLE_HOOK if SOC_NRF5340_CPUNET
96	select ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK if SOC_NRF5340_CPUNET
97	help
98	  Indicates that the pre-tick workaround for the anomaly 165 that affects
99	  the nRF5340 SoC should be applied. The workaround applies to wake ups caused
100	  by EVENTS_COMPARE and EVENTS_OVRFLW on RTC0 and RTC1 for which interrupts are
101	  enabled through INTENSET register. The case when these events are generated
102	  by EVTEN but without interrupts enabled through INTENSET is not handled.
103	  The EVENTS_TICK event is not handled.
104
105if SOC_NRF53_RTC_PRETICK
106
107config SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET
108	int "IPC 0 channel for RTC pretick"
109	range 0 15
110	default 10
111
112config SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET
113	int "IPC 1 channel for RTC pretick"
114	range 0 15
115	default 11
116
117endif
118
119if SOC_NRF5340_CPUAPP
120
121config SOC_DCDC_NRF53X_APP
122	bool
123	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
124	select DEPRECATED
125	help
126	  This option is deprecated, use devicetree instead. Example
127	  configuration:
128
129	  &vregmain {
130	    regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
131	  };
132
133	  Enable nRF53 series System on Chip Application MCU DC/DC converter.
134
135config SOC_DCDC_NRF53X_NET
136	bool
137	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
138	select DEPRECATED
139	help
140	  This option is deprecated, use devicetree instead. Example
141	  configuration:
142
143	  &vregradio {
144	    regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
145	  };
146
147	  Enable nRF53 series System on Chip Network MCU DC/DC converter.
148
149config SOC_DCDC_NRF53X_HV
150	bool
151	select DEPRECATED
152	help
153	  This option is deprecated, use devicetree instead. Example
154	  configuration:
155
156	  &vregh {
157	    status = "okay";
158	  };
159
160	  Enable nRF53 series System on Chip High Voltage DC/DC converter.
161
162config NRF_SPU_FLASH_REGION_SIZE
163	hex
164	default 0x4000
165	help
166	  FLASH region size for the NRF_SPU peripheral
167
168config NRF_SPU_RAM_REGION_SIZE
169	hex
170	default 0x2000
171	help
172	  RAM region size for the NRF_SPU peripheral
173
174config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340
175	bool "Forward GPIO pins to network core"
176	depends on NRF_SOC_SECURE_SUPPORTED
177	default y if $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER))
178	help
179	  Will forward configured pins with the forwarder compatible to the network core for usage.
180
181config SOC_NRF53_CPUNET_MGMT
182	bool
183	select ONOFF
184	help
185	  hidden option for including the nRF53 network CPU management
186
187config SOC_NRF53_CPUNET_ENABLE
188	bool "NRF53 Network MCU is enabled at boot time"
189	default y if NRF_802154_SER_HOST
190	select SOC_NRF53_CPUNET_MGMT
191	help
192	  This option enables releasing the Network 'force off' signal, which
193	  as a consequence will power up the Network MCU during system boot.
194	  Additionally, the option allocates GPIO pins that will be used by UARTE
195	  of the Network MCU.
196	  Note: GPIO pin allocation can only be configured by the secure Application
197	  MCU firmware, so when this option is used with the non-secure version of
198	  the board, the application needs to take into consideration, that the
199	  secure firmware image must already have configured GPIO allocation for the
200	  Network MCU.
201
202config BOARD_ENABLE_CPUNET
203	bool "[DEPRECATED] NRF53 Network MCU is enabled at boot time"
204	select SOC_NRF53_CPUNET_ENABLE
205	select DEPRECATED
206	help
207	  Use SOC_NRF53_CPUNET_ENABLE instead.
208
209if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
210
211config SOC_ENABLE_LFXO
212	bool "LFXO"
213	select DEPRECATED
214	help
215	  This option is deprecated, use DT instead. For this option to apply,
216	  make sure to select either "internal" or "external" in the
217	  load-capacitors property.
218
219	  Enable the low-frequency oscillator (LFXO) functionality on XL1 and
220	  XL2 pins.
221	  This option must be enabled if either application or network core is
222	  to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular
223	  GPIOs.
224
225choice SOC_LFXO_LOAD_CAPACITANCE
226	prompt "LFXO load capacitance"
227	depends on SOC_ENABLE_LFXO
228
229config SOC_LFXO_CAP_EXTERNAL
230	bool "Use external load capacitors"
231	select DEPRECATED
232	help
233	  This option is deprecated, use DT instead. Example configuration:
234
235	  &lfxo {
236	      load-capacitors = "external";
237	  };
238
239config SOC_LFXO_CAP_INT_6PF
240	bool "6 pF internal load capacitance"
241	select DEPRECATED
242	help
243	  This option is deprecated, use DT instead. Example configuration:
244
245	  &lfxo {
246	      load-capacitors = "internal";
247	      load-capacitance-picofarad = <6>;
248	  };
249
250config SOC_LFXO_CAP_INT_7PF
251	bool "7 pF internal load capacitance"
252	select DEPRECATED
253	help
254	  This option is deprecated, use DT instead. Example configuration:
255
256	  &lfxo {
257	      load-capacitors = "internal";
258	      load-capacitance-picofarad = <7>;
259	  };
260
261config SOC_LFXO_CAP_INT_9PF
262	bool "9 pF internal load capacitance"
263	select DEPRECATED
264	help
265	  This option is deprecated, use DT instead. Example configuration:
266
267	  &lfxo {
268	      load-capacitors = "internal";
269	      load-capacitance-picofarad = <9>;
270	  };
271
272endchoice
273
274choice SOC_HFXO_LOAD_CAPACITANCE
275	prompt "HFXO load capacitance"
276	default SOC_HFXO_CAP_DEFAULT
277
278config SOC_HFXO_CAP_DEFAULT
279	bool "SoC default"
280	help
281	  This option is deprecated, use DT instead. For this configuration to
282	  apply, no DT changes are required from the SoC DT file defaults.
283
284	  When this option is used, the SoC initialization routine does not
285	  touch the XOSC32MCAPS register value, so the default setting for
286	  the SoC is in effect. Please note that this may not necessarily be
287	  the reset value (0) for the register, as the register can be set
288	  during the device trimming in the SystemInit() function.
289
290config SOC_HFXO_CAP_EXTERNAL
291	bool "Use external load capacitors"
292	select DEPRECATED
293	help
294	  This option is deprecated, use DT instead. Example configuration:
295
296	  &hfxo {
297	      load-capacitors = "external";
298	  };
299
300config SOC_HFXO_CAP_INTERNAL
301	bool "Use internal load capacitors"
302	depends on NRF_SOC_SECURE_SUPPORTED
303	select DEPRECATED
304	help
305	  This option is deprecated, use DT instead. Example configuration:
306
307	  &hfxo {
308	      load-capacitors = "internal";
309	      ...
310	  };
311
312	  See CONFIG_SOC_HFXO_CAP_INT_VALUE_X2 for more information.
313
314endchoice
315
316config SOC_HFXO_CAP_INT_VALUE_X2
317	int "Doubled value of HFXO internal load capacitors (in pF)"
318	depends on SOC_HFXO_CAP_INTERNAL
319	range 14 40
320	help
321	  This option is deprecated, use DT instead. Example configuration:
322
323	  &hfxo {
324	      load-capacitors = "internal";
325	      load-capacitance-femtofarad = <7000>;
326	  };
327
328	  Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps
329	  can be enabled on pins XC1 and XC2. This option specifies doubled
330	  capacitance value for the two capacitors. Set it to 14 to get 7.0 pF
331	  for each capacitor, 15 to get 7.5 pF, and so on.
332
333endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
334
335endif # SOC_NRF5340_CPUAPP
336
337
338config NRF_ENABLE_CACHE
339	bool "Cache"
340	depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \
341			|| SOC_NRF5340_CPUNET
342	default y
343	help
344	  Instruction and Data cache is available on nRF5340 CPUAPP
345	  (Application MCU). It may only be accessed by Secure code.
346
347	  Instruction cache only (I-Cache) is available in nRF5340
348	  CPUNET (Network MCU).
349
350config BUILD_WITH_TFM
351	# TF-M nRF53 platform enables the cache unconditionally.
352	select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP
353
354rsource "Kconfig.sync_rtc"
355
356endif # SOC_SERIES_NRF53X
357