1 /* 2 * Copyright (c) 2017 Oticon A/S 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _NRF_HW_MODEL_PPI_H 7 #define _NRF_HW_MODEL_PPI_H 8 9 #ifdef __cplusplus 10 extern "C"{ 11 #endif 12 13 //Signals/Events types HW models may send to the PPI 14 typedef enum { //Note that, for performance, it is better to leave commented the unused ones 15 //0 0x40000000 CLOCK 16 //0 0x40000000 POWER 17 //CLOCK: 18 CLOCK_EVENTS_HFCLKSTARTED , 19 CLOCK_EVENTS_LFCLKSTARTED , 20 CLOCK_EVENTS_DONE , 21 CLOCK_EVENTS_CTTO , 22 CLOCK_EVENTS_CTSTARTED , 23 CLOCK_EVENTS_CTSTOPPED , 24 25 //POWER: 26 // POWER_EVENTS_POFWARN , 27 // POWER_EVENTS_SLEEPENTER , 28 // POWER_EVENTS_SLEEPEXIT , 29 // POWER_EVENTS_USBDETECTED , 30 // POWER_EVENTS_USBREMOVED , 31 // POWER_EVENTS_USBPWRRDY , 32 33 //1 0x40001000 RADIO 34 //RADIO: 35 RADIO_EVENTS_READY , 36 RADIO_EVENTS_ADDRESS , 37 RADIO_EVENTS_PAYLOAD , 38 RADIO_EVENTS_END , 39 RADIO_EVENTS_DISABLED , 40 RADIO_EVENTS_DEVMATCH , 41 RADIO_EVENTS_DEVMISS , 42 RADIO_EVENTS_RSSIEND , 43 RADIO_EVENTS_BCMATCH , 44 RADIO_EVENTS_CRCOK , 45 RADIO_EVENTS_CRCERROR , 46 RADIO_EVENTS_FRAMESTART , 47 RADIO_EVENTS_EDEND , 48 RADIO_EVENTS_EDSTOPPED , 49 RADIO_EVENTS_CCAIDLE , 50 RADIO_EVENTS_CCABUSY , 51 RADIO_EVENTS_CCASTOPPED , 52 RADIO_EVENTS_RATEBOOST , 53 RADIO_EVENTS_TXREADY , 54 RADIO_EVENTS_RXREADY , 55 RADIO_EVENTS_MHRMATCH , 56 RADIO_EVENTS_SYNC , 57 RADIO_EVENTS_PHYEND , 58 RADIO_EVENTS_CTEPRESENT , 59 60 // 2 0x40002000 UARTE 61 // 2 0x40002000 UART 62 // 3 0x40003000 TWIM 63 // 3 0x40003000 SPIS 64 // 3 0x40003000 SPIM 65 // 3 0x40003000 SPI 66 // 3 0x40003000 TWIS 67 // 3 0x40003000 TWI 68 // 4 0x40004000 TWIS 69 // 4 0x40004000 SPIS 70 // 4 0x40004000 SPIM 71 // 4 0x40004000 TWI 72 // 4 0x40004000 TWIM 73 // 4 0x40004000 SPI 74 // 5 0x40005000 NFCT 75 // 6 0x40006000 GPIOTE 76 GPIOTE_EVENTS_IN_0, 77 GPIOTE_EVENTS_IN_1, 78 GPIOTE_EVENTS_IN_2, 79 GPIOTE_EVENTS_IN_3, 80 GPIOTE_EVENTS_IN_4, 81 GPIOTE_EVENTS_IN_5, 82 GPIOTE_EVENTS_IN_6, 83 GPIOTE_EVENTS_IN_7, 84 GPIOTE_EVENTS_PORT, 85 86 // 7 0x40007000 SAADC 87 88 //8 0x40008000 TIMER0 89 //TIMER 90 TIMER0_EVENTS_COMPARE_0 , 91 TIMER0_EVENTS_COMPARE_1 , 92 TIMER0_EVENTS_COMPARE_2 , 93 TIMER0_EVENTS_COMPARE_3 , 94 // TIMER0_EVENTS_COMPARE_4 , 95 // TIMER0_EVENTS_COMPARE_5 , 96 97 //9 0x40009000 Timer 1 98 TIMER1_EVENTS_COMPARE_0 , 99 TIMER1_EVENTS_COMPARE_1 , 100 TIMER1_EVENTS_COMPARE_2 , 101 TIMER1_EVENTS_COMPARE_3 , 102 // TIMER1_EVENTS_COMPARE_4 , 103 // TIMER1_EVENTS_COMPARE_5 , 104 105 //10 0x4000A000 Timer 2 106 TIMER2_EVENTS_COMPARE_0 , 107 TIMER2_EVENTS_COMPARE_1 , 108 TIMER2_EVENTS_COMPARE_2 , 109 TIMER2_EVENTS_COMPARE_3 , 110 // TIMER2_EVENTS_COMPARE_4 , 111 // TIMER2_EVENTS_COMPARE_5 , 112 113 114 //11 0x4000B000 RTC0 115 //RTC 116 RTC0_EVENTS_TICK , 117 RTC0_EVENTS_OVRFLW , 118 RTC0_EVENTS_COMPARE_0 , 119 RTC0_EVENTS_COMPARE_1 , 120 RTC0_EVENTS_COMPARE_2 , 121 RTC0_EVENTS_COMPARE_3 , 122 123 //12 0x4000C000 Temperature sensor 124 TEMP_EVENTS_DATARDY, 125 126 //13 0x4000D000 Random number generator 127 //RNG 128 RNG_EVENTS_VALRDY , 129 130 //14 0x4000E000 ECB AES 131 ECB_EVENTS_ENDECB, 132 ECB_EVENTS_ERRORECB, 133 134 //15 0x4000F000 AAR 135 AAR_EVENTS_END, 136 AAR_EVENTS_RESOLVED, 137 AAR_EVENTS_NOTRESOLVED, 138 139 //15 0x4000F000 CCM AES 140 CCM_EVENTS_ENDKSGEN, 141 CCM_EVENTS_ENDCRYPT, 142 CCM_EVENTS_ERROR, 143 144 //16 0x40010000 WDT 145 146 //17 0x40011000 RTC1 147 RTC1_EVENTS_TICK , 148 RTC1_EVENTS_OVRFLW , 149 RTC1_EVENTS_COMPARE_0 , 150 RTC1_EVENTS_COMPARE_1 , 151 RTC1_EVENTS_COMPARE_2 , 152 RTC1_EVENTS_COMPARE_3 , 153 154 // 18 0x40012000 QDEC 155 // 19 0x40013000 LPCOMP 156 // 19 0x40013000 COMP 157 // 20 0x40014000 EGU 158 EGU0_EVENTS_TRIGGERED_0, //Careful!: These EGU events (inside each instance) are assumed consecutive in the EGU model 159 EGU0_EVENTS_TRIGGERED_1, 160 EGU0_EVENTS_TRIGGERED_2, 161 EGU0_EVENTS_TRIGGERED_3, 162 EGU0_EVENTS_TRIGGERED_4, 163 EGU0_EVENTS_TRIGGERED_5, 164 EGU0_EVENTS_TRIGGERED_6, 165 EGU0_EVENTS_TRIGGERED_7, 166 EGU0_EVENTS_TRIGGERED_8, 167 EGU0_EVENTS_TRIGGERED_9, 168 EGU0_EVENTS_TRIGGERED_10, 169 EGU0_EVENTS_TRIGGERED_11, 170 EGU0_EVENTS_TRIGGERED_12, 171 EGU0_EVENTS_TRIGGERED_13, 172 EGU0_EVENTS_TRIGGERED_14, 173 EGU0_EVENTS_TRIGGERED_15, 174 // 20 0x40014000 SWI 175 // 21 0x40015000 EGU 176 EGU1_EVENTS_TRIGGERED_0, 177 EGU1_EVENTS_TRIGGERED_1, 178 EGU1_EVENTS_TRIGGERED_2, 179 EGU1_EVENTS_TRIGGERED_3, 180 EGU1_EVENTS_TRIGGERED_4, 181 EGU1_EVENTS_TRIGGERED_5, 182 EGU1_EVENTS_TRIGGERED_6, 183 EGU1_EVENTS_TRIGGERED_7, 184 EGU1_EVENTS_TRIGGERED_8, 185 EGU1_EVENTS_TRIGGERED_9, 186 EGU1_EVENTS_TRIGGERED_10, 187 EGU1_EVENTS_TRIGGERED_11, 188 EGU1_EVENTS_TRIGGERED_12, 189 EGU1_EVENTS_TRIGGERED_13, 190 EGU1_EVENTS_TRIGGERED_14, 191 EGU1_EVENTS_TRIGGERED_15, 192 // 21 0x40015000 SWI 193 // 22 0x40016000 EGU 194 EGU2_EVENTS_TRIGGERED_0, 195 EGU2_EVENTS_TRIGGERED_1, 196 EGU2_EVENTS_TRIGGERED_2, 197 EGU2_EVENTS_TRIGGERED_3, 198 EGU2_EVENTS_TRIGGERED_4, 199 EGU2_EVENTS_TRIGGERED_5, 200 EGU2_EVENTS_TRIGGERED_6, 201 EGU2_EVENTS_TRIGGERED_7, 202 EGU2_EVENTS_TRIGGERED_8, 203 EGU2_EVENTS_TRIGGERED_9, 204 EGU2_EVENTS_TRIGGERED_10, 205 EGU2_EVENTS_TRIGGERED_11, 206 EGU2_EVENTS_TRIGGERED_12, 207 EGU2_EVENTS_TRIGGERED_13, 208 EGU2_EVENTS_TRIGGERED_14, 209 EGU2_EVENTS_TRIGGERED_15, 210 // 22 0x40016000 SWI 211 // 23 0x40017000 EGU 212 EGU3_EVENTS_TRIGGERED_0, 213 EGU3_EVENTS_TRIGGERED_1, 214 EGU3_EVENTS_TRIGGERED_2, 215 EGU3_EVENTS_TRIGGERED_3, 216 EGU3_EVENTS_TRIGGERED_4, 217 EGU3_EVENTS_TRIGGERED_5, 218 EGU3_EVENTS_TRIGGERED_6, 219 EGU3_EVENTS_TRIGGERED_7, 220 EGU3_EVENTS_TRIGGERED_8, 221 EGU3_EVENTS_TRIGGERED_9, 222 EGU3_EVENTS_TRIGGERED_10, 223 EGU3_EVENTS_TRIGGERED_11, 224 EGU3_EVENTS_TRIGGERED_12, 225 EGU3_EVENTS_TRIGGERED_13, 226 EGU3_EVENTS_TRIGGERED_14, 227 EGU3_EVENTS_TRIGGERED_15, 228 // 23 0x40017000 SWI 229 // 24 0x40018000 SWI 230 // 24 0x40018000 EGU 231 EGU4_EVENTS_TRIGGERED_0, 232 EGU4_EVENTS_TRIGGERED_1, 233 EGU4_EVENTS_TRIGGERED_2, 234 EGU4_EVENTS_TRIGGERED_3, 235 EGU4_EVENTS_TRIGGERED_4, 236 EGU4_EVENTS_TRIGGERED_5, 237 EGU4_EVENTS_TRIGGERED_6, 238 EGU4_EVENTS_TRIGGERED_7, 239 EGU4_EVENTS_TRIGGERED_8, 240 EGU4_EVENTS_TRIGGERED_9, 241 EGU4_EVENTS_TRIGGERED_10, 242 EGU4_EVENTS_TRIGGERED_11, 243 EGU4_EVENTS_TRIGGERED_12, 244 EGU4_EVENTS_TRIGGERED_13, 245 EGU4_EVENTS_TRIGGERED_14, 246 EGU4_EVENTS_TRIGGERED_15, 247 // 25 0x40019000 SWI 248 // 25 0x40019000 EGU 249 EGU5_EVENTS_TRIGGERED_0, 250 EGU5_EVENTS_TRIGGERED_1, 251 EGU5_EVENTS_TRIGGERED_2, 252 EGU5_EVENTS_TRIGGERED_3, 253 EGU5_EVENTS_TRIGGERED_4, 254 EGU5_EVENTS_TRIGGERED_5, 255 EGU5_EVENTS_TRIGGERED_6, 256 EGU5_EVENTS_TRIGGERED_7, 257 EGU5_EVENTS_TRIGGERED_8, 258 EGU5_EVENTS_TRIGGERED_9, 259 EGU5_EVENTS_TRIGGERED_10, 260 EGU5_EVENTS_TRIGGERED_11, 261 EGU5_EVENTS_TRIGGERED_12, 262 EGU5_EVENTS_TRIGGERED_13, 263 EGU5_EVENTS_TRIGGERED_14, 264 EGU5_EVENTS_TRIGGERED_15, 265 266 // 26 0x4001A000 TIMER3 267 TIMER3_EVENTS_COMPARE_0 , 268 TIMER3_EVENTS_COMPARE_1 , 269 TIMER3_EVENTS_COMPARE_2 , 270 TIMER3_EVENTS_COMPARE_3 , 271 TIMER3_EVENTS_COMPARE_4 , 272 TIMER3_EVENTS_COMPARE_5 , 273 274 // 27 0x4001B000 TIMER4 275 TIMER4_EVENTS_COMPARE_0 , 276 TIMER4_EVENTS_COMPARE_1 , 277 TIMER4_EVENTS_COMPARE_2 , 278 TIMER4_EVENTS_COMPARE_3 , 279 TIMER4_EVENTS_COMPARE_4 , 280 TIMER4_EVENTS_COMPARE_5 , 281 282 // 28 0x4001C000 PWM 283 // 29 0x4001D000 PDM 284 // 30 0x4001E000 ACL 285 // 30 0x4001E000 NVMC 286 287 //31 0x4001F000 PPI 288 //PPI 289 //No events 290 291 // 32 0x40020000 MWU 292 // 33 0x40021000 PWM 293 // 34 0x40022000 PWM 294 // 35 0x40023000 SPIM 295 // 35 0x40023000 SPIS 296 // 35 0x40023000 SPI 297 // 36 0x40024000 RTC 298 RTC2_EVENTS_TICK , 299 RTC2_EVENTS_OVRFLW , 300 RTC2_EVENTS_COMPARE_0 , 301 RTC2_EVENTS_COMPARE_1 , 302 RTC2_EVENTS_COMPARE_2 , 303 RTC2_EVENTS_COMPARE_3 , 304 305 // 37 0x40025000 I2S 306 // 38 0x40026000 FPU 307 // 39 0x40027000 USBD 308 // 40 0x40028000 UARTE 309 // 41 0x40029000 QSPI 310 // 45 0x4002D000 PWM 311 // 47 0x4002F000 SPIM 312 // 0 0x50000000 GPIO 313 // 0 0x50000000 GPIO 314 // 0 0x50000300 GPIO 315 // 42 0x5002A000 CRYPTOCELL 316 // N/A 0x10000000 FICR 317 // N/A 0x10001000 UICR 318 319 NUMBER_PPI_EVENTS 320 } ppi_event_types_t; 321 322 #define NUMBER_PPI_CHANNELS 32 323 324 void nrf_ppi_event(ppi_event_types_t event); 325 void nrf_ppi_regw_sideeffects_TEP(int ch_nbr); 326 void nrf_ppi_regw_sideeffects_EEP(int ch_nbr); 327 void nrf_ppi_regw_sideeffects_FORK_TEP(int ch_nbr); 328 void nrf_ppi_regw_sideeffects_TASKS_CHG_DIS(int i); 329 void nrf_ppi_regw_sideeffects_TASKS_CHG_EN(int i); 330 void nrf_ppi_regw_sideeffects_CHENSET(void); 331 void nrf_ppi_regw_sideeffects_CHENCLR(void); 332 333 #ifdef __cplusplus 334 } 335 #endif 336 337 #endif 338
