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Searched refs:hri_gclk_write_PCHCTRL_reg (Results 1 – 7 of 7) sorted by relevance

/loramac-node-latest/src/boards/SAMR34/
Duart-board.c39 …hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | ( 1 << GCLK_P… in UartMcuInit()
40 …hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | ( 1 << GCLK_P… in UartMcuInit()
Di2c-board.c48 hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM1_GCLK_ID_CORE, in I2cMcuInit()
50 hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM1_GCLK_ID_SLOW, in I2cMcuInit()
Dspi-board.c34 …hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | ( 1 << GCLK_P… in SpiInit()
35 …hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | ( 1 << GCLK_P… in SpiInit()
Dboard.c79 …hri_gclk_write_PCHCTRL_reg( GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | ( 1 << GCLK_PCHCTRL_CHEN_Pos ) … in BoardInitMcu()
/loramac-node-latest/src/boards/mcu/saml21/hpl/oscctrl/
Dhpl_oscctrl.c110 …hri_gclk_write_PCHCTRL_reg(GCLK, 0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK… in _oscctrl_init_referenced_generators()
139 …hri_gclk_write_PCHCTRL_reg(GCLK, 1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DPLL_GCLK… in _oscctrl_init_referenced_generators()
/loramac-node-latest/src/boards/mcu/saml21/hpl/gclk/
Dhpl_gclk_base.h81 hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); in _gclk_enable_channel()
/loramac-node-latest/src/boards/mcu/saml21/hri/
Dhri_gclk_l21.h661 static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl… in hri_gclk_write_PCHCTRL_reg() function