1 /**
2 * \file
3 *
4 * \brief SAM AC
5 *
6 * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 */
42
43 #ifdef _SAML21_AC_COMPONENT_
44 #ifndef _HRI_AC_L21_H_INCLUDED_
45 #define _HRI_AC_L21_H_INCLUDED_
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53
54 #if defined(ENABLE_AC_CRITICAL_SECTIONS)
55 #define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define AC_CRITICAL_SECTION_ENTER()
59 #define AC_CRITICAL_SECTION_LEAVE()
60 #endif
61
62 typedef uint16_t hri_ac_evctrl_reg_t;
63 typedef uint32_t hri_ac_compctrl_reg_t;
64 typedef uint32_t hri_ac_syncbusy_reg_t;
65 typedef uint8_t hri_ac_ctrla_reg_t;
66 typedef uint8_t hri_ac_ctrlb_reg_t;
67 typedef uint8_t hri_ac_dbgctrl_reg_t;
68 typedef uint8_t hri_ac_intenset_reg_t;
69 typedef uint8_t hri_ac_intflag_reg_t;
70 typedef uint8_t hri_ac_scaler_reg_t;
71 typedef uint8_t hri_ac_statusa_reg_t;
72 typedef uint8_t hri_ac_statusb_reg_t;
73 typedef uint8_t hri_ac_winctrl_reg_t;
74
hri_ac_wait_for_sync(const void * const hw,hri_ac_syncbusy_reg_t reg)75 static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg)
76 {
77 while (((Ac *)hw)->SYNCBUSY.reg & reg) {
78 };
79 }
80
hri_ac_is_syncing(const void * const hw,hri_ac_syncbusy_reg_t reg)81 static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg)
82 {
83 return ((Ac *)hw)->SYNCBUSY.reg & reg;
84 }
85
hri_ac_set_INTEN_COMP0_bit(const void * const hw)86 static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw)
87 {
88 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
89 }
90
hri_ac_get_INTEN_COMP0_bit(const void * const hw)91 static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw)
92 {
93 return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos;
94 }
95
hri_ac_write_INTEN_COMP0_bit(const void * const hw,bool value)96 static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value)
97 {
98 if (value == 0x0) {
99 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
100 } else {
101 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0;
102 }
103 }
104
hri_ac_clear_INTEN_COMP0_bit(const void * const hw)105 static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw)
106 {
107 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0;
108 }
109
hri_ac_set_INTEN_COMP1_bit(const void * const hw)110 static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw)
111 {
112 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
113 }
114
hri_ac_get_INTEN_COMP1_bit(const void * const hw)115 static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw)
116 {
117 return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos;
118 }
119
hri_ac_write_INTEN_COMP1_bit(const void * const hw,bool value)120 static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value)
121 {
122 if (value == 0x0) {
123 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
124 } else {
125 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1;
126 }
127 }
128
hri_ac_clear_INTEN_COMP1_bit(const void * const hw)129 static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw)
130 {
131 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1;
132 }
133
hri_ac_set_INTEN_WIN0_bit(const void * const hw)134 static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw)
135 {
136 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
137 }
138
hri_ac_get_INTEN_WIN0_bit(const void * const hw)139 static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw)
140 {
141 return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos;
142 }
143
hri_ac_write_INTEN_WIN0_bit(const void * const hw,bool value)144 static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value)
145 {
146 if (value == 0x0) {
147 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
148 } else {
149 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0;
150 }
151 }
152
hri_ac_clear_INTEN_WIN0_bit(const void * const hw)153 static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw)
154 {
155 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0;
156 }
157
hri_ac_set_INTEN_reg(const void * const hw,hri_ac_intenset_reg_t mask)158 static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
159 {
160 ((Ac *)hw)->INTENSET.reg = mask;
161 }
162
hri_ac_get_INTEN_reg(const void * const hw,hri_ac_intenset_reg_t mask)163 static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
164 {
165 uint8_t tmp;
166 tmp = ((Ac *)hw)->INTENSET.reg;
167 tmp &= mask;
168 return tmp;
169 }
170
hri_ac_read_INTEN_reg(const void * const hw)171 static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw)
172 {
173 return ((Ac *)hw)->INTENSET.reg;
174 }
175
hri_ac_write_INTEN_reg(const void * const hw,hri_ac_intenset_reg_t data)176 static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data)
177 {
178 ((Ac *)hw)->INTENSET.reg = data;
179 ((Ac *)hw)->INTENCLR.reg = ~data;
180 }
181
hri_ac_clear_INTEN_reg(const void * const hw,hri_ac_intenset_reg_t mask)182 static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask)
183 {
184 ((Ac *)hw)->INTENCLR.reg = mask;
185 }
186
hri_ac_get_INTFLAG_COMP0_bit(const void * const hw)187 static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw)
188 {
189 return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
190 }
191
hri_ac_clear_INTFLAG_COMP0_bit(const void * const hw)192 static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw)
193 {
194 ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
195 }
196
hri_ac_get_INTFLAG_COMP1_bit(const void * const hw)197 static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw)
198 {
199 return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
200 }
201
hri_ac_clear_INTFLAG_COMP1_bit(const void * const hw)202 static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw)
203 {
204 ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
205 }
206
hri_ac_get_INTFLAG_WIN0_bit(const void * const hw)207 static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw)
208 {
209 return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
210 }
211
hri_ac_clear_INTFLAG_WIN0_bit(const void * const hw)212 static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw)
213 {
214 ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
215 }
216
hri_ac_get_interrupt_COMP0_bit(const void * const hw)217 static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw)
218 {
219 return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos;
220 }
221
hri_ac_clear_interrupt_COMP0_bit(const void * const hw)222 static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw)
223 {
224 ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0;
225 }
226
hri_ac_get_interrupt_COMP1_bit(const void * const hw)227 static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw)
228 {
229 return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos;
230 }
231
hri_ac_clear_interrupt_COMP1_bit(const void * const hw)232 static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw)
233 {
234 ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1;
235 }
236
hri_ac_get_interrupt_WIN0_bit(const void * const hw)237 static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw)
238 {
239 return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos;
240 }
241
hri_ac_clear_interrupt_WIN0_bit(const void * const hw)242 static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw)
243 {
244 ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0;
245 }
246
hri_ac_get_INTFLAG_reg(const void * const hw,hri_ac_intflag_reg_t mask)247 static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
248 {
249 uint8_t tmp;
250 tmp = ((Ac *)hw)->INTFLAG.reg;
251 tmp &= mask;
252 return tmp;
253 }
254
hri_ac_read_INTFLAG_reg(const void * const hw)255 static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw)
256 {
257 return ((Ac *)hw)->INTFLAG.reg;
258 }
259
hri_ac_clear_INTFLAG_reg(const void * const hw,hri_ac_intflag_reg_t mask)260 static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask)
261 {
262 ((Ac *)hw)->INTFLAG.reg = mask;
263 }
264
hri_ac_write_CTRLB_reg(const void * const hw,hri_ac_ctrlb_reg_t data)265 static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data)
266 {
267 AC_CRITICAL_SECTION_ENTER();
268 ((Ac *)hw)->CTRLB.reg = data;
269 AC_CRITICAL_SECTION_LEAVE();
270 }
271
hri_ac_set_CTRLA_SWRST_bit(const void * const hw)272 static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw)
273 {
274 AC_CRITICAL_SECTION_ENTER();
275 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
276 ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST;
277 AC_CRITICAL_SECTION_LEAVE();
278 }
279
hri_ac_get_CTRLA_SWRST_bit(const void * const hw)280 static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw)
281 {
282 uint8_t tmp;
283 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST);
284 tmp = ((Ac *)hw)->CTRLA.reg;
285 tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos;
286 return (bool)tmp;
287 }
288
hri_ac_set_CTRLA_ENABLE_bit(const void * const hw)289 static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw)
290 {
291 AC_CRITICAL_SECTION_ENTER();
292 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
293 ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE;
294 AC_CRITICAL_SECTION_LEAVE();
295 }
296
hri_ac_get_CTRLA_ENABLE_bit(const void * const hw)297 static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw)
298 {
299 uint8_t tmp;
300 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
301 tmp = ((Ac *)hw)->CTRLA.reg;
302 tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos;
303 return (bool)tmp;
304 }
305
hri_ac_write_CTRLA_ENABLE_bit(const void * const hw,bool value)306 static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
307 {
308 uint8_t tmp;
309 AC_CRITICAL_SECTION_ENTER();
310 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
311 tmp = ((Ac *)hw)->CTRLA.reg;
312 tmp &= ~AC_CTRLA_ENABLE;
313 tmp |= value << AC_CTRLA_ENABLE_Pos;
314 ((Ac *)hw)->CTRLA.reg = tmp;
315 AC_CRITICAL_SECTION_LEAVE();
316 }
317
hri_ac_clear_CTRLA_ENABLE_bit(const void * const hw)318 static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw)
319 {
320 AC_CRITICAL_SECTION_ENTER();
321 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
322 ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE;
323 AC_CRITICAL_SECTION_LEAVE();
324 }
325
hri_ac_toggle_CTRLA_ENABLE_bit(const void * const hw)326 static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw)
327 {
328 AC_CRITICAL_SECTION_ENTER();
329 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE);
330 ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE;
331 AC_CRITICAL_SECTION_LEAVE();
332 }
333
hri_ac_set_CTRLA_reg(const void * const hw,hri_ac_ctrla_reg_t mask)334 static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
335 {
336 AC_CRITICAL_SECTION_ENTER();
337 ((Ac *)hw)->CTRLA.reg |= mask;
338 AC_CRITICAL_SECTION_LEAVE();
339 }
340
hri_ac_get_CTRLA_reg(const void * const hw,hri_ac_ctrla_reg_t mask)341 static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
342 {
343 uint8_t tmp;
344 tmp = ((Ac *)hw)->CTRLA.reg;
345 tmp &= mask;
346 return tmp;
347 }
348
hri_ac_write_CTRLA_reg(const void * const hw,hri_ac_ctrla_reg_t data)349 static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data)
350 {
351 AC_CRITICAL_SECTION_ENTER();
352 ((Ac *)hw)->CTRLA.reg = data;
353 AC_CRITICAL_SECTION_LEAVE();
354 }
355
hri_ac_clear_CTRLA_reg(const void * const hw,hri_ac_ctrla_reg_t mask)356 static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
357 {
358 AC_CRITICAL_SECTION_ENTER();
359 ((Ac *)hw)->CTRLA.reg &= ~mask;
360 AC_CRITICAL_SECTION_LEAVE();
361 }
362
hri_ac_toggle_CTRLA_reg(const void * const hw,hri_ac_ctrla_reg_t mask)363 static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask)
364 {
365 AC_CRITICAL_SECTION_ENTER();
366 ((Ac *)hw)->CTRLA.reg ^= mask;
367 AC_CRITICAL_SECTION_LEAVE();
368 }
369
hri_ac_read_CTRLA_reg(const void * const hw)370 static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw)
371 {
372 return ((Ac *)hw)->CTRLA.reg;
373 }
374
hri_ac_set_EVCTRL_COMPEO0_bit(const void * const hw)375 static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw)
376 {
377 AC_CRITICAL_SECTION_ENTER();
378 ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0;
379 AC_CRITICAL_SECTION_LEAVE();
380 }
381
hri_ac_get_EVCTRL_COMPEO0_bit(const void * const hw)382 static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw)
383 {
384 uint16_t tmp;
385 tmp = ((Ac *)hw)->EVCTRL.reg;
386 tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos;
387 return (bool)tmp;
388 }
389
hri_ac_write_EVCTRL_COMPEO0_bit(const void * const hw,bool value)390 static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value)
391 {
392 uint16_t tmp;
393 AC_CRITICAL_SECTION_ENTER();
394 tmp = ((Ac *)hw)->EVCTRL.reg;
395 tmp &= ~AC_EVCTRL_COMPEO0;
396 tmp |= value << AC_EVCTRL_COMPEO0_Pos;
397 ((Ac *)hw)->EVCTRL.reg = tmp;
398 AC_CRITICAL_SECTION_LEAVE();
399 }
400
hri_ac_clear_EVCTRL_COMPEO0_bit(const void * const hw)401 static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw)
402 {
403 AC_CRITICAL_SECTION_ENTER();
404 ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0;
405 AC_CRITICAL_SECTION_LEAVE();
406 }
407
hri_ac_toggle_EVCTRL_COMPEO0_bit(const void * const hw)408 static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw)
409 {
410 AC_CRITICAL_SECTION_ENTER();
411 ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0;
412 AC_CRITICAL_SECTION_LEAVE();
413 }
414
hri_ac_set_EVCTRL_COMPEO1_bit(const void * const hw)415 static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw)
416 {
417 AC_CRITICAL_SECTION_ENTER();
418 ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1;
419 AC_CRITICAL_SECTION_LEAVE();
420 }
421
hri_ac_get_EVCTRL_COMPEO1_bit(const void * const hw)422 static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw)
423 {
424 uint16_t tmp;
425 tmp = ((Ac *)hw)->EVCTRL.reg;
426 tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos;
427 return (bool)tmp;
428 }
429
hri_ac_write_EVCTRL_COMPEO1_bit(const void * const hw,bool value)430 static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value)
431 {
432 uint16_t tmp;
433 AC_CRITICAL_SECTION_ENTER();
434 tmp = ((Ac *)hw)->EVCTRL.reg;
435 tmp &= ~AC_EVCTRL_COMPEO1;
436 tmp |= value << AC_EVCTRL_COMPEO1_Pos;
437 ((Ac *)hw)->EVCTRL.reg = tmp;
438 AC_CRITICAL_SECTION_LEAVE();
439 }
440
hri_ac_clear_EVCTRL_COMPEO1_bit(const void * const hw)441 static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw)
442 {
443 AC_CRITICAL_SECTION_ENTER();
444 ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1;
445 AC_CRITICAL_SECTION_LEAVE();
446 }
447
hri_ac_toggle_EVCTRL_COMPEO1_bit(const void * const hw)448 static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw)
449 {
450 AC_CRITICAL_SECTION_ENTER();
451 ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1;
452 AC_CRITICAL_SECTION_LEAVE();
453 }
454
hri_ac_set_EVCTRL_WINEO0_bit(const void * const hw)455 static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw)
456 {
457 AC_CRITICAL_SECTION_ENTER();
458 ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0;
459 AC_CRITICAL_SECTION_LEAVE();
460 }
461
hri_ac_get_EVCTRL_WINEO0_bit(const void * const hw)462 static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw)
463 {
464 uint16_t tmp;
465 tmp = ((Ac *)hw)->EVCTRL.reg;
466 tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos;
467 return (bool)tmp;
468 }
469
hri_ac_write_EVCTRL_WINEO0_bit(const void * const hw,bool value)470 static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value)
471 {
472 uint16_t tmp;
473 AC_CRITICAL_SECTION_ENTER();
474 tmp = ((Ac *)hw)->EVCTRL.reg;
475 tmp &= ~AC_EVCTRL_WINEO0;
476 tmp |= value << AC_EVCTRL_WINEO0_Pos;
477 ((Ac *)hw)->EVCTRL.reg = tmp;
478 AC_CRITICAL_SECTION_LEAVE();
479 }
480
hri_ac_clear_EVCTRL_WINEO0_bit(const void * const hw)481 static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw)
482 {
483 AC_CRITICAL_SECTION_ENTER();
484 ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0;
485 AC_CRITICAL_SECTION_LEAVE();
486 }
487
hri_ac_toggle_EVCTRL_WINEO0_bit(const void * const hw)488 static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw)
489 {
490 AC_CRITICAL_SECTION_ENTER();
491 ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0;
492 AC_CRITICAL_SECTION_LEAVE();
493 }
494
hri_ac_set_EVCTRL_COMPEI0_bit(const void * const hw)495 static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw)
496 {
497 AC_CRITICAL_SECTION_ENTER();
498 ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0;
499 AC_CRITICAL_SECTION_LEAVE();
500 }
501
hri_ac_get_EVCTRL_COMPEI0_bit(const void * const hw)502 static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw)
503 {
504 uint16_t tmp;
505 tmp = ((Ac *)hw)->EVCTRL.reg;
506 tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos;
507 return (bool)tmp;
508 }
509
hri_ac_write_EVCTRL_COMPEI0_bit(const void * const hw,bool value)510 static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value)
511 {
512 uint16_t tmp;
513 AC_CRITICAL_SECTION_ENTER();
514 tmp = ((Ac *)hw)->EVCTRL.reg;
515 tmp &= ~AC_EVCTRL_COMPEI0;
516 tmp |= value << AC_EVCTRL_COMPEI0_Pos;
517 ((Ac *)hw)->EVCTRL.reg = tmp;
518 AC_CRITICAL_SECTION_LEAVE();
519 }
520
hri_ac_clear_EVCTRL_COMPEI0_bit(const void * const hw)521 static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw)
522 {
523 AC_CRITICAL_SECTION_ENTER();
524 ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0;
525 AC_CRITICAL_SECTION_LEAVE();
526 }
527
hri_ac_toggle_EVCTRL_COMPEI0_bit(const void * const hw)528 static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw)
529 {
530 AC_CRITICAL_SECTION_ENTER();
531 ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0;
532 AC_CRITICAL_SECTION_LEAVE();
533 }
534
hri_ac_set_EVCTRL_COMPEI1_bit(const void * const hw)535 static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw)
536 {
537 AC_CRITICAL_SECTION_ENTER();
538 ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1;
539 AC_CRITICAL_SECTION_LEAVE();
540 }
541
hri_ac_get_EVCTRL_COMPEI1_bit(const void * const hw)542 static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw)
543 {
544 uint16_t tmp;
545 tmp = ((Ac *)hw)->EVCTRL.reg;
546 tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos;
547 return (bool)tmp;
548 }
549
hri_ac_write_EVCTRL_COMPEI1_bit(const void * const hw,bool value)550 static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value)
551 {
552 uint16_t tmp;
553 AC_CRITICAL_SECTION_ENTER();
554 tmp = ((Ac *)hw)->EVCTRL.reg;
555 tmp &= ~AC_EVCTRL_COMPEI1;
556 tmp |= value << AC_EVCTRL_COMPEI1_Pos;
557 ((Ac *)hw)->EVCTRL.reg = tmp;
558 AC_CRITICAL_SECTION_LEAVE();
559 }
560
hri_ac_clear_EVCTRL_COMPEI1_bit(const void * const hw)561 static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw)
562 {
563 AC_CRITICAL_SECTION_ENTER();
564 ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1;
565 AC_CRITICAL_SECTION_LEAVE();
566 }
567
hri_ac_toggle_EVCTRL_COMPEI1_bit(const void * const hw)568 static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw)
569 {
570 AC_CRITICAL_SECTION_ENTER();
571 ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1;
572 AC_CRITICAL_SECTION_LEAVE();
573 }
574
hri_ac_set_EVCTRL_INVEI0_bit(const void * const hw)575 static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw)
576 {
577 AC_CRITICAL_SECTION_ENTER();
578 ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0;
579 AC_CRITICAL_SECTION_LEAVE();
580 }
581
hri_ac_get_EVCTRL_INVEI0_bit(const void * const hw)582 static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw)
583 {
584 uint16_t tmp;
585 tmp = ((Ac *)hw)->EVCTRL.reg;
586 tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos;
587 return (bool)tmp;
588 }
589
hri_ac_write_EVCTRL_INVEI0_bit(const void * const hw,bool value)590 static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value)
591 {
592 uint16_t tmp;
593 AC_CRITICAL_SECTION_ENTER();
594 tmp = ((Ac *)hw)->EVCTRL.reg;
595 tmp &= ~AC_EVCTRL_INVEI0;
596 tmp |= value << AC_EVCTRL_INVEI0_Pos;
597 ((Ac *)hw)->EVCTRL.reg = tmp;
598 AC_CRITICAL_SECTION_LEAVE();
599 }
600
hri_ac_clear_EVCTRL_INVEI0_bit(const void * const hw)601 static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw)
602 {
603 AC_CRITICAL_SECTION_ENTER();
604 ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0;
605 AC_CRITICAL_SECTION_LEAVE();
606 }
607
hri_ac_toggle_EVCTRL_INVEI0_bit(const void * const hw)608 static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw)
609 {
610 AC_CRITICAL_SECTION_ENTER();
611 ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0;
612 AC_CRITICAL_SECTION_LEAVE();
613 }
614
hri_ac_set_EVCTRL_INVEI1_bit(const void * const hw)615 static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw)
616 {
617 AC_CRITICAL_SECTION_ENTER();
618 ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1;
619 AC_CRITICAL_SECTION_LEAVE();
620 }
621
hri_ac_get_EVCTRL_INVEI1_bit(const void * const hw)622 static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw)
623 {
624 uint16_t tmp;
625 tmp = ((Ac *)hw)->EVCTRL.reg;
626 tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos;
627 return (bool)tmp;
628 }
629
hri_ac_write_EVCTRL_INVEI1_bit(const void * const hw,bool value)630 static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value)
631 {
632 uint16_t tmp;
633 AC_CRITICAL_SECTION_ENTER();
634 tmp = ((Ac *)hw)->EVCTRL.reg;
635 tmp &= ~AC_EVCTRL_INVEI1;
636 tmp |= value << AC_EVCTRL_INVEI1_Pos;
637 ((Ac *)hw)->EVCTRL.reg = tmp;
638 AC_CRITICAL_SECTION_LEAVE();
639 }
640
hri_ac_clear_EVCTRL_INVEI1_bit(const void * const hw)641 static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw)
642 {
643 AC_CRITICAL_SECTION_ENTER();
644 ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1;
645 AC_CRITICAL_SECTION_LEAVE();
646 }
647
hri_ac_toggle_EVCTRL_INVEI1_bit(const void * const hw)648 static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw)
649 {
650 AC_CRITICAL_SECTION_ENTER();
651 ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1;
652 AC_CRITICAL_SECTION_LEAVE();
653 }
654
hri_ac_set_EVCTRL_reg(const void * const hw,hri_ac_evctrl_reg_t mask)655 static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
656 {
657 AC_CRITICAL_SECTION_ENTER();
658 ((Ac *)hw)->EVCTRL.reg |= mask;
659 AC_CRITICAL_SECTION_LEAVE();
660 }
661
hri_ac_get_EVCTRL_reg(const void * const hw,hri_ac_evctrl_reg_t mask)662 static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
663 {
664 uint16_t tmp;
665 tmp = ((Ac *)hw)->EVCTRL.reg;
666 tmp &= mask;
667 return tmp;
668 }
669
hri_ac_write_EVCTRL_reg(const void * const hw,hri_ac_evctrl_reg_t data)670 static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data)
671 {
672 AC_CRITICAL_SECTION_ENTER();
673 ((Ac *)hw)->EVCTRL.reg = data;
674 AC_CRITICAL_SECTION_LEAVE();
675 }
676
hri_ac_clear_EVCTRL_reg(const void * const hw,hri_ac_evctrl_reg_t mask)677 static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
678 {
679 AC_CRITICAL_SECTION_ENTER();
680 ((Ac *)hw)->EVCTRL.reg &= ~mask;
681 AC_CRITICAL_SECTION_LEAVE();
682 }
683
hri_ac_toggle_EVCTRL_reg(const void * const hw,hri_ac_evctrl_reg_t mask)684 static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask)
685 {
686 AC_CRITICAL_SECTION_ENTER();
687 ((Ac *)hw)->EVCTRL.reg ^= mask;
688 AC_CRITICAL_SECTION_LEAVE();
689 }
690
hri_ac_read_EVCTRL_reg(const void * const hw)691 static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw)
692 {
693 return ((Ac *)hw)->EVCTRL.reg;
694 }
695
hri_ac_set_DBGCTRL_DBGRUN_bit(const void * const hw)696 static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
697 {
698 AC_CRITICAL_SECTION_ENTER();
699 ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN;
700 AC_CRITICAL_SECTION_LEAVE();
701 }
702
hri_ac_get_DBGCTRL_DBGRUN_bit(const void * const hw)703 static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
704 {
705 uint8_t tmp;
706 tmp = ((Ac *)hw)->DBGCTRL.reg;
707 tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos;
708 return (bool)tmp;
709 }
710
hri_ac_write_DBGCTRL_DBGRUN_bit(const void * const hw,bool value)711 static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
712 {
713 uint8_t tmp;
714 AC_CRITICAL_SECTION_ENTER();
715 tmp = ((Ac *)hw)->DBGCTRL.reg;
716 tmp &= ~AC_DBGCTRL_DBGRUN;
717 tmp |= value << AC_DBGCTRL_DBGRUN_Pos;
718 ((Ac *)hw)->DBGCTRL.reg = tmp;
719 AC_CRITICAL_SECTION_LEAVE();
720 }
721
hri_ac_clear_DBGCTRL_DBGRUN_bit(const void * const hw)722 static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
723 {
724 AC_CRITICAL_SECTION_ENTER();
725 ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN;
726 AC_CRITICAL_SECTION_LEAVE();
727 }
728
hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void * const hw)729 static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
730 {
731 AC_CRITICAL_SECTION_ENTER();
732 ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN;
733 AC_CRITICAL_SECTION_LEAVE();
734 }
735
hri_ac_set_DBGCTRL_reg(const void * const hw,hri_ac_dbgctrl_reg_t mask)736 static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
737 {
738 AC_CRITICAL_SECTION_ENTER();
739 ((Ac *)hw)->DBGCTRL.reg |= mask;
740 AC_CRITICAL_SECTION_LEAVE();
741 }
742
hri_ac_get_DBGCTRL_reg(const void * const hw,hri_ac_dbgctrl_reg_t mask)743 static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
744 {
745 uint8_t tmp;
746 tmp = ((Ac *)hw)->DBGCTRL.reg;
747 tmp &= mask;
748 return tmp;
749 }
750
hri_ac_write_DBGCTRL_reg(const void * const hw,hri_ac_dbgctrl_reg_t data)751 static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data)
752 {
753 AC_CRITICAL_SECTION_ENTER();
754 ((Ac *)hw)->DBGCTRL.reg = data;
755 AC_CRITICAL_SECTION_LEAVE();
756 }
757
hri_ac_clear_DBGCTRL_reg(const void * const hw,hri_ac_dbgctrl_reg_t mask)758 static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
759 {
760 AC_CRITICAL_SECTION_ENTER();
761 ((Ac *)hw)->DBGCTRL.reg &= ~mask;
762 AC_CRITICAL_SECTION_LEAVE();
763 }
764
hri_ac_toggle_DBGCTRL_reg(const void * const hw,hri_ac_dbgctrl_reg_t mask)765 static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask)
766 {
767 AC_CRITICAL_SECTION_ENTER();
768 ((Ac *)hw)->DBGCTRL.reg ^= mask;
769 AC_CRITICAL_SECTION_LEAVE();
770 }
771
hri_ac_read_DBGCTRL_reg(const void * const hw)772 static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw)
773 {
774 return ((Ac *)hw)->DBGCTRL.reg;
775 }
776
hri_ac_set_WINCTRL_WEN0_bit(const void * const hw)777 static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw)
778 {
779 AC_CRITICAL_SECTION_ENTER();
780 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
781 ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0;
782 AC_CRITICAL_SECTION_LEAVE();
783 }
784
hri_ac_get_WINCTRL_WEN0_bit(const void * const hw)785 static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw)
786 {
787 uint8_t tmp;
788 tmp = ((Ac *)hw)->WINCTRL.reg;
789 tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos;
790 return (bool)tmp;
791 }
792
hri_ac_write_WINCTRL_WEN0_bit(const void * const hw,bool value)793 static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value)
794 {
795 uint8_t tmp;
796 AC_CRITICAL_SECTION_ENTER();
797 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
798 tmp = ((Ac *)hw)->WINCTRL.reg;
799 tmp &= ~AC_WINCTRL_WEN0;
800 tmp |= value << AC_WINCTRL_WEN0_Pos;
801 ((Ac *)hw)->WINCTRL.reg = tmp;
802 AC_CRITICAL_SECTION_LEAVE();
803 }
804
hri_ac_clear_WINCTRL_WEN0_bit(const void * const hw)805 static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw)
806 {
807 AC_CRITICAL_SECTION_ENTER();
808 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
809 ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
810 AC_CRITICAL_SECTION_LEAVE();
811 }
812
hri_ac_toggle_WINCTRL_WEN0_bit(const void * const hw)813 static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw)
814 {
815 AC_CRITICAL_SECTION_ENTER();
816 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
817 ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0;
818 AC_CRITICAL_SECTION_LEAVE();
819 }
820
hri_ac_set_WINCTRL_WINTSEL0_bf(const void * const hw,hri_ac_winctrl_reg_t mask)821 static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
822 {
823 AC_CRITICAL_SECTION_ENTER();
824 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
825 ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask);
826 AC_CRITICAL_SECTION_LEAVE();
827 }
828
hri_ac_get_WINCTRL_WINTSEL0_bf(const void * const hw,hri_ac_winctrl_reg_t mask)829 static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
830 {
831 uint8_t tmp;
832 tmp = ((Ac *)hw)->WINCTRL.reg;
833 tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos;
834 return tmp;
835 }
836
hri_ac_write_WINCTRL_WINTSEL0_bf(const void * const hw,hri_ac_winctrl_reg_t data)837 static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data)
838 {
839 uint8_t tmp;
840 AC_CRITICAL_SECTION_ENTER();
841 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
842 tmp = ((Ac *)hw)->WINCTRL.reg;
843 tmp &= ~AC_WINCTRL_WINTSEL0_Msk;
844 tmp |= AC_WINCTRL_WINTSEL0(data);
845 ((Ac *)hw)->WINCTRL.reg = tmp;
846 AC_CRITICAL_SECTION_LEAVE();
847 }
848
hri_ac_clear_WINCTRL_WINTSEL0_bf(const void * const hw,hri_ac_winctrl_reg_t mask)849 static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
850 {
851 AC_CRITICAL_SECTION_ENTER();
852 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
853 ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask);
854 AC_CRITICAL_SECTION_LEAVE();
855 }
856
hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void * const hw,hri_ac_winctrl_reg_t mask)857 static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask)
858 {
859 AC_CRITICAL_SECTION_ENTER();
860 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
861 ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask);
862 AC_CRITICAL_SECTION_LEAVE();
863 }
864
hri_ac_read_WINCTRL_WINTSEL0_bf(const void * const hw)865 static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw)
866 {
867 uint8_t tmp;
868 tmp = ((Ac *)hw)->WINCTRL.reg;
869 tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos;
870 return tmp;
871 }
872
hri_ac_set_WINCTRL_reg(const void * const hw,hri_ac_winctrl_reg_t mask)873 static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
874 {
875 AC_CRITICAL_SECTION_ENTER();
876 ((Ac *)hw)->WINCTRL.reg |= mask;
877 AC_CRITICAL_SECTION_LEAVE();
878 }
879
hri_ac_get_WINCTRL_reg(const void * const hw,hri_ac_winctrl_reg_t mask)880 static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
881 {
882 uint8_t tmp;
883 tmp = ((Ac *)hw)->WINCTRL.reg;
884 tmp &= mask;
885 return tmp;
886 }
887
hri_ac_write_WINCTRL_reg(const void * const hw,hri_ac_winctrl_reg_t data)888 static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data)
889 {
890 AC_CRITICAL_SECTION_ENTER();
891 ((Ac *)hw)->WINCTRL.reg = data;
892 AC_CRITICAL_SECTION_LEAVE();
893 }
894
hri_ac_clear_WINCTRL_reg(const void * const hw,hri_ac_winctrl_reg_t mask)895 static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
896 {
897 AC_CRITICAL_SECTION_ENTER();
898 ((Ac *)hw)->WINCTRL.reg &= ~mask;
899 AC_CRITICAL_SECTION_LEAVE();
900 }
901
hri_ac_toggle_WINCTRL_reg(const void * const hw,hri_ac_winctrl_reg_t mask)902 static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask)
903 {
904 AC_CRITICAL_SECTION_ENTER();
905 ((Ac *)hw)->WINCTRL.reg ^= mask;
906 AC_CRITICAL_SECTION_LEAVE();
907 }
908
hri_ac_read_WINCTRL_reg(const void * const hw)909 static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw)
910 {
911 return ((Ac *)hw)->WINCTRL.reg;
912 }
913
hri_ac_set_SCALER_VALUE_bf(const void * const hw,uint8_t index,hri_ac_scaler_reg_t mask)914 static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
915 {
916 AC_CRITICAL_SECTION_ENTER();
917 ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask);
918 AC_CRITICAL_SECTION_LEAVE();
919 }
920
hri_ac_get_SCALER_VALUE_bf(const void * const hw,uint8_t index,hri_ac_scaler_reg_t mask)921 static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index,
922 hri_ac_scaler_reg_t mask)
923 {
924 uint8_t tmp;
925 tmp = ((Ac *)hw)->SCALER[index].reg;
926 tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos;
927 return tmp;
928 }
929
hri_ac_write_SCALER_VALUE_bf(const void * const hw,uint8_t index,hri_ac_scaler_reg_t data)930 static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
931 {
932 uint8_t tmp;
933 AC_CRITICAL_SECTION_ENTER();
934 tmp = ((Ac *)hw)->SCALER[index].reg;
935 tmp &= ~AC_SCALER_VALUE_Msk;
936 tmp |= AC_SCALER_VALUE(data);
937 ((Ac *)hw)->SCALER[index].reg = tmp;
938 AC_CRITICAL_SECTION_LEAVE();
939 }
940
hri_ac_clear_SCALER_VALUE_bf(const void * const hw,uint8_t index,hri_ac_scaler_reg_t mask)941 static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
942 {
943 AC_CRITICAL_SECTION_ENTER();
944 ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask);
945 AC_CRITICAL_SECTION_LEAVE();
946 }
947
hri_ac_toggle_SCALER_VALUE_bf(const void * const hw,uint8_t index,hri_ac_scaler_reg_t mask)948 static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
949 {
950 AC_CRITICAL_SECTION_ENTER();
951 ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask);
952 AC_CRITICAL_SECTION_LEAVE();
953 }
954
hri_ac_read_SCALER_VALUE_bf(const void * const hw,uint8_t index)955 static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index)
956 {
957 uint8_t tmp;
958 tmp = ((Ac *)hw)->SCALER[index].reg;
959 tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos;
960 return tmp;
961 }
962
hri_ac_set_SCALER_reg(const void * const hw,uint8_t index,hri_ac_scaler_reg_t mask)963 static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
964 {
965 AC_CRITICAL_SECTION_ENTER();
966 ((Ac *)hw)->SCALER[index].reg |= mask;
967 AC_CRITICAL_SECTION_LEAVE();
968 }
969
hri_ac_get_SCALER_reg(const void * const hw,uint8_t index,hri_ac_scaler_reg_t mask)970 static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
971 {
972 uint8_t tmp;
973 tmp = ((Ac *)hw)->SCALER[index].reg;
974 tmp &= mask;
975 return tmp;
976 }
977
hri_ac_write_SCALER_reg(const void * const hw,uint8_t index,hri_ac_scaler_reg_t data)978 static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data)
979 {
980 AC_CRITICAL_SECTION_ENTER();
981 ((Ac *)hw)->SCALER[index].reg = data;
982 AC_CRITICAL_SECTION_LEAVE();
983 }
984
hri_ac_clear_SCALER_reg(const void * const hw,uint8_t index,hri_ac_scaler_reg_t mask)985 static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
986 {
987 AC_CRITICAL_SECTION_ENTER();
988 ((Ac *)hw)->SCALER[index].reg &= ~mask;
989 AC_CRITICAL_SECTION_LEAVE();
990 }
991
hri_ac_toggle_SCALER_reg(const void * const hw,uint8_t index,hri_ac_scaler_reg_t mask)992 static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask)
993 {
994 AC_CRITICAL_SECTION_ENTER();
995 ((Ac *)hw)->SCALER[index].reg ^= mask;
996 AC_CRITICAL_SECTION_LEAVE();
997 }
998
hri_ac_read_SCALER_reg(const void * const hw,uint8_t index)999 static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index)
1000 {
1001 return ((Ac *)hw)->SCALER[index].reg;
1002 }
1003
hri_ac_set_COMPCTRL_ENABLE_bit(const void * const hw,uint8_t index)1004 static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
1005 {
1006 AC_CRITICAL_SECTION_ENTER();
1007 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
1008 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE;
1009 AC_CRITICAL_SECTION_LEAVE();
1010 }
1011
hri_ac_get_COMPCTRL_ENABLE_bit(const void * const hw,uint8_t index)1012 static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
1013 {
1014 uint32_t tmp;
1015 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
1016 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1017 tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos;
1018 return (bool)tmp;
1019 }
1020
hri_ac_write_COMPCTRL_ENABLE_bit(const void * const hw,uint8_t index,bool value)1021 static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value)
1022 {
1023 uint32_t tmp;
1024 AC_CRITICAL_SECTION_ENTER();
1025 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
1026 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1027 tmp &= ~AC_COMPCTRL_ENABLE;
1028 tmp |= value << AC_COMPCTRL_ENABLE_Pos;
1029 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1030 AC_CRITICAL_SECTION_LEAVE();
1031 }
1032
hri_ac_clear_COMPCTRL_ENABLE_bit(const void * const hw,uint8_t index)1033 static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
1034 {
1035 AC_CRITICAL_SECTION_ENTER();
1036 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
1037 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE;
1038 AC_CRITICAL_SECTION_LEAVE();
1039 }
1040
hri_ac_toggle_COMPCTRL_ENABLE_bit(const void * const hw,uint8_t index)1041 static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index)
1042 {
1043 AC_CRITICAL_SECTION_ENTER();
1044 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE);
1045 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE;
1046 AC_CRITICAL_SECTION_LEAVE();
1047 }
1048
hri_ac_set_COMPCTRL_SINGLE_bit(const void * const hw,uint8_t index)1049 static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
1050 {
1051 AC_CRITICAL_SECTION_ENTER();
1052 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1053 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE;
1054 AC_CRITICAL_SECTION_LEAVE();
1055 }
1056
hri_ac_get_COMPCTRL_SINGLE_bit(const void * const hw,uint8_t index)1057 static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
1058 {
1059 uint32_t tmp;
1060 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1061 tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos;
1062 return (bool)tmp;
1063 }
1064
hri_ac_write_COMPCTRL_SINGLE_bit(const void * const hw,uint8_t index,bool value)1065 static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value)
1066 {
1067 uint32_t tmp;
1068 AC_CRITICAL_SECTION_ENTER();
1069 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1070 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1071 tmp &= ~AC_COMPCTRL_SINGLE;
1072 tmp |= value << AC_COMPCTRL_SINGLE_Pos;
1073 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1074 AC_CRITICAL_SECTION_LEAVE();
1075 }
1076
hri_ac_clear_COMPCTRL_SINGLE_bit(const void * const hw,uint8_t index)1077 static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
1078 {
1079 AC_CRITICAL_SECTION_ENTER();
1080 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1081 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE;
1082 AC_CRITICAL_SECTION_LEAVE();
1083 }
1084
hri_ac_toggle_COMPCTRL_SINGLE_bit(const void * const hw,uint8_t index)1085 static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index)
1086 {
1087 AC_CRITICAL_SECTION_ENTER();
1088 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1089 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE;
1090 AC_CRITICAL_SECTION_LEAVE();
1091 }
1092
hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void * const hw,uint8_t index)1093 static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
1094 {
1095 AC_CRITICAL_SECTION_ENTER();
1096 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1097 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY;
1098 AC_CRITICAL_SECTION_LEAVE();
1099 }
1100
hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void * const hw,uint8_t index)1101 static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
1102 {
1103 uint32_t tmp;
1104 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1105 tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos;
1106 return (bool)tmp;
1107 }
1108
hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void * const hw,uint8_t index,bool value)1109 static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
1110 {
1111 uint32_t tmp;
1112 AC_CRITICAL_SECTION_ENTER();
1113 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1114 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1115 tmp &= ~AC_COMPCTRL_RUNSTDBY;
1116 tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos;
1117 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1118 AC_CRITICAL_SECTION_LEAVE();
1119 }
1120
hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void * const hw,uint8_t index)1121 static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
1122 {
1123 AC_CRITICAL_SECTION_ENTER();
1124 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1125 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY;
1126 AC_CRITICAL_SECTION_LEAVE();
1127 }
1128
hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void * const hw,uint8_t index)1129 static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
1130 {
1131 AC_CRITICAL_SECTION_ENTER();
1132 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1133 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY;
1134 AC_CRITICAL_SECTION_LEAVE();
1135 }
1136
hri_ac_set_COMPCTRL_SWAP_bit(const void * const hw,uint8_t index)1137 static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
1138 {
1139 AC_CRITICAL_SECTION_ENTER();
1140 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1141 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP;
1142 AC_CRITICAL_SECTION_LEAVE();
1143 }
1144
hri_ac_get_COMPCTRL_SWAP_bit(const void * const hw,uint8_t index)1145 static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
1146 {
1147 uint32_t tmp;
1148 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1149 tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos;
1150 return (bool)tmp;
1151 }
1152
hri_ac_write_COMPCTRL_SWAP_bit(const void * const hw,uint8_t index,bool value)1153 static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value)
1154 {
1155 uint32_t tmp;
1156 AC_CRITICAL_SECTION_ENTER();
1157 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1158 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1159 tmp &= ~AC_COMPCTRL_SWAP;
1160 tmp |= value << AC_COMPCTRL_SWAP_Pos;
1161 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1162 AC_CRITICAL_SECTION_LEAVE();
1163 }
1164
hri_ac_clear_COMPCTRL_SWAP_bit(const void * const hw,uint8_t index)1165 static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
1166 {
1167 AC_CRITICAL_SECTION_ENTER();
1168 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1169 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP;
1170 AC_CRITICAL_SECTION_LEAVE();
1171 }
1172
hri_ac_toggle_COMPCTRL_SWAP_bit(const void * const hw,uint8_t index)1173 static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index)
1174 {
1175 AC_CRITICAL_SECTION_ENTER();
1176 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1177 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP;
1178 AC_CRITICAL_SECTION_LEAVE();
1179 }
1180
hri_ac_set_COMPCTRL_HYSTEN_bit(const void * const hw,uint8_t index)1181 static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
1182 {
1183 AC_CRITICAL_SECTION_ENTER();
1184 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1185 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN;
1186 AC_CRITICAL_SECTION_LEAVE();
1187 }
1188
hri_ac_get_COMPCTRL_HYSTEN_bit(const void * const hw,uint8_t index)1189 static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
1190 {
1191 uint32_t tmp;
1192 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1193 tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos;
1194 return (bool)tmp;
1195 }
1196
hri_ac_write_COMPCTRL_HYSTEN_bit(const void * const hw,uint8_t index,bool value)1197 static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value)
1198 {
1199 uint32_t tmp;
1200 AC_CRITICAL_SECTION_ENTER();
1201 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1202 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1203 tmp &= ~AC_COMPCTRL_HYSTEN;
1204 tmp |= value << AC_COMPCTRL_HYSTEN_Pos;
1205 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1206 AC_CRITICAL_SECTION_LEAVE();
1207 }
1208
hri_ac_clear_COMPCTRL_HYSTEN_bit(const void * const hw,uint8_t index)1209 static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
1210 {
1211 AC_CRITICAL_SECTION_ENTER();
1212 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1213 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN;
1214 AC_CRITICAL_SECTION_LEAVE();
1215 }
1216
hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void * const hw,uint8_t index)1217 static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index)
1218 {
1219 AC_CRITICAL_SECTION_ENTER();
1220 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1221 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN;
1222 AC_CRITICAL_SECTION_LEAVE();
1223 }
1224
hri_ac_set_COMPCTRL_INTSEL_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1225 static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1226 {
1227 AC_CRITICAL_SECTION_ENTER();
1228 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1229 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask);
1230 AC_CRITICAL_SECTION_LEAVE();
1231 }
1232
hri_ac_get_COMPCTRL_INTSEL_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1233 static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index,
1234 hri_ac_compctrl_reg_t mask)
1235 {
1236 uint32_t tmp;
1237 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1238 tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos;
1239 return tmp;
1240 }
1241
hri_ac_write_COMPCTRL_INTSEL_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t data)1242 static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
1243 {
1244 uint32_t tmp;
1245 AC_CRITICAL_SECTION_ENTER();
1246 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1247 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1248 tmp &= ~AC_COMPCTRL_INTSEL_Msk;
1249 tmp |= AC_COMPCTRL_INTSEL(data);
1250 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1251 AC_CRITICAL_SECTION_LEAVE();
1252 }
1253
hri_ac_clear_COMPCTRL_INTSEL_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1254 static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1255 {
1256 AC_CRITICAL_SECTION_ENTER();
1257 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1258 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask);
1259 AC_CRITICAL_SECTION_LEAVE();
1260 }
1261
hri_ac_toggle_COMPCTRL_INTSEL_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1262 static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1263 {
1264 AC_CRITICAL_SECTION_ENTER();
1265 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1266 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask);
1267 AC_CRITICAL_SECTION_LEAVE();
1268 }
1269
hri_ac_read_COMPCTRL_INTSEL_bf(const void * const hw,uint8_t index)1270 static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index)
1271 {
1272 uint32_t tmp;
1273 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1274 tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos;
1275 return tmp;
1276 }
1277
hri_ac_set_COMPCTRL_MUXNEG_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1278 static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1279 {
1280 AC_CRITICAL_SECTION_ENTER();
1281 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1282 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask);
1283 AC_CRITICAL_SECTION_LEAVE();
1284 }
1285
hri_ac_get_COMPCTRL_MUXNEG_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1286 static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index,
1287 hri_ac_compctrl_reg_t mask)
1288 {
1289 uint32_t tmp;
1290 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1291 tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos;
1292 return tmp;
1293 }
1294
hri_ac_write_COMPCTRL_MUXNEG_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t data)1295 static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
1296 {
1297 uint32_t tmp;
1298 AC_CRITICAL_SECTION_ENTER();
1299 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1300 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1301 tmp &= ~AC_COMPCTRL_MUXNEG_Msk;
1302 tmp |= AC_COMPCTRL_MUXNEG(data);
1303 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1304 AC_CRITICAL_SECTION_LEAVE();
1305 }
1306
hri_ac_clear_COMPCTRL_MUXNEG_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1307 static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1308 {
1309 AC_CRITICAL_SECTION_ENTER();
1310 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1311 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask);
1312 AC_CRITICAL_SECTION_LEAVE();
1313 }
1314
hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1315 static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1316 {
1317 AC_CRITICAL_SECTION_ENTER();
1318 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1319 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask);
1320 AC_CRITICAL_SECTION_LEAVE();
1321 }
1322
hri_ac_read_COMPCTRL_MUXNEG_bf(const void * const hw,uint8_t index)1323 static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index)
1324 {
1325 uint32_t tmp;
1326 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1327 tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos;
1328 return tmp;
1329 }
1330
hri_ac_set_COMPCTRL_MUXPOS_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1331 static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1332 {
1333 AC_CRITICAL_SECTION_ENTER();
1334 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1335 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask);
1336 AC_CRITICAL_SECTION_LEAVE();
1337 }
1338
hri_ac_get_COMPCTRL_MUXPOS_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1339 static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index,
1340 hri_ac_compctrl_reg_t mask)
1341 {
1342 uint32_t tmp;
1343 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1344 tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos;
1345 return tmp;
1346 }
1347
hri_ac_write_COMPCTRL_MUXPOS_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t data)1348 static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
1349 {
1350 uint32_t tmp;
1351 AC_CRITICAL_SECTION_ENTER();
1352 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1353 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1354 tmp &= ~AC_COMPCTRL_MUXPOS_Msk;
1355 tmp |= AC_COMPCTRL_MUXPOS(data);
1356 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1357 AC_CRITICAL_SECTION_LEAVE();
1358 }
1359
hri_ac_clear_COMPCTRL_MUXPOS_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1360 static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1361 {
1362 AC_CRITICAL_SECTION_ENTER();
1363 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1364 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask);
1365 AC_CRITICAL_SECTION_LEAVE();
1366 }
1367
hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1368 static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1369 {
1370 AC_CRITICAL_SECTION_ENTER();
1371 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1372 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask);
1373 AC_CRITICAL_SECTION_LEAVE();
1374 }
1375
hri_ac_read_COMPCTRL_MUXPOS_bf(const void * const hw,uint8_t index)1376 static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index)
1377 {
1378 uint32_t tmp;
1379 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1380 tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos;
1381 return tmp;
1382 }
1383
hri_ac_set_COMPCTRL_SPEED_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1384 static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1385 {
1386 AC_CRITICAL_SECTION_ENTER();
1387 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1388 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask);
1389 AC_CRITICAL_SECTION_LEAVE();
1390 }
1391
hri_ac_get_COMPCTRL_SPEED_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1392 static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index,
1393 hri_ac_compctrl_reg_t mask)
1394 {
1395 uint32_t tmp;
1396 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1397 tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos;
1398 return tmp;
1399 }
1400
hri_ac_write_COMPCTRL_SPEED_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t data)1401 static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
1402 {
1403 uint32_t tmp;
1404 AC_CRITICAL_SECTION_ENTER();
1405 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1406 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1407 tmp &= ~AC_COMPCTRL_SPEED_Msk;
1408 tmp |= AC_COMPCTRL_SPEED(data);
1409 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1410 AC_CRITICAL_SECTION_LEAVE();
1411 }
1412
hri_ac_clear_COMPCTRL_SPEED_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1413 static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1414 {
1415 AC_CRITICAL_SECTION_ENTER();
1416 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1417 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask);
1418 AC_CRITICAL_SECTION_LEAVE();
1419 }
1420
hri_ac_toggle_COMPCTRL_SPEED_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1421 static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1422 {
1423 AC_CRITICAL_SECTION_ENTER();
1424 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1425 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask);
1426 AC_CRITICAL_SECTION_LEAVE();
1427 }
1428
hri_ac_read_COMPCTRL_SPEED_bf(const void * const hw,uint8_t index)1429 static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index)
1430 {
1431 uint32_t tmp;
1432 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1433 tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos;
1434 return tmp;
1435 }
1436
hri_ac_set_COMPCTRL_HYST_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1437 static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1438 {
1439 AC_CRITICAL_SECTION_ENTER();
1440 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1441 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask);
1442 AC_CRITICAL_SECTION_LEAVE();
1443 }
1444
hri_ac_get_COMPCTRL_HYST_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1445 static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index,
1446 hri_ac_compctrl_reg_t mask)
1447 {
1448 uint32_t tmp;
1449 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1450 tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos;
1451 return tmp;
1452 }
1453
hri_ac_write_COMPCTRL_HYST_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t data)1454 static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
1455 {
1456 uint32_t tmp;
1457 AC_CRITICAL_SECTION_ENTER();
1458 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1459 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1460 tmp &= ~AC_COMPCTRL_HYST_Msk;
1461 tmp |= AC_COMPCTRL_HYST(data);
1462 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1463 AC_CRITICAL_SECTION_LEAVE();
1464 }
1465
hri_ac_clear_COMPCTRL_HYST_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1466 static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1467 {
1468 AC_CRITICAL_SECTION_ENTER();
1469 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1470 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask);
1471 AC_CRITICAL_SECTION_LEAVE();
1472 }
1473
hri_ac_toggle_COMPCTRL_HYST_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1474 static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1475 {
1476 AC_CRITICAL_SECTION_ENTER();
1477 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1478 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask);
1479 AC_CRITICAL_SECTION_LEAVE();
1480 }
1481
hri_ac_read_COMPCTRL_HYST_bf(const void * const hw,uint8_t index)1482 static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index)
1483 {
1484 uint32_t tmp;
1485 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1486 tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos;
1487 return tmp;
1488 }
1489
hri_ac_set_COMPCTRL_FLEN_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1490 static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1491 {
1492 AC_CRITICAL_SECTION_ENTER();
1493 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1494 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask);
1495 AC_CRITICAL_SECTION_LEAVE();
1496 }
1497
hri_ac_get_COMPCTRL_FLEN_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1498 static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index,
1499 hri_ac_compctrl_reg_t mask)
1500 {
1501 uint32_t tmp;
1502 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1503 tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos;
1504 return tmp;
1505 }
1506
hri_ac_write_COMPCTRL_FLEN_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t data)1507 static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
1508 {
1509 uint32_t tmp;
1510 AC_CRITICAL_SECTION_ENTER();
1511 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1512 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1513 tmp &= ~AC_COMPCTRL_FLEN_Msk;
1514 tmp |= AC_COMPCTRL_FLEN(data);
1515 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1516 AC_CRITICAL_SECTION_LEAVE();
1517 }
1518
hri_ac_clear_COMPCTRL_FLEN_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1519 static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1520 {
1521 AC_CRITICAL_SECTION_ENTER();
1522 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1523 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask);
1524 AC_CRITICAL_SECTION_LEAVE();
1525 }
1526
hri_ac_toggle_COMPCTRL_FLEN_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1527 static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1528 {
1529 AC_CRITICAL_SECTION_ENTER();
1530 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1531 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask);
1532 AC_CRITICAL_SECTION_LEAVE();
1533 }
1534
hri_ac_read_COMPCTRL_FLEN_bf(const void * const hw,uint8_t index)1535 static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index)
1536 {
1537 uint32_t tmp;
1538 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1539 tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos;
1540 return tmp;
1541 }
1542
hri_ac_set_COMPCTRL_OUT_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1543 static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1544 {
1545 AC_CRITICAL_SECTION_ENTER();
1546 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1547 ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask);
1548 AC_CRITICAL_SECTION_LEAVE();
1549 }
1550
hri_ac_get_COMPCTRL_OUT_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1551 static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index,
1552 hri_ac_compctrl_reg_t mask)
1553 {
1554 uint32_t tmp;
1555 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1556 tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos;
1557 return tmp;
1558 }
1559
hri_ac_write_COMPCTRL_OUT_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t data)1560 static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
1561 {
1562 uint32_t tmp;
1563 AC_CRITICAL_SECTION_ENTER();
1564 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1565 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1566 tmp &= ~AC_COMPCTRL_OUT_Msk;
1567 tmp |= AC_COMPCTRL_OUT(data);
1568 ((Ac *)hw)->COMPCTRL[index].reg = tmp;
1569 AC_CRITICAL_SECTION_LEAVE();
1570 }
1571
hri_ac_clear_COMPCTRL_OUT_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1572 static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1573 {
1574 AC_CRITICAL_SECTION_ENTER();
1575 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1576 ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask);
1577 AC_CRITICAL_SECTION_LEAVE();
1578 }
1579
hri_ac_toggle_COMPCTRL_OUT_bf(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1580 static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1581 {
1582 AC_CRITICAL_SECTION_ENTER();
1583 hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK);
1584 ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask);
1585 AC_CRITICAL_SECTION_LEAVE();
1586 }
1587
hri_ac_read_COMPCTRL_OUT_bf(const void * const hw,uint8_t index)1588 static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index)
1589 {
1590 uint32_t tmp;
1591 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1592 tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos;
1593 return tmp;
1594 }
1595
hri_ac_set_COMPCTRL_reg(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1596 static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1597 {
1598 AC_CRITICAL_SECTION_ENTER();
1599 ((Ac *)hw)->COMPCTRL[index].reg |= mask;
1600 AC_CRITICAL_SECTION_LEAVE();
1601 }
1602
hri_ac_get_COMPCTRL_reg(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1603 static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index,
1604 hri_ac_compctrl_reg_t mask)
1605 {
1606 uint32_t tmp;
1607 tmp = ((Ac *)hw)->COMPCTRL[index].reg;
1608 tmp &= mask;
1609 return tmp;
1610 }
1611
hri_ac_write_COMPCTRL_reg(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t data)1612 static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data)
1613 {
1614 AC_CRITICAL_SECTION_ENTER();
1615 ((Ac *)hw)->COMPCTRL[index].reg = data;
1616 AC_CRITICAL_SECTION_LEAVE();
1617 }
1618
hri_ac_clear_COMPCTRL_reg(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1619 static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1620 {
1621 AC_CRITICAL_SECTION_ENTER();
1622 ((Ac *)hw)->COMPCTRL[index].reg &= ~mask;
1623 AC_CRITICAL_SECTION_LEAVE();
1624 }
1625
hri_ac_toggle_COMPCTRL_reg(const void * const hw,uint8_t index,hri_ac_compctrl_reg_t mask)1626 static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask)
1627 {
1628 AC_CRITICAL_SECTION_ENTER();
1629 ((Ac *)hw)->COMPCTRL[index].reg ^= mask;
1630 AC_CRITICAL_SECTION_LEAVE();
1631 }
1632
hri_ac_read_COMPCTRL_reg(const void * const hw,uint8_t index)1633 static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index)
1634 {
1635 return ((Ac *)hw)->COMPCTRL[index].reg;
1636 }
1637
hri_ac_get_STATUSA_STATE0_bit(const void * const hw)1638 static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw)
1639 {
1640 return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos;
1641 }
1642
hri_ac_get_STATUSA_STATE1_bit(const void * const hw)1643 static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw)
1644 {
1645 return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos;
1646 }
1647
hri_ac_get_STATUSA_WSTATE0_bf(const void * const hw,hri_ac_statusa_reg_t mask)1648 static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask)
1649 {
1650 return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos;
1651 }
1652
hri_ac_read_STATUSA_WSTATE0_bf(const void * const hw)1653 static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw)
1654 {
1655 return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos;
1656 }
1657
hri_ac_get_STATUSA_reg(const void * const hw,hri_ac_statusa_reg_t mask)1658 static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask)
1659 {
1660 uint8_t tmp;
1661 tmp = ((Ac *)hw)->STATUSA.reg;
1662 tmp &= mask;
1663 return tmp;
1664 }
1665
hri_ac_read_STATUSA_reg(const void * const hw)1666 static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw)
1667 {
1668 return ((Ac *)hw)->STATUSA.reg;
1669 }
1670
hri_ac_get_STATUSB_READY0_bit(const void * const hw)1671 static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw)
1672 {
1673 return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos;
1674 }
1675
hri_ac_get_STATUSB_READY1_bit(const void * const hw)1676 static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw)
1677 {
1678 return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos;
1679 }
1680
hri_ac_get_STATUSB_reg(const void * const hw,hri_ac_statusb_reg_t mask)1681 static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask)
1682 {
1683 uint8_t tmp;
1684 tmp = ((Ac *)hw)->STATUSB.reg;
1685 tmp &= mask;
1686 return tmp;
1687 }
1688
hri_ac_read_STATUSB_reg(const void * const hw)1689 static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw)
1690 {
1691 return ((Ac *)hw)->STATUSB.reg;
1692 }
1693
hri_ac_get_SYNCBUSY_SWRST_bit(const void * const hw)1694 static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw)
1695 {
1696 return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos;
1697 }
1698
hri_ac_get_SYNCBUSY_ENABLE_bit(const void * const hw)1699 static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw)
1700 {
1701 return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos;
1702 }
1703
hri_ac_get_SYNCBUSY_WINCTRL_bit(const void * const hw)1704 static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw)
1705 {
1706 return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos;
1707 }
1708
hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void * const hw)1709 static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw)
1710 {
1711 return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos;
1712 }
1713
hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void * const hw)1714 static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw)
1715 {
1716 return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos;
1717 }
1718
hri_ac_get_SYNCBUSY_reg(const void * const hw,hri_ac_syncbusy_reg_t mask)1719 static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask)
1720 {
1721 uint32_t tmp;
1722 tmp = ((Ac *)hw)->SYNCBUSY.reg;
1723 tmp &= mask;
1724 return tmp;
1725 }
1726
hri_ac_read_SYNCBUSY_reg(const void * const hw)1727 static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw)
1728 {
1729 return ((Ac *)hw)->SYNCBUSY.reg;
1730 }
1731
1732 #ifdef __cplusplus
1733 }
1734 #endif
1735
1736 #endif /* _HRI_AC_L21_H_INCLUDED */
1737 #endif /* _SAML21_AC_COMPONENT_ */
1738
