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Searched refs:Timing (Results 1 – 25 of 30) sorted by relevance

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/loramac-node-latest/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_ll_fmc.c373 …_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
379 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
380 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
382 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Timing_Init()
384 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
385 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
386 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
387 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
388 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
392 …MODIFY_REG(Device->BTCR[Bank + 1], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
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Dstm32l4xx_ll_i2c.c191 LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing); in LL_I2C_Init()
235 I2C_InitStruct->Timing = 0U; in LL_I2C_StructInit()
Dstm32l4xx_hal_sram.c141 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_N… in HAL_SRAM_Init() argument
161 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
Dstm32l4xx_hal_nor.c180 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORS… in HAL_NOR_Init() argument
200 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
Dstm32l4xx_hal_dsi.c2341 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState S… in HAL_DSI_SetPHYTimings() argument
2347 assert_param(IS_DSI_PHY_TIMING(Timing)); in HAL_DSI_SetPHYTimings()
2350 switch(Timing) in HAL_DSI_SetPHYTimings()
/loramac-node-latest/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_ll_fsmc.c289 …ORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FSMC_NORSRAM_Timing_Init() argument
293 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FSMC_NORSRAM_Timing_Init()
294 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FSMC_NORSRAM_Timing_Init()
295 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); in FSMC_NORSRAM_Timing_Init()
296 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FSMC_NORSRAM_Timing_Init()
297 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); in FSMC_NORSRAM_Timing_Init()
298 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); in FSMC_NORSRAM_Timing_Init()
299 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); in FSMC_NORSRAM_Timing_Init()
305 (uint32_t)(Timing->AddressSetupTime | \ in FSMC_NORSRAM_Timing_Init()
306 … ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) | \ in FSMC_NORSRAM_Timing_Init()
[all …]
Dstm32l1xx_hal_sram.c140 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC… in HAL_SRAM_Init() argument
161 FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
Dstm32l1xx_hal_nor.c187 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NO… in HAL_NOR_Init() argument
208 FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); in HAL_NOR_Init()
/loramac-node-latest/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_dsi.h1178 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState S…
1298 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ argument
1299 ((Timing) == DSI_TLPX_CLK ) || \
1300 ((Timing) == DSI_THS_EXIT ) || \
1301 ((Timing) == DSI_TLPX_DATA ) || \
1302 ((Timing) == DSI_THS_ZERO ) || \
1303 ((Timing) == DSI_THS_TRAIL ) || \
1304 ((Timing) == DSI_THS_PREPARE ) || \
1305 ((Timing) == DSI_TCLK_ZERO ) || \
1306 ((Timing) == DSI_TCLK_PREPARE))
Dstm32l4xx_ll_fmc.h790 …NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
791 …ng_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, ui…
818 …mmonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
819 …buteSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Dstm32l4xx_hal_sram.h122 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_N…
Dstm32l4xx_hal_nor.h164 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORS…
Dstm32l4xx_ll_i2c.h90 …uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period… member
898 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) in LL_I2C_SetTiming() argument
900 WRITE_REG(I2Cx->TIMINGR, Timing); in LL_I2C_SetTiming()
Dstm32l4xx_hal_smbus.h66 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. member
Dstm32l4xx_hal_i2c.h66 uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. member
/loramac-node-latest/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_ll_i2c.c183 LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing); in LL_I2C_Init()
227 I2C_InitStruct->Timing = 0U; in LL_I2C_StructInit()
/loramac-node-latest/src/boards/NucleoL073/
Di2c-board.c58 I2cHandle.Init.Timing = 0x00707CBB; in I2cMcuFormat()
62 I2cHandle.Init.Timing = 0x00300F38; in I2cMcuFormat()
/loramac-node-latest/src/boards/NucleoL476/
Di2c-board.c58 I2cHandle.Init.Timing = 0x10909CEC; in I2cMcuFormat()
62 I2cHandle.Init.Timing = 0x00702991; in I2cMcuFormat()
/loramac-node-latest/src/boards/B-L072Z-LRWAN1/
Di2c-board.c58 I2cHandle.Init.Timing = 0x00707CBB; in I2cMcuFormat()
62 I2cHandle.Init.Timing = 0x00300F38; in I2cMcuFormat()
/loramac-node-latest/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_fsmc.h533 …RSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
534 …_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, ui…
Dstm32l1xx_hal_sram.h126 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC…
Dstm32l1xx_hal_nor.h228 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NO…
/loramac-node-latest/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_i2c.h90 …uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period… member
898 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) in LL_I2C_SetTiming() argument
900 WRITE_REG(I2Cx->TIMINGR, Timing); in LL_I2C_SetTiming()
Dstm32l0xx_hal_smbus.h66 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. member
Dstm32l0xx_hal_i2c.h66 uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. member

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