1 /** 2 * \file 3 * 4 * \brief Component description for TAL 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_TAL_COMPONENT_ 30 #define _SAML21_TAL_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR TAL */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_TAL Trigger Allocator */ 36 /*@{*/ 37 38 #define TAL_U2253 39 #define REV_TAL 0x102 40 41 /* -------- TAL_CTRLA : (TAL Offset: 0x00) (R/W 8) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint8_t reg; /*!< Type used for register access */ 50 } TAL_CTRLA_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define TAL_CTRLA_OFFSET 0x00 /**< \brief (TAL_CTRLA offset) Control A */ 54 #define TAL_CTRLA_RESETVALUE _U(0x00) /**< \brief (TAL_CTRLA reset_value) Control A */ 55 56 #define TAL_CTRLA_SWRST_Pos 0 /**< \brief (TAL_CTRLA) Software Reset */ 57 #define TAL_CTRLA_SWRST (_U(0x1) << TAL_CTRLA_SWRST_Pos) 58 #define TAL_CTRLA_ENABLE_Pos 1 /**< \brief (TAL_CTRLA) Enable */ 59 #define TAL_CTRLA_ENABLE (_U(0x1) << TAL_CTRLA_ENABLE_Pos) 60 #define TAL_CTRLA_MASK _U(0x03) /**< \brief (TAL_CTRLA) MASK Register */ 61 62 /* -------- TAL_RSTCTRL : (TAL Offset: 0x04) (R/W 8) Reset Control -------- */ 63 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 64 typedef union { 65 uint8_t reg; /*!< Type used for register access */ 66 } TAL_RSTCTRL_Type; 67 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 68 69 #define TAL_RSTCTRL_OFFSET 0x04 /**< \brief (TAL_RSTCTRL offset) Reset Control */ 70 #define TAL_RSTCTRL_RESETVALUE _U(0x00) /**< \brief (TAL_RSTCTRL reset_value) Reset Control */ 71 #define TAL_RSTCTRL_MASK _U(0x00) /**< \brief (TAL_RSTCTRL) MASK Register */ 72 73 /* -------- TAL_EXTCTRL : (TAL Offset: 0x05) (R/W 8) External Break Control -------- */ 74 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 75 typedef union { 76 struct { 77 uint8_t ENABLE:1; /*!< bit: 0 Enable BRK Pin */ 78 uint8_t INV:1; /*!< bit: 1 Invert BRK Pin */ 79 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 80 } bit; /*!< Structure used for bit access */ 81 uint8_t reg; /*!< Type used for register access */ 82 } TAL_EXTCTRL_Type; 83 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 84 85 #define TAL_EXTCTRL_OFFSET 0x05 /**< \brief (TAL_EXTCTRL offset) External Break Control */ 86 #define TAL_EXTCTRL_RESETVALUE _U(0x00) /**< \brief (TAL_EXTCTRL reset_value) External Break Control */ 87 88 #define TAL_EXTCTRL_ENABLE_Pos 0 /**< \brief (TAL_EXTCTRL) Enable BRK Pin */ 89 #define TAL_EXTCTRL_ENABLE (_U(0x1) << TAL_EXTCTRL_ENABLE_Pos) 90 #define TAL_EXTCTRL_INV_Pos 1 /**< \brief (TAL_EXTCTRL) Invert BRK Pin */ 91 #define TAL_EXTCTRL_INV (_U(0x1) << TAL_EXTCTRL_INV_Pos) 92 #define TAL_EXTCTRL_MASK _U(0x03) /**< \brief (TAL_EXTCTRL) MASK Register */ 93 94 /* -------- TAL_EVCTRL : (TAL Offset: 0x06) (R/W 8) Event Control -------- */ 95 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 96 typedef union { 97 struct { 98 uint8_t BRKEI:1; /*!< bit: 0 Break Input Event Enable */ 99 uint8_t BRKEO:1; /*!< bit: 1 Break Output Event Enable */ 100 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 101 } bit; /*!< Structure used for bit access */ 102 uint8_t reg; /*!< Type used for register access */ 103 } TAL_EVCTRL_Type; 104 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 105 106 #define TAL_EVCTRL_OFFSET 0x06 /**< \brief (TAL_EVCTRL offset) Event Control */ 107 #define TAL_EVCTRL_RESETVALUE _U(0x00) /**< \brief (TAL_EVCTRL reset_value) Event Control */ 108 109 #define TAL_EVCTRL_BRKEI_Pos 0 /**< \brief (TAL_EVCTRL) Break Input Event Enable */ 110 #define TAL_EVCTRL_BRKEI (_U(0x1) << TAL_EVCTRL_BRKEI_Pos) 111 #define TAL_EVCTRL_BRKEO_Pos 1 /**< \brief (TAL_EVCTRL) Break Output Event Enable */ 112 #define TAL_EVCTRL_BRKEO (_U(0x1) << TAL_EVCTRL_BRKEO_Pos) 113 #define TAL_EVCTRL_MASK _U(0x03) /**< \brief (TAL_EVCTRL) MASK Register */ 114 115 /* -------- TAL_INTENCLR : (TAL Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ 116 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 117 typedef union { 118 struct { 119 uint8_t BRK:1; /*!< bit: 0 Break Interrupt Enable */ 120 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 121 } bit; /*!< Structure used for bit access */ 122 uint8_t reg; /*!< Type used for register access */ 123 } TAL_INTENCLR_Type; 124 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 125 126 #define TAL_INTENCLR_OFFSET 0x08 /**< \brief (TAL_INTENCLR offset) Interrupt Enable Clear */ 127 #define TAL_INTENCLR_RESETVALUE _U(0x00) /**< \brief (TAL_INTENCLR reset_value) Interrupt Enable Clear */ 128 129 #define TAL_INTENCLR_BRK_Pos 0 /**< \brief (TAL_INTENCLR) Break Interrupt Enable */ 130 #define TAL_INTENCLR_BRK (_U(0x1) << TAL_INTENCLR_BRK_Pos) 131 #define TAL_INTENCLR_MASK _U(0x01) /**< \brief (TAL_INTENCLR) MASK Register */ 132 133 /* -------- TAL_INTENSET : (TAL Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ 134 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 135 typedef union { 136 struct { 137 uint8_t BRK:1; /*!< bit: 0 Break Interrupt Enable */ 138 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 139 } bit; /*!< Structure used for bit access */ 140 uint8_t reg; /*!< Type used for register access */ 141 } TAL_INTENSET_Type; 142 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 143 144 #define TAL_INTENSET_OFFSET 0x09 /**< \brief (TAL_INTENSET offset) Interrupt Enable Set */ 145 #define TAL_INTENSET_RESETVALUE _U(0x00) /**< \brief (TAL_INTENSET reset_value) Interrupt Enable Set */ 146 147 #define TAL_INTENSET_BRK_Pos 0 /**< \brief (TAL_INTENSET) Break Interrupt Enable */ 148 #define TAL_INTENSET_BRK (_U(0x1) << TAL_INTENSET_BRK_Pos) 149 #define TAL_INTENSET_MASK _U(0x01) /**< \brief (TAL_INTENSET) MASK Register */ 150 151 /* -------- TAL_INTFLAG : (TAL Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ 152 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 153 typedef union { // __I to avoid read-modify-write on write-to-clear register 154 struct { 155 __I uint8_t BRK:1; /*!< bit: 0 Break */ 156 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 157 } bit; /*!< Structure used for bit access */ 158 uint8_t reg; /*!< Type used for register access */ 159 } TAL_INTFLAG_Type; 160 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 161 162 #define TAL_INTFLAG_OFFSET 0x0A /**< \brief (TAL_INTFLAG offset) Interrupt Flag Status and Clear */ 163 #define TAL_INTFLAG_RESETVALUE _U(0x00) /**< \brief (TAL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 164 165 #define TAL_INTFLAG_BRK_Pos 0 /**< \brief (TAL_INTFLAG) Break */ 166 #define TAL_INTFLAG_BRK (_U(0x1) << TAL_INTFLAG_BRK_Pos) 167 #define TAL_INTFLAG_MASK _U(0x01) /**< \brief (TAL_INTFLAG) MASK Register */ 168 169 /* -------- TAL_GLOBMASK : (TAL Offset: 0x0B) (R/W 8) Global Break Requests Mask -------- */ 170 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 171 typedef union { 172 struct { 173 uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ 174 uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ 175 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 176 uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ 177 uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ 178 } bit; /*!< Structure used for bit access */ 179 uint8_t reg; /*!< Type used for register access */ 180 } TAL_GLOBMASK_Type; 181 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 182 183 #define TAL_GLOBMASK_OFFSET 0x0B /**< \brief (TAL_GLOBMASK offset) Global Break Requests Mask */ 184 #define TAL_GLOBMASK_RESETVALUE _U(0x00) /**< \brief (TAL_GLOBMASK reset_value) Global Break Requests Mask */ 185 186 #define TAL_GLOBMASK_CM0P_Pos 0 /**< \brief (TAL_GLOBMASK) CM0P Break Master */ 187 #define TAL_GLOBMASK_CM0P (_U(0x1) << TAL_GLOBMASK_CM0P_Pos) 188 #define TAL_GLOBMASK_PPP_Pos 1 /**< \brief (TAL_GLOBMASK) PPP Break Master */ 189 #define TAL_GLOBMASK_PPP (_U(0x1) << TAL_GLOBMASK_PPP_Pos) 190 #define TAL_GLOBMASK_EVBRK_Pos 6 /**< \brief (TAL_GLOBMASK) Event Break Master */ 191 #define TAL_GLOBMASK_EVBRK (_U(0x1) << TAL_GLOBMASK_EVBRK_Pos) 192 #define TAL_GLOBMASK_EXTBRK_Pos 7 /**< \brief (TAL_GLOBMASK) External Break Master */ 193 #define TAL_GLOBMASK_EXTBRK (_U(0x1) << TAL_GLOBMASK_EXTBRK_Pos) 194 #define TAL_GLOBMASK_MASK _U(0xC3) /**< \brief (TAL_GLOBMASK) MASK Register */ 195 196 /* -------- TAL_HALT : (TAL Offset: 0x0C) ( /W 8) Debug Halt Request -------- */ 197 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 198 typedef union { 199 struct { 200 uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ 201 uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ 202 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 203 uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ 204 uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ 205 } bit; /*!< Structure used for bit access */ 206 uint8_t reg; /*!< Type used for register access */ 207 } TAL_HALT_Type; 208 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 209 210 #define TAL_HALT_OFFSET 0x0C /**< \brief (TAL_HALT offset) Debug Halt Request */ 211 #define TAL_HALT_RESETVALUE _U(0x00) /**< \brief (TAL_HALT reset_value) Debug Halt Request */ 212 213 #define TAL_HALT_CM0P_Pos 0 /**< \brief (TAL_HALT) CM0P Break Master */ 214 #define TAL_HALT_CM0P (_U(0x1) << TAL_HALT_CM0P_Pos) 215 #define TAL_HALT_PPP_Pos 1 /**< \brief (TAL_HALT) PPP Break Master */ 216 #define TAL_HALT_PPP (_U(0x1) << TAL_HALT_PPP_Pos) 217 #define TAL_HALT_EVBRK_Pos 6 /**< \brief (TAL_HALT) Event Break Master */ 218 #define TAL_HALT_EVBRK (_U(0x1) << TAL_HALT_EVBRK_Pos) 219 #define TAL_HALT_EXTBRK_Pos 7 /**< \brief (TAL_HALT) External Break Master */ 220 #define TAL_HALT_EXTBRK (_U(0x1) << TAL_HALT_EXTBRK_Pos) 221 #define TAL_HALT_MASK _U(0xC3) /**< \brief (TAL_HALT) MASK Register */ 222 223 /* -------- TAL_RESTART : (TAL Offset: 0x0D) ( /W 8) Debug Restart Request -------- */ 224 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 225 typedef union { 226 struct { 227 uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ 228 uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ 229 uint8_t :5; /*!< bit: 2.. 6 Reserved */ 230 uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ 231 } bit; /*!< Structure used for bit access */ 232 uint8_t reg; /*!< Type used for register access */ 233 } TAL_RESTART_Type; 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 235 236 #define TAL_RESTART_OFFSET 0x0D /**< \brief (TAL_RESTART offset) Debug Restart Request */ 237 #define TAL_RESTART_RESETVALUE _U(0x00) /**< \brief (TAL_RESTART reset_value) Debug Restart Request */ 238 239 #define TAL_RESTART_CM0P_Pos 0 /**< \brief (TAL_RESTART) CM0P Break Master */ 240 #define TAL_RESTART_CM0P (_U(0x1) << TAL_RESTART_CM0P_Pos) 241 #define TAL_RESTART_PPP_Pos 1 /**< \brief (TAL_RESTART) PPP Break Master */ 242 #define TAL_RESTART_PPP (_U(0x1) << TAL_RESTART_PPP_Pos) 243 #define TAL_RESTART_EXTBRK_Pos 7 /**< \brief (TAL_RESTART) External Break Master */ 244 #define TAL_RESTART_EXTBRK (_U(0x1) << TAL_RESTART_EXTBRK_Pos) 245 #define TAL_RESTART_MASK _U(0x83) /**< \brief (TAL_RESTART) MASK Register */ 246 247 /* -------- TAL_BRKSTATUS : (TAL Offset: 0x0E) (R/ 16) Break Request Status -------- */ 248 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 249 typedef union { 250 struct { 251 uint16_t CM0P:2; /*!< bit: 0.. 1 CM0P Break Request */ 252 uint16_t PPP:2; /*!< bit: 2.. 3 PPP Break Request */ 253 uint16_t :8; /*!< bit: 4..11 Reserved */ 254 uint16_t EVBRK:2; /*!< bit: 12..13 Event Break Request */ 255 uint16_t EXTBRK:2; /*!< bit: 14..15 External Break Request */ 256 } bit; /*!< Structure used for bit access */ 257 uint16_t reg; /*!< Type used for register access */ 258 } TAL_BRKSTATUS_Type; 259 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 260 261 #define TAL_BRKSTATUS_OFFSET 0x0E /**< \brief (TAL_BRKSTATUS offset) Break Request Status */ 262 #define TAL_BRKSTATUS_RESETVALUE _U(0x0000) /**< \brief (TAL_BRKSTATUS reset_value) Break Request Status */ 263 264 #define TAL_BRKSTATUS_CM0P_Pos 0 /**< \brief (TAL_BRKSTATUS) CM0P Break Request */ 265 #define TAL_BRKSTATUS_CM0P_Msk (_U(0x3) << TAL_BRKSTATUS_CM0P_Pos) 266 #define TAL_BRKSTATUS_CM0P(value) (TAL_BRKSTATUS_CM0P_Msk & ((value) << TAL_BRKSTATUS_CM0P_Pos)) 267 #define TAL_BRKSTATUS_PPP_Pos 2 /**< \brief (TAL_BRKSTATUS) PPP Break Request */ 268 #define TAL_BRKSTATUS_PPP_Msk (_U(0x3) << TAL_BRKSTATUS_PPP_Pos) 269 #define TAL_BRKSTATUS_PPP(value) (TAL_BRKSTATUS_PPP_Msk & ((value) << TAL_BRKSTATUS_PPP_Pos)) 270 #define TAL_BRKSTATUS_EVBRK_Pos 12 /**< \brief (TAL_BRKSTATUS) Event Break Request */ 271 #define TAL_BRKSTATUS_EVBRK_Msk (_U(0x3) << TAL_BRKSTATUS_EVBRK_Pos) 272 #define TAL_BRKSTATUS_EVBRK(value) (TAL_BRKSTATUS_EVBRK_Msk & ((value) << TAL_BRKSTATUS_EVBRK_Pos)) 273 #define TAL_BRKSTATUS_EXTBRK_Pos 14 /**< \brief (TAL_BRKSTATUS) External Break Request */ 274 #define TAL_BRKSTATUS_EXTBRK_Msk (_U(0x3) << TAL_BRKSTATUS_EXTBRK_Pos) 275 #define TAL_BRKSTATUS_EXTBRK(value) (TAL_BRKSTATUS_EXTBRK_Msk & ((value) << TAL_BRKSTATUS_EXTBRK_Pos)) 276 #define TAL_BRKSTATUS_MASK _U(0xF00F) /**< \brief (TAL_BRKSTATUS) MASK Register */ 277 278 /* -------- TAL_CTICTRLA : (TAL Offset: 0x10) (R/W 8) CTIS Cross-Trigger Interface n Control A -------- */ 279 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 280 typedef union { 281 struct { 282 uint8_t ACTION:2; /*!< bit: 0.. 1 Action when global break issued */ 283 uint8_t RESTART:1; /*!< bit: 2 Action when global restart issued */ 284 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 285 } bit; /*!< Structure used for bit access */ 286 uint8_t reg; /*!< Type used for register access */ 287 } TAL_CTICTRLA_Type; 288 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 289 290 #define TAL_CTICTRLA_OFFSET 0x10 /**< \brief (TAL_CTICTRLA offset) Cross-Trigger Interface n Control A */ 291 #define TAL_CTICTRLA_RESETVALUE _U(0x00) /**< \brief (TAL_CTICTRLA reset_value) Cross-Trigger Interface n Control A */ 292 293 #define TAL_CTICTRLA_ACTION_Pos 0 /**< \brief (TAL_CTICTRLA) Action when global break issued */ 294 #define TAL_CTICTRLA_ACTION_Msk (_U(0x3) << TAL_CTICTRLA_ACTION_Pos) 295 #define TAL_CTICTRLA_ACTION(value) (TAL_CTICTRLA_ACTION_Msk & ((value) << TAL_CTICTRLA_ACTION_Pos)) 296 #define TAL_CTICTRLA_ACTION_BREAK_Val _U(0x0) /**< \brief (TAL_CTICTRLA) Break when requested */ 297 #define TAL_CTICTRLA_ACTION_INTERRUPT_Val _U(0x1) /**< \brief (TAL_CTICTRLA) Trigger DBG interrupt instead of break */ 298 #define TAL_CTICTRLA_ACTION_IGNORE_Val _U(0x2) /**< \brief (TAL_CTICTRLA) Ignore break request */ 299 #define TAL_CTICTRLA_ACTION_BREAK (TAL_CTICTRLA_ACTION_BREAK_Val << TAL_CTICTRLA_ACTION_Pos) 300 #define TAL_CTICTRLA_ACTION_INTERRUPT (TAL_CTICTRLA_ACTION_INTERRUPT_Val << TAL_CTICTRLA_ACTION_Pos) 301 #define TAL_CTICTRLA_ACTION_IGNORE (TAL_CTICTRLA_ACTION_IGNORE_Val << TAL_CTICTRLA_ACTION_Pos) 302 #define TAL_CTICTRLA_RESTART_Pos 2 /**< \brief (TAL_CTICTRLA) Action when global restart issued */ 303 #define TAL_CTICTRLA_RESTART (_U(0x1) << TAL_CTICTRLA_RESTART_Pos) 304 #define TAL_CTICTRLA_MASK _U(0x07) /**< \brief (TAL_CTICTRLA) MASK Register */ 305 306 /* -------- TAL_CTIMASK : (TAL Offset: 0x11) (R/W 8) CTIS Cross-Trigger Interface n Mask -------- */ 307 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 308 typedef union { 309 struct { 310 uint8_t CM0P:1; /*!< bit: 0 CM0P Break Master */ 311 uint8_t PPP:1; /*!< bit: 1 PPP Break Master */ 312 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 313 uint8_t EVBRK:1; /*!< bit: 6 Event Break Master */ 314 uint8_t EXTBRK:1; /*!< bit: 7 External Break Master */ 315 } bit; /*!< Structure used for bit access */ 316 uint8_t reg; /*!< Type used for register access */ 317 } TAL_CTIMASK_Type; 318 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 319 320 #define TAL_CTIMASK_OFFSET 0x11 /**< \brief (TAL_CTIMASK offset) Cross-Trigger Interface n Mask */ 321 #define TAL_CTIMASK_RESETVALUE _U(0x00) /**< \brief (TAL_CTIMASK reset_value) Cross-Trigger Interface n Mask */ 322 323 #define TAL_CTIMASK_CM0P_Pos 0 /**< \brief (TAL_CTIMASK) CM0P Break Master */ 324 #define TAL_CTIMASK_CM0P (_U(0x1) << TAL_CTIMASK_CM0P_Pos) 325 #define TAL_CTIMASK_PPP_Pos 1 /**< \brief (TAL_CTIMASK) PPP Break Master */ 326 #define TAL_CTIMASK_PPP (_U(0x1) << TAL_CTIMASK_PPP_Pos) 327 #define TAL_CTIMASK_EVBRK_Pos 6 /**< \brief (TAL_CTIMASK) Event Break Master */ 328 #define TAL_CTIMASK_EVBRK (_U(0x1) << TAL_CTIMASK_EVBRK_Pos) 329 #define TAL_CTIMASK_EXTBRK_Pos 7 /**< \brief (TAL_CTIMASK) External Break Master */ 330 #define TAL_CTIMASK_EXTBRK (_U(0x1) << TAL_CTIMASK_EXTBRK_Pos) 331 #define TAL_CTIMASK_MASK _U(0xC3) /**< \brief (TAL_CTIMASK) MASK Register */ 332 333 /* -------- TAL_INTSTATUS : (TAL Offset: 0x20) (R/ 8) Interrupt n Status -------- */ 334 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 335 typedef union { 336 struct { 337 uint8_t IRQ0:1; /*!< bit: 0 Interrupt Status for Interrupt Request 0 within Interrupt n */ 338 uint8_t IRQ1:1; /*!< bit: 1 Interrupt Status for Interrupt Request 1 within Interrupt n */ 339 uint8_t IRQ2:1; /*!< bit: 2 Interrupt Status for Interrupt Request 2 within Interrupt n */ 340 uint8_t IRQ3:1; /*!< bit: 3 Interrupt Status for Interrupt Request 3 within Interrupt n */ 341 uint8_t IRQ4:1; /*!< bit: 4 Interrupt Status for Interrupt Request 4 within Interrupt n */ 342 uint8_t IRQ5:1; /*!< bit: 5 Interrupt Status for Interrupt Request 5 within Interrupt n */ 343 uint8_t IRQ6:1; /*!< bit: 6 Interrupt Status for Interrupt Request 6 within Interrupt n */ 344 uint8_t IRQ7:1; /*!< bit: 7 Interrupt Status for Interrupt Request 7 within Interrupt n */ 345 } bit; /*!< Structure used for bit access */ 346 struct { 347 uint8_t IRQ:8; /*!< bit: 0.. 7 Interrupt Status for Interrupt Request x within Interrupt n */ 348 } vec; /*!< Structure used for vec access */ 349 uint8_t reg; /*!< Type used for register access */ 350 } TAL_INTSTATUS_Type; 351 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 352 353 #define TAL_INTSTATUS_OFFSET 0x20 /**< \brief (TAL_INTSTATUS offset) Interrupt n Status */ 354 #define TAL_INTSTATUS_RESETVALUE _U(0x00) /**< \brief (TAL_INTSTATUS reset_value) Interrupt n Status */ 355 356 #define TAL_INTSTATUS_IRQ0_Pos 0 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 0 within Interrupt n */ 357 #define TAL_INTSTATUS_IRQ0 (1 << TAL_INTSTATUS_IRQ0_Pos) 358 #define TAL_INTSTATUS_IRQ1_Pos 1 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 1 within Interrupt n */ 359 #define TAL_INTSTATUS_IRQ1 (1 << TAL_INTSTATUS_IRQ1_Pos) 360 #define TAL_INTSTATUS_IRQ2_Pos 2 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 2 within Interrupt n */ 361 #define TAL_INTSTATUS_IRQ2 (1 << TAL_INTSTATUS_IRQ2_Pos) 362 #define TAL_INTSTATUS_IRQ3_Pos 3 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 3 within Interrupt n */ 363 #define TAL_INTSTATUS_IRQ3 (1 << TAL_INTSTATUS_IRQ3_Pos) 364 #define TAL_INTSTATUS_IRQ4_Pos 4 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 4 within Interrupt n */ 365 #define TAL_INTSTATUS_IRQ4 (1 << TAL_INTSTATUS_IRQ4_Pos) 366 #define TAL_INTSTATUS_IRQ5_Pos 5 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 5 within Interrupt n */ 367 #define TAL_INTSTATUS_IRQ5 (1 << TAL_INTSTATUS_IRQ5_Pos) 368 #define TAL_INTSTATUS_IRQ6_Pos 6 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 6 within Interrupt n */ 369 #define TAL_INTSTATUS_IRQ6 (1 << TAL_INTSTATUS_IRQ6_Pos) 370 #define TAL_INTSTATUS_IRQ7_Pos 7 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request 7 within Interrupt n */ 371 #define TAL_INTSTATUS_IRQ7 (1 << TAL_INTSTATUS_IRQ7_Pos) 372 #define TAL_INTSTATUS_IRQ_Pos 0 /**< \brief (TAL_INTSTATUS) Interrupt Status for Interrupt Request x within Interrupt n */ 373 #define TAL_INTSTATUS_IRQ_Msk (_U(0xFF) << TAL_INTSTATUS_IRQ_Pos) 374 #define TAL_INTSTATUS_IRQ(value) (TAL_INTSTATUS_IRQ_Msk & ((value) << TAL_INTSTATUS_IRQ_Pos)) 375 #define TAL_INTSTATUS_MASK _U(0xFF) /**< \brief (TAL_INTSTATUS) MASK Register */ 376 377 /* -------- TAL_DMACPUSEL0 : (TAL Offset: 0x40) (R/W 32) DMA Channel Interrupts CPU Select 0 -------- */ 378 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 379 typedef union { 380 struct { 381 uint32_t CH0:1; /*!< bit: 0 DMA Channel 0 Interrupt CPU Select */ 382 uint32_t :1; /*!< bit: 1 Reserved */ 383 uint32_t CH1:1; /*!< bit: 2 DMA Channel 1 Interrupt CPU Select */ 384 uint32_t :1; /*!< bit: 3 Reserved */ 385 uint32_t CH2:1; /*!< bit: 4 DMA Channel 2 Interrupt CPU Select */ 386 uint32_t :1; /*!< bit: 5 Reserved */ 387 uint32_t CH3:1; /*!< bit: 6 DMA Channel 3 Interrupt CPU Select */ 388 uint32_t :1; /*!< bit: 7 Reserved */ 389 uint32_t CH4:1; /*!< bit: 8 DMA Channel 4 Interrupt CPU Select */ 390 uint32_t :1; /*!< bit: 9 Reserved */ 391 uint32_t CH5:1; /*!< bit: 10 DMA Channel 5 Interrupt CPU Select */ 392 uint32_t :1; /*!< bit: 11 Reserved */ 393 uint32_t CH6:1; /*!< bit: 12 DMA Channel 6 Interrupt CPU Select */ 394 uint32_t :1; /*!< bit: 13 Reserved */ 395 uint32_t CH7:1; /*!< bit: 14 DMA Channel 7 Interrupt CPU Select */ 396 uint32_t :1; /*!< bit: 15 Reserved */ 397 uint32_t CH8:1; /*!< bit: 16 DMA Channel 8 Interrupt CPU Select */ 398 uint32_t :1; /*!< bit: 17 Reserved */ 399 uint32_t CH9:1; /*!< bit: 18 DMA Channel 9 Interrupt CPU Select */ 400 uint32_t :1; /*!< bit: 19 Reserved */ 401 uint32_t CH10:1; /*!< bit: 20 DMA Channel 10 Interrupt CPU Select */ 402 uint32_t :1; /*!< bit: 21 Reserved */ 403 uint32_t CH11:1; /*!< bit: 22 DMA Channel 11 Interrupt CPU Select */ 404 uint32_t :1; /*!< bit: 23 Reserved */ 405 uint32_t CH12:1; /*!< bit: 24 DMA Channel 12 Interrupt CPU Select */ 406 uint32_t :1; /*!< bit: 25 Reserved */ 407 uint32_t CH13:1; /*!< bit: 26 DMA Channel 13 Interrupt CPU Select */ 408 uint32_t :1; /*!< bit: 27 Reserved */ 409 uint32_t CH14:1; /*!< bit: 28 DMA Channel 14 Interrupt CPU Select */ 410 uint32_t :1; /*!< bit: 29 Reserved */ 411 uint32_t CH15:1; /*!< bit: 30 DMA Channel 15 Interrupt CPU Select */ 412 uint32_t :1; /*!< bit: 31 Reserved */ 413 } bit; /*!< Structure used for bit access */ 414 uint32_t reg; /*!< Type used for register access */ 415 } TAL_DMACPUSEL0_Type; 416 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 417 418 #define TAL_DMACPUSEL0_OFFSET 0x40 /**< \brief (TAL_DMACPUSEL0 offset) DMA Channel Interrupts CPU Select 0 */ 419 #define TAL_DMACPUSEL0_RESETVALUE _U(0x00000000) /**< \brief (TAL_DMACPUSEL0 reset_value) DMA Channel Interrupts CPU Select 0 */ 420 421 #define TAL_DMACPUSEL0_CH0_Pos 0 /**< \brief (TAL_DMACPUSEL0) DMA Channel 0 Interrupt CPU Select */ 422 #define TAL_DMACPUSEL0_CH0_Msk (_U(0x1) << TAL_DMACPUSEL0_CH0_Pos) 423 #define TAL_DMACPUSEL0_CH0(value) (TAL_DMACPUSEL0_CH0_Msk & ((value) << TAL_DMACPUSEL0_CH0_Pos)) 424 #define TAL_DMACPUSEL0_CH1_Pos 2 /**< \brief (TAL_DMACPUSEL0) DMA Channel 1 Interrupt CPU Select */ 425 #define TAL_DMACPUSEL0_CH1_Msk (_U(0x1) << TAL_DMACPUSEL0_CH1_Pos) 426 #define TAL_DMACPUSEL0_CH1(value) (TAL_DMACPUSEL0_CH1_Msk & ((value) << TAL_DMACPUSEL0_CH1_Pos)) 427 #define TAL_DMACPUSEL0_CH2_Pos 4 /**< \brief (TAL_DMACPUSEL0) DMA Channel 2 Interrupt CPU Select */ 428 #define TAL_DMACPUSEL0_CH2_Msk (_U(0x1) << TAL_DMACPUSEL0_CH2_Pos) 429 #define TAL_DMACPUSEL0_CH2(value) (TAL_DMACPUSEL0_CH2_Msk & ((value) << TAL_DMACPUSEL0_CH2_Pos)) 430 #define TAL_DMACPUSEL0_CH3_Pos 6 /**< \brief (TAL_DMACPUSEL0) DMA Channel 3 Interrupt CPU Select */ 431 #define TAL_DMACPUSEL0_CH3_Msk (_U(0x1) << TAL_DMACPUSEL0_CH3_Pos) 432 #define TAL_DMACPUSEL0_CH3(value) (TAL_DMACPUSEL0_CH3_Msk & ((value) << TAL_DMACPUSEL0_CH3_Pos)) 433 #define TAL_DMACPUSEL0_CH4_Pos 8 /**< \brief (TAL_DMACPUSEL0) DMA Channel 4 Interrupt CPU Select */ 434 #define TAL_DMACPUSEL0_CH4_Msk (_U(0x1) << TAL_DMACPUSEL0_CH4_Pos) 435 #define TAL_DMACPUSEL0_CH4(value) (TAL_DMACPUSEL0_CH4_Msk & ((value) << TAL_DMACPUSEL0_CH4_Pos)) 436 #define TAL_DMACPUSEL0_CH5_Pos 10 /**< \brief (TAL_DMACPUSEL0) DMA Channel 5 Interrupt CPU Select */ 437 #define TAL_DMACPUSEL0_CH5_Msk (_U(0x1) << TAL_DMACPUSEL0_CH5_Pos) 438 #define TAL_DMACPUSEL0_CH5(value) (TAL_DMACPUSEL0_CH5_Msk & ((value) << TAL_DMACPUSEL0_CH5_Pos)) 439 #define TAL_DMACPUSEL0_CH6_Pos 12 /**< \brief (TAL_DMACPUSEL0) DMA Channel 6 Interrupt CPU Select */ 440 #define TAL_DMACPUSEL0_CH6_Msk (_U(0x1) << TAL_DMACPUSEL0_CH6_Pos) 441 #define TAL_DMACPUSEL0_CH6(value) (TAL_DMACPUSEL0_CH6_Msk & ((value) << TAL_DMACPUSEL0_CH6_Pos)) 442 #define TAL_DMACPUSEL0_CH7_Pos 14 /**< \brief (TAL_DMACPUSEL0) DMA Channel 7 Interrupt CPU Select */ 443 #define TAL_DMACPUSEL0_CH7_Msk (_U(0x1) << TAL_DMACPUSEL0_CH7_Pos) 444 #define TAL_DMACPUSEL0_CH7(value) (TAL_DMACPUSEL0_CH7_Msk & ((value) << TAL_DMACPUSEL0_CH7_Pos)) 445 #define TAL_DMACPUSEL0_CH8_Pos 16 /**< \brief (TAL_DMACPUSEL0) DMA Channel 8 Interrupt CPU Select */ 446 #define TAL_DMACPUSEL0_CH8_Msk (_U(0x1) << TAL_DMACPUSEL0_CH8_Pos) 447 #define TAL_DMACPUSEL0_CH8(value) (TAL_DMACPUSEL0_CH8_Msk & ((value) << TAL_DMACPUSEL0_CH8_Pos)) 448 #define TAL_DMACPUSEL0_CH9_Pos 18 /**< \brief (TAL_DMACPUSEL0) DMA Channel 9 Interrupt CPU Select */ 449 #define TAL_DMACPUSEL0_CH9_Msk (_U(0x1) << TAL_DMACPUSEL0_CH9_Pos) 450 #define TAL_DMACPUSEL0_CH9(value) (TAL_DMACPUSEL0_CH9_Msk & ((value) << TAL_DMACPUSEL0_CH9_Pos)) 451 #define TAL_DMACPUSEL0_CH10_Pos 20 /**< \brief (TAL_DMACPUSEL0) DMA Channel 10 Interrupt CPU Select */ 452 #define TAL_DMACPUSEL0_CH10_Msk (_U(0x1) << TAL_DMACPUSEL0_CH10_Pos) 453 #define TAL_DMACPUSEL0_CH10(value) (TAL_DMACPUSEL0_CH10_Msk & ((value) << TAL_DMACPUSEL0_CH10_Pos)) 454 #define TAL_DMACPUSEL0_CH11_Pos 22 /**< \brief (TAL_DMACPUSEL0) DMA Channel 11 Interrupt CPU Select */ 455 #define TAL_DMACPUSEL0_CH11_Msk (_U(0x1) << TAL_DMACPUSEL0_CH11_Pos) 456 #define TAL_DMACPUSEL0_CH11(value) (TAL_DMACPUSEL0_CH11_Msk & ((value) << TAL_DMACPUSEL0_CH11_Pos)) 457 #define TAL_DMACPUSEL0_CH12_Pos 24 /**< \brief (TAL_DMACPUSEL0) DMA Channel 12 Interrupt CPU Select */ 458 #define TAL_DMACPUSEL0_CH12_Msk (_U(0x1) << TAL_DMACPUSEL0_CH12_Pos) 459 #define TAL_DMACPUSEL0_CH12(value) (TAL_DMACPUSEL0_CH12_Msk & ((value) << TAL_DMACPUSEL0_CH12_Pos)) 460 #define TAL_DMACPUSEL0_CH13_Pos 26 /**< \brief (TAL_DMACPUSEL0) DMA Channel 13 Interrupt CPU Select */ 461 #define TAL_DMACPUSEL0_CH13_Msk (_U(0x1) << TAL_DMACPUSEL0_CH13_Pos) 462 #define TAL_DMACPUSEL0_CH13(value) (TAL_DMACPUSEL0_CH13_Msk & ((value) << TAL_DMACPUSEL0_CH13_Pos)) 463 #define TAL_DMACPUSEL0_CH14_Pos 28 /**< \brief (TAL_DMACPUSEL0) DMA Channel 14 Interrupt CPU Select */ 464 #define TAL_DMACPUSEL0_CH14_Msk (_U(0x1) << TAL_DMACPUSEL0_CH14_Pos) 465 #define TAL_DMACPUSEL0_CH14(value) (TAL_DMACPUSEL0_CH14_Msk & ((value) << TAL_DMACPUSEL0_CH14_Pos)) 466 #define TAL_DMACPUSEL0_CH15_Pos 30 /**< \brief (TAL_DMACPUSEL0) DMA Channel 15 Interrupt CPU Select */ 467 #define TAL_DMACPUSEL0_CH15_Msk (_U(0x1) << TAL_DMACPUSEL0_CH15_Pos) 468 #define TAL_DMACPUSEL0_CH15(value) (TAL_DMACPUSEL0_CH15_Msk & ((value) << TAL_DMACPUSEL0_CH15_Pos)) 469 #define TAL_DMACPUSEL0_MASK _U(0x55555555) /**< \brief (TAL_DMACPUSEL0) MASK Register */ 470 471 /* -------- TAL_EVCPUSEL0 : (TAL Offset: 0x48) (R/W 32) EVSYS Channel Interrupts CPU Select 0 -------- */ 472 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 473 typedef union { 474 struct { 475 uint32_t CH0:1; /*!< bit: 0 Event Channel 0 Interrupt CPU Select */ 476 uint32_t :1; /*!< bit: 1 Reserved */ 477 uint32_t CH1:1; /*!< bit: 2 Event Channel 1 Interrupt CPU Select */ 478 uint32_t :1; /*!< bit: 3 Reserved */ 479 uint32_t CH2:1; /*!< bit: 4 Event Channel 2 Interrupt CPU Select */ 480 uint32_t :1; /*!< bit: 5 Reserved */ 481 uint32_t CH3:1; /*!< bit: 6 Event Channel 3 Interrupt CPU Select */ 482 uint32_t :1; /*!< bit: 7 Reserved */ 483 uint32_t CH4:1; /*!< bit: 8 Event Channel 4 Interrupt CPU Select */ 484 uint32_t :1; /*!< bit: 9 Reserved */ 485 uint32_t CH5:1; /*!< bit: 10 Event Channel 5 Interrupt CPU Select */ 486 uint32_t :1; /*!< bit: 11 Reserved */ 487 uint32_t CH6:1; /*!< bit: 12 Event Channel 6 Interrupt CPU Select */ 488 uint32_t :1; /*!< bit: 13 Reserved */ 489 uint32_t CH7:1; /*!< bit: 14 Event Channel 7 Interrupt CPU Select */ 490 uint32_t :1; /*!< bit: 15 Reserved */ 491 uint32_t CH8:1; /*!< bit: 16 Event Channel 8 Interrupt CPU Select */ 492 uint32_t :1; /*!< bit: 17 Reserved */ 493 uint32_t CH9:1; /*!< bit: 18 Event Channel 9 Interrupt CPU Select */ 494 uint32_t :1; /*!< bit: 19 Reserved */ 495 uint32_t CH10:1; /*!< bit: 20 Event Channel 10 Interrupt CPU Select */ 496 uint32_t :1; /*!< bit: 21 Reserved */ 497 uint32_t CH11:1; /*!< bit: 22 Event Channel 11 Interrupt CPU Select */ 498 uint32_t :9; /*!< bit: 23..31 Reserved */ 499 } bit; /*!< Structure used for bit access */ 500 uint32_t reg; /*!< Type used for register access */ 501 } TAL_EVCPUSEL0_Type; 502 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 503 504 #define TAL_EVCPUSEL0_OFFSET 0x48 /**< \brief (TAL_EVCPUSEL0 offset) EVSYS Channel Interrupts CPU Select 0 */ 505 #define TAL_EVCPUSEL0_RESETVALUE _U(0x00000000) /**< \brief (TAL_EVCPUSEL0 reset_value) EVSYS Channel Interrupts CPU Select 0 */ 506 507 #define TAL_EVCPUSEL0_CH0_Pos 0 /**< \brief (TAL_EVCPUSEL0) Event Channel 0 Interrupt CPU Select */ 508 #define TAL_EVCPUSEL0_CH0_Msk (_U(0x1) << TAL_EVCPUSEL0_CH0_Pos) 509 #define TAL_EVCPUSEL0_CH0(value) (TAL_EVCPUSEL0_CH0_Msk & ((value) << TAL_EVCPUSEL0_CH0_Pos)) 510 #define TAL_EVCPUSEL0_CH1_Pos 2 /**< \brief (TAL_EVCPUSEL0) Event Channel 1 Interrupt CPU Select */ 511 #define TAL_EVCPUSEL0_CH1_Msk (_U(0x1) << TAL_EVCPUSEL0_CH1_Pos) 512 #define TAL_EVCPUSEL0_CH1(value) (TAL_EVCPUSEL0_CH1_Msk & ((value) << TAL_EVCPUSEL0_CH1_Pos)) 513 #define TAL_EVCPUSEL0_CH2_Pos 4 /**< \brief (TAL_EVCPUSEL0) Event Channel 2 Interrupt CPU Select */ 514 #define TAL_EVCPUSEL0_CH2_Msk (_U(0x1) << TAL_EVCPUSEL0_CH2_Pos) 515 #define TAL_EVCPUSEL0_CH2(value) (TAL_EVCPUSEL0_CH2_Msk & ((value) << TAL_EVCPUSEL0_CH2_Pos)) 516 #define TAL_EVCPUSEL0_CH3_Pos 6 /**< \brief (TAL_EVCPUSEL0) Event Channel 3 Interrupt CPU Select */ 517 #define TAL_EVCPUSEL0_CH3_Msk (_U(0x1) << TAL_EVCPUSEL0_CH3_Pos) 518 #define TAL_EVCPUSEL0_CH3(value) (TAL_EVCPUSEL0_CH3_Msk & ((value) << TAL_EVCPUSEL0_CH3_Pos)) 519 #define TAL_EVCPUSEL0_CH4_Pos 8 /**< \brief (TAL_EVCPUSEL0) Event Channel 4 Interrupt CPU Select */ 520 #define TAL_EVCPUSEL0_CH4_Msk (_U(0x1) << TAL_EVCPUSEL0_CH4_Pos) 521 #define TAL_EVCPUSEL0_CH4(value) (TAL_EVCPUSEL0_CH4_Msk & ((value) << TAL_EVCPUSEL0_CH4_Pos)) 522 #define TAL_EVCPUSEL0_CH5_Pos 10 /**< \brief (TAL_EVCPUSEL0) Event Channel 5 Interrupt CPU Select */ 523 #define TAL_EVCPUSEL0_CH5_Msk (_U(0x1) << TAL_EVCPUSEL0_CH5_Pos) 524 #define TAL_EVCPUSEL0_CH5(value) (TAL_EVCPUSEL0_CH5_Msk & ((value) << TAL_EVCPUSEL0_CH5_Pos)) 525 #define TAL_EVCPUSEL0_CH6_Pos 12 /**< \brief (TAL_EVCPUSEL0) Event Channel 6 Interrupt CPU Select */ 526 #define TAL_EVCPUSEL0_CH6_Msk (_U(0x1) << TAL_EVCPUSEL0_CH6_Pos) 527 #define TAL_EVCPUSEL0_CH6(value) (TAL_EVCPUSEL0_CH6_Msk & ((value) << TAL_EVCPUSEL0_CH6_Pos)) 528 #define TAL_EVCPUSEL0_CH7_Pos 14 /**< \brief (TAL_EVCPUSEL0) Event Channel 7 Interrupt CPU Select */ 529 #define TAL_EVCPUSEL0_CH7_Msk (_U(0x1) << TAL_EVCPUSEL0_CH7_Pos) 530 #define TAL_EVCPUSEL0_CH7(value) (TAL_EVCPUSEL0_CH7_Msk & ((value) << TAL_EVCPUSEL0_CH7_Pos)) 531 #define TAL_EVCPUSEL0_CH8_Pos 16 /**< \brief (TAL_EVCPUSEL0) Event Channel 8 Interrupt CPU Select */ 532 #define TAL_EVCPUSEL0_CH8_Msk (_U(0x1) << TAL_EVCPUSEL0_CH8_Pos) 533 #define TAL_EVCPUSEL0_CH8(value) (TAL_EVCPUSEL0_CH8_Msk & ((value) << TAL_EVCPUSEL0_CH8_Pos)) 534 #define TAL_EVCPUSEL0_CH9_Pos 18 /**< \brief (TAL_EVCPUSEL0) Event Channel 9 Interrupt CPU Select */ 535 #define TAL_EVCPUSEL0_CH9_Msk (_U(0x1) << TAL_EVCPUSEL0_CH9_Pos) 536 #define TAL_EVCPUSEL0_CH9(value) (TAL_EVCPUSEL0_CH9_Msk & ((value) << TAL_EVCPUSEL0_CH9_Pos)) 537 #define TAL_EVCPUSEL0_CH10_Pos 20 /**< \brief (TAL_EVCPUSEL0) Event Channel 10 Interrupt CPU Select */ 538 #define TAL_EVCPUSEL0_CH10_Msk (_U(0x1) << TAL_EVCPUSEL0_CH10_Pos) 539 #define TAL_EVCPUSEL0_CH10(value) (TAL_EVCPUSEL0_CH10_Msk & ((value) << TAL_EVCPUSEL0_CH10_Pos)) 540 #define TAL_EVCPUSEL0_CH11_Pos 22 /**< \brief (TAL_EVCPUSEL0) Event Channel 11 Interrupt CPU Select */ 541 #define TAL_EVCPUSEL0_CH11_Msk (_U(0x1) << TAL_EVCPUSEL0_CH11_Pos) 542 #define TAL_EVCPUSEL0_CH11(value) (TAL_EVCPUSEL0_CH11_Msk & ((value) << TAL_EVCPUSEL0_CH11_Pos)) 543 #define TAL_EVCPUSEL0_MASK _U(0x00555555) /**< \brief (TAL_EVCPUSEL0) MASK Register */ 544 545 /* -------- TAL_EICCPUSEL0 : (TAL Offset: 0x50) (R/W 32) EIC External Interrupts CPU Select 0 -------- */ 546 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 547 typedef union { 548 struct { 549 uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 CPU Select */ 550 uint32_t :1; /*!< bit: 1 Reserved */ 551 uint32_t EXTINT1:1; /*!< bit: 2 External Interrupt 1 CPU Select */ 552 uint32_t :1; /*!< bit: 3 Reserved */ 553 uint32_t EXTINT2:1; /*!< bit: 4 External Interrupt 2 CPU Select */ 554 uint32_t :1; /*!< bit: 5 Reserved */ 555 uint32_t EXTINT3:1; /*!< bit: 6 External Interrupt 3 CPU Select */ 556 uint32_t :1; /*!< bit: 7 Reserved */ 557 uint32_t EXTINT4:1; /*!< bit: 8 External Interrupt 4 CPU Select */ 558 uint32_t :1; /*!< bit: 9 Reserved */ 559 uint32_t EXTINT5:1; /*!< bit: 10 External Interrupt 5 CPU Select */ 560 uint32_t :1; /*!< bit: 11 Reserved */ 561 uint32_t EXTINT6:1; /*!< bit: 12 External Interrupt 6 CPU Select */ 562 uint32_t :1; /*!< bit: 13 Reserved */ 563 uint32_t EXTINT7:1; /*!< bit: 14 External Interrupt 7 CPU Select */ 564 uint32_t :1; /*!< bit: 15 Reserved */ 565 uint32_t EXTINT8:1; /*!< bit: 16 External Interrupt 8 CPU Select */ 566 uint32_t :1; /*!< bit: 17 Reserved */ 567 uint32_t EXTINT9:1; /*!< bit: 18 External Interrupt 9 CPU Select */ 568 uint32_t :1; /*!< bit: 19 Reserved */ 569 uint32_t EXTINT10:1; /*!< bit: 20 External Interrupt 10 CPU Select */ 570 uint32_t :1; /*!< bit: 21 Reserved */ 571 uint32_t EXTINT11:1; /*!< bit: 22 External Interrupt 11 CPU Select */ 572 uint32_t :1; /*!< bit: 23 Reserved */ 573 uint32_t EXTINT12:1; /*!< bit: 24 External Interrupt 12 CPU Select */ 574 uint32_t :1; /*!< bit: 25 Reserved */ 575 uint32_t EXTINT13:1; /*!< bit: 26 External Interrupt 13 CPU Select */ 576 uint32_t :1; /*!< bit: 27 Reserved */ 577 uint32_t EXTINT14:1; /*!< bit: 28 External Interrupt 14 CPU Select */ 578 uint32_t :1; /*!< bit: 29 Reserved */ 579 uint32_t EXTINT15:1; /*!< bit: 30 External Interrupt 15 CPU Select */ 580 uint32_t :1; /*!< bit: 31 Reserved */ 581 } bit; /*!< Structure used for bit access */ 582 uint32_t reg; /*!< Type used for register access */ 583 } TAL_EICCPUSEL0_Type; 584 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 585 586 #define TAL_EICCPUSEL0_OFFSET 0x50 /**< \brief (TAL_EICCPUSEL0 offset) EIC External Interrupts CPU Select 0 */ 587 #define TAL_EICCPUSEL0_RESETVALUE _U(0x00000000) /**< \brief (TAL_EICCPUSEL0 reset_value) EIC External Interrupts CPU Select 0 */ 588 589 #define TAL_EICCPUSEL0_EXTINT0_Pos 0 /**< \brief (TAL_EICCPUSEL0) External Interrupt 0 CPU Select */ 590 #define TAL_EICCPUSEL0_EXTINT0_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT0_Pos) 591 #define TAL_EICCPUSEL0_EXTINT0(value) (TAL_EICCPUSEL0_EXTINT0_Msk & ((value) << TAL_EICCPUSEL0_EXTINT0_Pos)) 592 #define TAL_EICCPUSEL0_EXTINT1_Pos 2 /**< \brief (TAL_EICCPUSEL0) External Interrupt 1 CPU Select */ 593 #define TAL_EICCPUSEL0_EXTINT1_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT1_Pos) 594 #define TAL_EICCPUSEL0_EXTINT1(value) (TAL_EICCPUSEL0_EXTINT1_Msk & ((value) << TAL_EICCPUSEL0_EXTINT1_Pos)) 595 #define TAL_EICCPUSEL0_EXTINT2_Pos 4 /**< \brief (TAL_EICCPUSEL0) External Interrupt 2 CPU Select */ 596 #define TAL_EICCPUSEL0_EXTINT2_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT2_Pos) 597 #define TAL_EICCPUSEL0_EXTINT2(value) (TAL_EICCPUSEL0_EXTINT2_Msk & ((value) << TAL_EICCPUSEL0_EXTINT2_Pos)) 598 #define TAL_EICCPUSEL0_EXTINT3_Pos 6 /**< \brief (TAL_EICCPUSEL0) External Interrupt 3 CPU Select */ 599 #define TAL_EICCPUSEL0_EXTINT3_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT3_Pos) 600 #define TAL_EICCPUSEL0_EXTINT3(value) (TAL_EICCPUSEL0_EXTINT3_Msk & ((value) << TAL_EICCPUSEL0_EXTINT3_Pos)) 601 #define TAL_EICCPUSEL0_EXTINT4_Pos 8 /**< \brief (TAL_EICCPUSEL0) External Interrupt 4 CPU Select */ 602 #define TAL_EICCPUSEL0_EXTINT4_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT4_Pos) 603 #define TAL_EICCPUSEL0_EXTINT4(value) (TAL_EICCPUSEL0_EXTINT4_Msk & ((value) << TAL_EICCPUSEL0_EXTINT4_Pos)) 604 #define TAL_EICCPUSEL0_EXTINT5_Pos 10 /**< \brief (TAL_EICCPUSEL0) External Interrupt 5 CPU Select */ 605 #define TAL_EICCPUSEL0_EXTINT5_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT5_Pos) 606 #define TAL_EICCPUSEL0_EXTINT5(value) (TAL_EICCPUSEL0_EXTINT5_Msk & ((value) << TAL_EICCPUSEL0_EXTINT5_Pos)) 607 #define TAL_EICCPUSEL0_EXTINT6_Pos 12 /**< \brief (TAL_EICCPUSEL0) External Interrupt 6 CPU Select */ 608 #define TAL_EICCPUSEL0_EXTINT6_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT6_Pos) 609 #define TAL_EICCPUSEL0_EXTINT6(value) (TAL_EICCPUSEL0_EXTINT6_Msk & ((value) << TAL_EICCPUSEL0_EXTINT6_Pos)) 610 #define TAL_EICCPUSEL0_EXTINT7_Pos 14 /**< \brief (TAL_EICCPUSEL0) External Interrupt 7 CPU Select */ 611 #define TAL_EICCPUSEL0_EXTINT7_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT7_Pos) 612 #define TAL_EICCPUSEL0_EXTINT7(value) (TAL_EICCPUSEL0_EXTINT7_Msk & ((value) << TAL_EICCPUSEL0_EXTINT7_Pos)) 613 #define TAL_EICCPUSEL0_EXTINT8_Pos 16 /**< \brief (TAL_EICCPUSEL0) External Interrupt 8 CPU Select */ 614 #define TAL_EICCPUSEL0_EXTINT8_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT8_Pos) 615 #define TAL_EICCPUSEL0_EXTINT8(value) (TAL_EICCPUSEL0_EXTINT8_Msk & ((value) << TAL_EICCPUSEL0_EXTINT8_Pos)) 616 #define TAL_EICCPUSEL0_EXTINT9_Pos 18 /**< \brief (TAL_EICCPUSEL0) External Interrupt 9 CPU Select */ 617 #define TAL_EICCPUSEL0_EXTINT9_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT9_Pos) 618 #define TAL_EICCPUSEL0_EXTINT9(value) (TAL_EICCPUSEL0_EXTINT9_Msk & ((value) << TAL_EICCPUSEL0_EXTINT9_Pos)) 619 #define TAL_EICCPUSEL0_EXTINT10_Pos 20 /**< \brief (TAL_EICCPUSEL0) External Interrupt 10 CPU Select */ 620 #define TAL_EICCPUSEL0_EXTINT10_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT10_Pos) 621 #define TAL_EICCPUSEL0_EXTINT10(value) (TAL_EICCPUSEL0_EXTINT10_Msk & ((value) << TAL_EICCPUSEL0_EXTINT10_Pos)) 622 #define TAL_EICCPUSEL0_EXTINT11_Pos 22 /**< \brief (TAL_EICCPUSEL0) External Interrupt 11 CPU Select */ 623 #define TAL_EICCPUSEL0_EXTINT11_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT11_Pos) 624 #define TAL_EICCPUSEL0_EXTINT11(value) (TAL_EICCPUSEL0_EXTINT11_Msk & ((value) << TAL_EICCPUSEL0_EXTINT11_Pos)) 625 #define TAL_EICCPUSEL0_EXTINT12_Pos 24 /**< \brief (TAL_EICCPUSEL0) External Interrupt 12 CPU Select */ 626 #define TAL_EICCPUSEL0_EXTINT12_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT12_Pos) 627 #define TAL_EICCPUSEL0_EXTINT12(value) (TAL_EICCPUSEL0_EXTINT12_Msk & ((value) << TAL_EICCPUSEL0_EXTINT12_Pos)) 628 #define TAL_EICCPUSEL0_EXTINT13_Pos 26 /**< \brief (TAL_EICCPUSEL0) External Interrupt 13 CPU Select */ 629 #define TAL_EICCPUSEL0_EXTINT13_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT13_Pos) 630 #define TAL_EICCPUSEL0_EXTINT13(value) (TAL_EICCPUSEL0_EXTINT13_Msk & ((value) << TAL_EICCPUSEL0_EXTINT13_Pos)) 631 #define TAL_EICCPUSEL0_EXTINT14_Pos 28 /**< \brief (TAL_EICCPUSEL0) External Interrupt 14 CPU Select */ 632 #define TAL_EICCPUSEL0_EXTINT14_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT14_Pos) 633 #define TAL_EICCPUSEL0_EXTINT14(value) (TAL_EICCPUSEL0_EXTINT14_Msk & ((value) << TAL_EICCPUSEL0_EXTINT14_Pos)) 634 #define TAL_EICCPUSEL0_EXTINT15_Pos 30 /**< \brief (TAL_EICCPUSEL0) External Interrupt 15 CPU Select */ 635 #define TAL_EICCPUSEL0_EXTINT15_Msk (_U(0x1) << TAL_EICCPUSEL0_EXTINT15_Pos) 636 #define TAL_EICCPUSEL0_EXTINT15(value) (TAL_EICCPUSEL0_EXTINT15_Msk & ((value) << TAL_EICCPUSEL0_EXTINT15_Pos)) 637 #define TAL_EICCPUSEL0_MASK _U(0x55555555) /**< \brief (TAL_EICCPUSEL0) MASK Register */ 638 639 /* -------- TAL_INTCPUSEL0 : (TAL Offset: 0x58) (R/W 32) Interrupts CPU Select 0 -------- */ 640 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 641 typedef union { 642 struct { 643 uint32_t SYSTEM:1; /*!< bit: 0 SYSTEM Interrupt CPU Select */ 644 uint32_t :1; /*!< bit: 1 Reserved */ 645 uint32_t WDT:1; /*!< bit: 2 WDT Interrupt CPU Select */ 646 uint32_t :1; /*!< bit: 3 Reserved */ 647 uint32_t RTC:1; /*!< bit: 4 RTC Interrupt CPU Select */ 648 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 649 uint32_t NVMCTRL:1; /*!< bit: 8 NVMCTRL Interrupt CPU Select */ 650 uint32_t :3; /*!< bit: 9..11 Reserved */ 651 uint32_t USB:1; /*!< bit: 12 USB Interrupt CPU Select */ 652 uint32_t :3; /*!< bit: 13..15 Reserved */ 653 uint32_t SERCOM0:1; /*!< bit: 16 SERCOM0 Interrupt CPU Select */ 654 uint32_t :1; /*!< bit: 17 Reserved */ 655 uint32_t SERCOM1:1; /*!< bit: 18 SERCOM1 Interrupt CPU Select */ 656 uint32_t :1; /*!< bit: 19 Reserved */ 657 uint32_t SERCOM2:1; /*!< bit: 20 SERCOM2 Interrupt CPU Select */ 658 uint32_t :1; /*!< bit: 21 Reserved */ 659 uint32_t SERCOM3:1; /*!< bit: 22 SERCOM3 Interrupt CPU Select */ 660 uint32_t :1; /*!< bit: 23 Reserved */ 661 uint32_t SERCOM4:1; /*!< bit: 24 SERCOM4 Interrupt CPU Select */ 662 uint32_t :1; /*!< bit: 25 Reserved */ 663 uint32_t SERCOM5:1; /*!< bit: 26 SERCOM5 Interrupt CPU Select */ 664 uint32_t :1; /*!< bit: 27 Reserved */ 665 uint32_t TCC0:1; /*!< bit: 28 TCC0 Interrupt CPU Select */ 666 uint32_t :1; /*!< bit: 29 Reserved */ 667 uint32_t TCC1:1; /*!< bit: 30 TCC1 Interrupt CPU Select */ 668 uint32_t :1; /*!< bit: 31 Reserved */ 669 } bit; /*!< Structure used for bit access */ 670 uint32_t reg; /*!< Type used for register access */ 671 } TAL_INTCPUSEL0_Type; 672 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 673 674 #define TAL_INTCPUSEL0_OFFSET 0x58 /**< \brief (TAL_INTCPUSEL0 offset) Interrupts CPU Select 0 */ 675 #define TAL_INTCPUSEL0_RESETVALUE _U(0x00000000) /**< \brief (TAL_INTCPUSEL0 reset_value) Interrupts CPU Select 0 */ 676 677 #define TAL_INTCPUSEL0_SYSTEM_Pos 0 /**< \brief (TAL_INTCPUSEL0) SYSTEM Interrupt CPU Select */ 678 #define TAL_INTCPUSEL0_SYSTEM_Msk (_U(0x1) << TAL_INTCPUSEL0_SYSTEM_Pos) 679 #define TAL_INTCPUSEL0_SYSTEM(value) (TAL_INTCPUSEL0_SYSTEM_Msk & ((value) << TAL_INTCPUSEL0_SYSTEM_Pos)) 680 #define TAL_INTCPUSEL0_WDT_Pos 2 /**< \brief (TAL_INTCPUSEL0) WDT Interrupt CPU Select */ 681 #define TAL_INTCPUSEL0_WDT_Msk (_U(0x1) << TAL_INTCPUSEL0_WDT_Pos) 682 #define TAL_INTCPUSEL0_WDT(value) (TAL_INTCPUSEL0_WDT_Msk & ((value) << TAL_INTCPUSEL0_WDT_Pos)) 683 #define TAL_INTCPUSEL0_RTC_Pos 4 /**< \brief (TAL_INTCPUSEL0) RTC Interrupt CPU Select */ 684 #define TAL_INTCPUSEL0_RTC_Msk (_U(0x1) << TAL_INTCPUSEL0_RTC_Pos) 685 #define TAL_INTCPUSEL0_RTC(value) (TAL_INTCPUSEL0_RTC_Msk & ((value) << TAL_INTCPUSEL0_RTC_Pos)) 686 #define TAL_INTCPUSEL0_NVMCTRL_Pos 8 /**< \brief (TAL_INTCPUSEL0) NVMCTRL Interrupt CPU Select */ 687 #define TAL_INTCPUSEL0_NVMCTRL_Msk (_U(0x1) << TAL_INTCPUSEL0_NVMCTRL_Pos) 688 #define TAL_INTCPUSEL0_NVMCTRL(value) (TAL_INTCPUSEL0_NVMCTRL_Msk & ((value) << TAL_INTCPUSEL0_NVMCTRL_Pos)) 689 #define TAL_INTCPUSEL0_USB_Pos 12 /**< \brief (TAL_INTCPUSEL0) USB Interrupt CPU Select */ 690 #define TAL_INTCPUSEL0_USB_Msk (_U(0x1) << TAL_INTCPUSEL0_USB_Pos) 691 #define TAL_INTCPUSEL0_USB(value) (TAL_INTCPUSEL0_USB_Msk & ((value) << TAL_INTCPUSEL0_USB_Pos)) 692 #define TAL_INTCPUSEL0_SERCOM0_Pos 16 /**< \brief (TAL_INTCPUSEL0) SERCOM0 Interrupt CPU Select */ 693 #define TAL_INTCPUSEL0_SERCOM0_Msk (_U(0x1) << TAL_INTCPUSEL0_SERCOM0_Pos) 694 #define TAL_INTCPUSEL0_SERCOM0(value) (TAL_INTCPUSEL0_SERCOM0_Msk & ((value) << TAL_INTCPUSEL0_SERCOM0_Pos)) 695 #define TAL_INTCPUSEL0_SERCOM1_Pos 18 /**< \brief (TAL_INTCPUSEL0) SERCOM1 Interrupt CPU Select */ 696 #define TAL_INTCPUSEL0_SERCOM1_Msk (_U(0x1) << TAL_INTCPUSEL0_SERCOM1_Pos) 697 #define TAL_INTCPUSEL0_SERCOM1(value) (TAL_INTCPUSEL0_SERCOM1_Msk & ((value) << TAL_INTCPUSEL0_SERCOM1_Pos)) 698 #define TAL_INTCPUSEL0_SERCOM2_Pos 20 /**< \brief (TAL_INTCPUSEL0) SERCOM2 Interrupt CPU Select */ 699 #define TAL_INTCPUSEL0_SERCOM2_Msk (_U(0x1) << TAL_INTCPUSEL0_SERCOM2_Pos) 700 #define TAL_INTCPUSEL0_SERCOM2(value) (TAL_INTCPUSEL0_SERCOM2_Msk & ((value) << TAL_INTCPUSEL0_SERCOM2_Pos)) 701 #define TAL_INTCPUSEL0_SERCOM3_Pos 22 /**< \brief (TAL_INTCPUSEL0) SERCOM3 Interrupt CPU Select */ 702 #define TAL_INTCPUSEL0_SERCOM3_Msk (_U(0x1) << TAL_INTCPUSEL0_SERCOM3_Pos) 703 #define TAL_INTCPUSEL0_SERCOM3(value) (TAL_INTCPUSEL0_SERCOM3_Msk & ((value) << TAL_INTCPUSEL0_SERCOM3_Pos)) 704 #define TAL_INTCPUSEL0_SERCOM4_Pos 24 /**< \brief (TAL_INTCPUSEL0) SERCOM4 Interrupt CPU Select */ 705 #define TAL_INTCPUSEL0_SERCOM4_Msk (_U(0x1) << TAL_INTCPUSEL0_SERCOM4_Pos) 706 #define TAL_INTCPUSEL0_SERCOM4(value) (TAL_INTCPUSEL0_SERCOM4_Msk & ((value) << TAL_INTCPUSEL0_SERCOM4_Pos)) 707 #define TAL_INTCPUSEL0_SERCOM5_Pos 26 /**< \brief (TAL_INTCPUSEL0) SERCOM5 Interrupt CPU Select */ 708 #define TAL_INTCPUSEL0_SERCOM5_Msk (_U(0x1) << TAL_INTCPUSEL0_SERCOM5_Pos) 709 #define TAL_INTCPUSEL0_SERCOM5(value) (TAL_INTCPUSEL0_SERCOM5_Msk & ((value) << TAL_INTCPUSEL0_SERCOM5_Pos)) 710 #define TAL_INTCPUSEL0_TCC0_Pos 28 /**< \brief (TAL_INTCPUSEL0) TCC0 Interrupt CPU Select */ 711 #define TAL_INTCPUSEL0_TCC0_Msk (_U(0x1) << TAL_INTCPUSEL0_TCC0_Pos) 712 #define TAL_INTCPUSEL0_TCC0(value) (TAL_INTCPUSEL0_TCC0_Msk & ((value) << TAL_INTCPUSEL0_TCC0_Pos)) 713 #define TAL_INTCPUSEL0_TCC1_Pos 30 /**< \brief (TAL_INTCPUSEL0) TCC1 Interrupt CPU Select */ 714 #define TAL_INTCPUSEL0_TCC1_Msk (_U(0x1) << TAL_INTCPUSEL0_TCC1_Pos) 715 #define TAL_INTCPUSEL0_TCC1(value) (TAL_INTCPUSEL0_TCC1_Msk & ((value) << TAL_INTCPUSEL0_TCC1_Pos)) 716 #define TAL_INTCPUSEL0_MASK _U(0x55551115) /**< \brief (TAL_INTCPUSEL0) MASK Register */ 717 718 /* -------- TAL_INTCPUSEL1 : (TAL Offset: 0x5C) (R/W 32) Interrupts CPU Select 1 -------- */ 719 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 720 typedef union { 721 struct { 722 uint32_t TCC2:1; /*!< bit: 0 TCC2 Interrupt CPU Select */ 723 uint32_t :1; /*!< bit: 1 Reserved */ 724 uint32_t TC0:1; /*!< bit: 2 TC0 Interrupt CPU Select */ 725 uint32_t :1; /*!< bit: 3 Reserved */ 726 uint32_t TC1:1; /*!< bit: 4 TC1 Interrupt CPU Select */ 727 uint32_t :1; /*!< bit: 5 Reserved */ 728 uint32_t TC2:1; /*!< bit: 6 TC2 Interrupt CPU Select */ 729 uint32_t :1; /*!< bit: 7 Reserved */ 730 uint32_t TC3:1; /*!< bit: 8 TC3 Interrupt CPU Select */ 731 uint32_t :1; /*!< bit: 9 Reserved */ 732 uint32_t TC4:1; /*!< bit: 10 TC4 Interrupt CPU Select */ 733 uint32_t :1; /*!< bit: 11 Reserved */ 734 uint32_t ADC:1; /*!< bit: 12 ADC Interrupt CPU Select */ 735 uint32_t :1; /*!< bit: 13 Reserved */ 736 uint32_t AC:1; /*!< bit: 14 AC Interrupt CPU Select */ 737 uint32_t :1; /*!< bit: 15 Reserved */ 738 uint32_t DAC:1; /*!< bit: 16 DAC Interrupt CPU Select */ 739 uint32_t :1; /*!< bit: 17 Reserved */ 740 uint32_t PTC:1; /*!< bit: 18 PTC Interrupt CPU Select */ 741 uint32_t :1; /*!< bit: 19 Reserved */ 742 uint32_t AES:1; /*!< bit: 20 AES Interrupt CPU Select */ 743 uint32_t :1; /*!< bit: 21 Reserved */ 744 uint32_t TRNG:1; /*!< bit: 22 TRNG Interrupt CPU Select */ 745 uint32_t :1; /*!< bit: 23 Reserved */ 746 uint32_t PICOP:1; /*!< bit: 24 PICOP Interrupt CPU Select */ 747 uint32_t :7; /*!< bit: 25..31 Reserved */ 748 } bit; /*!< Structure used for bit access */ 749 uint32_t reg; /*!< Type used for register access */ 750 } TAL_INTCPUSEL1_Type; 751 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 752 753 #define TAL_INTCPUSEL1_OFFSET 0x5C /**< \brief (TAL_INTCPUSEL1 offset) Interrupts CPU Select 1 */ 754 #define TAL_INTCPUSEL1_RESETVALUE _U(0x00000000) /**< \brief (TAL_INTCPUSEL1 reset_value) Interrupts CPU Select 1 */ 755 756 #define TAL_INTCPUSEL1_TCC2_Pos 0 /**< \brief (TAL_INTCPUSEL1) TCC2 Interrupt CPU Select */ 757 #define TAL_INTCPUSEL1_TCC2_Msk (_U(0x1) << TAL_INTCPUSEL1_TCC2_Pos) 758 #define TAL_INTCPUSEL1_TCC2(value) (TAL_INTCPUSEL1_TCC2_Msk & ((value) << TAL_INTCPUSEL1_TCC2_Pos)) 759 #define TAL_INTCPUSEL1_TC0_Pos 2 /**< \brief (TAL_INTCPUSEL1) TC0 Interrupt CPU Select */ 760 #define TAL_INTCPUSEL1_TC0_Msk (_U(0x1) << TAL_INTCPUSEL1_TC0_Pos) 761 #define TAL_INTCPUSEL1_TC0(value) (TAL_INTCPUSEL1_TC0_Msk & ((value) << TAL_INTCPUSEL1_TC0_Pos)) 762 #define TAL_INTCPUSEL1_TC1_Pos 4 /**< \brief (TAL_INTCPUSEL1) TC1 Interrupt CPU Select */ 763 #define TAL_INTCPUSEL1_TC1_Msk (_U(0x1) << TAL_INTCPUSEL1_TC1_Pos) 764 #define TAL_INTCPUSEL1_TC1(value) (TAL_INTCPUSEL1_TC1_Msk & ((value) << TAL_INTCPUSEL1_TC1_Pos)) 765 #define TAL_INTCPUSEL1_TC2_Pos 6 /**< \brief (TAL_INTCPUSEL1) TC2 Interrupt CPU Select */ 766 #define TAL_INTCPUSEL1_TC2_Msk (_U(0x1) << TAL_INTCPUSEL1_TC2_Pos) 767 #define TAL_INTCPUSEL1_TC2(value) (TAL_INTCPUSEL1_TC2_Msk & ((value) << TAL_INTCPUSEL1_TC2_Pos)) 768 #define TAL_INTCPUSEL1_TC3_Pos 8 /**< \brief (TAL_INTCPUSEL1) TC3 Interrupt CPU Select */ 769 #define TAL_INTCPUSEL1_TC3_Msk (_U(0x1) << TAL_INTCPUSEL1_TC3_Pos) 770 #define TAL_INTCPUSEL1_TC3(value) (TAL_INTCPUSEL1_TC3_Msk & ((value) << TAL_INTCPUSEL1_TC3_Pos)) 771 #define TAL_INTCPUSEL1_TC4_Pos 10 /**< \brief (TAL_INTCPUSEL1) TC4 Interrupt CPU Select */ 772 #define TAL_INTCPUSEL1_TC4_Msk (_U(0x1) << TAL_INTCPUSEL1_TC4_Pos) 773 #define TAL_INTCPUSEL1_TC4(value) (TAL_INTCPUSEL1_TC4_Msk & ((value) << TAL_INTCPUSEL1_TC4_Pos)) 774 #define TAL_INTCPUSEL1_ADC_Pos 12 /**< \brief (TAL_INTCPUSEL1) ADC Interrupt CPU Select */ 775 #define TAL_INTCPUSEL1_ADC_Msk (_U(0x1) << TAL_INTCPUSEL1_ADC_Pos) 776 #define TAL_INTCPUSEL1_ADC(value) (TAL_INTCPUSEL1_ADC_Msk & ((value) << TAL_INTCPUSEL1_ADC_Pos)) 777 #define TAL_INTCPUSEL1_AC_Pos 14 /**< \brief (TAL_INTCPUSEL1) AC Interrupt CPU Select */ 778 #define TAL_INTCPUSEL1_AC_Msk (_U(0x1) << TAL_INTCPUSEL1_AC_Pos) 779 #define TAL_INTCPUSEL1_AC(value) (TAL_INTCPUSEL1_AC_Msk & ((value) << TAL_INTCPUSEL1_AC_Pos)) 780 #define TAL_INTCPUSEL1_DAC_Pos 16 /**< \brief (TAL_INTCPUSEL1) DAC Interrupt CPU Select */ 781 #define TAL_INTCPUSEL1_DAC_Msk (_U(0x1) << TAL_INTCPUSEL1_DAC_Pos) 782 #define TAL_INTCPUSEL1_DAC(value) (TAL_INTCPUSEL1_DAC_Msk & ((value) << TAL_INTCPUSEL1_DAC_Pos)) 783 #define TAL_INTCPUSEL1_PTC_Pos 18 /**< \brief (TAL_INTCPUSEL1) PTC Interrupt CPU Select */ 784 #define TAL_INTCPUSEL1_PTC_Msk (_U(0x1) << TAL_INTCPUSEL1_PTC_Pos) 785 #define TAL_INTCPUSEL1_PTC(value) (TAL_INTCPUSEL1_PTC_Msk & ((value) << TAL_INTCPUSEL1_PTC_Pos)) 786 #define TAL_INTCPUSEL1_AES_Pos 20 /**< \brief (TAL_INTCPUSEL1) AES Interrupt CPU Select */ 787 #define TAL_INTCPUSEL1_AES_Msk (_U(0x1) << TAL_INTCPUSEL1_AES_Pos) 788 #define TAL_INTCPUSEL1_AES(value) (TAL_INTCPUSEL1_AES_Msk & ((value) << TAL_INTCPUSEL1_AES_Pos)) 789 #define TAL_INTCPUSEL1_TRNG_Pos 22 /**< \brief (TAL_INTCPUSEL1) TRNG Interrupt CPU Select */ 790 #define TAL_INTCPUSEL1_TRNG_Msk (_U(0x1) << TAL_INTCPUSEL1_TRNG_Pos) 791 #define TAL_INTCPUSEL1_TRNG(value) (TAL_INTCPUSEL1_TRNG_Msk & ((value) << TAL_INTCPUSEL1_TRNG_Pos)) 792 #define TAL_INTCPUSEL1_PICOP_Pos 24 /**< \brief (TAL_INTCPUSEL1) PICOP Interrupt CPU Select */ 793 #define TAL_INTCPUSEL1_PICOP_Msk (_U(0x1) << TAL_INTCPUSEL1_PICOP_Pos) 794 #define TAL_INTCPUSEL1_PICOP(value) (TAL_INTCPUSEL1_PICOP_Msk & ((value) << TAL_INTCPUSEL1_PICOP_Pos)) 795 #define TAL_INTCPUSEL1_MASK _U(0x01555555) /**< \brief (TAL_INTCPUSEL1) MASK Register */ 796 797 /* -------- TAL_IRQTRIG : (TAL Offset: 0x60) (R/W 16) Interrupt Trigger -------- */ 798 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 799 typedef union { 800 struct { 801 uint16_t ENABLE:1; /*!< bit: 0 Trigger Enable */ 802 uint16_t IRQNUM:5; /*!< bit: 1.. 5 Interrupt Request Number */ 803 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 804 uint16_t OVERRIDE:8; /*!< bit: 8..15 Interrupt Request Override Value */ 805 } bit; /*!< Structure used for bit access */ 806 uint16_t reg; /*!< Type used for register access */ 807 } TAL_IRQTRIG_Type; 808 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 809 810 #define TAL_IRQTRIG_OFFSET 0x60 /**< \brief (TAL_IRQTRIG offset) Interrupt Trigger */ 811 #define TAL_IRQTRIG_RESETVALUE _U(0x0000) /**< \brief (TAL_IRQTRIG reset_value) Interrupt Trigger */ 812 813 #define TAL_IRQTRIG_ENABLE_Pos 0 /**< \brief (TAL_IRQTRIG) Trigger Enable */ 814 #define TAL_IRQTRIG_ENABLE (_U(0x1) << TAL_IRQTRIG_ENABLE_Pos) 815 #define TAL_IRQTRIG_IRQNUM_Pos 1 /**< \brief (TAL_IRQTRIG) Interrupt Request Number */ 816 #define TAL_IRQTRIG_IRQNUM_Msk (_U(0x1F) << TAL_IRQTRIG_IRQNUM_Pos) 817 #define TAL_IRQTRIG_IRQNUM(value) (TAL_IRQTRIG_IRQNUM_Msk & ((value) << TAL_IRQTRIG_IRQNUM_Pos)) 818 #define TAL_IRQTRIG_OVERRIDE_Pos 8 /**< \brief (TAL_IRQTRIG) Interrupt Request Override Value */ 819 #define TAL_IRQTRIG_OVERRIDE_Msk (_U(0xFF) << TAL_IRQTRIG_OVERRIDE_Pos) 820 #define TAL_IRQTRIG_OVERRIDE(value) (TAL_IRQTRIG_OVERRIDE_Msk & ((value) << TAL_IRQTRIG_OVERRIDE_Pos)) 821 #define TAL_IRQTRIG_MASK _U(0xFF3F) /**< \brief (TAL_IRQTRIG) MASK Register */ 822 823 /* -------- TAL_CPUIRQS : (TAL Offset: 0x64) (R/ 32) Interrupt Status for CPU n -------- */ 824 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 825 typedef union { 826 struct { 827 uint32_t CPUIRQS:29; /*!< bit: 0..28 Interrupt Requests for CPU n */ 828 uint32_t :3; /*!< bit: 29..31 Reserved */ 829 } bit; /*!< Structure used for bit access */ 830 uint32_t reg; /*!< Type used for register access */ 831 } TAL_CPUIRQS_Type; 832 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 833 834 #define TAL_CPUIRQS_OFFSET 0x64 /**< \brief (TAL_CPUIRQS offset) Interrupt Status for CPU n */ 835 #define TAL_CPUIRQS_RESETVALUE _U(0x00000000) /**< \brief (TAL_CPUIRQS reset_value) Interrupt Status for CPU n */ 836 837 #define TAL_CPUIRQS_CPUIRQS_Pos 0 /**< \brief (TAL_CPUIRQS) Interrupt Requests for CPU n */ 838 #define TAL_CPUIRQS_CPUIRQS_Msk (_U(0x1FFFFFFF) << TAL_CPUIRQS_CPUIRQS_Pos) 839 #define TAL_CPUIRQS_CPUIRQS(value) (TAL_CPUIRQS_CPUIRQS_Msk & ((value) << TAL_CPUIRQS_CPUIRQS_Pos)) 840 #define TAL_CPUIRQS_MASK _U(0x1FFFFFFF) /**< \brief (TAL_CPUIRQS) MASK Register */ 841 842 /** \brief TalCtis hardware registers */ 843 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 844 typedef struct { 845 __IO TAL_CTICTRLA_Type CTICTRLA; /**< \brief Offset: 0x00 (R/W 8) Cross-Trigger Interface n Control A */ 846 __IO TAL_CTIMASK_Type CTIMASK; /**< \brief Offset: 0x01 (R/W 8) Cross-Trigger Interface n Mask */ 847 } TalCtis; 848 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 849 850 /** \brief TAL hardware registers */ 851 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 852 typedef struct { 853 __IO TAL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 854 RoReg8 Reserved1[0x3]; 855 __IO TAL_RSTCTRL_Type RSTCTRL; /**< \brief Offset: 0x04 (R/W 8) Reset Control */ 856 __IO TAL_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x05 (R/W 8) External Break Control */ 857 __IO TAL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 8) Event Control */ 858 RoReg8 Reserved2[0x1]; 859 __IO TAL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 860 __IO TAL_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 861 __IO TAL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 862 __IO TAL_GLOBMASK_Type GLOBMASK; /**< \brief Offset: 0x0B (R/W 8) Global Break Requests Mask */ 863 __O TAL_HALT_Type HALT; /**< \brief Offset: 0x0C ( /W 8) Debug Halt Request */ 864 __O TAL_RESTART_Type RESTART; /**< \brief Offset: 0x0D ( /W 8) Debug Restart Request */ 865 __I TAL_BRKSTATUS_Type BRKSTATUS; /**< \brief Offset: 0x0E (R/ 16) Break Request Status */ 866 TalCtis Ctis[4]; /**< \brief Offset: 0x10 TalCtis groups [CTI_NUM] */ 867 RoReg8 Reserved3[0x8]; 868 __I TAL_INTSTATUS_Type INTSTATUS[29]; /**< \brief Offset: 0x20 (R/ 8) Interrupt n Status */ 869 RoReg8 Reserved4[0x3]; 870 __IO TAL_DMACPUSEL0_Type DMACPUSEL0; /**< \brief Offset: 0x40 (R/W 32) DMA Channel Interrupts CPU Select 0 */ 871 RoReg8 Reserved5[0x4]; 872 __IO TAL_EVCPUSEL0_Type EVCPUSEL0; /**< \brief Offset: 0x48 (R/W 32) EVSYS Channel Interrupts CPU Select 0 */ 873 RoReg8 Reserved6[0x4]; 874 __IO TAL_EICCPUSEL0_Type EICCPUSEL0; /**< \brief Offset: 0x50 (R/W 32) EIC External Interrupts CPU Select 0 */ 875 RoReg8 Reserved7[0x4]; 876 __IO TAL_INTCPUSEL0_Type INTCPUSEL0; /**< \brief Offset: 0x58 (R/W 32) Interrupts CPU Select 0 */ 877 __IO TAL_INTCPUSEL1_Type INTCPUSEL1; /**< \brief Offset: 0x5C (R/W 32) Interrupts CPU Select 1 */ 878 __IO TAL_IRQTRIG_Type IRQTRIG; /**< \brief Offset: 0x60 (R/W 16) Interrupt Trigger */ 879 RoReg8 Reserved8[0x2]; 880 __I TAL_CPUIRQS_Type CPUIRQS[2]; /**< \brief Offset: 0x64 (R/ 32) Interrupt Status for CPU n */ 881 } Tal; 882 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 883 884 /*@}*/ 885 886 #endif /* _SAML21_TAL_COMPONENT_ */ 887
