1 /*! 2 * \file sx1272Regs-Fsk.h 3 * 4 * \brief SX1272 FSK modem registers and bits definitions 5 * 6 * \copyright Revised BSD License, see section \ref LICENSE. 7 * 8 * \code 9 * ______ _ 10 * / _____) _ | | 11 * ( (____ _____ ____ _| |_ _____ ____| |__ 12 * \____ \| ___ | (_ _) ___ |/ ___) _ \ 13 * _____) ) ____| | | || |_| ____( (___| | | | 14 * (______/|_____)_|_|_| \__)_____)\____)_| |_| 15 * (C)2013-2017 Semtech 16 * 17 * \endcode 18 * 19 * \author Miguel Luis ( Semtech ) 20 * 21 * \author Gregory Cristian ( Semtech ) 22 */ 23 #ifndef __SX1272_REGS_FSK_H__ 24 #define __SX1272_REGS_FSK_H__ 25 26 #ifdef __cplusplus 27 extern "C" 28 { 29 #endif 30 31 /*! 32 * ============================================================================ 33 * SX1272 Internal registers Address 34 * ============================================================================ 35 */ 36 #define REG_FIFO 0x00 37 // Common settings 38 #define REG_OPMODE 0x01 39 #define REG_BITRATEMSB 0x02 40 #define REG_BITRATELSB 0x03 41 #define REG_FDEVMSB 0x04 42 #define REG_FDEVLSB 0x05 43 #define REG_FRFMSB 0x06 44 #define REG_FRFMID 0x07 45 #define REG_FRFLSB 0x08 46 // Tx settings 47 #define REG_PACONFIG 0x09 48 #define REG_PARAMP 0x0A 49 #define REG_OCP 0x0B 50 // Rx settings 51 #define REG_LNA 0x0C 52 #define REG_RXCONFIG 0x0D 53 #define REG_RSSICONFIG 0x0E 54 #define REG_RSSICOLLISION 0x0F 55 #define REG_RSSITHRESH 0x10 56 #define REG_RSSIVALUE 0x11 57 #define REG_RXBW 0x12 58 #define REG_AFCBW 0x13 59 #define REG_OOKPEAK 0x14 60 #define REG_OOKFIX 0x15 61 #define REG_OOKAVG 0x16 62 #define REG_RES17 0x17 63 #define REG_RES18 0x18 64 #define REG_RES19 0x19 65 #define REG_AFCFEI 0x1A 66 #define REG_AFCMSB 0x1B 67 #define REG_AFCLSB 0x1C 68 #define REG_FEIMSB 0x1D 69 #define REG_FEILSB 0x1E 70 #define REG_PREAMBLEDETECT 0x1F 71 #define REG_RXTIMEOUT1 0x20 72 #define REG_RXTIMEOUT2 0x21 73 #define REG_RXTIMEOUT3 0x22 74 #define REG_RXDELAY 0x23 75 // Oscillator settings 76 #define REG_OSC 0x24 77 // Packet handler settings 78 #define REG_PREAMBLEMSB 0x25 79 #define REG_PREAMBLELSB 0x26 80 #define REG_SYNCCONFIG 0x27 81 #define REG_SYNCVALUE1 0x28 82 #define REG_SYNCVALUE2 0x29 83 #define REG_SYNCVALUE3 0x2A 84 #define REG_SYNCVALUE4 0x2B 85 #define REG_SYNCVALUE5 0x2C 86 #define REG_SYNCVALUE6 0x2D 87 #define REG_SYNCVALUE7 0x2E 88 #define REG_SYNCVALUE8 0x2F 89 #define REG_PACKETCONFIG1 0x30 90 #define REG_PACKETCONFIG2 0x31 91 #define REG_PAYLOADLENGTH 0x32 92 #define REG_NODEADRS 0x33 93 #define REG_BROADCASTADRS 0x34 94 #define REG_FIFOTHRESH 0x35 95 // SM settings 96 #define REG_SEQCONFIG1 0x36 97 #define REG_SEQCONFIG2 0x37 98 #define REG_TIMERRESOL 0x38 99 #define REG_TIMER1COEF 0x39 100 #define REG_TIMER2COEF 0x3A 101 // Service settings 102 #define REG_IMAGECAL 0x3B 103 #define REG_TEMP 0x3C 104 #define REG_LOWBAT 0x3D 105 // Status 106 #define REG_IRQFLAGS1 0x3E 107 #define REG_IRQFLAGS2 0x3F 108 // I/O settings 109 #define REG_DIOMAPPING1 0x40 110 #define REG_DIOMAPPING2 0x41 111 // Version 112 #define REG_VERSION 0x42 113 // Additional settings 114 #define REG_AGCREF 0x43 115 #define REG_AGCTHRESH1 0x44 116 #define REG_AGCTHRESH2 0x45 117 #define REG_AGCTHRESH3 0x46 118 #define REG_PLLHOP 0x4B 119 #define REG_TCXO 0x58 120 #define REG_PADAC 0x5A 121 #define REG_PLL 0x5C 122 #define REG_PLLLOWPN 0x5E 123 #define REG_FORMERTEMP 0x6C 124 #define REG_BITRATEFRAC 0x70 125 126 /*! 127 * ============================================================================ 128 * SX1272 FSK bits control definition 129 * ============================================================================ 130 */ 131 132 /*! 133 * RegFifo 134 */ 135 136 /*! 137 * RegOpMode 138 */ 139 #define RF_OPMODE_LONGRANGEMODE_MASK 0x7F 140 #define RF_OPMODE_LONGRANGEMODE_OFF 0x00 141 #define RF_OPMODE_LONGRANGEMODE_ON 0x80 142 143 #define RF_OPMODE_MODULATIONTYPE_MASK 0x9F 144 #define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default 145 #define RF_OPMODE_MODULATIONTYPE_OOK 0x20 146 147 #define RF_OPMODE_MODULATIONSHAPING_MASK 0xE7 148 #define RF_OPMODE_MODULATIONSHAPING_00 0x00 // Default 149 #define RF_OPMODE_MODULATIONSHAPING_01 0x08 150 #define RF_OPMODE_MODULATIONSHAPING_10 0x10 151 #define RF_OPMODE_MODULATIONSHAPING_11 0x18 152 153 #define RF_OPMODE_MASK 0xF8 154 #define RF_OPMODE_SLEEP 0x00 155 #define RF_OPMODE_STANDBY 0x01 // Default 156 #define RF_OPMODE_SYNTHESIZER_TX 0x02 157 #define RF_OPMODE_TRANSMITTER 0x03 158 #define RF_OPMODE_SYNTHESIZER_RX 0x04 159 #define RF_OPMODE_RECEIVER 0x05 160 161 /*! 162 * RegBitRate (bits/sec) 163 */ 164 #define RF_BITRATEMSB_1200_BPS 0x68 165 #define RF_BITRATELSB_1200_BPS 0x2B 166 #define RF_BITRATEMSB_2400_BPS 0x34 167 #define RF_BITRATELSB_2400_BPS 0x15 168 #define RF_BITRATEMSB_4800_BPS 0x1A // Default 169 #define RF_BITRATELSB_4800_BPS 0x0B // Default 170 #define RF_BITRATEMSB_9600_BPS 0x0D 171 #define RF_BITRATELSB_9600_BPS 0x05 172 #define RF_BITRATEMSB_15000_BPS 0x08 173 #define RF_BITRATELSB_15000_BPS 0x55 174 #define RF_BITRATEMSB_19200_BPS 0x06 175 #define RF_BITRATELSB_19200_BPS 0x83 176 #define RF_BITRATEMSB_38400_BPS 0x03 177 #define RF_BITRATELSB_38400_BPS 0x41 178 #define RF_BITRATEMSB_76800_BPS 0x01 179 #define RF_BITRATELSB_76800_BPS 0xA1 180 #define RF_BITRATEMSB_153600_BPS 0x00 181 #define RF_BITRATELSB_153600_BPS 0xD0 182 #define RF_BITRATEMSB_57600_BPS 0x02 183 #define RF_BITRATELSB_57600_BPS 0x2C 184 #define RF_BITRATEMSB_115200_BPS 0x01 185 #define RF_BITRATELSB_115200_BPS 0x16 186 #define RF_BITRATEMSB_12500_BPS 0x0A 187 #define RF_BITRATELSB_12500_BPS 0x00 188 #define RF_BITRATEMSB_25000_BPS 0x05 189 #define RF_BITRATELSB_25000_BPS 0x00 190 #define RF_BITRATEMSB_50000_BPS 0x02 191 #define RF_BITRATELSB_50000_BPS 0x80 192 #define RF_BITRATEMSB_100000_BPS 0x01 193 #define RF_BITRATELSB_100000_BPS 0x40 194 #define RF_BITRATEMSB_150000_BPS 0x00 195 #define RF_BITRATELSB_150000_BPS 0xD5 196 #define RF_BITRATEMSB_200000_BPS 0x00 197 #define RF_BITRATELSB_200000_BPS 0xA0 198 #define RF_BITRATEMSB_250000_BPS 0x00 199 #define RF_BITRATELSB_250000_BPS 0x80 200 #define RF_BITRATEMSB_32768_BPS 0x03 201 #define RF_BITRATELSB_32768_BPS 0xD1 202 203 /*! 204 * RegFdev (Hz) 205 */ 206 #define RF_FDEVMSB_2000_HZ 0x00 207 #define RF_FDEVLSB_2000_HZ 0x21 208 #define RF_FDEVMSB_5000_HZ 0x00 // Default 209 #define RF_FDEVLSB_5000_HZ 0x52 // Default 210 #define RF_FDEVMSB_10000_HZ 0x00 211 #define RF_FDEVLSB_10000_HZ 0xA4 212 #define RF_FDEVMSB_15000_HZ 0x00 213 #define RF_FDEVLSB_15000_HZ 0xF6 214 #define RF_FDEVMSB_20000_HZ 0x01 215 #define RF_FDEVLSB_20000_HZ 0x48 216 #define RF_FDEVMSB_25000_HZ 0x01 217 #define RF_FDEVLSB_25000_HZ 0x9A 218 #define RF_FDEVMSB_30000_HZ 0x01 219 #define RF_FDEVLSB_30000_HZ 0xEC 220 #define RF_FDEVMSB_35000_HZ 0x02 221 #define RF_FDEVLSB_35000_HZ 0x3D 222 #define RF_FDEVMSB_40000_HZ 0x02 223 #define RF_FDEVLSB_40000_HZ 0x8F 224 #define RF_FDEVMSB_45000_HZ 0x02 225 #define RF_FDEVLSB_45000_HZ 0xE1 226 #define RF_FDEVMSB_50000_HZ 0x03 227 #define RF_FDEVLSB_50000_HZ 0x33 228 #define RF_FDEVMSB_55000_HZ 0x03 229 #define RF_FDEVLSB_55000_HZ 0x85 230 #define RF_FDEVMSB_60000_HZ 0x03 231 #define RF_FDEVLSB_60000_HZ 0xD7 232 #define RF_FDEVMSB_65000_HZ 0x04 233 #define RF_FDEVLSB_65000_HZ 0x29 234 #define RF_FDEVMSB_70000_HZ 0x04 235 #define RF_FDEVLSB_70000_HZ 0x7B 236 #define RF_FDEVMSB_75000_HZ 0x04 237 #define RF_FDEVLSB_75000_HZ 0xCD 238 #define RF_FDEVMSB_80000_HZ 0x05 239 #define RF_FDEVLSB_80000_HZ 0x1F 240 #define RF_FDEVMSB_85000_HZ 0x05 241 #define RF_FDEVLSB_85000_HZ 0x71 242 #define RF_FDEVMSB_90000_HZ 0x05 243 #define RF_FDEVLSB_90000_HZ 0xC3 244 #define RF_FDEVMSB_95000_HZ 0x06 245 #define RF_FDEVLSB_95000_HZ 0x14 246 #define RF_FDEVMSB_100000_HZ 0x06 247 #define RF_FDEVLSB_100000_HZ 0x66 248 #define RF_FDEVMSB_110000_HZ 0x07 249 #define RF_FDEVLSB_110000_HZ 0x0A 250 #define RF_FDEVMSB_120000_HZ 0x07 251 #define RF_FDEVLSB_120000_HZ 0xAE 252 #define RF_FDEVMSB_130000_HZ 0x08 253 #define RF_FDEVLSB_130000_HZ 0x52 254 #define RF_FDEVMSB_140000_HZ 0x08 255 #define RF_FDEVLSB_140000_HZ 0xF6 256 #define RF_FDEVMSB_150000_HZ 0x09 257 #define RF_FDEVLSB_150000_HZ 0x9A 258 #define RF_FDEVMSB_160000_HZ 0x0A 259 #define RF_FDEVLSB_160000_HZ 0x3D 260 #define RF_FDEVMSB_170000_HZ 0x0A 261 #define RF_FDEVLSB_170000_HZ 0xE1 262 #define RF_FDEVMSB_180000_HZ 0x0B 263 #define RF_FDEVLSB_180000_HZ 0x85 264 #define RF_FDEVMSB_190000_HZ 0x0C 265 #define RF_FDEVLSB_190000_HZ 0x29 266 #define RF_FDEVMSB_200000_HZ 0x0C 267 #define RF_FDEVLSB_200000_HZ 0xCD 268 269 /*! 270 * RegFrf (MHz) 271 */ 272 #define RF_FRFMSB_863_MHZ 0xD7 273 #define RF_FRFMID_863_MHZ 0xC0 274 #define RF_FRFLSB_863_MHZ 0x00 275 #define RF_FRFMSB_864_MHZ 0xD8 276 #define RF_FRFMID_864_MHZ 0x00 277 #define RF_FRFLSB_864_MHZ 0x00 278 #define RF_FRFMSB_865_MHZ 0xD8 279 #define RF_FRFMID_865_MHZ 0x40 280 #define RF_FRFLSB_865_MHZ 0x00 281 #define RF_FRFMSB_866_MHZ 0xD8 282 #define RF_FRFMID_866_MHZ 0x80 283 #define RF_FRFLSB_866_MHZ 0x00 284 #define RF_FRFMSB_867_MHZ 0xD8 285 #define RF_FRFMID_867_MHZ 0xC0 286 #define RF_FRFLSB_867_MHZ 0x00 287 #define RF_FRFMSB_868_MHZ 0xD9 288 #define RF_FRFMID_868_MHZ 0x00 289 #define RF_FRFLSB_868_MHZ 0x00 290 #define RF_FRFMSB_869_MHZ 0xD9 291 #define RF_FRFMID_869_MHZ 0x40 292 #define RF_FRFLSB_869_MHZ 0x00 293 #define RF_FRFMSB_870_MHZ 0xD9 294 #define RF_FRFMID_870_MHZ 0x80 295 #define RF_FRFLSB_870_MHZ 0x00 296 297 #define RF_FRFMSB_902_MHZ 0xE1 298 #define RF_FRFMID_902_MHZ 0x80 299 #define RF_FRFLSB_902_MHZ 0x00 300 #define RF_FRFMSB_903_MHZ 0xE1 301 #define RF_FRFMID_903_MHZ 0xC0 302 #define RF_FRFLSB_903_MHZ 0x00 303 #define RF_FRFMSB_904_MHZ 0xE2 304 #define RF_FRFMID_904_MHZ 0x00 305 #define RF_FRFLSB_904_MHZ 0x00 306 #define RF_FRFMSB_905_MHZ 0xE2 307 #define RF_FRFMID_905_MHZ 0x40 308 #define RF_FRFLSB_905_MHZ 0x00 309 #define RF_FRFMSB_906_MHZ 0xE2 310 #define RF_FRFMID_906_MHZ 0x80 311 #define RF_FRFLSB_906_MHZ 0x00 312 #define RF_FRFMSB_907_MHZ 0xE2 313 #define RF_FRFMID_907_MHZ 0xC0 314 #define RF_FRFLSB_907_MHZ 0x00 315 #define RF_FRFMSB_908_MHZ 0xE3 316 #define RF_FRFMID_908_MHZ 0x00 317 #define RF_FRFLSB_908_MHZ 0x00 318 #define RF_FRFMSB_909_MHZ 0xE3 319 #define RF_FRFMID_909_MHZ 0x40 320 #define RF_FRFLSB_909_MHZ 0x00 321 #define RF_FRFMSB_910_MHZ 0xE3 322 #define RF_FRFMID_910_MHZ 0x80 323 #define RF_FRFLSB_910_MHZ 0x00 324 #define RF_FRFMSB_911_MHZ 0xE3 325 #define RF_FRFMID_911_MHZ 0xC0 326 #define RF_FRFLSB_911_MHZ 0x00 327 #define RF_FRFMSB_912_MHZ 0xE4 328 #define RF_FRFMID_912_MHZ 0x00 329 #define RF_FRFLSB_912_MHZ 0x00 330 #define RF_FRFMSB_913_MHZ 0xE4 331 #define RF_FRFMID_913_MHZ 0x40 332 #define RF_FRFLSB_913_MHZ 0x00 333 #define RF_FRFMSB_914_MHZ 0xE4 334 #define RF_FRFMID_914_MHZ 0x80 335 #define RF_FRFLSB_914_MHZ 0x00 336 #define RF_FRFMSB_915_MHZ 0xE4 // Default 337 #define RF_FRFMID_915_MHZ 0xC0 // Default 338 #define RF_FRFLSB_915_MHZ 0x00 // Default 339 #define RF_FRFMSB_916_MHZ 0xE5 340 #define RF_FRFMID_916_MHZ 0x00 341 #define RF_FRFLSB_916_MHZ 0x00 342 #define RF_FRFMSB_917_MHZ 0xE5 343 #define RF_FRFMID_917_MHZ 0x40 344 #define RF_FRFLSB_917_MHZ 0x00 345 #define RF_FRFMSB_918_MHZ 0xE5 346 #define RF_FRFMID_918_MHZ 0x80 347 #define RF_FRFLSB_918_MHZ 0x00 348 #define RF_FRFMSB_919_MHZ 0xE5 349 #define RF_FRFMID_919_MHZ 0xC0 350 #define RF_FRFLSB_919_MHZ 0x00 351 #define RF_FRFMSB_920_MHZ 0xE6 352 #define RF_FRFMID_920_MHZ 0x00 353 #define RF_FRFLSB_920_MHZ 0x00 354 #define RF_FRFMSB_921_MHZ 0xE6 355 #define RF_FRFMID_921_MHZ 0x40 356 #define RF_FRFLSB_921_MHZ 0x00 357 #define RF_FRFMSB_922_MHZ 0xE6 358 #define RF_FRFMID_922_MHZ 0x80 359 #define RF_FRFLSB_922_MHZ 0x00 360 #define RF_FRFMSB_923_MHZ 0xE6 361 #define RF_FRFMID_923_MHZ 0xC0 362 #define RF_FRFLSB_923_MHZ 0x00 363 #define RF_FRFMSB_924_MHZ 0xE7 364 #define RF_FRFMID_924_MHZ 0x00 365 #define RF_FRFLSB_924_MHZ 0x00 366 #define RF_FRFMSB_925_MHZ 0xE7 367 #define RF_FRFMID_925_MHZ 0x40 368 #define RF_FRFLSB_925_MHZ 0x00 369 #define RF_FRFMSB_926_MHZ 0xE7 370 #define RF_FRFMID_926_MHZ 0x80 371 #define RF_FRFLSB_926_MHZ 0x00 372 #define RF_FRFMSB_927_MHZ 0xE7 373 #define RF_FRFMID_927_MHZ 0xC0 374 #define RF_FRFLSB_927_MHZ 0x00 375 #define RF_FRFMSB_928_MHZ 0xE8 376 #define RF_FRFMID_928_MHZ 0x00 377 #define RF_FRFLSB_928_MHZ 0x00 378 379 /*! 380 * RegPaConfig 381 */ 382 #define RF_PACONFIG_PASELECT_MASK 0x7F 383 #define RF_PACONFIG_PASELECT_PABOOST 0x80 384 #define RF_PACONFIG_PASELECT_RFO 0x00 // Default 385 386 #define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0 387 388 /*! 389 * RegPaRamp 390 */ 391 #define RF_PARAMP_LOWPNTXPLL_MASK 0xEF 392 #define RF_PARAMP_LOWPNTXPLL_OFF 0x10 // Default 393 #define RF_PARAMP_LOWPNTXPLL_ON 0x00 394 395 #define RF_PARAMP_MASK 0xF0 396 #define RF_PARAMP_3400_US 0x00 397 #define RF_PARAMP_2000_US 0x01 398 #define RF_PARAMP_1000_US 0x02 399 #define RF_PARAMP_0500_US 0x03 400 #define RF_PARAMP_0250_US 0x04 401 #define RF_PARAMP_0125_US 0x05 402 #define RF_PARAMP_0100_US 0x06 403 #define RF_PARAMP_0062_US 0x07 404 #define RF_PARAMP_0050_US 0x08 405 #define RF_PARAMP_0040_US 0x09 // Default 406 #define RF_PARAMP_0031_US 0x0A 407 #define RF_PARAMP_0025_US 0x0B 408 #define RF_PARAMP_0020_US 0x0C 409 #define RF_PARAMP_0015_US 0x0D 410 #define RF_PARAMP_0012_US 0x0E 411 #define RF_PARAMP_0010_US 0x0F 412 413 /*! 414 * RegOcp 415 */ 416 #define RF_OCP_MASK 0xDF 417 #define RF_OCP_ON 0x20 // Default 418 #define RF_OCP_OFF 0x00 419 420 #define RF_OCP_TRIM_MASK 0xE0 421 #define RF_OCP_TRIM_045_MA 0x00 422 #define RF_OCP_TRIM_050_MA 0x01 423 #define RF_OCP_TRIM_055_MA 0x02 424 #define RF_OCP_TRIM_060_MA 0x03 425 #define RF_OCP_TRIM_065_MA 0x04 426 #define RF_OCP_TRIM_070_MA 0x05 427 #define RF_OCP_TRIM_075_MA 0x06 428 #define RF_OCP_TRIM_080_MA 0x07 429 #define RF_OCP_TRIM_085_MA 0x08 430 #define RF_OCP_TRIM_090_MA 0x09 431 #define RF_OCP_TRIM_095_MA 0x0A 432 #define RF_OCP_TRIM_100_MA 0x0B // Default 433 #define RF_OCP_TRIM_105_MA 0x0C 434 #define RF_OCP_TRIM_110_MA 0x0D 435 #define RF_OCP_TRIM_115_MA 0x0E 436 #define RF_OCP_TRIM_120_MA 0x0F 437 #define RF_OCP_TRIM_130_MA 0x10 438 #define RF_OCP_TRIM_140_MA 0x11 439 #define RF_OCP_TRIM_150_MA 0x12 440 #define RF_OCP_TRIM_160_MA 0x13 441 #define RF_OCP_TRIM_170_MA 0x14 442 #define RF_OCP_TRIM_180_MA 0x15 443 #define RF_OCP_TRIM_190_MA 0x16 444 #define RF_OCP_TRIM_200_MA 0x17 445 #define RF_OCP_TRIM_210_MA 0x18 446 #define RF_OCP_TRIM_220_MA 0x19 447 #define RF_OCP_TRIM_230_MA 0x1A 448 #define RF_OCP_TRIM_240_MA 0x1B 449 450 /*! 451 * RegLna 452 */ 453 #define RF_LNA_GAIN_MASK 0x1F 454 #define RF_LNA_GAIN_G1 0x20 // Default 455 #define RF_LNA_GAIN_G2 0x40 456 #define RF_LNA_GAIN_G3 0x60 457 #define RF_LNA_GAIN_G4 0x80 458 #define RF_LNA_GAIN_G5 0xA0 459 #define RF_LNA_GAIN_G6 0xC0 460 461 #define RF_LNA_BOOST_MASK 0xFC 462 #define RF_LNA_BOOST_OFF 0x00 // Default 463 #define RF_LNA_BOOST_ON 0x03 464 465 /*! 466 * RegRxConfig 467 */ 468 #define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F 469 #define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80 470 #define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default 471 472 #define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only 473 474 #define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only 475 476 #define RF_RXCONFIG_AFCAUTO_MASK 0xEF 477 #define RF_RXCONFIG_AFCAUTO_ON 0x10 478 #define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default 479 480 #define RF_RXCONFIG_AGCAUTO_MASK 0xF7 481 #define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default 482 #define RF_RXCONFIG_AGCAUTO_OFF 0x00 483 484 #define RF_RXCONFIG_RXTRIGER_MASK 0xF8 485 #define RF_RXCONFIG_RXTRIGER_OFF 0x00 486 #define RF_RXCONFIG_RXTRIGER_RSSI 0x01 487 #define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default 488 #define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07 489 490 /*! 491 * RegRssiConfig 492 */ 493 #define RF_RSSICONFIG_OFFSET_MASK 0x07 494 #define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default 495 #define RF_RSSICONFIG_OFFSET_P_01_DB 0x08 496 #define RF_RSSICONFIG_OFFSET_P_02_DB 0x10 497 #define RF_RSSICONFIG_OFFSET_P_03_DB 0x18 498 #define RF_RSSICONFIG_OFFSET_P_04_DB 0x20 499 #define RF_RSSICONFIG_OFFSET_P_05_DB 0x28 500 #define RF_RSSICONFIG_OFFSET_P_06_DB 0x30 501 #define RF_RSSICONFIG_OFFSET_P_07_DB 0x38 502 #define RF_RSSICONFIG_OFFSET_P_08_DB 0x40 503 #define RF_RSSICONFIG_OFFSET_P_09_DB 0x48 504 #define RF_RSSICONFIG_OFFSET_P_10_DB 0x50 505 #define RF_RSSICONFIG_OFFSET_P_11_DB 0x58 506 #define RF_RSSICONFIG_OFFSET_P_12_DB 0x60 507 #define RF_RSSICONFIG_OFFSET_P_13_DB 0x68 508 #define RF_RSSICONFIG_OFFSET_P_14_DB 0x70 509 #define RF_RSSICONFIG_OFFSET_P_15_DB 0x78 510 #define RF_RSSICONFIG_OFFSET_M_16_DB 0x80 511 #define RF_RSSICONFIG_OFFSET_M_15_DB 0x88 512 #define RF_RSSICONFIG_OFFSET_M_14_DB 0x90 513 #define RF_RSSICONFIG_OFFSET_M_13_DB 0x98 514 #define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0 515 #define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8 516 #define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0 517 #define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8 518 #define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0 519 #define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8 520 #define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0 521 #define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8 522 #define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0 523 #define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8 524 #define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0 525 #define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8 526 527 #define RF_RSSICONFIG_SMOOTHING_MASK 0xF8 528 #define RF_RSSICONFIG_SMOOTHING_2 0x00 529 #define RF_RSSICONFIG_SMOOTHING_4 0x01 530 #define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default 531 #define RF_RSSICONFIG_SMOOTHING_16 0x03 532 #define RF_RSSICONFIG_SMOOTHING_32 0x04 533 #define RF_RSSICONFIG_SMOOTHING_64 0x05 534 #define RF_RSSICONFIG_SMOOTHING_128 0x06 535 #define RF_RSSICONFIG_SMOOTHING_256 0x07 536 537 /*! 538 * RegRssiCollision 539 */ 540 #define RF_RSSICOLISION_THRESHOLD 0x0A // Default 541 542 /*! 543 * RegRssiThresh 544 */ 545 #define RF_RSSITHRESH_THRESHOLD 0xFF // Default 546 547 /*! 548 * RegRssiValue (Read Only) 549 */ 550 551 /*! 552 * RegRxBw 553 */ 554 #define RF_RXBW_MANT_MASK 0xE7 555 #define RF_RXBW_MANT_16 0x00 556 #define RF_RXBW_MANT_20 0x08 557 #define RF_RXBW_MANT_24 0x10 // Default 558 559 #define RF_RXBW_EXP_MASK 0xF8 560 #define RF_RXBW_EXP_0 0x00 561 #define RF_RXBW_EXP_1 0x01 562 #define RF_RXBW_EXP_2 0x02 563 #define RF_RXBW_EXP_3 0x03 564 #define RF_RXBW_EXP_4 0x04 565 #define RF_RXBW_EXP_5 0x05 // Default 566 #define RF_RXBW_EXP_6 0x06 567 #define RF_RXBW_EXP_7 0x07 568 569 /*! 570 * RegAfcBw 571 */ 572 #define RF_AFCBW_MANTAFC_MASK 0xE7 573 #define RF_AFCBW_MANTAFC_16 0x00 574 #define RF_AFCBW_MANTAFC_20 0x08 // Default 575 #define RF_AFCBW_MANTAFC_24 0x10 576 577 #define RF_AFCBW_EXPAFC_MASK 0xF8 578 #define RF_AFCBW_EXPAFC_0 0x00 579 #define RF_AFCBW_EXPAFC_1 0x01 580 #define RF_AFCBW_EXPAFC_2 0x02 581 #define RF_AFCBW_EXPAFC_3 0x03 // Default 582 #define RF_AFCBW_EXPAFC_4 0x04 583 #define RF_AFCBW_EXPAFC_5 0x05 584 #define RF_AFCBW_EXPAFC_6 0x06 585 #define RF_AFCBW_EXPAFC_7 0x07 586 587 /*! 588 * RegOokPeak 589 */ 590 #define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default 591 #define RF_OOKPEAK_BITSYNC_ON 0x20 // Default 592 #define RF_OOKPEAK_BITSYNC_OFF 0x00 593 594 #define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7 595 #define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00 596 #define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default 597 #define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10 598 599 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8 600 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default 601 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01 602 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02 603 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03 604 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04 605 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05 606 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06 607 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07 608 609 /*! 610 * RegOokFix 611 */ 612 #define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default 613 614 /*! 615 * RegOokAvg 616 */ 617 #define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F 618 #define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default 619 #define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20 620 #define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40 621 #define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60 622 #define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80 623 #define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0 624 #define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0 625 #define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0 626 627 #define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3 628 #define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default 629 #define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04 630 #define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08 631 #define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C 632 633 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC 634 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00 635 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01 636 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default 637 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03 638 639 /*! 640 * RegAfcFei 641 */ 642 #define RF_AFCFEI_AGCSTART 0x10 643 644 #define RF_AFCFEI_AFCCLEAR 0x02 645 646 #define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE 647 #define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01 648 #define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default 649 650 /*! 651 * RegAfcMsb (Read Only) 652 */ 653 654 /*! 655 * RegAfcLsb (Read Only) 656 */ 657 658 /*! 659 * RegFeiMsb (Read Only) 660 */ 661 662 /*! 663 * RegFeiLsb (Read Only) 664 */ 665 666 /*! 667 * RegPreambleDetect 668 */ 669 #define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F 670 #define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default 671 #define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00 672 673 #define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F 674 #define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00 675 #define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default 676 #define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40 677 #define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60 678 679 #define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0 680 #define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00 681 #define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01 682 #define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02 683 #define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03 684 #define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04 685 #define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05 686 #define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06 687 #define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07 688 #define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08 689 #define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09 690 #define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default 691 #define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B 692 #define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C 693 #define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D 694 #define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E 695 #define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F 696 #define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10 697 #define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11 698 #define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12 699 #define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13 700 #define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14 701 #define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15 702 #define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16 703 #define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17 704 #define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18 705 #define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19 706 #define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A 707 #define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B 708 #define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C 709 #define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D 710 #define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E 711 #define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F 712 713 /*! 714 * RegRxTimeout1 715 */ 716 #define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default 717 718 /*! 719 * RegRxTimeout2 720 */ 721 #define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default 722 723 /*! 724 * RegRxTimeout3 725 */ 726 #define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default 727 728 /*! 729 * RegRxDelay 730 */ 731 #define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default 732 733 /*! 734 * RegOsc 735 */ 736 #define RF_OSC_RCCALSTART 0x08 737 738 #define RF_OSC_CLKOUT_MASK 0xF8 739 #define RF_OSC_CLKOUT_32_MHZ 0x00 740 #define RF_OSC_CLKOUT_16_MHZ 0x01 741 #define RF_OSC_CLKOUT_8_MHZ 0x02 742 #define RF_OSC_CLKOUT_4_MHZ 0x03 743 #define RF_OSC_CLKOUT_2_MHZ 0x04 744 #define RF_OSC_CLKOUT_1_MHZ 0x05 745 #define RF_OSC_CLKOUT_RC 0x06 746 #define RF_OSC_CLKOUT_OFF 0x07 // Default 747 748 /*! 749 * RegPreambleMsb/RegPreambleLsb 750 */ 751 #define RF_PREAMBLEMSB_SIZE 0x00 // Default 752 #define RF_PREAMBLELSB_SIZE 0x03 // Default 753 754 /*! 755 * RegSyncConfig 756 */ 757 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F 758 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default 759 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40 760 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00 761 762 763 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF 764 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20 765 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default 766 767 #define RF_SYNCCONFIG_SYNC_MASK 0xEF 768 #define RF_SYNCCONFIG_SYNC_ON 0x10 // Default 769 #define RF_SYNCCONFIG_SYNC_OFF 0x00 770 771 #define RF_SYNCCONFIG_FIFOFILLCONDITION_MASK 0xF7 772 #define RF_SYNCCONFIG_FIFOFILLCONDITION_AUTO 0x00 // Default 773 #define RF_SYNCCONFIG_FIFOFILLCONDITION_MANUAL 0x08 774 775 #define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8 776 #define RF_SYNCCONFIG_SYNCSIZE_1 0x00 777 #define RF_SYNCCONFIG_SYNCSIZE_2 0x01 778 #define RF_SYNCCONFIG_SYNCSIZE_3 0x02 779 #define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default 780 #define RF_SYNCCONFIG_SYNCSIZE_5 0x04 781 #define RF_SYNCCONFIG_SYNCSIZE_6 0x05 782 #define RF_SYNCCONFIG_SYNCSIZE_7 0x06 783 #define RF_SYNCCONFIG_SYNCSIZE_8 0x07 784 785 /*! 786 * RegSyncValue1-8 787 */ 788 #define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default 789 #define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default 790 #define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default 791 #define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default 792 #define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default 793 #define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default 794 #define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default 795 #define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default 796 797 /*! 798 * RegPacketConfig1 799 */ 800 #define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F 801 #define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00 802 #define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default 803 804 #define RF_PACKETCONFIG1_DCFREE_MASK 0x9F 805 #define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default 806 #define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20 807 #define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40 808 809 #define RF_PACKETCONFIG1_CRC_MASK 0xEF 810 #define RF_PACKETCONFIG1_CRC_ON 0x10 // Default 811 #define RF_PACKETCONFIG1_CRC_OFF 0x00 812 813 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7 814 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default 815 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 816 817 #define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9 818 #define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default 819 #define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02 820 #define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04 821 822 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE 823 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default 824 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01 825 826 /*! 827 * RegPacketConfig2 828 */ 829 #define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF 830 #define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00 831 #define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default 832 833 #define RF_PACKETCONFIG2_IOHOME_MASK 0xDF 834 #define RF_PACKETCONFIG2_IOHOME_ON 0x20 835 #define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default 836 837 #define RF_PACKETCONFIG2_BEACON_MASK 0xF7 838 #define RF_PACKETCONFIG2_BEACON_ON 0x08 839 #define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default 840 841 #define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8 842 843 /*! 844 * RegPayloadLength 845 */ 846 #define RF_PAYLOADLENGTH_LENGTH 0x40 // Default 847 848 /*! 849 * RegNodeAdrs 850 */ 851 #define RF_NODEADDRESS_ADDRESS 0x00 852 853 /*! 854 * RegBroadcastAdrs 855 */ 856 #define RF_BROADCASTADDRESS_ADDRESS 0x00 857 858 /*! 859 * RegFifoThresh 860 */ 861 #define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F 862 #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00 863 #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80 // Default 864 865 #define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0 866 #define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default 867 868 /*! 869 * RegSeqConfig1 870 */ 871 #define RF_SEQCONFIG1_SEQUENCER_START 0x80 872 873 #define RF_SEQCONFIG1_SEQUENCER_STOP 0x40 874 875 #define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF 876 #define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20 877 #define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default 878 879 #define RF_SEQCONFIG1_FROMSTART_MASK 0xE7 880 #define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default 881 #define RF_SEQCONFIG1_FROMSTART_TORX 0x08 882 #define RF_SEQCONFIG1_FROMSTART_TOTX 0x10 883 #define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18 884 885 #define RF_SEQCONFIG1_LPS_MASK 0xFB 886 #define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default 887 #define RF_SEQCONFIG1_LPS_IDLE 0x04 888 889 #define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD 890 #define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default 891 #define RF_SEQCONFIG1_FROMIDLE_TORX 0x02 892 893 #define RF_SEQCONFIG1_FROMTX_MASK 0xFE 894 #define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default 895 #define RF_SEQCONFIG1_FROMTX_TORX 0x01 896 897 /*! 898 * RegSeqConfig2 899 */ 900 #define RF_SEQCONFIG2_FROMRX_MASK 0x1F 901 #define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default 902 #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20 903 #define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40 904 #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60 905 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80 906 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0 907 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0 908 #define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0 909 910 #define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7 911 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default 912 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08 913 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10 914 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18 915 916 #define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8 917 #define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default 918 #define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01 919 #define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02 920 #define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03 921 #define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04 922 923 /*! 924 * RegTimerResol 925 */ 926 #define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3 927 #define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default 928 #define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04 929 #define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08 930 #define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C 931 932 #define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC 933 #define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default 934 #define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01 935 #define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02 936 #define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03 937 938 /*! 939 * RegTimer1Coef 940 */ 941 #define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default 942 943 /*! 944 * RegTimer2Coef 945 */ 946 #define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default 947 948 /*! 949 * RegImageCal 950 */ 951 #define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F 952 #define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80 953 #define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default 954 955 #define RF_IMAGECAL_IMAGECAL_MASK 0xBF 956 #define RF_IMAGECAL_IMAGECAL_START 0x40 957 958 #define RF_IMAGECAL_IMAGECAL_RUNNING 0x20 959 #define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default 960 961 #define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08 962 #define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00 963 964 #define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9 965 #define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00 966 #define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default 967 #define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04 968 #define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06 969 970 #define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE 971 #define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default 972 #define RF_IMAGECAL_TEMPMONITOR_OFF 0x01 973 974 /*! 975 * RegTemp (Read Only) 976 */ 977 978 /*! 979 * RegLowBat 980 */ 981 #define RF_LOWBAT_MASK 0xF7 982 #define RF_LOWBAT_ON 0x08 983 #define RF_LOWBAT_OFF 0x00 // Default 984 985 #define RF_LOWBAT_TRIM_MASK 0xF8 986 #define RF_LOWBAT_TRIM_1695 0x00 987 #define RF_LOWBAT_TRIM_1764 0x01 988 #define RF_LOWBAT_TRIM_1835 0x02 // Default 989 #define RF_LOWBAT_TRIM_1905 0x03 990 #define RF_LOWBAT_TRIM_1976 0x04 991 #define RF_LOWBAT_TRIM_2045 0x05 992 #define RF_LOWBAT_TRIM_2116 0x06 993 #define RF_LOWBAT_TRIM_2185 0x07 994 995 /*! 996 * RegIrqFlags1 997 */ 998 #define RF_IRQFLAGS1_MODEREADY 0x80 999 1000 #define RF_IRQFLAGS1_RXREADY 0x40 1001 1002 #define RF_IRQFLAGS1_TXREADY 0x20 1003 1004 #define RF_IRQFLAGS1_PLLLOCK 0x10 1005 1006 #define RF_IRQFLAGS1_RSSI 0x08 1007 1008 #define RF_IRQFLAGS1_TIMEOUT 0x04 1009 1010 #define RF_IRQFLAGS1_PREAMBLEDETECT 0x02 1011 1012 #define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01 1013 1014 /*! 1015 * RegIrqFlags2 1016 */ 1017 #define RF_IRQFLAGS2_FIFOFULL 0x80 1018 1019 #define RF_IRQFLAGS2_FIFOEMPTY 0x40 1020 1021 #define RF_IRQFLAGS2_FIFOLEVEL 0x20 1022 1023 #define RF_IRQFLAGS2_FIFOOVERRUN 0x10 1024 1025 #define RF_IRQFLAGS2_PACKETSENT 0x08 1026 1027 #define RF_IRQFLAGS2_PAYLOADREADY 0x04 1028 1029 #define RF_IRQFLAGS2_CRCOK 0x02 1030 1031 #define RF_IRQFLAGS2_LOWBAT 0x01 1032 1033 /*! 1034 * RegDioMapping1 1035 */ 1036 #define RF_DIOMAPPING1_DIO0_MASK 0x3F 1037 #define RF_DIOMAPPING1_DIO0_00 0x00 // Default 1038 #define RF_DIOMAPPING1_DIO0_01 0x40 1039 #define RF_DIOMAPPING1_DIO0_10 0x80 1040 #define RF_DIOMAPPING1_DIO0_11 0xC0 1041 1042 #define RF_DIOMAPPING1_DIO1_MASK 0xCF 1043 #define RF_DIOMAPPING1_DIO1_00 0x00 // Default 1044 #define RF_DIOMAPPING1_DIO1_01 0x10 1045 #define RF_DIOMAPPING1_DIO1_10 0x20 1046 #define RF_DIOMAPPING1_DIO1_11 0x30 1047 1048 #define RF_DIOMAPPING1_DIO2_MASK 0xF3 1049 #define RF_DIOMAPPING1_DIO2_00 0x00 // Default 1050 #define RF_DIOMAPPING1_DIO2_01 0x04 1051 #define RF_DIOMAPPING1_DIO2_10 0x08 1052 #define RF_DIOMAPPING1_DIO2_11 0x0C 1053 1054 #define RF_DIOMAPPING1_DIO3_MASK 0xFC 1055 #define RF_DIOMAPPING1_DIO3_00 0x00 // Default 1056 #define RF_DIOMAPPING1_DIO3_01 0x01 1057 #define RF_DIOMAPPING1_DIO3_10 0x02 1058 #define RF_DIOMAPPING1_DIO3_11 0x03 1059 1060 /*! 1061 * RegDioMapping2 1062 */ 1063 #define RF_DIOMAPPING2_DIO4_MASK 0x3F 1064 #define RF_DIOMAPPING2_DIO4_00 0x00 // Default 1065 #define RF_DIOMAPPING2_DIO4_01 0x40 1066 #define RF_DIOMAPPING2_DIO4_10 0x80 1067 #define RF_DIOMAPPING2_DIO4_11 0xC0 1068 1069 #define RF_DIOMAPPING2_DIO5_MASK 0xCF 1070 #define RF_DIOMAPPING2_DIO5_00 0x00 // Default 1071 #define RF_DIOMAPPING2_DIO5_01 0x10 1072 #define RF_DIOMAPPING2_DIO5_10 0x20 1073 #define RF_DIOMAPPING2_DIO5_11 0x30 1074 1075 #define RF_DIOMAPPING2_MAP_MASK 0xFE 1076 #define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 1077 #define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default 1078 1079 /*! 1080 * RegVersion (Read Only) 1081 */ 1082 1083 /*! 1084 * RegAgcRef 1085 */ 1086 1087 /*! 1088 * RegAgcThresh1 1089 */ 1090 1091 /*! 1092 * RegAgcThresh2 1093 */ 1094 1095 /*! 1096 * RegAgcThresh3 1097 */ 1098 1099 /*! 1100 * RegPllHop 1101 */ 1102 #define RF_PLLHOP_FASTHOP_MASK 0x7F 1103 #define RF_PLLHOP_FASTHOP_ON 0x80 1104 #define RF_PLLHOP_FASTHOP_OFF 0x00 // Default 1105 1106 /*! 1107 * RegTcxo 1108 */ 1109 #define RF_TCXO_TCXOINPUT_MASK 0xEF 1110 #define RF_TCXO_TCXOINPUT_ON 0x10 1111 #define RF_TCXO_TCXOINPUT_OFF 0x00 // Default 1112 1113 /*! 1114 * RegPaDac 1115 */ 1116 #define RF_PADAC_20DBM_MASK 0xF8 1117 #define RF_PADAC_20DBM_ON 0x07 1118 #define RF_PADAC_20DBM_OFF 0x04 // Default 1119 1120 /*! 1121 * RegPll 1122 */ 1123 #define RF_PLL_BANDWIDTH_MASK 0x3F 1124 #define RF_PLL_BANDWIDTH_75 0x00 1125 #define RF_PLL_BANDWIDTH_150 0x40 1126 #define RF_PLL_BANDWIDTH_225 0x80 1127 #define RF_PLL_BANDWIDTH_300 0xC0 // Default 1128 1129 /*! 1130 * RegPllLowPn 1131 */ 1132 #define RF_PLLLOWPN_BANDWIDTH_MASK 0x3F 1133 #define RF_PLLLOWPN_BANDWIDTH_75 0x00 1134 #define RF_PLLLOWPN_BANDWIDTH_150 0x40 1135 #define RF_PLLLOWPN_BANDWIDTH_225 0x80 1136 #define RF_PLLLOWPN_BANDWIDTH_300 0xC0 // Default 1137 1138 /*! 1139 * RegFormerTemp 1140 */ 1141 1142 /*! 1143 * RegBitrateFrac 1144 */ 1145 #define RF_BITRATEFRAC_MASK 0xF0 1146 1147 #ifdef __cplusplus 1148 } 1149 #endif 1150 1151 #endif // __SX1272_REGS_FSK_H__ 1152
