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Searched refs:MODE1 (Results 1 – 2 of 2) sorted by relevance

/loramac-node-latest/src/boards/mcu/saml21/hri/
Dhri_rtc_l21.h110 while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { in hri_rtcmode1_wait_for_sync()
116 return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; in hri_rtcmode1_is_syncing()
4741 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; in hri_rtcmode1_set_INTEN_PER0_bit()
4746 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; in hri_rtcmode1_get_INTEN_PER0_bit()
4752 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; in hri_rtcmode1_write_INTEN_PER0_bit()
4754 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; in hri_rtcmode1_write_INTEN_PER0_bit()
4760 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; in hri_rtcmode1_clear_INTEN_PER0_bit()
4765 ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; in hri_rtcmode1_set_INTEN_PER1_bit()
4770 return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; in hri_rtcmode1_get_INTEN_PER1_bit()
4776 ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; in hri_rtcmode1_write_INTEN_PER1_bit()
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/loramac-node-latest/src/boards/mcu/saml21/saml21b/include/component/
Drtc.h1406 …RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Com… member