Searched refs:MODE0 (Results 1 – 2 of 2) sorted by relevance
99 while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { in hri_rtcmode0_wait_for_sync()105 return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; in hri_rtcmode0_is_syncing()3014 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; in hri_rtcmode0_set_INTEN_PER0_bit()3019 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; in hri_rtcmode0_get_INTEN_PER0_bit()3025 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; in hri_rtcmode0_write_INTEN_PER0_bit()3027 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; in hri_rtcmode0_write_INTEN_PER0_bit()3033 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; in hri_rtcmode0_clear_INTEN_PER0_bit()3038 ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; in hri_rtcmode0_set_INTEN_PER1_bit()3043 return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; in hri_rtcmode0_get_INTEN_PER1_bit()3049 ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; in hri_rtcmode0_write_INTEN_PER1_bit()[all …]
1405 …RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit … member
