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Searched refs:DHCSR (Results 1 – 8 of 8) sorted by relevance

/loramac-node-latest/src/boards/mcu/saml21/cmsis/
Dcore_cm3.h1154 …__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member
Dcore_sc300.h1134 …__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member
Dcore_cm4.h1300 …__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member
Dcore_cm7.h1487 …__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member
/loramac-node-latest/src/boards/mcu/stm32/cmsis/
Dcore_cm3.h1237 …__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member
Dcore_sc300.h1219 …__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member
Dcore_cm4.h1406 …__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member
Dcore_cm7.h1614 …__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member