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Searched refs:Ccl (Results 1 – 13 of 13) sorted by relevance

/loramac-node-latest/src/boards/mcu/saml21/hri/
Dhri_ccl_l21.h69 ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; in hri_ccl_set_CTRL_SWRST_bit()
76 tmp = ((Ccl *)hw)->CTRL.reg; in hri_ccl_get_CTRL_SWRST_bit()
84 ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; in hri_ccl_set_CTRL_ENABLE_bit()
91 tmp = ((Ccl *)hw)->CTRL.reg; in hri_ccl_get_CTRL_ENABLE_bit()
100 tmp = ((Ccl *)hw)->CTRL.reg; in hri_ccl_write_CTRL_ENABLE_bit()
103 ((Ccl *)hw)->CTRL.reg = tmp; in hri_ccl_write_CTRL_ENABLE_bit()
110 ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; in hri_ccl_clear_CTRL_ENABLE_bit()
117 ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; in hri_ccl_toggle_CTRL_ENABLE_bit()
124 ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; in hri_ccl_set_CTRL_RUNSTDBY_bit()
131 tmp = ((Ccl *)hw)->CTRL.reg; in hri_ccl_get_CTRL_RUNSTDBY_bit()
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/loramac-node-latest/src/boards/mcu/saml21/saml21b/include/component/
Dccl.h182 } Ccl; typedef
/loramac-node-latest/src/boards/mcu/saml21/saml21b/include/
Dsaml21e15b.h445 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */
Dsaml21e17b.h445 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */
Dsaml21e18b.h445 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */
Dsaml21g16b.h445 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */
Dsaml21g17b.h445 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */
Dsaml21g18b.h445 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */
Dsaml21e16b.h445 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */
Dsaml21j16b.h455 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */
Dsaml21j17b.h455 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */
Dsaml21j18b.h455 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */
Dsaml21j18bu.h455 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */