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Searched refs:CPUDIV (Results 1 – 2 of 2) sorted by relevance

/loramac-node-latest/src/boards/mcu/saml21/hri/
Dhri_mclk_l21.h210 ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask); in hri_mclk_set_CPUDIV_CPUDIV_bf()
217 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_CPUDIV_bf()
226 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_write_CPUDIV_CPUDIV_bf()
229 ((Mclk *)hw)->CPUDIV.reg = tmp; in hri_mclk_write_CPUDIV_CPUDIV_bf()
236 ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_CPUDIV(mask); in hri_mclk_clear_CPUDIV_CPUDIV_bf()
243 ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_CPUDIV(mask); in hri_mclk_toggle_CPUDIV_CPUDIV_bf()
250 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_read_CPUDIV_CPUDIV_bf()
258 ((Mclk *)hw)->CPUDIV.reg |= mask; in hri_mclk_set_CPUDIV_reg()
265 tmp = ((Mclk *)hw)->CPUDIV.reg; in hri_mclk_get_CPUDIV_reg()
273 ((Mclk *)hw)->CPUDIV.reg = data; in hri_mclk_write_CPUDIV_reg()
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/loramac-node-latest/src/boards/mcu/saml21/saml21b/include/component/
Dmclk.h110 uint8_t CPUDIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */ member
475 …__IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x04 (R/W 8) CPU Clock Division */ member