Searched refs:CHINTENSET (Results 1 – 2 of 2) sorted by relevance
92 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; in hri_dmac_set_CHINTEN_TERR_bit()97 return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; in hri_dmac_get_CHINTEN_TERR_bit()105 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; in hri_dmac_write_CHINTEN_TERR_bit()116 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; in hri_dmac_set_CHINTEN_TCMPL_bit()121 return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; in hri_dmac_get_CHINTEN_TCMPL_bit()129 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; in hri_dmac_write_CHINTEN_TCMPL_bit()140 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; in hri_dmac_set_CHINTEN_SUSP_bit()145 return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; in hri_dmac_get_CHINTEN_SUSP_bit()153 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; in hri_dmac_write_CHINTEN_SUSP_bit()164 ((Dmac *)hw)->CHINTENSET.reg = mask; in hri_dmac_set_CHINTEN_reg()[all …]
1091 …__IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt En… member
