Searched refs:CHCTRLA (Results 1 – 2 of 2) sorted by relevance
2876 ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; in hri_dmac_set_CHCTRLA_SWRST_bit()2883 tmp = ((Dmac *)hw)->CHCTRLA.reg; in hri_dmac_get_CHCTRLA_SWRST_bit()2891 ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; in hri_dmac_set_CHCTRLA_ENABLE_bit()2898 tmp = ((Dmac *)hw)->CHCTRLA.reg; in hri_dmac_get_CHCTRLA_ENABLE_bit()2907 tmp = ((Dmac *)hw)->CHCTRLA.reg; in hri_dmac_write_CHCTRLA_ENABLE_bit()2910 ((Dmac *)hw)->CHCTRLA.reg = tmp; in hri_dmac_write_CHCTRLA_ENABLE_bit()2917 ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; in hri_dmac_clear_CHCTRLA_ENABLE_bit()2924 ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; in hri_dmac_toggle_CHCTRLA_ENABLE_bit()2931 ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; in hri_dmac_set_CHCTRLA_RUNSTDBY_bit()2938 tmp = ((Dmac *)hw)->CHCTRLA.reg; in hri_dmac_get_CHCTRLA_RUNSTDBY_bit()[all …]
1086 __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ member
