1 /** 2 * \file 3 * 4 * \brief Component description for DMAC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_DMAC_COMPONENT_ 30 #define _SAML21_DMAC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR DMAC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_DMAC Direct Memory Access Controller */ 36 /*@{*/ 37 38 #define DMAC_U2223 39 #define REV_DMAC 0x222 40 41 /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ 47 uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ 48 uint16_t :5; /*!< bit: 3.. 7 Reserved */ 49 uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ 50 uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ 51 uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ 52 uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ 53 uint16_t :4; /*!< bit: 12..15 Reserved */ 54 } bit; /*!< Structure used for bit access */ 55 struct { 56 uint16_t :8; /*!< bit: 0.. 7 Reserved */ 57 uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ 58 uint16_t :4; /*!< bit: 12..15 Reserved */ 59 } vec; /*!< Structure used for vec access */ 60 uint16_t reg; /*!< Type used for register access */ 61 } DMAC_CTRL_Type; 62 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 63 64 #define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ 65 #define DMAC_CTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ 66 67 #define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ 68 #define DMAC_CTRL_SWRST (_U(0x1) << DMAC_CTRL_SWRST_Pos) 69 #define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ 70 #define DMAC_CTRL_DMAENABLE (_U(0x1) << DMAC_CTRL_DMAENABLE_Pos) 71 #define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ 72 #define DMAC_CTRL_CRCENABLE (_U(0x1) << DMAC_CTRL_CRCENABLE_Pos) 73 #define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ 74 #define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) 75 #define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ 76 #define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) 77 #define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ 78 #define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) 79 #define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ 80 #define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) 81 #define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ 82 #define DMAC_CTRL_LVLEN_Msk (_U(0xF) << DMAC_CTRL_LVLEN_Pos) 83 #define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) 84 #define DMAC_CTRL_MASK _U(0x0F07) /**< \brief (DMAC_CTRL) MASK Register */ 85 86 /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ 87 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 88 typedef union { 89 struct { 90 uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ 91 uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ 92 uint16_t :4; /*!< bit: 4.. 7 Reserved */ 93 uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ 94 uint16_t :2; /*!< bit: 14..15 Reserved */ 95 } bit; /*!< Structure used for bit access */ 96 uint16_t reg; /*!< Type used for register access */ 97 } DMAC_CRCCTRL_Type; 98 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 99 100 #define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ 101 #define DMAC_CRCCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ 102 103 #define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ 104 #define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) 105 #define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) 106 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ 107 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ 108 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ 109 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) 110 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) 111 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) 112 #define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ 113 #define DMAC_CRCCTRL_CRCPOLY_Msk (_U(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) 114 #define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) 115 #define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ 116 #define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ 117 #define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) 118 #define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) 119 #define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ 120 #define DMAC_CRCCTRL_CRCSRC_Msk (_U(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) 121 #define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) 122 #define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) No action */ 123 #define DMAC_CRCCTRL_CRCSRC_IO_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ 124 #define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) 125 #define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) 126 #define DMAC_CRCCTRL_MASK _U(0x3F0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ 127 128 /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ 129 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 130 typedef union { 131 struct { 132 uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ 133 } bit; /*!< Structure used for bit access */ 134 uint32_t reg; /*!< Type used for register access */ 135 } DMAC_CRCDATAIN_Type; 136 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 137 138 #define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ 139 #define DMAC_CRCDATAIN_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ 140 141 #define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ 142 #define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) 143 #define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) 144 #define DMAC_CRCDATAIN_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ 145 146 /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 148 typedef union { 149 struct { 150 uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ 151 } bit; /*!< Structure used for bit access */ 152 uint32_t reg; /*!< Type used for register access */ 153 } DMAC_CRCCHKSUM_Type; 154 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 155 156 #define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ 157 #define DMAC_CRCCHKSUM_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ 158 159 #define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ 160 #define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) 161 #define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) 162 #define DMAC_CRCCHKSUM_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ 163 164 /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ 165 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 166 typedef union { 167 struct { 168 uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ 169 uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ 170 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 171 } bit; /*!< Structure used for bit access */ 172 uint8_t reg; /*!< Type used for register access */ 173 } DMAC_CRCSTATUS_Type; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 #define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ 177 #define DMAC_CRCSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ 178 179 #define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ 180 #define DMAC_CRCSTATUS_CRCBUSY (_U(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) 181 #define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ 182 #define DMAC_CRCSTATUS_CRCZERO (_U(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) 183 #define DMAC_CRCSTATUS_MASK _U(0x03) /**< \brief (DMAC_CRCSTATUS) MASK Register */ 184 185 /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ 186 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 187 typedef union { 188 struct { 189 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 190 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 191 } bit; /*!< Structure used for bit access */ 192 uint8_t reg; /*!< Type used for register access */ 193 } DMAC_DBGCTRL_Type; 194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 195 196 #define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ 197 #define DMAC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ 198 199 #define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ 200 #define DMAC_DBGCTRL_DBGRUN (_U(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) 201 #define DMAC_DBGCTRL_MASK _U(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ 202 203 /* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ 204 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 205 typedef union { 206 struct { 207 uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ 208 uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ 209 uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ 210 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 211 } bit; /*!< Structure used for bit access */ 212 uint8_t reg; /*!< Type used for register access */ 213 } DMAC_QOSCTRL_Type; 214 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 215 216 #define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ 217 #define DMAC_QOSCTRL_RESETVALUE _U(0x2A) /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ 218 219 #define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ 220 #define DMAC_QOSCTRL_WRBQOS_Msk (_U(0x3) << DMAC_QOSCTRL_WRBQOS_Pos) 221 #define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) 222 #define DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ 223 #define DMAC_QOSCTRL_WRBQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ 224 #define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ 225 #define DMAC_QOSCTRL_WRBQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ 226 #define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) 227 #define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) 228 #define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) 229 #define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) 230 #define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ 231 #define DMAC_QOSCTRL_FQOS_Msk (_U(0x3) << DMAC_QOSCTRL_FQOS_Pos) 232 #define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) 233 #define DMAC_QOSCTRL_FQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ 234 #define DMAC_QOSCTRL_FQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ 235 #define DMAC_QOSCTRL_FQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ 236 #define DMAC_QOSCTRL_FQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ 237 #define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) 238 #define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) 239 #define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) 240 #define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) 241 #define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ 242 #define DMAC_QOSCTRL_DQOS_Msk (_U(0x3) << DMAC_QOSCTRL_DQOS_Pos) 243 #define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) 244 #define DMAC_QOSCTRL_DQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ 245 #define DMAC_QOSCTRL_DQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ 246 #define DMAC_QOSCTRL_DQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ 247 #define DMAC_QOSCTRL_DQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ 248 #define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) 249 #define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) 250 #define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) 251 #define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) 252 #define DMAC_QOSCTRL_MASK _U(0x3F) /**< \brief (DMAC_QOSCTRL) MASK Register */ 253 254 /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ 255 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 256 typedef union { 257 struct { 258 uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ 259 uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ 260 uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ 261 uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ 262 uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ 263 uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ 264 uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ 265 uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ 266 uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ 267 uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ 268 uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ 269 uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ 270 uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ 271 uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ 272 uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ 273 uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ 274 uint32_t :16; /*!< bit: 16..31 Reserved */ 275 } bit; /*!< Structure used for bit access */ 276 struct { 277 uint32_t SWTRIG:16; /*!< bit: 0..15 Channel x Software Trigger */ 278 uint32_t :16; /*!< bit: 16..31 Reserved */ 279 } vec; /*!< Structure used for vec access */ 280 uint32_t reg; /*!< Type used for register access */ 281 } DMAC_SWTRIGCTRL_Type; 282 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 283 284 #define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ 285 #define DMAC_SWTRIGCTRL_RESETVALUE _U(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ 286 287 #define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ 288 #define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) 289 #define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ 290 #define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) 291 #define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ 292 #define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) 293 #define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ 294 #define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) 295 #define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ 296 #define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) 297 #define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ 298 #define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) 299 #define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ 300 #define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) 301 #define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ 302 #define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) 303 #define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ 304 #define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) 305 #define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ 306 #define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) 307 #define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ 308 #define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) 309 #define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ 310 #define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) 311 #define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ 312 #define DMAC_SWTRIGCTRL_SWTRIG12 (1 << DMAC_SWTRIGCTRL_SWTRIG12_Pos) 313 #define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ 314 #define DMAC_SWTRIGCTRL_SWTRIG13 (1 << DMAC_SWTRIGCTRL_SWTRIG13_Pos) 315 #define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ 316 #define DMAC_SWTRIGCTRL_SWTRIG14 (1 << DMAC_SWTRIGCTRL_SWTRIG14_Pos) 317 #define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ 318 #define DMAC_SWTRIGCTRL_SWTRIG15 (1 << DMAC_SWTRIGCTRL_SWTRIG15_Pos) 319 #define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ 320 #define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U(0xFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) 321 #define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) 322 #define DMAC_SWTRIGCTRL_MASK _U(0x0000FFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ 323 324 /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ 325 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 326 typedef union { 327 struct { 328 uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ 329 uint32_t :3; /*!< bit: 4.. 6 Reserved */ 330 uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ 331 uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ 332 uint32_t :3; /*!< bit: 12..14 Reserved */ 333 uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ 334 uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ 335 uint32_t :3; /*!< bit: 20..22 Reserved */ 336 uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ 337 uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ 338 uint32_t :3; /*!< bit: 28..30 Reserved */ 339 uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ 340 } bit; /*!< Structure used for bit access */ 341 uint32_t reg; /*!< Type used for register access */ 342 } DMAC_PRICTRL0_Type; 343 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 344 345 #define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ 346 #define DMAC_PRICTRL0_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ 347 348 #define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ 349 #define DMAC_PRICTRL0_LVLPRI0_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos) 350 #define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) 351 #define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ 352 #define DMAC_PRICTRL0_RRLVLEN0 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) 353 #define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ 354 #define DMAC_PRICTRL0_LVLPRI1_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos) 355 #define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) 356 #define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ 357 #define DMAC_PRICTRL0_RRLVLEN1 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) 358 #define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ 359 #define DMAC_PRICTRL0_LVLPRI2_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos) 360 #define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) 361 #define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ 362 #define DMAC_PRICTRL0_RRLVLEN2 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) 363 #define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ 364 #define DMAC_PRICTRL0_LVLPRI3_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos) 365 #define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) 366 #define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ 367 #define DMAC_PRICTRL0_RRLVLEN3 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) 368 #define DMAC_PRICTRL0_MASK _U(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */ 369 370 /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ 371 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 372 typedef union { 373 struct { 374 uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ 375 uint16_t :4; /*!< bit: 4.. 7 Reserved */ 376 uint16_t TERR:1; /*!< bit: 8 Transfer Error */ 377 uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ 378 uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ 379 uint16_t :2; /*!< bit: 11..12 Reserved */ 380 uint16_t FERR:1; /*!< bit: 13 Fetch Error */ 381 uint16_t BUSY:1; /*!< bit: 14 Busy */ 382 uint16_t PEND:1; /*!< bit: 15 Pending */ 383 } bit; /*!< Structure used for bit access */ 384 uint16_t reg; /*!< Type used for register access */ 385 } DMAC_INTPEND_Type; 386 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 387 388 #define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ 389 #define DMAC_INTPEND_RESETVALUE _U(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ 390 391 #define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ 392 #define DMAC_INTPEND_ID_Msk (_U(0xF) << DMAC_INTPEND_ID_Pos) 393 #define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) 394 #define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ 395 #define DMAC_INTPEND_TERR (_U(0x1) << DMAC_INTPEND_TERR_Pos) 396 #define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ 397 #define DMAC_INTPEND_TCMPL (_U(0x1) << DMAC_INTPEND_TCMPL_Pos) 398 #define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ 399 #define DMAC_INTPEND_SUSP (_U(0x1) << DMAC_INTPEND_SUSP_Pos) 400 #define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ 401 #define DMAC_INTPEND_FERR (_U(0x1) << DMAC_INTPEND_FERR_Pos) 402 #define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ 403 #define DMAC_INTPEND_BUSY (_U(0x1) << DMAC_INTPEND_BUSY_Pos) 404 #define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ 405 #define DMAC_INTPEND_PEND (_U(0x1) << DMAC_INTPEND_PEND_Pos) 406 #define DMAC_INTPEND_MASK _U(0xE70F) /**< \brief (DMAC_INTPEND) MASK Register */ 407 408 /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ 409 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 410 typedef union { 411 struct { 412 uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ 413 uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ 414 uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ 415 uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ 416 uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ 417 uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ 418 uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ 419 uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ 420 uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ 421 uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ 422 uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ 423 uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ 424 uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ 425 uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ 426 uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ 427 uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ 428 uint32_t :16; /*!< bit: 16..31 Reserved */ 429 } bit; /*!< Structure used for bit access */ 430 struct { 431 uint32_t CHINT:16; /*!< bit: 0..15 Channel x Pending Interrupt */ 432 uint32_t :16; /*!< bit: 16..31 Reserved */ 433 } vec; /*!< Structure used for vec access */ 434 uint32_t reg; /*!< Type used for register access */ 435 } DMAC_INTSTATUS_Type; 436 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 437 438 #define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ 439 #define DMAC_INTSTATUS_RESETVALUE _U(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ 440 441 #define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ 442 #define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) 443 #define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ 444 #define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) 445 #define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ 446 #define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) 447 #define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ 448 #define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) 449 #define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ 450 #define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) 451 #define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ 452 #define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) 453 #define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ 454 #define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) 455 #define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ 456 #define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) 457 #define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ 458 #define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) 459 #define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ 460 #define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) 461 #define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ 462 #define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) 463 #define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ 464 #define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) 465 #define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ 466 #define DMAC_INTSTATUS_CHINT12 (1 << DMAC_INTSTATUS_CHINT12_Pos) 467 #define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ 468 #define DMAC_INTSTATUS_CHINT13 (1 << DMAC_INTSTATUS_CHINT13_Pos) 469 #define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ 470 #define DMAC_INTSTATUS_CHINT14 (1 << DMAC_INTSTATUS_CHINT14_Pos) 471 #define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ 472 #define DMAC_INTSTATUS_CHINT15 (1 << DMAC_INTSTATUS_CHINT15_Pos) 473 #define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ 474 #define DMAC_INTSTATUS_CHINT_Msk (_U(0xFFFF) << DMAC_INTSTATUS_CHINT_Pos) 475 #define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) 476 #define DMAC_INTSTATUS_MASK _U(0x0000FFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ 477 478 /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ 479 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 480 typedef union { 481 struct { 482 uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ 483 uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ 484 uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ 485 uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ 486 uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ 487 uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ 488 uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ 489 uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ 490 uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ 491 uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ 492 uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ 493 uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ 494 uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ 495 uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ 496 uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ 497 uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ 498 uint32_t :16; /*!< bit: 16..31 Reserved */ 499 } bit; /*!< Structure used for bit access */ 500 struct { 501 uint32_t BUSYCH:16; /*!< bit: 0..15 Busy Channel x */ 502 uint32_t :16; /*!< bit: 16..31 Reserved */ 503 } vec; /*!< Structure used for vec access */ 504 uint32_t reg; /*!< Type used for register access */ 505 } DMAC_BUSYCH_Type; 506 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 507 508 #define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ 509 #define DMAC_BUSYCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ 510 511 #define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ 512 #define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) 513 #define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ 514 #define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) 515 #define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ 516 #define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) 517 #define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ 518 #define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) 519 #define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ 520 #define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) 521 #define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ 522 #define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) 523 #define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ 524 #define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) 525 #define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ 526 #define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) 527 #define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ 528 #define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) 529 #define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ 530 #define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) 531 #define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ 532 #define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) 533 #define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ 534 #define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) 535 #define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ 536 #define DMAC_BUSYCH_BUSYCH12 (1 << DMAC_BUSYCH_BUSYCH12_Pos) 537 #define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ 538 #define DMAC_BUSYCH_BUSYCH13 (1 << DMAC_BUSYCH_BUSYCH13_Pos) 539 #define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ 540 #define DMAC_BUSYCH_BUSYCH14 (1 << DMAC_BUSYCH_BUSYCH14_Pos) 541 #define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ 542 #define DMAC_BUSYCH_BUSYCH15 (1 << DMAC_BUSYCH_BUSYCH15_Pos) 543 #define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ 544 #define DMAC_BUSYCH_BUSYCH_Msk (_U(0xFFFF) << DMAC_BUSYCH_BUSYCH_Pos) 545 #define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) 546 #define DMAC_BUSYCH_MASK _U(0x0000FFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ 547 548 /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ 549 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 550 typedef union { 551 struct { 552 uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ 553 uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ 554 uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ 555 uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ 556 uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ 557 uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ 558 uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ 559 uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ 560 uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ 561 uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ 562 uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ 563 uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ 564 uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ 565 uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ 566 uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ 567 uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ 568 uint32_t :16; /*!< bit: 16..31 Reserved */ 569 } bit; /*!< Structure used for bit access */ 570 struct { 571 uint32_t PENDCH:16; /*!< bit: 0..15 Pending Channel x */ 572 uint32_t :16; /*!< bit: 16..31 Reserved */ 573 } vec; /*!< Structure used for vec access */ 574 uint32_t reg; /*!< Type used for register access */ 575 } DMAC_PENDCH_Type; 576 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 577 578 #define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ 579 #define DMAC_PENDCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ 580 581 #define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ 582 #define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) 583 #define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ 584 #define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) 585 #define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ 586 #define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) 587 #define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ 588 #define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) 589 #define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ 590 #define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) 591 #define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ 592 #define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) 593 #define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ 594 #define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) 595 #define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ 596 #define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) 597 #define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ 598 #define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) 599 #define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ 600 #define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) 601 #define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ 602 #define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) 603 #define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ 604 #define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) 605 #define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ 606 #define DMAC_PENDCH_PENDCH12 (1 << DMAC_PENDCH_PENDCH12_Pos) 607 #define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ 608 #define DMAC_PENDCH_PENDCH13 (1 << DMAC_PENDCH_PENDCH13_Pos) 609 #define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ 610 #define DMAC_PENDCH_PENDCH14 (1 << DMAC_PENDCH_PENDCH14_Pos) 611 #define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ 612 #define DMAC_PENDCH_PENDCH15 (1 << DMAC_PENDCH_PENDCH15_Pos) 613 #define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ 614 #define DMAC_PENDCH_PENDCH_Msk (_U(0xFFFF) << DMAC_PENDCH_PENDCH_Pos) 615 #define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) 616 #define DMAC_PENDCH_MASK _U(0x0000FFFF) /**< \brief (DMAC_PENDCH) MASK Register */ 617 618 /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ 619 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 620 typedef union { 621 struct { 622 uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ 623 uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ 624 uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ 625 uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ 626 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 627 uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ 628 uint32_t :2; /*!< bit: 13..14 Reserved */ 629 uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ 630 uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ 631 } bit; /*!< Structure used for bit access */ 632 struct { 633 uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ 634 uint32_t :28; /*!< bit: 4..31 Reserved */ 635 } vec; /*!< Structure used for vec access */ 636 uint32_t reg; /*!< Type used for register access */ 637 } DMAC_ACTIVE_Type; 638 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 639 640 #define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ 641 #define DMAC_ACTIVE_RESETVALUE _U(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ 642 643 #define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ 644 #define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) 645 #define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ 646 #define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) 647 #define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ 648 #define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) 649 #define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ 650 #define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) 651 #define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ 652 #define DMAC_ACTIVE_LVLEX_Msk (_U(0xF) << DMAC_ACTIVE_LVLEX_Pos) 653 #define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) 654 #define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ 655 #define DMAC_ACTIVE_ID_Msk (_U(0x1F) << DMAC_ACTIVE_ID_Pos) 656 #define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) 657 #define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ 658 #define DMAC_ACTIVE_ABUSY (_U(0x1) << DMAC_ACTIVE_ABUSY_Pos) 659 #define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ 660 #define DMAC_ACTIVE_BTCNT_Msk (_U(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) 661 #define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) 662 #define DMAC_ACTIVE_MASK _U(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ 663 664 /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ 665 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 666 typedef union { 667 struct { 668 uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ 669 } bit; /*!< Structure used for bit access */ 670 uint32_t reg; /*!< Type used for register access */ 671 } DMAC_BASEADDR_Type; 672 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 673 674 #define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ 675 #define DMAC_BASEADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ 676 677 #define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ 678 #define DMAC_BASEADDR_BASEADDR_Msk (_U(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) 679 #define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) 680 #define DMAC_BASEADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ 681 682 /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ 683 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 684 typedef union { 685 struct { 686 uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ 687 } bit; /*!< Structure used for bit access */ 688 uint32_t reg; /*!< Type used for register access */ 689 } DMAC_WRBADDR_Type; 690 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 691 692 #define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ 693 #define DMAC_WRBADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ 694 695 #define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ 696 #define DMAC_WRBADDR_WRBADDR_Msk (_U(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) 697 #define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) 698 #define DMAC_WRBADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ 699 700 /* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ 701 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 702 typedef union { 703 struct { 704 uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ 705 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 706 } bit; /*!< Structure used for bit access */ 707 uint8_t reg; /*!< Type used for register access */ 708 } DMAC_CHID_Type; 709 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 710 711 #define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ 712 #define DMAC_CHID_RESETVALUE _U(0x00) /**< \brief (DMAC_CHID reset_value) Channel ID */ 713 714 #define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ 715 #define DMAC_CHID_ID_Msk (_U(0xF) << DMAC_CHID_ID_Pos) 716 #define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) 717 #define DMAC_CHID_MASK _U(0x0F) /**< \brief (DMAC_CHID) MASK Register */ 718 719 /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ 720 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 721 typedef union { 722 struct { 723 uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ 724 uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ 725 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 726 uint8_t RUNSTDBY:1; /*!< bit: 6 Channel run in standby */ 727 uint8_t :1; /*!< bit: 7 Reserved */ 728 } bit; /*!< Structure used for bit access */ 729 uint8_t reg; /*!< Type used for register access */ 730 } DMAC_CHCTRLA_Type; 731 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 732 733 #define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ 734 #define DMAC_CHCTRLA_RESETVALUE _U(0x00) /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ 735 736 #define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ 737 #define DMAC_CHCTRLA_SWRST (_U(0x1) << DMAC_CHCTRLA_SWRST_Pos) 738 #define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ 739 #define DMAC_CHCTRLA_ENABLE (_U(0x1) << DMAC_CHCTRLA_ENABLE_Pos) 740 #define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel run in standby */ 741 #define DMAC_CHCTRLA_RUNSTDBY (_U(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) 742 #define DMAC_CHCTRLA_MASK _U(0x43) /**< \brief (DMAC_CHCTRLA) MASK Register */ 743 744 /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ 745 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 746 typedef union { 747 struct { 748 uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ 749 uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ 750 uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ 751 uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ 752 uint32_t :1; /*!< bit: 7 Reserved */ 753 uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ 754 uint32_t :8; /*!< bit: 14..21 Reserved */ 755 uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ 756 uint32_t CMD:2; /*!< bit: 24..25 Software Command */ 757 uint32_t :6; /*!< bit: 26..31 Reserved */ 758 } bit; /*!< Structure used for bit access */ 759 uint32_t reg; /*!< Type used for register access */ 760 } DMAC_CHCTRLB_Type; 761 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 762 763 #define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ 764 #define DMAC_CHCTRLB_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ 765 766 #define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ 767 #define DMAC_CHCTRLB_EVACT_Msk (_U(0x7) << DMAC_CHCTRLB_EVACT_Pos) 768 #define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) 769 #define DMAC_CHCTRLB_EVACT_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */ 770 #define DMAC_CHCTRLB_EVACT_TRIG_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ 771 #define DMAC_CHCTRLB_EVACT_CTRIG_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ 772 #define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ 773 #define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U(0x4) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ 774 #define DMAC_CHCTRLB_EVACT_RESUME_Val _U(0x5) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ 775 #define DMAC_CHCTRLB_EVACT_SSKIP_Val _U(0x6) /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ 776 #define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) 777 #define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) 778 #define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) 779 #define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) 780 #define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) 781 #define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) 782 #define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) 783 #define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ 784 #define DMAC_CHCTRLB_EVIE (_U(0x1) << DMAC_CHCTRLB_EVIE_Pos) 785 #define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ 786 #define DMAC_CHCTRLB_EVOE (_U(0x1) << DMAC_CHCTRLB_EVOE_Pos) 787 #define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ 788 #define DMAC_CHCTRLB_LVL_Msk (_U(0x3) << DMAC_CHCTRLB_LVL_Pos) 789 #define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) 790 #define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ 791 #define DMAC_CHCTRLB_TRIGSRC_Msk (_U(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos) 792 #define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) 793 #define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ 794 #define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) 795 #define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ 796 #define DMAC_CHCTRLB_TRIGACT_Msk (_U(0x3) << DMAC_CHCTRLB_TRIGACT_Pos) 797 #define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) 798 #define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ 799 #define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ 800 #define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ 801 #define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) 802 #define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) 803 #define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) 804 #define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ 805 #define DMAC_CHCTRLB_CMD_Msk (_U(0x3) << DMAC_CHCTRLB_CMD_Pos) 806 #define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) 807 #define DMAC_CHCTRLB_CMD_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */ 808 #define DMAC_CHCTRLB_CMD_SUSPEND_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ 809 #define DMAC_CHCTRLB_CMD_RESUME_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ 810 #define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) 811 #define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) 812 #define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) 813 #define DMAC_CHCTRLB_MASK _U(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */ 814 815 /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ 816 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 817 typedef union { 818 struct { 819 uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ 820 uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ 821 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ 822 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 823 } bit; /*!< Structure used for bit access */ 824 uint8_t reg; /*!< Type used for register access */ 825 } DMAC_CHINTENCLR_Type; 826 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 827 828 #define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ 829 #define DMAC_CHINTENCLR_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ 830 831 #define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ 832 #define DMAC_CHINTENCLR_TERR (_U(0x1) << DMAC_CHINTENCLR_TERR_Pos) 833 #define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ 834 #define DMAC_CHINTENCLR_TCMPL (_U(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) 835 #define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ 836 #define DMAC_CHINTENCLR_SUSP (_U(0x1) << DMAC_CHINTENCLR_SUSP_Pos) 837 #define DMAC_CHINTENCLR_MASK _U(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ 838 839 /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ 840 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 841 typedef union { 842 struct { 843 uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ 844 uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ 845 uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ 846 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 847 } bit; /*!< Structure used for bit access */ 848 uint8_t reg; /*!< Type used for register access */ 849 } DMAC_CHINTENSET_Type; 850 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 851 852 #define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ 853 #define DMAC_CHINTENSET_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ 854 855 #define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ 856 #define DMAC_CHINTENSET_TERR (_U(0x1) << DMAC_CHINTENSET_TERR_Pos) 857 #define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ 858 #define DMAC_CHINTENSET_TCMPL (_U(0x1) << DMAC_CHINTENSET_TCMPL_Pos) 859 #define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ 860 #define DMAC_CHINTENSET_SUSP (_U(0x1) << DMAC_CHINTENSET_SUSP_Pos) 861 #define DMAC_CHINTENSET_MASK _U(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ 862 863 /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ 864 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 865 typedef union { // __I to avoid read-modify-write on write-to-clear register 866 struct { 867 __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ 868 __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ 869 __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ 870 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ 871 } bit; /*!< Structure used for bit access */ 872 uint8_t reg; /*!< Type used for register access */ 873 } DMAC_CHINTFLAG_Type; 874 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 875 876 #define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ 877 #define DMAC_CHINTFLAG_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ 878 879 #define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ 880 #define DMAC_CHINTFLAG_TERR (_U(0x1) << DMAC_CHINTFLAG_TERR_Pos) 881 #define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ 882 #define DMAC_CHINTFLAG_TCMPL (_U(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) 883 #define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ 884 #define DMAC_CHINTFLAG_SUSP (_U(0x1) << DMAC_CHINTFLAG_SUSP_Pos) 885 #define DMAC_CHINTFLAG_MASK _U(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ 886 887 /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ 888 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 889 typedef union { 890 struct { 891 uint8_t PEND:1; /*!< bit: 0 Channel Pending */ 892 uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ 893 uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ 894 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 895 } bit; /*!< Structure used for bit access */ 896 uint8_t reg; /*!< Type used for register access */ 897 } DMAC_CHSTATUS_Type; 898 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 899 900 #define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ 901 #define DMAC_CHSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ 902 903 #define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ 904 #define DMAC_CHSTATUS_PEND (_U(0x1) << DMAC_CHSTATUS_PEND_Pos) 905 #define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ 906 #define DMAC_CHSTATUS_BUSY (_U(0x1) << DMAC_CHSTATUS_BUSY_Pos) 907 #define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ 908 #define DMAC_CHSTATUS_FERR (_U(0x1) << DMAC_CHSTATUS_FERR_Pos) 909 #define DMAC_CHSTATUS_MASK _U(0x07) /**< \brief (DMAC_CHSTATUS) MASK Register */ 910 911 /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ 912 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 913 typedef union { 914 struct { 915 uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ 916 uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ 917 uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ 918 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 919 uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ 920 uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ 921 uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ 922 uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ 923 uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ 924 } bit; /*!< Structure used for bit access */ 925 uint16_t reg; /*!< Type used for register access */ 926 } DMAC_BTCTRL_Type; 927 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 928 929 #define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ 930 #define DMAC_BTCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ 931 932 #define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ 933 #define DMAC_BTCTRL_VALID (_U(0x1) << DMAC_BTCTRL_VALID_Pos) 934 #define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ 935 #define DMAC_BTCTRL_EVOSEL_Msk (_U(0x3) << DMAC_BTCTRL_EVOSEL_Pos) 936 #define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) 937 #define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ 938 #define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ 939 #define DMAC_BTCTRL_EVOSEL_BEAT_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ 940 #define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) 941 #define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) 942 #define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) 943 #define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ 944 #define DMAC_BTCTRL_BLOCKACT_Msk (_U(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) 945 #define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) 946 #define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ 947 #define DMAC_BTCTRL_BLOCKACT_INT_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ 948 #define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ 949 #define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ 950 #define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) 951 #define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) 952 #define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) 953 #define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) 954 #define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ 955 #define DMAC_BTCTRL_BEATSIZE_Msk (_U(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) 956 #define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) 957 #define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ 958 #define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ 959 #define DMAC_BTCTRL_BEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ 960 #define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) 961 #define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) 962 #define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) 963 #define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ 964 #define DMAC_BTCTRL_SRCINC (_U(0x1) << DMAC_BTCTRL_SRCINC_Pos) 965 #define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ 966 #define DMAC_BTCTRL_DSTINC (_U(0x1) << DMAC_BTCTRL_DSTINC_Pos) 967 #define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ 968 #define DMAC_BTCTRL_STEPSEL (_U(0x1) << DMAC_BTCTRL_STEPSEL_Pos) 969 #define DMAC_BTCTRL_STEPSEL_DST_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ 970 #define DMAC_BTCTRL_STEPSEL_SRC_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ 971 #define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) 972 #define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) 973 #define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ 974 #define DMAC_BTCTRL_STEPSIZE_Msk (_U(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) 975 #define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) 976 #define DMAC_BTCTRL_STEPSIZE_X1_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 1 */ 977 #define DMAC_BTCTRL_STEPSIZE_X2_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 2 */ 978 #define DMAC_BTCTRL_STEPSIZE_X4_Val _U(0x2) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 4 */ 979 #define DMAC_BTCTRL_STEPSIZE_X8_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 8 */ 980 #define DMAC_BTCTRL_STEPSIZE_X16_Val _U(0x4) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 16 */ 981 #define DMAC_BTCTRL_STEPSIZE_X32_Val _U(0x5) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 32 */ 982 #define DMAC_BTCTRL_STEPSIZE_X64_Val _U(0x6) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 64 */ 983 #define DMAC_BTCTRL_STEPSIZE_X128_Val _U(0x7) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 128 */ 984 #define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos) 985 #define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos) 986 #define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos) 987 #define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos) 988 #define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos) 989 #define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos) 990 #define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos) 991 #define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos) 992 #define DMAC_BTCTRL_MASK _U(0xFF1F) /**< \brief (DMAC_BTCTRL) MASK Register */ 993 994 /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */ 995 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 996 typedef union { 997 struct { 998 uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ 999 } bit; /*!< Structure used for bit access */ 1000 uint16_t reg; /*!< Type used for register access */ 1001 } DMAC_BTCNT_Type; 1002 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1003 1004 #define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */ 1005 1006 #define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */ 1007 #define DMAC_BTCNT_BTCNT_Msk (_U(0xFFFF) << DMAC_BTCNT_BTCNT_Pos) 1008 #define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos)) 1009 #define DMAC_BTCNT_MASK _U(0xFFFF) /**< \brief (DMAC_BTCNT) MASK Register */ 1010 1011 /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */ 1012 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1013 typedef union { 1014 struct { 1015 uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ 1016 } bit; /*!< Structure used for bit access */ 1017 uint32_t reg; /*!< Type used for register access */ 1018 } DMAC_SRCADDR_Type; 1019 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1020 1021 #define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */ 1022 1023 #define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */ 1024 #define DMAC_SRCADDR_SRCADDR_Msk (_U(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos) 1025 #define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos)) 1026 #define DMAC_SRCADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_SRCADDR) MASK Register */ 1027 1028 /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */ 1029 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1030 typedef union { 1031 struct { 1032 uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ 1033 } bit; /*!< Structure used for bit access */ 1034 uint32_t reg; /*!< Type used for register access */ 1035 } DMAC_DSTADDR_Type; 1036 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1037 1038 #define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */ 1039 1040 #define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */ 1041 #define DMAC_DSTADDR_DSTADDR_Msk (_U(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos) 1042 #define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos)) 1043 #define DMAC_DSTADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_DSTADDR) MASK Register */ 1044 1045 /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */ 1046 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1047 typedef union { 1048 struct { 1049 uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ 1050 } bit; /*!< Structure used for bit access */ 1051 uint32_t reg; /*!< Type used for register access */ 1052 } DMAC_DESCADDR_Type; 1053 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1054 1055 #define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */ 1056 1057 #define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */ 1058 #define DMAC_DESCADDR_DESCADDR_Msk (_U(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos) 1059 #define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos)) 1060 #define DMAC_DESCADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_DESCADDR) MASK Register */ 1061 1062 /** \brief DMAC APB hardware registers */ 1063 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1064 typedef struct { 1065 __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ 1066 __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ 1067 __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ 1068 __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ 1069 __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ 1070 __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ 1071 __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */ 1072 RoReg8 Reserved1[0x1]; 1073 __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ 1074 __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ 1075 RoReg8 Reserved2[0x8]; 1076 __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ 1077 RoReg8 Reserved3[0x2]; 1078 __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ 1079 __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ 1080 __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ 1081 __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ 1082 __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ 1083 __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ 1084 RoReg8 Reserved4[0x3]; 1085 __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ 1086 __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ 1087 RoReg8 Reserved5[0x3]; 1088 __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ 1089 RoReg8 Reserved6[0x4]; 1090 __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ 1091 __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ 1092 __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ 1093 __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ 1094 } Dmac; 1095 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1096 1097 /** \brief DMAC Descriptor SRAM registers */ 1098 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1099 typedef struct { 1100 __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ 1101 __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ 1102 __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */ 1103 __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */ 1104 __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ 1105 } DmacDescriptor 1106 #ifdef __GNUC__ 1107 __attribute__ ((aligned (8))) 1108 #endif 1109 ; 1110 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1111 1112 #ifdef __GNUC__ 1113 #define SECTION_DMAC_DESCRIPTOR __attribute__ ((section(".lpram"))) 1114 #elif defined(__ICCARM__) 1115 #define SECTION_DMAC_DESCRIPTOR @".lpram" 1116 #endif 1117 1118 /*@}*/ 1119 1120 #endif /* _SAML21_DMAC_COMPONENT_ */ 1121
