1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Convertor (ADC)
7 * peripheral:
8 * + Operation functions
9 * ++ Start, stop, get result of conversions of injected
10 * group, using 2 possible modes: polling, interruption.
11 * ++ Calibration (ADC automatic self-calibration)
12 * + Control functions
13 * ++ Channels configuration on injected group
14 * Other functions (generic functions) are available in file
15 * "stm32l1xx_hal_adc.c".
16 *
17 @verbatim
18 [..]
19 (@) Sections "ADC peripheral features" and "How to use this driver" are
20 available in file of generic functions "stm32l1xx_hal_adc.c".
21 [..]
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
27 *
28 * Redistribution and use in source and binary forms, with or without modification,
29 * are permitted provided that the following conditions are met:
30 * 1. Redistributions of source code must retain the above copyright notice,
31 * this list of conditions and the following disclaimer.
32 * 2. Redistributions in binary form must reproduce the above copyright notice,
33 * this list of conditions and the following disclaimer in the documentation
34 * and/or other materials provided with the distribution.
35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
36 * may be used to endorse or promote products derived from this software
37 * without specific prior written permission.
38 *
39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 *
50 ******************************************************************************
51 */
52
53 /* Includes ------------------------------------------------------------------*/
54 #include "stm32l1xx_hal.h"
55
56 /** @addtogroup STM32L1xx_HAL_Driver
57 * @{
58 */
59
60 /** @defgroup ADCEx ADCEx
61 * @brief ADC Extension HAL module driver
62 * @{
63 */
64
65 #ifdef HAL_ADC_MODULE_ENABLED
66
67 /* Private typedef -----------------------------------------------------------*/
68 /* Private define ------------------------------------------------------------*/
69 /** @defgroup ADCEx_Private_Constants ADCEx Private Constants
70 * @{
71 */
72
73 /* ADC conversion cycles (unit: ADC clock cycles) */
74 /* (selected sampling time + conversion time of 12 ADC clock cycles, with */
75 /* resolution 12 bits) */
76 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_4CYCLE5 ( 16U)
77 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_9CYCLES ( 21U)
78 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_16CYCLES ( 28U)
79 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES ( 36U)
80 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_48CYCLES ( 60U)
81 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES (108U)
82 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES (204U)
83 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES (396U)
84
85 /* Delay for temperature sensor stabilization time. */
86 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
87 /* Unit: us */
88 #define ADC_TEMPSENSOR_DELAY_US (10U)
89
90 /**
91 * @}
92 */
93
94 /* Private macro -------------------------------------------------------------*/
95 /* Private variables ---------------------------------------------------------*/
96 /* Private function prototypes -----------------------------------------------*/
97 /* Private functions ---------------------------------------------------------*/
98
99 /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
100 * @{
101 */
102
103 /** @defgroup ADCEx_Exported_Functions_Group1 ADC Extended IO operation functions
104 * @brief ADC Extended Input and Output operation functions
105 *
106 @verbatim
107 ===============================================================================
108 ##### IO operation functions #####
109 ===============================================================================
110 [..] This section provides functions allowing to:
111 (+) Start conversion of injected group.
112 (+) Stop conversion of injected group.
113 (+) Poll for conversion complete on injected group.
114 (+) Get result of injected channel conversion.
115 (+) Start conversion of injected group and enable interruptions.
116 (+) Stop conversion of injected group and disable interruptions.
117
118 @endverbatim
119 * @{
120 */
121
122 /**
123 * @brief Enables ADC, starts conversion of injected group.
124 * Interruptions enabled in this function: None.
125 * @param hadc: ADC handle
126 * @retval HAL status
127 */
HAL_ADCEx_InjectedStart(ADC_HandleTypeDef * hadc)128 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
129 {
130 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
131
132 /* Check the parameters */
133 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
134
135 /* Process locked */
136 __HAL_LOCK(hadc);
137
138 /* Enable the ADC peripheral */
139 tmp_hal_status = ADC_Enable(hadc);
140
141 /* Start conversion if ADC is effectively enabled */
142 if (tmp_hal_status == HAL_OK)
143 {
144 /* Set ADC state */
145 /* - Clear state bitfield related to injected group conversion results */
146 /* - Set state bitfield related to injected operation */
147 ADC_STATE_CLR_SET(hadc->State,
148 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
149 HAL_ADC_STATE_INJ_BUSY);
150
151 /* Check if a regular conversion is ongoing */
152 /* Note: On this device, there is no ADC error code fields related to */
153 /* conversions on group injected only. In case of conversion on */
154 /* going on group regular, no error code is reset. */
155 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
156 {
157 /* Reset ADC all error code fields */
158 ADC_CLEAR_ERRORCODE(hadc);
159 }
160
161 /* Process unlocked */
162 /* Unlock before starting ADC conversions: in case of potential */
163 /* interruption, to let the process to ADC IRQ Handler. */
164 __HAL_UNLOCK(hadc);
165
166 /* Clear injected group conversion flag */
167 /* (To ensure of no unknown state from potential previous ADC operations) */
168 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
169
170 /* Enable conversion of injected group. */
171 /* If software start has been selected, conversion starts immediately. */
172 /* If external trigger has been selected, conversion will start at next */
173 /* trigger event. */
174 /* If automatic injected conversion is enabled, conversion will start */
175 /* after next regular group conversion. */
176 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
177 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
178 {
179 /* Enable ADC software conversion for injected channels */
180 SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART);
181 }
182 }
183
184 /* Return function status */
185 return tmp_hal_status;
186 }
187
188 /**
189 * @brief Stop conversion of injected channels. Disable ADC peripheral if
190 * no regular conversion is on going.
191 * @note If ADC must be disabled and if conversion is on going on
192 * regular group, function HAL_ADC_Stop must be used to stop both
193 * injected and regular groups, and disable the ADC.
194 * @note If injected group mode auto-injection is enabled,
195 * function HAL_ADC_Stop must be used.
196 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
197 * @param hadc: ADC handle
198 * @retval None
199 */
HAL_ADCEx_InjectedStop(ADC_HandleTypeDef * hadc)200 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
201 {
202 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
203
204 /* Check the parameters */
205 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
206
207 /* Process locked */
208 __HAL_LOCK(hadc);
209
210 /* Stop potential conversion and disable ADC peripheral */
211 /* Conditioned to: */
212 /* - No conversion on the other group (regular group) is intended to */
213 /* continue (injected and regular groups stop conversion and ADC disable */
214 /* are common) */
215 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
216 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
217 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
218 {
219 /* Stop potential conversion on going, on regular and injected groups */
220 /* Disable ADC peripheral */
221 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
222
223 /* Check if ADC is effectively disabled */
224 if (tmp_hal_status == HAL_OK)
225 {
226 /* Set ADC state */
227 ADC_STATE_CLR_SET(hadc->State,
228 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
229 HAL_ADC_STATE_READY);
230 }
231 }
232 else
233 {
234 /* Update ADC state machine to error */
235 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
236
237 tmp_hal_status = HAL_ERROR;
238 }
239
240 /* Process unlocked */
241 __HAL_UNLOCK(hadc);
242
243 /* Return function status */
244 return tmp_hal_status;
245 }
246
247 /**
248 * @brief Wait for injected group conversion to be completed.
249 * @param hadc: ADC handle
250 * @param Timeout: Timeout value in millisecond.
251 * @retval HAL status
252 */
HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)253 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
254 {
255 uint32_t tickstart;
256
257 /* Variables for polling in case of scan mode enabled and polling for each */
258 /* conversion. */
259 /* Note: Variable "conversion_timeout_cpu_cycles" set to offset 28 CPU */
260 /* cycles to compensate number of CPU cycles for processing of variable */
261 /* "conversion_timeout_cpu_cycles_max" */
262 uint32_t conversion_timeout_cpu_cycles = 28;
263 uint32_t conversion_timeout_cpu_cycles_max = 0;
264
265 /* Check the parameters */
266 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
267
268 /* Get timeout */
269 tickstart = HAL_GetTick();
270
271 /* Polling for end of conversion: differentiation if single/sequence */
272 /* conversion. */
273 /* For injected group, flag JEOC is set only at the end of the sequence, */
274 /* not for each conversion within the sequence. */
275 /* If setting "EOCSelection" is set to poll for each single conversion, */
276 /* management of polling depends on setting of injected group sequencer: */
277 /* - If single conversion for injected group (scan mode disabled or */
278 /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */
279 /* conversion completion. */
280 /* - If sequence conversion for injected group (scan mode enabled and */
281 /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
282 /* sequence. */
283 /* To poll for each conversion, the maximum conversion time is computed */
284 /* from ADC conversion time (selected sampling time + conversion time of */
285 /* 12 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
286 /* settings, conversion time range can vary from 8 to several thousands */
287 /* of CPU cycles). */
288
289 /* Note: On STM32L1, setting "EOCSelection" is related to regular group */
290 /* only, by hardware. For compatibility with other STM32 devices, */
291 /* this setting is related also to injected group by software. */
292 if (((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) ||
293 (hadc->Init.EOCSelection != ADC_EOC_SINGLE_CONV) )
294 {
295 /* Wait until End of Conversion flag is raised */
296 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
297 {
298 /* Check if timeout is disabled (set to infinite wait) */
299 if(Timeout != HAL_MAX_DELAY)
300 {
301 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
302 {
303 /* Update ADC state machine to timeout */
304 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
305
306 /* Process unlocked */
307 __HAL_UNLOCK(hadc);
308
309 return HAL_TIMEOUT;
310 }
311 }
312 }
313 }
314 else
315 {
316 /* Computation of CPU cycles corresponding to ADC conversion cycles. */
317 /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
318 /* channels. */
319 conversion_timeout_cpu_cycles_max = ADC_GET_CLOCK_PRESCALER_DECIMAL(hadc);
320 conversion_timeout_cpu_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
321
322 /* Poll with maximum conversion time */
323 while(conversion_timeout_cpu_cycles < conversion_timeout_cpu_cycles_max)
324 {
325 /* Check if timeout is disabled (set to infinite wait) */
326 if(Timeout != HAL_MAX_DELAY)
327 {
328 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
329 {
330 /* Update ADC state machine to timeout */
331 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
332
333 /* Process unlocked */
334 __HAL_UNLOCK(hadc);
335
336 return HAL_TIMEOUT;
337 }
338 }
339 conversion_timeout_cpu_cycles ++;
340 }
341 }
342
343 /* Clear end of conversion flag of injected group if low power feature */
344 /* "Auto Wait" is disabled, to not interfere with this feature until data */
345 /* register is read using function HAL_ADCEx_InjectedGetValue(). */
346 if (hadc->Init.LowPowerAutoWait == DISABLE)
347 {
348 /* Clear injected group conversion flag */
349 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
350 }
351
352 /* Update ADC state machine */
353 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
354
355 /* Determine whether any further conversion upcoming on group injected */
356 /* by external trigger, continuous mode or scan sequence on going. */
357 /* Note: On STM32L1, there is no independent flag of end of sequence. */
358 /* The test of scan sequence on going is done either with scan */
359 /* sequence disabled or with end of conversion flag set to */
360 /* of end of sequence. */
361 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
362 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
363 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
364 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
365 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
366 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
367 {
368 /* Set ADC state */
369 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
370
371 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
372 {
373 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
374 }
375 }
376
377 /* Return ADC state */
378 return HAL_OK;
379 }
380
381 /**
382 * @brief Enables ADC, starts conversion of injected group with interruption.
383 * - JEOC (end of conversion of injected group)
384 * Each of these interruptions has its dedicated callback function.
385 * @param hadc: ADC handle
386 * @retval HAL status.
387 */
HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef * hadc)388 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
389 {
390 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
391
392 /* Check the parameters */
393 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
394
395 /* Process locked */
396 __HAL_LOCK(hadc);
397
398 /* Enable the ADC peripheral */
399 tmp_hal_status = ADC_Enable(hadc);
400
401 /* Start conversion if ADC is effectively enabled */
402 if (tmp_hal_status == HAL_OK)
403 {
404 /* Set ADC state */
405 /* - Clear state bitfield related to injected group conversion results */
406 /* - Set state bitfield related to injected operation */
407 ADC_STATE_CLR_SET(hadc->State,
408 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
409 HAL_ADC_STATE_INJ_BUSY);
410
411 /* Check if a regular conversion is ongoing */
412 /* Note: On this device, there is no ADC error code fields related to */
413 /* conversions on group injected only. In case of conversion on */
414 /* going on group regular, no error code is reset. */
415 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
416 {
417 /* Reset ADC all error code fields */
418 ADC_CLEAR_ERRORCODE(hadc);
419 }
420
421 /* Process unlocked */
422 /* Unlock before starting ADC conversions: in case of potential */
423 /* interruption, to let the process to ADC IRQ Handler. */
424 __HAL_UNLOCK(hadc);
425
426 /* Clear injected group conversion flag */
427 /* (To ensure of no unknown state from potential previous ADC operations) */
428 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
429
430 /* Enable end of conversion interrupt for injected channels */
431 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
432
433 /* Enable conversion of injected group. */
434 /* If software start has been selected, conversion starts immediately. */
435 /* If external trigger has been selected, conversion will start at next */
436 /* trigger event. */
437 /* If automatic injected conversion is enabled, conversion will start */
438 /* after next regular group conversion. */
439 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
440 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
441 {
442 /* Enable ADC software conversion for injected channels */
443 SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART);
444 }
445 }
446
447 /* Return function status */
448 return tmp_hal_status;
449 }
450
451 /**
452 * @brief Stop conversion of injected channels, disable interruption of
453 * end-of-conversion. Disable ADC peripheral if no regular conversion
454 * is on going.
455 * @note If ADC must be disabled and if conversion is on going on
456 * regular group, function HAL_ADC_Stop must be used to stop both
457 * injected and regular groups, and disable the ADC.
458 * @note If injected group mode auto-injection is enabled,
459 * function HAL_ADC_Stop must be used.
460 * @param hadc: ADC handle
461 * @retval None
462 */
HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef * hadc)463 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
464 {
465 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
466
467 /* Check the parameters */
468 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
469
470 /* Process locked */
471 __HAL_LOCK(hadc);
472
473 /* Stop potential conversion and disable ADC peripheral */
474 /* Conditioned to: */
475 /* - No conversion on the other group (regular group) is intended to */
476 /* continue (injected and regular groups stop conversion and ADC disable */
477 /* are common) */
478 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
479 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
480 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
481 {
482 /* Stop potential conversion on going, on regular and injected groups */
483 /* Disable ADC peripheral */
484 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
485
486 /* Check if ADC is effectively disabled */
487 if (tmp_hal_status == HAL_OK)
488 {
489 /* Disable ADC end of conversion interrupt for injected channels */
490 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
491
492 /* Set ADC state */
493 ADC_STATE_CLR_SET(hadc->State,
494 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
495 HAL_ADC_STATE_READY);
496 }
497 }
498 else
499 {
500 /* Update ADC state machine to error */
501 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
502
503 tmp_hal_status = HAL_ERROR;
504 }
505
506 /* Process unlocked */
507 __HAL_UNLOCK(hadc);
508
509 /* Return function status */
510 return tmp_hal_status;
511 }
512
513 /**
514 * @brief Get ADC injected group conversion result.
515 * @note Reading register JDRx automatically clears ADC flag JEOC
516 * (ADC group injected end of unitary conversion).
517 * @note This function does not clear ADC flag JEOS
518 * (ADC group injected end of sequence conversion)
519 * Occurrence of flag JEOS rising:
520 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
521 * to flag JEOC.
522 * - If sequencer is composed of several ranks, during the scan
523 * sequence flag JEOC only is raised, at the end of the scan sequence
524 * both flags JEOC and EOS are raised.
525 * Flag JEOS must not be cleared by this function because
526 * it would not be compliant with low power features
527 * (feature low power auto-wait, not available on all STM32 families).
528 * To clear this flag, either use function:
529 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
530 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
531 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
532 * @param hadc: ADC handle
533 * @param InjectedRank: the converted ADC injected rank.
534 * This parameter can be one of the following values:
535 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
536 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
537 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
538 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
539 * @retval ADC group injected conversion data
540 */
HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef * hadc,uint32_t InjectedRank)541 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
542 {
543 uint32_t tmp_jdr = 0;
544
545 /* Check the parameters */
546 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
547 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
548
549 /* Get ADC converted value */
550 switch(InjectedRank)
551 {
552 case ADC_INJECTED_RANK_4:
553 tmp_jdr = hadc->Instance->JDR4;
554 break;
555 case ADC_INJECTED_RANK_3:
556 tmp_jdr = hadc->Instance->JDR3;
557 break;
558 case ADC_INJECTED_RANK_2:
559 tmp_jdr = hadc->Instance->JDR2;
560 break;
561 case ADC_INJECTED_RANK_1:
562 default:
563 tmp_jdr = hadc->Instance->JDR1;
564 break;
565 }
566
567 /* Return ADC converted value */
568 return tmp_jdr;
569 }
570
571 /**
572 * @brief Injected conversion complete callback in non blocking mode
573 * @param hadc: ADC handle
574 * @retval None
575 */
HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef * hadc)576 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
577 {
578 /* Prevent unused argument(s) compilation warning */
579 UNUSED(hadc);
580
581 /* NOTE : This function Should not be modified, when the callback is needed,
582 the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
583 */
584 }
585
586 /**
587 * @}
588 */
589
590 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
591 * @brief ADC Extended Peripheral Control functions
592 *
593 @verbatim
594 ===============================================================================
595 ##### Peripheral Control functions #####
596 ===============================================================================
597 [..] This section provides functions allowing to:
598 (+) Configure channels on injected group
599
600 @endverbatim
601 * @{
602 */
603
604 /**
605 * @brief Configures the ADC injected group and the selected channel to be
606 * linked to the injected group.
607 * @note Possibility to update parameters on the fly:
608 * This function initializes injected group, following calls to this
609 * function can be used to reconfigure some parameters of structure
610 * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
611 * The setting of these parameters is conditioned to ADC state:
612 * this function must be called when ADC is not under conversion.
613 * @param hadc: ADC handle
614 * @param sConfigInjected: Structure of ADC injected group and ADC channel for
615 * injected group.
616 * @retval None
617 */
HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef * hadc,ADC_InjectionConfTypeDef * sConfigInjected)618 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
619 {
620 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
621 __IO uint32_t wait_loop_index = 0;
622
623 /* Check the parameters */
624 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
625 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
626 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
627 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
628 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
629 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, sConfigInjected->InjectedOffset));
630
631 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
632 {
633 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
634 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
635 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
636 }
637
638 if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
639 {
640 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
641 }
642
643 /* Process locked */
644 __HAL_LOCK(hadc);
645
646 /* Configuration of injected group sequencer: */
647 /* - if scan mode is disabled, injected channels sequence length is set to */
648 /* 0x00: 1 channel converted (channel on regular rank 1) */
649 /* Parameter "InjectedNbrOfConversion" is discarded. */
650 /* Note: Scan mode is present by hardware on this device and, if */
651 /* disabled, discards automatically nb of conversions. Anyway, nb of */
652 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
653 /* - if scan mode is enabled, injected channels sequence length is set to */
654 /* parameter ""InjectedNbrOfConversion". */
655 if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
656 {
657 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
658 {
659 /* Clear the old SQx bits for all injected ranks */
660 MODIFY_REG(hadc->Instance->JSQR ,
661 ADC_JSQR_JL |
662 ADC_JSQR_JSQ4 |
663 ADC_JSQR_JSQ3 |
664 ADC_JSQR_JSQ2 |
665 ADC_JSQR_JSQ1 ,
666 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
667 ADC_INJECTED_RANK_1,
668 0x01) );
669 }
670 /* If another injected rank than rank1 was intended to be set, and could */
671 /* not due to ScanConvMode disabled, error is reported. */
672 else
673 {
674 /* Update ADC state machine to error */
675 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
676
677 tmp_hal_status = HAL_ERROR;
678 }
679 }
680 else
681 {
682 /* Since injected channels rank conv. order depends on total number of */
683 /* injected conversions, selected rank must be below or equal to total */
684 /* number of injected conversions to be updated. */
685 if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
686 {
687 /* Clear the old SQx bits for the selected rank */
688 /* Set the SQx bits for the selected rank */
689 MODIFY_REG(hadc->Instance->JSQR ,
690
691 ADC_JSQR_JL |
692 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
693 sConfigInjected->InjectedRank,
694 sConfigInjected->InjectedNbrOfConversion) ,
695
696 ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
697 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
698 sConfigInjected->InjectedRank,
699 sConfigInjected->InjectedNbrOfConversion) );
700 }
701 else
702 {
703 /* Clear the old SQx bits for the selected rank */
704 MODIFY_REG(hadc->Instance->JSQR ,
705
706 ADC_JSQR_JL |
707 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
708 sConfigInjected->InjectedRank,
709 sConfigInjected->InjectedNbrOfConversion) ,
710
711 0x00000000 );
712 }
713 }
714
715 /* Enable external trigger if trigger selection is different of software */
716 /* start. */
717 /* Note: This configuration keeps the hardware feature of parameter */
718 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
719 /* software start. */
720
721 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
722 {
723 MODIFY_REG(hadc->Instance->CR2 ,
724 ADC_CR2_JEXTEN |
725 ADC_CR2_JEXTSEL ,
726 sConfigInjected->ExternalTrigInjecConv |
727 sConfigInjected->ExternalTrigInjecConvEdge );
728 }
729 else
730 {
731 MODIFY_REG(hadc->Instance->CR2,
732 ADC_CR2_JEXTEN |
733 ADC_CR2_JEXTSEL ,
734 0x00000000 );
735 }
736
737 /* Configuration of injected group */
738 /* Parameters update conditioned to ADC state: */
739 /* Parameters that can be updated only when ADC is disabled: */
740 /* - Automatic injected conversion */
741 /* - Injected discontinuous mode */
742 if ((ADC_IS_ENABLE(hadc) == RESET))
743 {
744 hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO |
745 ADC_CR1_JDISCEN );
746
747 /* Automatic injected conversion can be enabled if injected group */
748 /* external triggers are disabled. */
749 if (sConfigInjected->AutoInjectedConv == ENABLE)
750 {
751 if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
752 {
753 SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
754 }
755 else
756 {
757 /* Update ADC state machine to error */
758 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
759
760 tmp_hal_status = HAL_ERROR;
761 }
762 }
763
764 /* Injected discontinuous can be enabled only if auto-injected mode is */
765 /* disabled. */
766 if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
767 {
768 if (sConfigInjected->AutoInjectedConv == DISABLE)
769 {
770 SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
771 }
772 else
773 {
774 /* Update ADC state machine to error */
775 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
776
777 tmp_hal_status = HAL_ERROR;
778 }
779 }
780 }
781
782 /* Channel sampling time configuration */
783 /* For InjectedChannels 0 to 9 */
784 if (sConfigInjected->InjectedChannel < ADC_CHANNEL_10)
785 {
786 MODIFY_REG(hadc->Instance->SMPR3,
787 ADC_SMPR3(ADC_SMPR3_SMP0, sConfigInjected->InjectedChannel),
788 ADC_SMPR3(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
789 }
790 /* For InjectedChannels 10 to 19 */
791 else if (sConfigInjected->InjectedChannel < ADC_CHANNEL_20)
792 {
793 MODIFY_REG(hadc->Instance->SMPR2,
794 ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel),
795 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
796 }
797 /* For InjectedChannels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
798 /* For InjectedChannels 20 to 29 for devices Cat4, Cat.5 */
799 else if (sConfigInjected->InjectedChannel <= ADC_SMPR1_CHANNEL_MAX)
800 {
801 MODIFY_REG(hadc->Instance->SMPR1,
802 ADC_SMPR1(ADC_SMPR1_SMP20, sConfigInjected->InjectedChannel),
803 ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
804 }
805 /* For InjectedChannels 30 to 31 for devices Cat4, Cat.5 */
806 else
807 {
808 ADC_SMPR0_CHANNEL_SET(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
809 }
810
811
812 /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
813 switch(sConfigInjected->InjectedRank)
814 {
815 case 1:
816 /* Set injected channel 1 offset */
817 MODIFY_REG(hadc->Instance->JOFR1,
818 ADC_JOFR1_JOFFSET1,
819 sConfigInjected->InjectedOffset);
820 break;
821 case 2:
822 /* Set injected channel 2 offset */
823 MODIFY_REG(hadc->Instance->JOFR2,
824 ADC_JOFR2_JOFFSET2,
825 sConfigInjected->InjectedOffset);
826 break;
827 case 3:
828 /* Set injected channel 3 offset */
829 MODIFY_REG(hadc->Instance->JOFR3,
830 ADC_JOFR3_JOFFSET3,
831 sConfigInjected->InjectedOffset);
832 break;
833 case 4:
834 default:
835 MODIFY_REG(hadc->Instance->JOFR4,
836 ADC_JOFR4_JOFFSET4,
837 sConfigInjected->InjectedOffset);
838 break;
839 }
840
841 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
842 /* and VREFINT measurement path. */
843 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
844 (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
845 {
846 SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
847
848 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
849 {
850 /* Delay for temperature sensor stabilization time */
851 /* Compute number of CPU cycles to wait for */
852 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
853 while(wait_loop_index != 0)
854 {
855 wait_loop_index--;
856 }
857 }
858 }
859
860 /* Process unlocked */
861 __HAL_UNLOCK(hadc);
862
863 /* Return function status */
864 return tmp_hal_status;
865 }
866
867 /**
868 * @}
869 */
870
871 /**
872 * @}
873 */
874
875 #endif /* HAL_ADC_MODULE_ENABLED */
876 /**
877 * @}
878 */
879
880 /**
881 * @}
882 */
883
884 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
885
