1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 37 /* Define to prevent recursive inclusion -------------------------------------*/ 38 #ifndef __STM32L1xx_HAL_H 39 #define __STM32L1xx_HAL_H 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* Includes ------------------------------------------------------------------*/ 46 #include "stm32l1xx_hal_conf.h" 47 48 /** @addtogroup STM32L1xx_HAL_Driver 49 * @{ 50 */ 51 52 /** @addtogroup HAL 53 * @{ 54 */ 55 56 /* Exported types ------------------------------------------------------------*/ 57 /* Exported constants --------------------------------------------------------*/ 58 /** @defgroup HAL_Exported_Constants HAL Exported Constants 59 * @{ 60 */ 61 62 /** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG 63 * @{ 64 */ 65 66 /** @defgroup SYSCFG_BootMode Boot Mode 67 * @{ 68 */ 69 70 #define SYSCFG_BOOT_MAINFLASH (0x00000000U) 71 #define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0) 72 #if defined(FSMC_R_BASE) 73 #define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1) 74 #endif /* FSMC_R_BASE */ 75 #define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE) 76 77 /** 78 * @} 79 */ 80 81 /** 82 * @} 83 */ 84 85 /** @defgroup RI_Constants RI: Routing Interface 86 * @{ 87 */ 88 89 /** @defgroup RI_InputCapture Input Capture 90 * @{ 91 */ 92 93 #define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */ 94 #define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */ 95 #define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */ 96 #define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */ 97 98 /** 99 * @} 100 */ 101 102 /** @defgroup TIM_Select TIM Select 103 * @{ 104 */ 105 106 #define TIM_SELECT_NONE (0x00000000U) /*!< None selected */ 107 #define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */ 108 #define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */ 109 #define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */ 110 111 #define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \ 112 ((__TIM__) == TIM_SELECT_TIM2) || \ 113 ((__TIM__) == TIM_SELECT_TIM3) || \ 114 ((__TIM__) == TIM_SELECT_TIM4)) 115 116 /** 117 * @} 118 */ 119 120 /** @defgroup RI_InputCaptureRouting Input Capture Routing 121 * @{ 122 */ 123 /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ 124 #define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */ 125 #define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */ 126 #define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */ 127 #define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */ 128 #define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */ 129 #define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */ 130 #define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */ 131 #define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */ 132 #define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */ 133 #define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */ 134 #define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */ 135 #define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */ 136 #define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */ 137 #define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */ 138 #define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */ 139 #define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */ 140 141 #define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \ 142 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \ 143 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \ 144 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \ 145 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \ 146 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \ 147 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \ 148 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \ 149 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \ 150 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \ 151 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \ 152 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \ 153 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \ 154 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \ 155 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \ 156 ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15)) 157 158 /** 159 * @} 160 */ 161 162 /** @defgroup RI_IOSwitch IO Switch 163 * @{ 164 */ 165 #define RI_ASCR1_REGISTER (0x80000000U) 166 /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */ 167 #define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0) 168 #define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1) 169 #define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2) 170 #define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3) 171 #define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4) 172 #define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5) 173 #define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6) 174 #define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7) 175 #define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8) 176 #define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9) 177 #define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10) 178 #define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11) 179 #define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12) 180 #define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13) 181 #define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14) 182 #define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15) 183 #define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18) 184 #define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19) 185 #define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20) 186 #define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21) 187 #define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22) 188 #define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23) 189 #define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24) 190 #define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25) 191 #define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */ 192 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ 193 #define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27) 194 #define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28) 195 #define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29) 196 #define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30) 197 #define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31) 198 #endif /* RI_ASCR2_CH1b */ 199 200 /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ 201 #define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1) 202 #define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2) 203 #define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3) 204 #define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4) 205 #define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1) 206 #define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2) 207 #define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1) 208 #define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2) 209 #define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3) 210 #define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1) 211 #define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2) 212 #define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3) 213 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */ 214 #define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b) 215 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ 216 #define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b) 217 #define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b) 218 #define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b) 219 #define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b) 220 #define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b) 221 #define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b) 222 #define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b) 223 #define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b) 224 #define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b) 225 #define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b) 226 #endif /* RI_ASCR2_CH1b */ 227 #define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3) 228 #define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4) 229 #endif /* RI_ASCR2_CH0b */ 230 231 232 #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ 233 234 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ 235 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ 236 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ 237 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ 238 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ 239 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ 240 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ 241 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ 242 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ 243 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ 244 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ 245 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ 246 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \ 247 ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \ 248 ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \ 249 ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \ 250 ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \ 251 ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \ 252 ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \ 253 ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \ 254 ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \ 255 ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \ 256 ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \ 257 ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \ 258 ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \ 259 ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \ 260 ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \ 261 ((__IOSWITCH__) == RI_IOSWITCH_CH12b)) 262 263 #else /* !RI_ASCR2_CH1b */ 264 265 #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */ 266 267 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ 268 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ 269 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ 270 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ 271 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ 272 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ 273 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ 274 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ 275 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ 276 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ 277 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ 278 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ 279 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ 280 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ 281 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ 282 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ 283 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ 284 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ 285 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b)) 286 287 #else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */ 288 289 #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ 290 ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ 291 ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ 292 ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ 293 ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ 294 ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ 295 ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ 296 ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ 297 ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ 298 ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ 299 ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ 300 ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ 301 ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ 302 ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ 303 ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ 304 ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ 305 ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ 306 ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ 307 ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)) 308 309 #endif /* RI_ASCR2_CH0b */ 310 #endif /* RI_ASCR2_CH1b */ 311 312 /** 313 * @} 314 */ 315 316 /** @defgroup RI_Pin PIN define 317 * @{ 318 */ 319 #define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ 320 #define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ 321 #define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ 322 #define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ 323 #define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ 324 #define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ 325 #define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ 326 #define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ 327 #define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ 328 #define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ 329 #define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ 330 #define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ 331 #define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ 332 #define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ 333 #define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ 334 #define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ 335 #define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */ 336 337 #define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00) 338 339 /** 340 * @} 341 */ 342 343 /** 344 * @} 345 */ 346 347 /** 348 * @} 349 */ 350 351 /* Exported macro ------------------------------------------------------------*/ 352 353 /** @defgroup HAL_Exported_Macros HAL Exported Macros 354 * @{ 355 */ 356 357 /** @defgroup DBGMCU_Macros DBGMCU: Debug MCU 358 * @{ 359 */ 360 361 /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode 362 * @brief Freeze/Unfreeze Peripherals in Debug mode 363 * @{ 364 */ 365 366 /** 367 * @brief TIM2 Peripherals Debug mode 368 */ 369 #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) 370 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) 371 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) 372 #endif 373 374 /** 375 * @brief TIM3 Peripherals Debug mode 376 */ 377 #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) 378 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) 379 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) 380 #endif 381 382 /** 383 * @brief TIM4 Peripherals Debug mode 384 */ 385 #if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP) 386 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) 387 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) 388 #endif 389 390 /** 391 * @brief TIM5 Peripherals Debug mode 392 */ 393 #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP) 394 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) 395 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) 396 #endif 397 398 /** 399 * @brief TIM6 Peripherals Debug mode 400 */ 401 #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) 402 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 403 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) 404 #endif 405 406 /** 407 * @brief TIM7 Peripherals Debug mode 408 */ 409 #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) 410 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 411 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) 412 #endif 413 414 /** 415 * @brief RTC Peripherals Debug mode 416 */ 417 #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) 418 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) 419 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) 420 #endif 421 422 /** 423 * @brief WWDG Peripherals Debug mode 424 */ 425 #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) 426 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) 427 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) 428 #endif 429 430 /** 431 * @brief IWDG Peripherals Debug mode 432 */ 433 #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) 434 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) 435 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) 436 #endif 437 438 /** 439 * @brief I2C1 Peripherals Debug mode 440 */ 441 #if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) 442 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) 443 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) 444 #endif 445 446 /** 447 * @brief I2C2 Peripherals Debug mode 448 */ 449 #if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) 450 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) 451 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) 452 #endif 453 454 /** 455 * @brief TIM9 Peripherals Debug mode 456 */ 457 #if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP) 458 #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) 459 #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) 460 #endif 461 462 /** 463 * @brief TIM10 Peripherals Debug mode 464 */ 465 #if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP) 466 #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) 467 #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) 468 #endif 469 470 /** 471 * @brief TIM11 Peripherals Debug mode 472 */ 473 #if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP) 474 #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) 475 #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) 476 #endif 477 478 479 /** 480 * @} 481 */ 482 483 /** 484 * @} 485 */ 486 487 /** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG 488 * @{ 489 */ 490 491 /** @defgroup SYSCFG_VrefInt VREFINT configuration 492 * @{ 493 */ 494 495 /** 496 * @brief Enables or disables the output of internal reference voltage 497 * (VREFINT) on I/O pin. 498 * The VREFINT output can be routed to any I/O in group 3: 499 * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1). 500 * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2). 501 * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2), 502 * CH1b (PF11) or CH2b (PF12). 503 * Note: Comparator peripheral clock must be preliminarility enabled, 504 * either in COMP user function "HAL_COMP_MspInit()" (should be 505 * done if comparators are used) or by direct clock enable: 506 * Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()". 507 * Note: In addition with this macro, Vrefint output buffer must be 508 * connected to the selected I/O pin. Refer to macro 509 * "__HAL_RI_IOSWITCH_CLOSE()". 510 * @note ENABLE: Internal reference voltage connected to I/O group 3 511 * @note DISABLE: Internal reference voltage disconnected from I/O group 3 512 * @retval None 513 */ 514 #define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) 515 #define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) 516 517 /** 518 * @} 519 */ 520 521 /** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration 522 * @{ 523 */ 524 525 /** 526 * @brief Main Flash memory mapped at 0x00000000 527 */ 528 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 529 530 /** @brief System Flash memory mapped at 0x00000000 531 */ 532 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) 533 534 /** @brief Embedded SRAM mapped at 0x00000000 535 */ 536 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1) 537 538 #if defined(FSMC_R_BASE) 539 /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 540 */ 541 #define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) 542 543 #endif /* FSMC_R_BASE */ 544 545 /** 546 * @brief Returns the boot mode as configured by user. 547 * @retval The boot mode as configured by user. The returned value can be one 548 * of the following values: 549 * @arg SYSCFG_BOOT_MAINFLASH 550 * @arg SYSCFG_BOOT_SYSTEMFLASH 551 * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD) 552 * @arg SYSCFG_BOOT_SRAM 553 */ 554 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE) 555 556 /** 557 * @} 558 */ 559 560 /** @defgroup SYSCFG_USBConfig USB DP line Configuration 561 * @{ 562 */ 563 564 /** 565 * @brief Control the internal pull-up on USB DP line. 566 */ 567 #define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) 568 569 #define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) 570 571 /** 572 * @} 573 */ 574 575 /** 576 * @} 577 */ 578 579 /** @defgroup RI_Macris RI: Routing Interface 580 * @{ 581 */ 582 583 /** @defgroup RI_InputCaputureConfig Input Capture configuration 584 * @{ 585 */ 586 587 /** 588 * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin. 589 * @param __TIMSELECT__: Timer select. 590 * This parameter can be one of the following values: 591 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. 592 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. 593 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. 594 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. 595 * @param __INPUT__: selects which pin to be routed to Input Capture. 596 * This parameter must be a value of @ref RI_InputCaptureRouting 597 * e.g. 598 * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1) 599 * allows routing of Input capture IC1 of TIM2 to PA4. 600 * For details about correspondence between RI_INPUTCAPTUREROUTING_x 601 * and I/O pins refer to the parameters' description in the header file 602 * or refer to the product reference manual. 603 * @note Input capture selection bits are not reset by this function. 604 * To reset input capture selection bits, use SYSCFG_RIDeInit() function. 605 * @note The I/O should be configured in alternate function mode (AF14) using 606 * GPIO_PinAFConfig() function. 607 * @retval None. 608 */ 609 #define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \ 610 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ 611 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ 612 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ 613 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \ 614 MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \ 615 }while(0) 616 617 /** 618 * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin. 619 * @param __TIMSELECT__: Timer select. 620 * This parameter can be one of the following values: 621 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. 622 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. 623 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. 624 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. 625 * @param __INPUT__: selects which pin to be routed to Input Capture. 626 * This parameter must be a value of @ref RI_InputCaptureRouting 627 * @retval None. 628 */ 629 #define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \ 630 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ 631 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ 632 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ 633 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \ 634 MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \ 635 }while(0) 636 637 /** 638 * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin. 639 * @param __TIMSELECT__: Timer select. 640 * This parameter can be one of the following values: 641 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. 642 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. 643 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. 644 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. 645 * @param __INPUT__: selects which pin to be routed to Input Capture. 646 * This parameter must be a value of @ref RI_InputCaptureRouting 647 * @retval None. 648 */ 649 #define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \ 650 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ 651 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ 652 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ 653 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \ 654 MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \ 655 }while(0) 656 657 /** 658 * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin. 659 * @param __TIMSELECT__: Timer select. 660 * This parameter can be one of the following values: 661 * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. 662 * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. 663 * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. 664 * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. 665 * @param __INPUT__: selects which pin to be routed to Input Capture. 666 * This parameter must be a value of @ref RI_InputCaptureRouting 667 * @retval None. 668 */ 669 #define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \ 670 do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ 671 assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ 672 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ 673 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \ 674 MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \ 675 }while(0) 676 677 /** 678 * @} 679 */ 680 681 /** @defgroup RI_SwitchControlConfig Switch Control configuration 682 * @{ 683 */ 684 685 /** 686 * @brief Enable or disable the switch control mode. 687 * @note ENABLE: ADC analog switches closed if the corresponding 688 * I/O switch is also closed. 689 * When using COMP1, switch control mode must be enabled. 690 * @note DISABLE: ADC analog switches open or controlled by the ADC interface. 691 * When using the ADC for acquisition, switch control mode 692 * must be disabled. 693 * @note COMP1 comparator and ADC cannot be used at the same time since 694 * they share the ADC switch matrix. 695 * @retval None 696 */ 697 #define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM) 698 699 #define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM) 700 701 /* 702 * @brief Close or Open the routing interface Input Output switches. 703 * @param __IOSWITCH__: selects the I/O analog switch number. 704 * This parameter must be a value of @ref RI_IOSwitch 705 * @retval None 706 */ 707 #define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ 708 if ((__IOSWITCH__) >> 31 != 0 ) \ 709 { \ 710 SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ 711 } \ 712 else \ 713 { \ 714 SET_BIT(RI->ASCR2, (__IOSWITCH__)); \ 715 } \ 716 }while(0) 717 718 #define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ 719 if ((__IOSWITCH__) >> 31 != 0 ) \ 720 { \ 721 CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ 722 } \ 723 else \ 724 { \ 725 CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \ 726 } \ 727 }while(0) 728 729 #if defined (COMP_CSR_SW1) 730 /** 731 * @brief Close or open the internal switch COMP1_SW1. 732 * This switch connects I/O pin PC3 (can be used as ADC channel 13) 733 * and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel 734 * 26) and COMP1 non-inverting input. 735 * Pin PC3 connection depends on another switch setting, refer to 736 * macro "__HAL_ADC_CHANNEL_SPEED_FAST()". 737 * @retval None. 738 */ 739 #define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1) 740 741 #define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1) 742 #endif /* COMP_CSR_SW1 */ 743 744 /** 745 * @} 746 */ 747 748 /** @defgroup RI_HystConfig Hysteresis Activation and Deactivation 749 * @{ 750 */ 751 752 /** 753 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A 754 * When the I/Os are programmed in input mode by standard I/O port 755 * registers, the Schmitt trigger and the hysteresis are enabled by default. 756 * When hysteresis is disabled, it is possible to read the 757 * corresponding port with a trigger level of VDDIO/2. 758 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 759 * This parameter must be a value of @ref RI_Pin 760 * @retval None 761 */ 762 #define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 763 CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \ 764 } while(0) 765 766 #define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 767 SET_BIT(RI->HYSCR1, (__IOPIN__)); \ 768 } while(0) 769 770 /** 771 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports B 772 * When the I/Os are programmed in input mode by standard I/O port 773 * registers, the Schmitt trigger and the hysteresis are enabled by default. 774 * When hysteresis is disabled, it is possible to read the 775 * corresponding port with a trigger level of VDDIO/2. 776 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 777 * This parameter must be a value of @ref RI_Pin 778 * @retval None 779 */ 780 #define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 781 CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ 782 } while(0) 783 784 #define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 785 SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ 786 } while(0) 787 788 /** 789 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports C 790 * When the I/Os are programmed in input mode by standard I/O port 791 * registers, the Schmitt trigger and the hysteresis are enabled by default. 792 * When hysteresis is disabled, it is possible to read the 793 * corresponding port with a trigger level of VDDIO/2. 794 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 795 * This parameter must be a value of @ref RI_Pin 796 * @retval None 797 */ 798 #define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 799 CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \ 800 } while(0) 801 802 #define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 803 SET_BIT(RI->HYSCR2, (__IOPIN__)); \ 804 } while(0) 805 806 /** 807 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports D 808 * When the I/Os are programmed in input mode by standard I/O port 809 * registers, the Schmitt trigger and the hysteresis are enabled by default. 810 * When hysteresis is disabled, it is possible to read the 811 * corresponding port with a trigger level of VDDIO/2. 812 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 813 * This parameter must be a value of @ref RI_Pin 814 * @retval None 815 */ 816 #define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 817 CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ 818 } while(0) 819 820 #define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 821 SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ 822 } while(0) 823 824 #if defined (GPIOE_BASE) 825 826 /** 827 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports E 828 * When the I/Os are programmed in input mode by standard I/O port 829 * registers, the Schmitt trigger and the hysteresis are enabled by default. 830 * When hysteresis is disabled, it is possible to read the 831 * corresponding port with a trigger level of VDDIO/2. 832 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 833 * This parameter must be a value of @ref RI_Pin 834 * @retval None 835 */ 836 #define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 837 CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \ 838 } while(0) 839 840 #define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 841 SET_BIT(RI->HYSCR3, (__IOPIN__)); \ 842 } while(0) 843 844 #endif /* GPIOE_BASE */ 845 846 #if defined(GPIOF_BASE) || defined(GPIOG_BASE) 847 848 /** 849 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports F 850 * When the I/Os are programmed in input mode by standard I/O port 851 * registers, the Schmitt trigger and the hysteresis are enabled by default. 852 * When hysteresis is disabled, it is possible to read the 853 * corresponding port with a trigger level of VDDIO/2. 854 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 855 * This parameter must be a value of @ref RI_Pin 856 * @retval None 857 */ 858 #define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 859 CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ 860 } while(0) 861 862 #define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 863 SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ 864 } while(0) 865 866 /** 867 * @brief Enable or disable Hysteresis of the input schmitt triger of Ports G 868 * When the I/Os are programmed in input mode by standard I/O port 869 * registers, the Schmitt trigger and the hysteresis are enabled by default. 870 * When hysteresis is disabled, it is possible to read the 871 * corresponding port with a trigger level of VDDIO/2. 872 * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. 873 * This parameter must be a value of @ref RI_Pin 874 * @retval None 875 */ 876 #define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 877 CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \ 878 } while(0) 879 880 #define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ 881 SET_BIT(RI->HYSCR4, (__IOPIN__)); \ 882 } while(0) 883 884 #endif /* GPIOF_BASE || GPIOG_BASE */ 885 886 /** 887 * @} 888 */ 889 890 /** 891 * @} 892 */ 893 894 /** 895 * @} 896 */ 897 898 /* Exported functions --------------------------------------------------------*/ 899 900 /** @addtogroup HAL_Exported_Functions 901 * @{ 902 */ 903 904 /** @addtogroup HAL_Exported_Functions_Group1 905 * @{ 906 */ 907 908 /* Initialization and de-initialization functions ******************************/ 909 HAL_StatusTypeDef HAL_Init(void); 910 HAL_StatusTypeDef HAL_DeInit(void); 911 void HAL_MspInit(void); 912 void HAL_MspDeInit(void); 913 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 914 915 /** 916 * @} 917 */ 918 919 /** @addtogroup HAL_Exported_Functions_Group2 920 * @{ 921 */ 922 923 /* Peripheral Control functions ************************************************/ 924 void HAL_IncTick(void); 925 void HAL_Delay(__IO uint32_t Delay); 926 uint32_t HAL_GetTick(void); 927 void HAL_SuspendTick(void); 928 void HAL_ResumeTick(void); 929 uint32_t HAL_GetHalVersion(void); 930 uint32_t HAL_GetREVID(void); 931 uint32_t HAL_GetDEVID(void); 932 void HAL_DBGMCU_EnableDBGSleepMode(void); 933 void HAL_DBGMCU_DisableDBGSleepMode(void); 934 void HAL_DBGMCU_EnableDBGStopMode(void); 935 void HAL_DBGMCU_DisableDBGStopMode(void); 936 void HAL_DBGMCU_EnableDBGStandbyMode(void); 937 void HAL_DBGMCU_DisableDBGStandbyMode(void); 938 939 /** 940 * @} 941 */ 942 943 /** 944 * @} 945 */ 946 947 948 /** 949 * @} 950 */ 951 952 /** 953 * @} 954 */ 955 956 #ifdef __cplusplus 957 } 958 #endif 959 960 #endif /* __STM32L1xx_HAL_H */ 961 962 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 963
