1 /** 2 ****************************************************************************** 3 * @file stm32l152xe.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for STM32L1xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral�s registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 18 * 19 * Redistribution and use in source and binary forms, with or without modification, 20 * are permitted provided that the following conditions are met: 21 * 1. Redistributions of source code must retain the above copyright notice, 22 * this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright notice, 24 * this list of conditions and the following disclaimer in the documentation 25 * and/or other materials provided with the distribution. 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 ****************************************************************************** 42 */ 43 44 /** @addtogroup CMSIS 45 * @{ 46 */ 47 48 /** @addtogroup stm32l152xe 49 * @{ 50 */ 51 52 #ifndef __STM32L152xE_H 53 #define __STM32L152xE_H 54 55 #ifdef __cplusplus 56 extern "C" { 57 #endif 58 59 60 /** @addtogroup Configuration_section_for_CMSIS 61 * @{ 62 */ 63 /** 64 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 65 */ 66 #define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ 67 #define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ 68 #define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 70 71 /** 72 * @} 73 */ 74 75 /** @addtogroup Peripheral_interrupt_number_definition 76 * @{ 77 */ 78 79 /** 80 * @brief STM32L1xx Interrupt Number Definition, according to the selected device 81 * in @ref Library_configuration_section 82 */ 83 84 /*!< Interrupt Number Definition */ 85 typedef enum 86 { 87 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 89 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 91 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 93 SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 95 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 96 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 97 98 /****** STM32L specific Interrupt Numbers ***********************************************************/ 99 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 100 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 101 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ 102 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ 103 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 104 RCC_IRQn = 5, /*!< RCC global Interrupt */ 105 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 106 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 107 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ 108 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 109 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 110 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ 111 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ 112 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ 113 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ 114 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ 115 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ 116 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ 117 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ 118 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ 119 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ 120 DAC_IRQn = 21, /*!< DAC Interrupt */ 121 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ 122 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 123 LCD_IRQn = 24, /*!< LCD Interrupt */ 124 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ 125 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ 126 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ 127 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 128 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 129 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ 130 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 131 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 132 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 133 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 134 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 135 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 136 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 137 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 138 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 139 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 140 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ 141 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ 142 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ 143 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ 144 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ 145 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ 146 UART4_IRQn = 48, /*!< UART4 global Interrupt */ 147 UART5_IRQn = 49, /*!< UART5 global Interrupt */ 148 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ 149 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ 150 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ 151 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ 152 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ 153 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ 154 } IRQn_Type; 155 156 /** 157 * @} 158 */ 159 160 #include "core_cm3.h" 161 #include "system_stm32l1xx.h" 162 #include <stdint.h> 163 164 /** @addtogroup Peripheral_registers_structures 165 * @{ 166 */ 167 168 /** 169 * @brief Analog to Digital Converter 170 */ 171 172 typedef struct 173 { 174 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ 175 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ 176 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ 177 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ 178 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ 179 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ 180 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ 181 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ 182 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ 183 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ 184 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ 185 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ 186 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ 187 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ 188 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ 189 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ 190 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ 191 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ 192 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ 193 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ 194 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ 195 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ 196 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ 197 __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ 198 } ADC_TypeDef; 199 200 typedef struct 201 { 202 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ 203 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ 204 } ADC_Common_TypeDef; 205 206 /** 207 * @brief Comparator 208 */ 209 210 typedef struct 211 { 212 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ 213 } COMP_TypeDef; 214 215 typedef struct 216 { 217 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 218 } COMP_Common_TypeDef; 219 220 /** 221 * @brief CRC calculation unit 222 */ 223 224 typedef struct 225 { 226 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 227 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 228 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ 229 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ 230 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 231 } CRC_TypeDef; 232 233 /** 234 * @brief Digital to Analog Converter 235 */ 236 237 typedef struct 238 { 239 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 240 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 241 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 242 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 243 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 244 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 245 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 246 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 247 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 248 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 249 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 250 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 251 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ 252 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 253 } DAC_TypeDef; 254 255 /** 256 * @brief Debug MCU 257 */ 258 259 typedef struct 260 { 261 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 262 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 263 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 264 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 265 }DBGMCU_TypeDef; 266 267 /** 268 * @brief DMA Controller 269 */ 270 271 typedef struct 272 { 273 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 274 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 275 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 276 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 277 } DMA_Channel_TypeDef; 278 279 typedef struct 280 { 281 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 282 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 283 } DMA_TypeDef; 284 285 /** 286 * @brief External Interrupt/Event Controller 287 */ 288 289 typedef struct 290 { 291 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 292 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 293 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 294 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 295 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 296 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 297 } EXTI_TypeDef; 298 299 /** 300 * @brief FLASH Registers 301 */ 302 typedef struct 303 { 304 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ 305 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ 306 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ 307 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ 308 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ 309 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ 310 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ 311 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */ 312 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */ 313 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */ 314 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */ 315 __IO uint32_t WRPR3; /*!< Write protection register 3, Address offset: 0x84 */ 316 __IO uint32_t WRPR4; /*!< Write protection register 4, Address offset: 0x88 */ 317 } FLASH_TypeDef; 318 319 /** 320 * @brief Option Bytes Registers 321 */ 322 typedef struct 323 { 324 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ 325 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ 326 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */ 327 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */ 328 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */ 329 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */ 330 __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */ 331 __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */ 332 uint32_t RESERVED[24]; /*!< Reserved, 0x20 -> 0x7C */ 333 __IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */ 334 __IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */ 335 } OB_TypeDef; 336 337 /** 338 * @brief Operational Amplifier (OPAMP) 339 */ 340 typedef struct 341 { 342 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ 343 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ 344 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ 345 } OPAMP_TypeDef; 346 347 typedef struct 348 { 349 __IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ 350 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ 351 } OPAMP_Common_TypeDef; 352 353 /** 354 * @brief General Purpose IO 355 */ 356 357 typedef struct 358 { 359 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 360 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 361 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 362 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 363 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 364 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 365 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ 366 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 367 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ 368 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 369 } GPIO_TypeDef; 370 371 /** 372 * @brief SysTem Configuration 373 */ 374 375 typedef struct 376 { 377 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ 378 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ 379 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ 380 } SYSCFG_TypeDef; 381 382 /** 383 * @brief Inter-integrated Circuit Interface 384 */ 385 386 typedef struct 387 { 388 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 389 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 390 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ 391 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ 392 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ 393 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ 394 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ 395 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ 396 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ 397 } I2C_TypeDef; 398 399 /** 400 * @brief Independent WATCHDOG 401 */ 402 403 typedef struct 404 { 405 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ 406 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ 407 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ 408 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ 409 } IWDG_TypeDef; 410 411 /** 412 * @brief LCD 413 */ 414 415 typedef struct 416 { 417 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ 418 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ 419 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ 420 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ 421 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ 422 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ 423 } LCD_TypeDef; 424 425 /** 426 * @brief Power Control 427 */ 428 429 typedef struct 430 { 431 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 432 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 433 } PWR_TypeDef; 434 435 /** 436 * @brief Reset and Clock Control 437 */ 438 439 typedef struct 440 { 441 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 442 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ 443 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ 444 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ 445 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ 446 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ 447 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ 448 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ 449 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ 450 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ 451 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ 452 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ 453 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ 454 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ 455 } RCC_TypeDef; 456 457 /** 458 * @brief Routing Interface 459 */ 460 461 typedef struct 462 { 463 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ 464 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ 465 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ 466 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ 467 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ 468 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ 469 __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ 470 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ 471 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ 472 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ 473 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ 474 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ 475 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ 476 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ 477 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ 478 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ 479 __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ 480 __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ 481 __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ 482 __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ 483 __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ 484 __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ 485 } RI_TypeDef; 486 487 /** 488 * @brief Real-Time Clock 489 */ 490 typedef struct 491 { 492 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 493 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 494 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 495 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 496 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 497 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 498 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ 499 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 500 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 501 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 502 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 503 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 504 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 505 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 506 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 507 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ 508 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 509 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 510 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ 511 uint32_t RESERVED7; /*!< Reserved, 0x4C */ 512 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 513 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 514 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 515 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 516 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 517 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ 518 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ 519 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ 520 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ 521 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ 522 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ 523 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ 524 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ 525 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ 526 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ 527 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ 528 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ 529 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ 530 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ 531 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ 532 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ 533 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ 534 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ 535 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ 536 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ 537 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ 538 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ 539 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ 540 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ 541 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ 542 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ 543 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ 544 } RTC_TypeDef; 545 546 /** 547 * @brief Serial Peripheral Interface 548 */ 549 550 typedef struct 551 { 552 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 553 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 554 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 555 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 556 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 557 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 558 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 559 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 560 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 561 } SPI_TypeDef; 562 563 /** 564 * @brief TIM 565 */ 566 typedef struct 567 { 568 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 569 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 570 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 571 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 572 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 573 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 574 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 575 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 576 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 577 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 578 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 579 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 580 uint32_t RESERVED12; /*!< Reserved, 0x30 */ 581 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 582 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 583 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 584 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 585 uint32_t RESERVED17; /*!< Reserved, 0x44 */ 586 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 587 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 588 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 589 } TIM_TypeDef; 590 /** 591 * @brief Universal Synchronous Asynchronous Receiver Transmitter 592 */ 593 594 typedef struct 595 { 596 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ 597 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ 598 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ 599 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ 600 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ 601 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ 602 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ 603 } USART_TypeDef; 604 605 /** 606 * @brief Universal Serial Bus Full Speed Device 607 */ 608 609 typedef struct 610 { 611 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ 612 __IO uint16_t RESERVED0; /*!< Reserved */ 613 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ 614 __IO uint16_t RESERVED1; /*!< Reserved */ 615 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ 616 __IO uint16_t RESERVED2; /*!< Reserved */ 617 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ 618 __IO uint16_t RESERVED3; /*!< Reserved */ 619 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ 620 __IO uint16_t RESERVED4; /*!< Reserved */ 621 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ 622 __IO uint16_t RESERVED5; /*!< Reserved */ 623 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ 624 __IO uint16_t RESERVED6; /*!< Reserved */ 625 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ 626 __IO uint16_t RESERVED7[17]; /*!< Reserved */ 627 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ 628 __IO uint16_t RESERVED8; /*!< Reserved */ 629 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ 630 __IO uint16_t RESERVED9; /*!< Reserved */ 631 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ 632 __IO uint16_t RESERVEDA; /*!< Reserved */ 633 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ 634 __IO uint16_t RESERVEDB; /*!< Reserved */ 635 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ 636 __IO uint16_t RESERVEDC; /*!< Reserved */ 637 } USB_TypeDef; 638 639 /** 640 * @brief Window WATCHDOG 641 */ 642 typedef struct 643 { 644 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 645 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 646 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 647 } WWDG_TypeDef; 648 649 /** 650 * @brief Universal Serial Bus Full Speed Device 651 */ 652 /** 653 * @} 654 */ 655 656 /** @addtogroup Peripheral_memory_map 657 * @{ 658 */ 659 660 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */ 661 #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */ 662 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ 663 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ 664 #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */ 665 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ 666 #define FLASH_BANK2_BASE ((uint32_t)0x08040000U) /*!< FLASH BANK2 base address in the alias region */ 667 #define FLASH_BANK1_END ((uint32_t)0x0803FFFFU) /*!< Program end FLASH BANK1 address */ 668 #define FLASH_BANK2_END ((uint32_t)0x0807FFFFU) /*!< Program end FLASH BANK2 address */ 669 #define FLASH_EEPROM_END ((uint32_t)0x08083FFFU) /*!< FLASH EEPROM end address (16KB) */ 670 671 /*!< Peripheral memory map */ 672 #define APB1PERIPH_BASE PERIPH_BASE 673 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) 674 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) 675 676 /*!< APB1 peripherals */ 677 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) 678 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) 679 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) 680 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U) 681 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U) 682 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U) 683 #define LCD_BASE (APB1PERIPH_BASE + 0x00002400U) 684 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) 685 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) 686 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) 687 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) 688 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U) 689 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) 690 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) 691 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U) 692 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000U) 693 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) 694 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) 695 696 /* USB device FS */ 697 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ 698 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ 699 700 /* USB device FS SRAM */ 701 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) 702 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400U) 703 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U) 704 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04U) 705 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU) 706 707 /*!< APB2 peripherals */ 708 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U) 709 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) 710 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U) 711 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U) 712 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U) 713 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) 714 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700U) 715 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) 716 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) 717 718 /*!< AHB peripherals */ 719 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U) 720 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U) 721 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U) 722 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U) 723 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U) 724 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U) 725 #define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800U) 726 #define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00U) 727 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) 728 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800U) 729 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */ 730 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ 731 #define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ 732 #define UID_BASE ((uint32_t)0x1FF800D0U) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ 733 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) 734 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) 735 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) 736 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) 737 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) 738 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) 739 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) 740 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) 741 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U) 742 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U) 743 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU) 744 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U) 745 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U) 746 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U) 747 #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */ 748 749 /** 750 * @} 751 */ 752 753 /** @addtogroup Peripheral_declaration 754 * @{ 755 */ 756 757 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 758 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 759 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 760 #define TIM5 ((TIM_TypeDef *) TIM5_BASE) 761 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 762 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 763 #define LCD ((LCD_TypeDef *) LCD_BASE) 764 #define RTC ((RTC_TypeDef *) RTC_BASE) 765 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 766 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 767 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 768 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 769 #define USART2 ((USART_TypeDef *) USART2_BASE) 770 #define USART3 ((USART_TypeDef *) USART3_BASE) 771 #define UART4 ((USART_TypeDef *) UART4_BASE) 772 #define UART5 ((USART_TypeDef *) UART5_BASE) 773 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 774 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 775 /* USB device FS */ 776 #define USB ((USB_TypeDef *) USB_BASE) 777 /* USB device FS SRAM */ 778 #define PWR ((PWR_TypeDef *) PWR_BASE) 779 780 #define DAC1 ((DAC_TypeDef *) DAC_BASE) 781 /* Legacy define */ 782 #define DAC DAC1 783 784 #define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */ 785 #define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ 786 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ 787 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */ 788 789 #define RI ((RI_TypeDef *) RI_BASE) 790 791 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) 792 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) 793 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U)) 794 #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE) 795 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 796 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 797 #define TIM9 ((TIM_TypeDef *) TIM9_BASE) 798 #define TIM10 ((TIM_TypeDef *) TIM10_BASE) 799 #define TIM11 ((TIM_TypeDef *) TIM11_BASE) 800 801 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 802 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 803 /* Legacy defines */ 804 #define ADC ADC1_COMMON 805 806 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 807 #define USART1 ((USART_TypeDef *) USART1_BASE) 808 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 809 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 810 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 811 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 812 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 813 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 814 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 815 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 816 #define CRC ((CRC_TypeDef *) CRC_BASE) 817 #define RCC ((RCC_TypeDef *) RCC_BASE) 818 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 819 #define OB ((OB_TypeDef *) OB_BASE) 820 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 821 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 822 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 823 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 824 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 825 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 826 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 827 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 828 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 829 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 830 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 831 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 832 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 833 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 834 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 835 836 /** 837 * @} 838 */ 839 840 /** @addtogroup Exported_constants 841 * @{ 842 */ 843 844 /** @addtogroup Peripheral_Registers_Bits_Definition 845 * @{ 846 */ 847 848 /******************************************************************************/ 849 /* Peripheral Registers Bits Definition */ 850 /******************************************************************************/ 851 /******************************************************************************/ 852 /* */ 853 /* Analog to Digital Converter (ADC) */ 854 /* */ 855 /******************************************************************************/ 856 857 /******************** Bit definition for ADC_SR register ********************/ 858 #define ADC_SR_AWD_Pos (0U) 859 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ 860 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ 861 #define ADC_SR_EOCS_Pos (1U) 862 #define ADC_SR_EOCS_Msk (0x1U << ADC_SR_EOCS_Pos) /*!< 0x00000002 */ 863 #define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */ 864 #define ADC_SR_JEOS_Pos (2U) 865 #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ 866 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 867 #define ADC_SR_JSTRT_Pos (3U) 868 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ 869 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ 870 #define ADC_SR_STRT_Pos (4U) 871 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ 872 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ 873 #define ADC_SR_OVR_Pos (5U) 874 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */ 875 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */ 876 #define ADC_SR_ADONS_Pos (6U) 877 #define ADC_SR_ADONS_Msk (0x1U << ADC_SR_ADONS_Pos) /*!< 0x00000040 */ 878 #define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */ 879 #define ADC_SR_RCNR_Pos (8U) 880 #define ADC_SR_RCNR_Msk (0x1U << ADC_SR_RCNR_Pos) /*!< 0x00000100 */ 881 #define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */ 882 #define ADC_SR_JCNR_Pos (9U) 883 #define ADC_SR_JCNR_Msk (0x1U << ADC_SR_JCNR_Pos) /*!< 0x00000200 */ 884 #define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */ 885 886 /* Legacy defines */ 887 #define ADC_SR_EOC (ADC_SR_EOCS) 888 #define ADC_SR_JEOC (ADC_SR_JEOS) 889 890 /******************* Bit definition for ADC_CR1 register ********************/ 891 #define ADC_CR1_AWDCH_Pos (0U) 892 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ 893 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 894 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ 895 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ 896 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ 897 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ 898 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ 899 900 #define ADC_CR1_EOCSIE_Pos (5U) 901 #define ADC_CR1_EOCSIE_Msk (0x1U << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */ 902 #define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */ 903 #define ADC_CR1_AWDIE_Pos (6U) 904 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ 905 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ 906 #define ADC_CR1_JEOSIE_Pos (7U) 907 #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ 908 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 909 #define ADC_CR1_SCAN_Pos (8U) 910 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ 911 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ 912 #define ADC_CR1_AWDSGL_Pos (9U) 913 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ 914 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 915 #define ADC_CR1_JAUTO_Pos (10U) 916 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ 917 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 918 #define ADC_CR1_DISCEN_Pos (11U) 919 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ 920 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 921 #define ADC_CR1_JDISCEN_Pos (12U) 922 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ 923 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ 924 925 #define ADC_CR1_DISCNUM_Pos (13U) 926 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ 927 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ 928 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ 929 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ 930 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ 931 932 #define ADC_CR1_PDD_Pos (16U) 933 #define ADC_CR1_PDD_Msk (0x1U << ADC_CR1_PDD_Pos) /*!< 0x00010000 */ 934 #define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */ 935 #define ADC_CR1_PDI_Pos (17U) 936 #define ADC_CR1_PDI_Msk (0x1U << ADC_CR1_PDI_Pos) /*!< 0x00020000 */ 937 #define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */ 938 939 #define ADC_CR1_JAWDEN_Pos (22U) 940 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ 941 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 942 #define ADC_CR1_AWDEN_Pos (23U) 943 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ 944 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 945 946 #define ADC_CR1_RES_Pos (24U) 947 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */ 948 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */ 949 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */ 950 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */ 951 952 #define ADC_CR1_OVRIE_Pos (26U) 953 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ 954 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 955 956 /* Legacy defines */ 957 #define ADC_CR1_EOCIE (ADC_CR1_EOCSIE) 958 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) 959 960 /******************* Bit definition for ADC_CR2 register ********************/ 961 #define ADC_CR2_ADON_Pos (0U) 962 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ 963 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ 964 #define ADC_CR2_CONT_Pos (1U) 965 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ 966 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ 967 #define ADC_CR2_CFG_Pos (2U) 968 #define ADC_CR2_CFG_Msk (0x1U << ADC_CR2_CFG_Pos) /*!< 0x00000004 */ 969 #define ADC_CR2_CFG ADC_CR2_CFG_Msk /*!< ADC channels bank selection */ 970 971 #define ADC_CR2_DELS_Pos (4U) 972 #define ADC_CR2_DELS_Msk (0x7U << ADC_CR2_DELS_Pos) /*!< 0x00000070 */ 973 #define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */ 974 #define ADC_CR2_DELS_0 (0x1U << ADC_CR2_DELS_Pos) /*!< 0x00000010 */ 975 #define ADC_CR2_DELS_1 (0x2U << ADC_CR2_DELS_Pos) /*!< 0x00000020 */ 976 #define ADC_CR2_DELS_2 (0x4U << ADC_CR2_DELS_Pos) /*!< 0x00000040 */ 977 978 #define ADC_CR2_DMA_Pos (8U) 979 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ 980 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ 981 #define ADC_CR2_DDS_Pos (9U) 982 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ 983 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */ 984 #define ADC_CR2_EOCS_Pos (10U) 985 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ 986 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */ 987 #define ADC_CR2_ALIGN_Pos (11U) 988 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ 989 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ 990 991 #define ADC_CR2_JEXTSEL_Pos (16U) 992 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ 993 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 994 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ 995 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ 996 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ 997 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ 998 999 #define ADC_CR2_JEXTEN_Pos (20U) 1000 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ 1001 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ 1002 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ 1003 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ 1004 1005 #define ADC_CR2_JSWSTART_Pos (22U) 1006 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ 1007 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ 1008 1009 #define ADC_CR2_EXTSEL_Pos (24U) 1010 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ 1011 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ 1012 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ 1013 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ 1014 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ 1015 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ 1016 1017 #define ADC_CR2_EXTEN_Pos (28U) 1018 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ 1019 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 1020 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ 1021 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ 1022 1023 #define ADC_CR2_SWSTART_Pos (30U) 1024 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ 1025 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ 1026 1027 /****************** Bit definition for ADC_SMPR1 register *******************/ 1028 #define ADC_SMPR1_SMP20_Pos (0U) 1029 #define ADC_SMPR1_SMP20_Msk (0x7U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */ 1030 #define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */ 1031 #define ADC_SMPR1_SMP20_0 (0x1U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */ 1032 #define ADC_SMPR1_SMP20_1 (0x2U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */ 1033 #define ADC_SMPR1_SMP20_2 (0x4U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */ 1034 1035 #define ADC_SMPR1_SMP21_Pos (3U) 1036 #define ADC_SMPR1_SMP21_Msk (0x7U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */ 1037 #define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */ 1038 #define ADC_SMPR1_SMP21_0 (0x1U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */ 1039 #define ADC_SMPR1_SMP21_1 (0x2U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */ 1040 #define ADC_SMPR1_SMP21_2 (0x4U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */ 1041 1042 #define ADC_SMPR1_SMP22_Pos (6U) 1043 #define ADC_SMPR1_SMP22_Msk (0x7U << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */ 1044 #define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */ 1045 #define ADC_SMPR1_SMP22_0 (0x1U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */ 1046 #define ADC_SMPR1_SMP22_1 (0x2U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */ 1047 #define ADC_SMPR1_SMP22_2 (0x4U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */ 1048 1049 #define ADC_SMPR1_SMP23_Pos (9U) 1050 #define ADC_SMPR1_SMP23_Msk (0x7U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */ 1051 #define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */ 1052 #define ADC_SMPR1_SMP23_0 (0x1U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */ 1053 #define ADC_SMPR1_SMP23_1 (0x2U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */ 1054 #define ADC_SMPR1_SMP23_2 (0x4U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */ 1055 1056 #define ADC_SMPR1_SMP24_Pos (12U) 1057 #define ADC_SMPR1_SMP24_Msk (0x7U << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */ 1058 #define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */ 1059 #define ADC_SMPR1_SMP24_0 (0x1U << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */ 1060 #define ADC_SMPR1_SMP24_1 (0x2U << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */ 1061 #define ADC_SMPR1_SMP24_2 (0x4U << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */ 1062 1063 #define ADC_SMPR1_SMP25_Pos (15U) 1064 #define ADC_SMPR1_SMP25_Msk (0x7U << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */ 1065 #define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */ 1066 #define ADC_SMPR1_SMP25_0 (0x1U << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */ 1067 #define ADC_SMPR1_SMP25_1 (0x2U << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */ 1068 #define ADC_SMPR1_SMP25_2 (0x4U << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */ 1069 1070 #define ADC_SMPR1_SMP26_Pos (18U) 1071 #define ADC_SMPR1_SMP26_Msk (0x7U << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */ 1072 #define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */ 1073 #define ADC_SMPR1_SMP26_0 (0x1U << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */ 1074 #define ADC_SMPR1_SMP26_1 (0x2U << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */ 1075 #define ADC_SMPR1_SMP26_2 (0x4U << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */ 1076 1077 #define ADC_SMPR1_SMP27_Pos (21U) 1078 #define ADC_SMPR1_SMP27_Msk (0x7U << ADC_SMPR1_SMP27_Pos) /*!< 0x00E00000 */ 1079 #define ADC_SMPR1_SMP27 ADC_SMPR1_SMP27_Msk /*!< ADC channel 27 sampling time selection */ 1080 #define ADC_SMPR1_SMP27_0 (0x1U << ADC_SMPR1_SMP27_Pos) /*!< 0x00200000 */ 1081 #define ADC_SMPR1_SMP27_1 (0x2U << ADC_SMPR1_SMP27_Pos) /*!< 0x00400000 */ 1082 #define ADC_SMPR1_SMP27_2 (0x4U << ADC_SMPR1_SMP27_Pos) /*!< 0x00800000 */ 1083 1084 #define ADC_SMPR1_SMP28_Pos (24U) 1085 #define ADC_SMPR1_SMP28_Msk (0x7U << ADC_SMPR1_SMP28_Pos) /*!< 0x07000000 */ 1086 #define ADC_SMPR1_SMP28 ADC_SMPR1_SMP28_Msk /*!< ADC channel 28 sampling time selection */ 1087 #define ADC_SMPR1_SMP28_0 (0x1U << ADC_SMPR1_SMP28_Pos) /*!< 0x01000000 */ 1088 #define ADC_SMPR1_SMP28_1 (0x2U << ADC_SMPR1_SMP28_Pos) /*!< 0x02000000 */ 1089 #define ADC_SMPR1_SMP28_2 (0x4U << ADC_SMPR1_SMP28_Pos) /*!< 0x04000000 */ 1090 1091 #define ADC_SMPR1_SMP29_Pos (27U) 1092 #define ADC_SMPR1_SMP29_Msk (0x7U << ADC_SMPR1_SMP29_Pos) /*!< 0x38000000 */ 1093 #define ADC_SMPR1_SMP29 ADC_SMPR1_SMP29_Msk /*!< ADC channel 29 sampling time selection */ 1094 #define ADC_SMPR1_SMP29_0 (0x1U << ADC_SMPR1_SMP29_Pos) /*!< 0x08000000 */ 1095 #define ADC_SMPR1_SMP29_1 (0x2U << ADC_SMPR1_SMP29_Pos) /*!< 0x10000000 */ 1096 #define ADC_SMPR1_SMP29_2 (0x4U << ADC_SMPR1_SMP29_Pos) /*!< 0x20000000 */ 1097 1098 /****************** Bit definition for ADC_SMPR2 register *******************/ 1099 #define ADC_SMPR2_SMP10_Pos (0U) 1100 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ 1101 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 1102 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ 1103 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ 1104 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ 1105 1106 #define ADC_SMPR2_SMP11_Pos (3U) 1107 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ 1108 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 1109 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ 1110 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ 1111 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ 1112 1113 #define ADC_SMPR2_SMP12_Pos (6U) 1114 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ 1115 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 1116 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ 1117 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ 1118 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ 1119 1120 #define ADC_SMPR2_SMP13_Pos (9U) 1121 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ 1122 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 1123 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ 1124 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ 1125 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ 1126 1127 #define ADC_SMPR2_SMP14_Pos (12U) 1128 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ 1129 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 1130 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ 1131 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ 1132 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ 1133 1134 #define ADC_SMPR2_SMP15_Pos (15U) 1135 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ 1136 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */ 1137 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ 1138 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ 1139 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ 1140 1141 #define ADC_SMPR2_SMP16_Pos (18U) 1142 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ 1143 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 1144 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ 1145 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ 1146 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ 1147 1148 #define ADC_SMPR2_SMP17_Pos (21U) 1149 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ 1150 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 1151 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ 1152 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ 1153 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ 1154 1155 #define ADC_SMPR2_SMP18_Pos (24U) 1156 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ 1157 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ 1158 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ 1159 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ 1160 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ 1161 1162 #define ADC_SMPR2_SMP19_Pos (27U) 1163 #define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ 1164 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */ 1165 #define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ 1166 #define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ 1167 #define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ 1168 1169 /****************** Bit definition for ADC_SMPR3 register *******************/ 1170 #define ADC_SMPR3_SMP0_Pos (0U) 1171 #define ADC_SMPR3_SMP0_Msk (0x7U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */ 1172 #define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 1173 #define ADC_SMPR3_SMP0_0 (0x1U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */ 1174 #define ADC_SMPR3_SMP0_1 (0x2U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */ 1175 #define ADC_SMPR3_SMP0_2 (0x4U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */ 1176 1177 #define ADC_SMPR3_SMP1_Pos (3U) 1178 #define ADC_SMPR3_SMP1_Msk (0x7U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */ 1179 #define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 1180 #define ADC_SMPR3_SMP1_0 (0x1U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */ 1181 #define ADC_SMPR3_SMP1_1 (0x2U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */ 1182 #define ADC_SMPR3_SMP1_2 (0x4U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */ 1183 1184 #define ADC_SMPR3_SMP2_Pos (6U) 1185 #define ADC_SMPR3_SMP2_Msk (0x7U << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */ 1186 #define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 1187 #define ADC_SMPR3_SMP2_0 (0x1U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */ 1188 #define ADC_SMPR3_SMP2_1 (0x2U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */ 1189 #define ADC_SMPR3_SMP2_2 (0x4U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */ 1190 1191 #define ADC_SMPR3_SMP3_Pos (9U) 1192 #define ADC_SMPR3_SMP3_Msk (0x7U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */ 1193 #define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 1194 #define ADC_SMPR3_SMP3_0 (0x1U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */ 1195 #define ADC_SMPR3_SMP3_1 (0x2U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */ 1196 #define ADC_SMPR3_SMP3_2 (0x4U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */ 1197 1198 #define ADC_SMPR3_SMP4_Pos (12U) 1199 #define ADC_SMPR3_SMP4_Msk (0x7U << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */ 1200 #define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 1201 #define ADC_SMPR3_SMP4_0 (0x1U << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */ 1202 #define ADC_SMPR3_SMP4_1 (0x2U << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */ 1203 #define ADC_SMPR3_SMP4_2 (0x4U << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */ 1204 1205 #define ADC_SMPR3_SMP5_Pos (15U) 1206 #define ADC_SMPR3_SMP5_Msk (0x7U << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */ 1207 #define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 1208 #define ADC_SMPR3_SMP5_0 (0x1U << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */ 1209 #define ADC_SMPR3_SMP5_1 (0x2U << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */ 1210 #define ADC_SMPR3_SMP5_2 (0x4U << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */ 1211 1212 #define ADC_SMPR3_SMP6_Pos (18U) 1213 #define ADC_SMPR3_SMP6_Msk (0x7U << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */ 1214 #define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 1215 #define ADC_SMPR3_SMP6_0 (0x1U << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */ 1216 #define ADC_SMPR3_SMP6_1 (0x2U << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */ 1217 #define ADC_SMPR3_SMP6_2 (0x4U << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */ 1218 1219 #define ADC_SMPR3_SMP7_Pos (21U) 1220 #define ADC_SMPR3_SMP7_Msk (0x7U << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */ 1221 #define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 1222 #define ADC_SMPR3_SMP7_0 (0x1U << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */ 1223 #define ADC_SMPR3_SMP7_1 (0x2U << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */ 1224 #define ADC_SMPR3_SMP7_2 (0x4U << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */ 1225 1226 #define ADC_SMPR3_SMP8_Pos (24U) 1227 #define ADC_SMPR3_SMP8_Msk (0x7U << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */ 1228 #define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 1229 #define ADC_SMPR3_SMP8_0 (0x1U << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */ 1230 #define ADC_SMPR3_SMP8_1 (0x2U << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */ 1231 #define ADC_SMPR3_SMP8_2 (0x4U << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */ 1232 1233 #define ADC_SMPR3_SMP9_Pos (27U) 1234 #define ADC_SMPR3_SMP9_Msk (0x7U << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */ 1235 #define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 1236 #define ADC_SMPR3_SMP9_0 (0x1U << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */ 1237 #define ADC_SMPR3_SMP9_1 (0x2U << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */ 1238 #define ADC_SMPR3_SMP9_2 (0x4U << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */ 1239 1240 /****************** Bit definition for ADC_JOFR1 register *******************/ 1241 #define ADC_JOFR1_JOFFSET1_Pos (0U) 1242 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ 1243 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ 1244 1245 /****************** Bit definition for ADC_JOFR2 register *******************/ 1246 #define ADC_JOFR2_JOFFSET2_Pos (0U) 1247 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ 1248 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ 1249 1250 /****************** Bit definition for ADC_JOFR3 register *******************/ 1251 #define ADC_JOFR3_JOFFSET3_Pos (0U) 1252 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ 1253 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ 1254 1255 /****************** Bit definition for ADC_JOFR4 register *******************/ 1256 #define ADC_JOFR4_JOFFSET4_Pos (0U) 1257 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ 1258 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ 1259 1260 /******************* Bit definition for ADC_HTR register ********************/ 1261 #define ADC_HTR_HT_Pos (0U) 1262 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ 1263 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ 1264 1265 /******************* Bit definition for ADC_LTR register ********************/ 1266 #define ADC_LTR_LT_Pos (0U) 1267 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ 1268 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ 1269 1270 /******************* Bit definition for ADC_SQR1 register *******************/ 1271 #define ADC_SQR1_L_Pos (20U) 1272 #define ADC_SQR1_L_Msk (0x1FU << ADC_SQR1_L_Pos) /*!< 0x01F00000 */ 1273 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 1274 #define ADC_SQR1_L_0 (0x01U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ 1275 #define ADC_SQR1_L_1 (0x02U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ 1276 #define ADC_SQR1_L_2 (0x04U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ 1277 #define ADC_SQR1_L_3 (0x08U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ 1278 #define ADC_SQR1_L_4 (0x10U << ADC_SQR1_L_Pos) /*!< 0x01000000 */ 1279 1280 #define ADC_SQR1_SQ28_Pos (15U) 1281 #define ADC_SQR1_SQ28_Msk (0x1FU << ADC_SQR1_SQ28_Pos) /*!< 0x000F8000 */ 1282 #define ADC_SQR1_SQ28 ADC_SQR1_SQ28_Msk /*!< ADC group regular sequencer rank 28 */ 1283 #define ADC_SQR1_SQ28_0 (0x01U << ADC_SQR1_SQ28_Pos) /*!< 0x00008000 */ 1284 #define ADC_SQR1_SQ28_1 (0x02U << ADC_SQR1_SQ28_Pos) /*!< 0x00010000 */ 1285 #define ADC_SQR1_SQ28_2 (0x04U << ADC_SQR1_SQ28_Pos) /*!< 0x00020000 */ 1286 #define ADC_SQR1_SQ28_3 (0x08U << ADC_SQR1_SQ28_Pos) /*!< 0x00040000 */ 1287 #define ADC_SQR1_SQ28_4 (0x10U << ADC_SQR1_SQ28_Pos) /*!< 0x00080000 */ 1288 1289 #define ADC_SQR1_SQ27_Pos (10U) 1290 #define ADC_SQR1_SQ27_Msk (0x1FU << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */ 1291 #define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */ 1292 #define ADC_SQR1_SQ27_0 (0x01U << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */ 1293 #define ADC_SQR1_SQ27_1 (0x02U << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */ 1294 #define ADC_SQR1_SQ27_2 (0x04U << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */ 1295 #define ADC_SQR1_SQ27_3 (0x08U << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */ 1296 #define ADC_SQR1_SQ27_4 (0x10U << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */ 1297 1298 #define ADC_SQR1_SQ26_Pos (5U) 1299 #define ADC_SQR1_SQ26_Msk (0x1FU << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */ 1300 #define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */ 1301 #define ADC_SQR1_SQ26_0 (0x01U << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */ 1302 #define ADC_SQR1_SQ26_1 (0x02U << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */ 1303 #define ADC_SQR1_SQ26_2 (0x04U << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */ 1304 #define ADC_SQR1_SQ26_3 (0x08U << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */ 1305 #define ADC_SQR1_SQ26_4 (0x10U << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */ 1306 1307 #define ADC_SQR1_SQ25_Pos (0U) 1308 #define ADC_SQR1_SQ25_Msk (0x1FU << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */ 1309 #define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */ 1310 #define ADC_SQR1_SQ25_0 (0x01U << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */ 1311 #define ADC_SQR1_SQ25_1 (0x02U << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */ 1312 #define ADC_SQR1_SQ25_2 (0x04U << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */ 1313 #define ADC_SQR1_SQ25_3 (0x08U << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */ 1314 #define ADC_SQR1_SQ25_4 (0x10U << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */ 1315 1316 /******************* Bit definition for ADC_SQR2 register *******************/ 1317 #define ADC_SQR2_SQ19_Pos (0U) 1318 #define ADC_SQR2_SQ19_Msk (0x1FU << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */ 1319 #define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */ 1320 #define ADC_SQR2_SQ19_0 (0x01U << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */ 1321 #define ADC_SQR2_SQ19_1 (0x02U << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */ 1322 #define ADC_SQR2_SQ19_2 (0x04U << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */ 1323 #define ADC_SQR2_SQ19_3 (0x08U << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */ 1324 #define ADC_SQR2_SQ19_4 (0x10U << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */ 1325 1326 #define ADC_SQR2_SQ20_Pos (5U) 1327 #define ADC_SQR2_SQ20_Msk (0x1FU << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */ 1328 #define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */ 1329 #define ADC_SQR2_SQ20_0 (0x01U << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */ 1330 #define ADC_SQR2_SQ20_1 (0x02U << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */ 1331 #define ADC_SQR2_SQ20_2 (0x04U << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */ 1332 #define ADC_SQR2_SQ20_3 (0x08U << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */ 1333 #define ADC_SQR2_SQ20_4 (0x10U << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */ 1334 1335 #define ADC_SQR2_SQ21_Pos (10U) 1336 #define ADC_SQR2_SQ21_Msk (0x1FU << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */ 1337 #define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */ 1338 #define ADC_SQR2_SQ21_0 (0x01U << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */ 1339 #define ADC_SQR2_SQ21_1 (0x02U << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */ 1340 #define ADC_SQR2_SQ21_2 (0x04U << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */ 1341 #define ADC_SQR2_SQ21_3 (0x08U << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */ 1342 #define ADC_SQR2_SQ21_4 (0x10U << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */ 1343 1344 #define ADC_SQR2_SQ22_Pos (15U) 1345 #define ADC_SQR2_SQ22_Msk (0x1FU << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */ 1346 #define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */ 1347 #define ADC_SQR2_SQ22_0 (0x01U << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */ 1348 #define ADC_SQR2_SQ22_1 (0x02U << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */ 1349 #define ADC_SQR2_SQ22_2 (0x04U << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */ 1350 #define ADC_SQR2_SQ22_3 (0x08U << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */ 1351 #define ADC_SQR2_SQ22_4 (0x10U << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */ 1352 1353 #define ADC_SQR2_SQ23_Pos (20U) 1354 #define ADC_SQR2_SQ23_Msk (0x1FU << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */ 1355 #define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */ 1356 #define ADC_SQR2_SQ23_0 (0x01U << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */ 1357 #define ADC_SQR2_SQ23_1 (0x02U << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */ 1358 #define ADC_SQR2_SQ23_2 (0x04U << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */ 1359 #define ADC_SQR2_SQ23_3 (0x08U << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */ 1360 #define ADC_SQR2_SQ23_4 (0x10U << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */ 1361 1362 #define ADC_SQR2_SQ24_Pos (25U) 1363 #define ADC_SQR2_SQ24_Msk (0x1FU << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */ 1364 #define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */ 1365 #define ADC_SQR2_SQ24_0 (0x01U << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */ 1366 #define ADC_SQR2_SQ24_1 (0x02U << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */ 1367 #define ADC_SQR2_SQ24_2 (0x04U << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */ 1368 #define ADC_SQR2_SQ24_3 (0x08U << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */ 1369 #define ADC_SQR2_SQ24_4 (0x10U << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */ 1370 1371 /******************* Bit definition for ADC_SQR3 register *******************/ 1372 #define ADC_SQR3_SQ13_Pos (0U) 1373 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */ 1374 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 1375 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */ 1376 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */ 1377 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */ 1378 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */ 1379 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */ 1380 1381 #define ADC_SQR3_SQ14_Pos (5U) 1382 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */ 1383 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 1384 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */ 1385 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */ 1386 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */ 1387 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */ 1388 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */ 1389 1390 #define ADC_SQR3_SQ15_Pos (10U) 1391 #define ADC_SQR3_SQ15_Msk (0x1FU << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */ 1392 #define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 1393 #define ADC_SQR3_SQ15_0 (0x01U << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */ 1394 #define ADC_SQR3_SQ15_1 (0x02U << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */ 1395 #define ADC_SQR3_SQ15_2 (0x04U << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */ 1396 #define ADC_SQR3_SQ15_3 (0x08U << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */ 1397 #define ADC_SQR3_SQ15_4 (0x10U << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */ 1398 1399 #define ADC_SQR3_SQ16_Pos (15U) 1400 #define ADC_SQR3_SQ16_Msk (0x1FU << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */ 1401 #define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 1402 #define ADC_SQR3_SQ16_0 (0x01U << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */ 1403 #define ADC_SQR3_SQ16_1 (0x02U << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */ 1404 #define ADC_SQR3_SQ16_2 (0x04U << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */ 1405 #define ADC_SQR3_SQ16_3 (0x08U << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */ 1406 #define ADC_SQR3_SQ16_4 (0x10U << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */ 1407 1408 #define ADC_SQR3_SQ17_Pos (20U) 1409 #define ADC_SQR3_SQ17_Msk (0x1FU << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */ 1410 #define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */ 1411 #define ADC_SQR3_SQ17_0 (0x01U << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */ 1412 #define ADC_SQR3_SQ17_1 (0x02U << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */ 1413 #define ADC_SQR3_SQ17_2 (0x04U << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */ 1414 #define ADC_SQR3_SQ17_3 (0x08U << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */ 1415 #define ADC_SQR3_SQ17_4 (0x10U << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */ 1416 1417 #define ADC_SQR3_SQ18_Pos (25U) 1418 #define ADC_SQR3_SQ18_Msk (0x1FU << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */ 1419 #define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */ 1420 #define ADC_SQR3_SQ18_0 (0x01U << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */ 1421 #define ADC_SQR3_SQ18_1 (0x02U << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */ 1422 #define ADC_SQR3_SQ18_2 (0x04U << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */ 1423 #define ADC_SQR3_SQ18_3 (0x08U << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */ 1424 #define ADC_SQR3_SQ18_4 (0x10U << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */ 1425 1426 /******************* Bit definition for ADC_SQR4 register *******************/ 1427 #define ADC_SQR4_SQ7_Pos (0U) 1428 #define ADC_SQR4_SQ7_Msk (0x1FU << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */ 1429 #define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 1430 #define ADC_SQR4_SQ7_0 (0x01U << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */ 1431 #define ADC_SQR4_SQ7_1 (0x02U << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */ 1432 #define ADC_SQR4_SQ7_2 (0x04U << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */ 1433 #define ADC_SQR4_SQ7_3 (0x08U << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */ 1434 #define ADC_SQR4_SQ7_4 (0x10U << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */ 1435 1436 #define ADC_SQR4_SQ8_Pos (5U) 1437 #define ADC_SQR4_SQ8_Msk (0x1FU << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */ 1438 #define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 1439 #define ADC_SQR4_SQ8_0 (0x01U << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */ 1440 #define ADC_SQR4_SQ8_1 (0x02U << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */ 1441 #define ADC_SQR4_SQ8_2 (0x04U << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */ 1442 #define ADC_SQR4_SQ8_3 (0x08U << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */ 1443 #define ADC_SQR4_SQ8_4 (0x10U << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */ 1444 1445 #define ADC_SQR4_SQ9_Pos (10U) 1446 #define ADC_SQR4_SQ9_Msk (0x1FU << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */ 1447 #define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 1448 #define ADC_SQR4_SQ9_0 (0x01U << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */ 1449 #define ADC_SQR4_SQ9_1 (0x02U << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */ 1450 #define ADC_SQR4_SQ9_2 (0x04U << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */ 1451 #define ADC_SQR4_SQ9_3 (0x08U << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */ 1452 #define ADC_SQR4_SQ9_4 (0x10U << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */ 1453 1454 #define ADC_SQR4_SQ10_Pos (15U) 1455 #define ADC_SQR4_SQ10_Msk (0x1FU << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */ 1456 #define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 1457 #define ADC_SQR4_SQ10_0 (0x01U << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */ 1458 #define ADC_SQR4_SQ10_1 (0x02U << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */ 1459 #define ADC_SQR4_SQ10_2 (0x04U << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */ 1460 #define ADC_SQR4_SQ10_3 (0x08U << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */ 1461 #define ADC_SQR4_SQ10_4 (0x10U << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */ 1462 1463 #define ADC_SQR4_SQ11_Pos (20U) 1464 #define ADC_SQR4_SQ11_Msk (0x1FU << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */ 1465 #define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ 1466 #define ADC_SQR4_SQ11_0 (0x01U << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */ 1467 #define ADC_SQR4_SQ11_1 (0x02U << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */ 1468 #define ADC_SQR4_SQ11_2 (0x04U << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */ 1469 #define ADC_SQR4_SQ11_3 (0x08U << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */ 1470 #define ADC_SQR4_SQ11_4 (0x10U << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */ 1471 1472 #define ADC_SQR4_SQ12_Pos (25U) 1473 #define ADC_SQR4_SQ12_Msk (0x1FU << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */ 1474 #define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 1475 #define ADC_SQR4_SQ12_0 (0x01U << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */ 1476 #define ADC_SQR4_SQ12_1 (0x02U << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */ 1477 #define ADC_SQR4_SQ12_2 (0x04U << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */ 1478 #define ADC_SQR4_SQ12_3 (0x08U << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */ 1479 #define ADC_SQR4_SQ12_4 (0x10U << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */ 1480 1481 /******************* Bit definition for ADC_SQR5 register *******************/ 1482 #define ADC_SQR5_SQ1_Pos (0U) 1483 #define ADC_SQR5_SQ1_Msk (0x1FU << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */ 1484 #define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 1485 #define ADC_SQR5_SQ1_0 (0x01U << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */ 1486 #define ADC_SQR5_SQ1_1 (0x02U << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */ 1487 #define ADC_SQR5_SQ1_2 (0x04U << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */ 1488 #define ADC_SQR5_SQ1_3 (0x08U << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */ 1489 #define ADC_SQR5_SQ1_4 (0x10U << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */ 1490 1491 #define ADC_SQR5_SQ2_Pos (5U) 1492 #define ADC_SQR5_SQ2_Msk (0x1FU << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */ 1493 #define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 1494 #define ADC_SQR5_SQ2_0 (0x01U << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */ 1495 #define ADC_SQR5_SQ2_1 (0x02U << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */ 1496 #define ADC_SQR5_SQ2_2 (0x04U << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */ 1497 #define ADC_SQR5_SQ2_3 (0x08U << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */ 1498 #define ADC_SQR5_SQ2_4 (0x10U << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */ 1499 1500 #define ADC_SQR5_SQ3_Pos (10U) 1501 #define ADC_SQR5_SQ3_Msk (0x1FU << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */ 1502 #define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 1503 #define ADC_SQR5_SQ3_0 (0x01U << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */ 1504 #define ADC_SQR5_SQ3_1 (0x02U << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */ 1505 #define ADC_SQR5_SQ3_2 (0x04U << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */ 1506 #define ADC_SQR5_SQ3_3 (0x08U << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */ 1507 #define ADC_SQR5_SQ3_4 (0x10U << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */ 1508 1509 #define ADC_SQR5_SQ4_Pos (15U) 1510 #define ADC_SQR5_SQ4_Msk (0x1FU << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */ 1511 #define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 1512 #define ADC_SQR5_SQ4_0 (0x01U << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */ 1513 #define ADC_SQR5_SQ4_1 (0x02U << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */ 1514 #define ADC_SQR5_SQ4_2 (0x04U << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */ 1515 #define ADC_SQR5_SQ4_3 (0x08U << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */ 1516 #define ADC_SQR5_SQ4_4 (0x10U << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */ 1517 1518 #define ADC_SQR5_SQ5_Pos (20U) 1519 #define ADC_SQR5_SQ5_Msk (0x1FU << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */ 1520 #define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 1521 #define ADC_SQR5_SQ5_0 (0x01U << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */ 1522 #define ADC_SQR5_SQ5_1 (0x02U << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */ 1523 #define ADC_SQR5_SQ5_2 (0x04U << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */ 1524 #define ADC_SQR5_SQ5_3 (0x08U << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */ 1525 #define ADC_SQR5_SQ5_4 (0x10U << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */ 1526 1527 #define ADC_SQR5_SQ6_Pos (25U) 1528 #define ADC_SQR5_SQ6_Msk (0x1FU << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */ 1529 #define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 1530 #define ADC_SQR5_SQ6_0 (0x01U << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */ 1531 #define ADC_SQR5_SQ6_1 (0x02U << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */ 1532 #define ADC_SQR5_SQ6_2 (0x04U << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */ 1533 #define ADC_SQR5_SQ6_3 (0x08U << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */ 1534 #define ADC_SQR5_SQ6_4 (0x10U << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */ 1535 1536 1537 /******************* Bit definition for ADC_JSQR register *******************/ 1538 #define ADC_JSQR_JSQ1_Pos (0U) 1539 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ 1540 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 1541 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ 1542 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ 1543 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ 1544 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ 1545 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ 1546 1547 #define ADC_JSQR_JSQ2_Pos (5U) 1548 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ 1549 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 1550 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ 1551 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ 1552 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ 1553 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ 1554 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ 1555 1556 #define ADC_JSQR_JSQ3_Pos (10U) 1557 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ 1558 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 1559 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ 1560 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ 1561 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ 1562 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ 1563 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ 1564 1565 #define ADC_JSQR_JSQ4_Pos (15U) 1566 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ 1567 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 1568 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ 1569 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ 1570 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ 1571 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ 1572 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ 1573 1574 #define ADC_JSQR_JL_Pos (20U) 1575 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ 1576 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 1577 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ 1578 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ 1579 1580 /******************* Bit definition for ADC_JDR1 register *******************/ 1581 #define ADC_JDR1_JDATA_Pos (0U) 1582 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 1583 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 1584 1585 /******************* Bit definition for ADC_JDR2 register *******************/ 1586 #define ADC_JDR2_JDATA_Pos (0U) 1587 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 1588 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 1589 1590 /******************* Bit definition for ADC_JDR3 register *******************/ 1591 #define ADC_JDR3_JDATA_Pos (0U) 1592 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 1593 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 1594 1595 /******************* Bit definition for ADC_JDR4 register *******************/ 1596 #define ADC_JDR4_JDATA_Pos (0U) 1597 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 1598 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 1599 1600 /******************** Bit definition for ADC_DR register ********************/ 1601 #define ADC_DR_DATA_Pos (0U) 1602 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 1603 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 1604 1605 /****************** Bit definition for ADC_SMPR0 register *******************/ 1606 #define ADC_SMPR0_SMP30_Pos (0U) 1607 #define ADC_SMPR0_SMP30_Msk (0x7U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000007 */ 1608 #define ADC_SMPR0_SMP30 ADC_SMPR0_SMP30_Msk /*!< ADC channel 30 sampling time selection */ 1609 #define ADC_SMPR0_SMP30_0 (0x1U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000001 */ 1610 #define ADC_SMPR0_SMP30_1 (0x2U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000002 */ 1611 #define ADC_SMPR0_SMP30_2 (0x4U << ADC_SMPR0_SMP30_Pos) /*!< 0x00000004 */ 1612 1613 #define ADC_SMPR0_SMP31_Pos (3U) 1614 #define ADC_SMPR0_SMP31_Msk (0x7U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000038 */ 1615 #define ADC_SMPR0_SMP31 ADC_SMPR0_SMP31_Msk /*!< ADC channel 31 sampling time selection */ 1616 #define ADC_SMPR0_SMP31_0 (0x1U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000008 */ 1617 #define ADC_SMPR0_SMP31_1 (0x2U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000010 */ 1618 #define ADC_SMPR0_SMP31_2 (0x4U << ADC_SMPR0_SMP31_Pos) /*!< 0x00000020 */ 1619 1620 /******************* Bit definition for ADC_CSR register ********************/ 1621 #define ADC_CSR_AWD1_Pos (0U) 1622 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ 1623 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */ 1624 #define ADC_CSR_EOCS1_Pos (1U) 1625 #define ADC_CSR_EOCS1_Msk (0x1U << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */ 1626 #define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */ 1627 #define ADC_CSR_JEOS1_Pos (2U) 1628 #define ADC_CSR_JEOS1_Msk (0x1U << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */ 1629 #define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ 1630 #define ADC_CSR_JSTRT1_Pos (3U) 1631 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ 1632 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */ 1633 #define ADC_CSR_STRT1_Pos (4U) 1634 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ 1635 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */ 1636 #define ADC_CSR_OVR1_Pos (5U) 1637 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ 1638 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */ 1639 #define ADC_CSR_ADONS1_Pos (6U) 1640 #define ADC_CSR_ADONS1_Msk (0x1U << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */ 1641 #define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */ 1642 1643 /* Legacy defines */ 1644 #define ADC_CSR_EOC1 (ADC_CSR_EOCS1) 1645 #define ADC_CSR_JEOC1 (ADC_CSR_JEOS1) 1646 1647 /******************* Bit definition for ADC_CCR register ********************/ 1648 #define ADC_CCR_ADCPRE_Pos (16U) 1649 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ 1650 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */ 1651 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ 1652 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ 1653 #define ADC_CCR_TSVREFE_Pos (23U) 1654 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ 1655 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ 1656 1657 /******************************************************************************/ 1658 /* */ 1659 /* Analog Comparators (COMP) */ 1660 /* */ 1661 /******************************************************************************/ 1662 1663 /****************** Bit definition for COMP_CSR register ********************/ 1664 #define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */ 1665 #define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */ 1666 #define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */ 1667 #define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */ 1668 #define COMP_CSR_CMP1EN_Pos (4U) 1669 #define COMP_CSR_CMP1EN_Msk (0x1U << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */ 1670 #define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */ 1671 #define COMP_CSR_CMP1OUT_Pos (7U) 1672 #define COMP_CSR_CMP1OUT_Msk (0x1U << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */ 1673 #define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */ 1674 #define COMP_CSR_SPEED_Pos (12U) 1675 #define COMP_CSR_SPEED_Msk (0x1U << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */ 1676 #define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */ 1677 #define COMP_CSR_CMP2OUT_Pos (13U) 1678 #define COMP_CSR_CMP2OUT_Msk (0x1U << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */ 1679 #define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */ 1680 1681 #define COMP_CSR_WNDWE_Pos (17U) 1682 #define COMP_CSR_WNDWE_Msk (0x1U << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */ 1683 #define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ 1684 1685 #define COMP_CSR_INSEL_Pos (18U) 1686 #define COMP_CSR_INSEL_Msk (0x7U << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */ 1687 #define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */ 1688 #define COMP_CSR_INSEL_0 (0x1U << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */ 1689 #define COMP_CSR_INSEL_1 (0x2U << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */ 1690 #define COMP_CSR_INSEL_2 (0x4U << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */ 1691 #define COMP_CSR_OUTSEL_Pos (21U) 1692 #define COMP_CSR_OUTSEL_Msk (0x7U << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */ 1693 #define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */ 1694 #define COMP_CSR_OUTSEL_0 (0x1U << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */ 1695 #define COMP_CSR_OUTSEL_1 (0x2U << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */ 1696 #define COMP_CSR_OUTSEL_2 (0x4U << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */ 1697 1698 /* Bits present in COMP register but not related to comparator */ 1699 /* (or partially related to comparator, in addition to other peripherals) */ 1700 #define COMP_CSR_SW1_Pos (5U) 1701 #define COMP_CSR_SW1_Msk (0x1U << COMP_CSR_SW1_Pos) /*!< 0x00000020 */ 1702 #define COMP_CSR_SW1 COMP_CSR_SW1_Msk /*!< SW1 analog switch enable */ 1703 #define COMP_CSR_VREFOUTEN_Pos (16U) 1704 #define COMP_CSR_VREFOUTEN_Msk (0x1U << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */ 1705 #define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */ 1706 1707 #define COMP_CSR_FCH3_Pos (26U) 1708 #define COMP_CSR_FCH3_Msk (0x1U << COMP_CSR_FCH3_Pos) /*!< 0x04000000 */ 1709 #define COMP_CSR_FCH3 COMP_CSR_FCH3_Msk /*!< Bit 26 */ 1710 #define COMP_CSR_FCH8_Pos (27U) 1711 #define COMP_CSR_FCH8_Msk (0x1U << COMP_CSR_FCH8_Pos) /*!< 0x08000000 */ 1712 #define COMP_CSR_FCH8 COMP_CSR_FCH8_Msk /*!< Bit 27 */ 1713 #define COMP_CSR_RCH13_Pos (28U) 1714 #define COMP_CSR_RCH13_Msk (0x1U << COMP_CSR_RCH13_Pos) /*!< 0x10000000 */ 1715 #define COMP_CSR_RCH13 COMP_CSR_RCH13_Msk /*!< Bit 28 */ 1716 1717 #define COMP_CSR_CAIE_Pos (29U) 1718 #define COMP_CSR_CAIE_Msk (0x1U << COMP_CSR_CAIE_Pos) /*!< 0x20000000 */ 1719 #define COMP_CSR_CAIE COMP_CSR_CAIE_Msk /*!< Bit 29 */ 1720 #define COMP_CSR_CAIF_Pos (30U) 1721 #define COMP_CSR_CAIF_Msk (0x1U << COMP_CSR_CAIF_Pos) /*!< 0x40000000 */ 1722 #define COMP_CSR_CAIF COMP_CSR_CAIF_Msk /*!< Bit 30 */ 1723 #define COMP_CSR_TSUSP_Pos (31U) 1724 #define COMP_CSR_TSUSP_Msk (0x1U << COMP_CSR_TSUSP_Pos) /*!< 0x80000000 */ 1725 #define COMP_CSR_TSUSP COMP_CSR_TSUSP_Msk /*!< Bit 31 */ 1726 1727 /******************************************************************************/ 1728 /* */ 1729 /* Operational Amplifier (OPAMP) */ 1730 /* */ 1731 /******************************************************************************/ 1732 /******************* Bit definition for OPAMP_CSR register ******************/ 1733 #define OPAMP_CSR_OPA1PD_Pos (0U) 1734 #define OPAMP_CSR_OPA1PD_Msk (0x1U << OPAMP_CSR_OPA1PD_Pos) /*!< 0x00000001 */ 1735 #define OPAMP_CSR_OPA1PD OPAMP_CSR_OPA1PD_Msk /*!< OPAMP1 disable */ 1736 #define OPAMP_CSR_S3SEL1_Pos (1U) 1737 #define OPAMP_CSR_S3SEL1_Msk (0x1U << OPAMP_CSR_S3SEL1_Pos) /*!< 0x00000002 */ 1738 #define OPAMP_CSR_S3SEL1 OPAMP_CSR_S3SEL1_Msk /*!< Switch 3 for OPAMP1 Enable */ 1739 #define OPAMP_CSR_S4SEL1_Pos (2U) 1740 #define OPAMP_CSR_S4SEL1_Msk (0x1U << OPAMP_CSR_S4SEL1_Pos) /*!< 0x00000004 */ 1741 #define OPAMP_CSR_S4SEL1 OPAMP_CSR_S4SEL1_Msk /*!< Switch 4 for OPAMP1 Enable */ 1742 #define OPAMP_CSR_S5SEL1_Pos (3U) 1743 #define OPAMP_CSR_S5SEL1_Msk (0x1U << OPAMP_CSR_S5SEL1_Pos) /*!< 0x00000008 */ 1744 #define OPAMP_CSR_S5SEL1 OPAMP_CSR_S5SEL1_Msk /*!< Switch 5 for OPAMP1 Enable */ 1745 #define OPAMP_CSR_S6SEL1_Pos (4U) 1746 #define OPAMP_CSR_S6SEL1_Msk (0x1U << OPAMP_CSR_S6SEL1_Pos) /*!< 0x00000010 */ 1747 #define OPAMP_CSR_S6SEL1 OPAMP_CSR_S6SEL1_Msk /*!< Switch 6 for OPAMP1 Enable */ 1748 #define OPAMP_CSR_OPA1CAL_L_Pos (5U) 1749 #define OPAMP_CSR_OPA1CAL_L_Msk (0x1U << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */ 1750 #define OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_L_Msk /*!< OPAMP1 Offset calibration for P differential pair */ 1751 #define OPAMP_CSR_OPA1CAL_H_Pos (6U) 1752 #define OPAMP_CSR_OPA1CAL_H_Msk (0x1U << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */ 1753 #define OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1CAL_H_Msk /*!< OPAMP1 Offset calibration for N differential pair */ 1754 #define OPAMP_CSR_OPA1LPM_Pos (7U) 1755 #define OPAMP_CSR_OPA1LPM_Msk (0x1U << OPAMP_CSR_OPA1LPM_Pos) /*!< 0x00000080 */ 1756 #define OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA1LPM_Msk /*!< OPAMP1 Low power enable */ 1757 #define OPAMP_CSR_OPA2PD_Pos (8U) 1758 #define OPAMP_CSR_OPA2PD_Msk (0x1U << OPAMP_CSR_OPA2PD_Pos) /*!< 0x00000100 */ 1759 #define OPAMP_CSR_OPA2PD OPAMP_CSR_OPA2PD_Msk /*!< OPAMP2 disable */ 1760 #define OPAMP_CSR_S3SEL2_Pos (9U) 1761 #define OPAMP_CSR_S3SEL2_Msk (0x1U << OPAMP_CSR_S3SEL2_Pos) /*!< 0x00000200 */ 1762 #define OPAMP_CSR_S3SEL2 OPAMP_CSR_S3SEL2_Msk /*!< Switch 3 for OPAMP2 Enable */ 1763 #define OPAMP_CSR_S4SEL2_Pos (10U) 1764 #define OPAMP_CSR_S4SEL2_Msk (0x1U << OPAMP_CSR_S4SEL2_Pos) /*!< 0x00000400 */ 1765 #define OPAMP_CSR_S4SEL2 OPAMP_CSR_S4SEL2_Msk /*!< Switch 4 for OPAMP2 Enable */ 1766 #define OPAMP_CSR_S5SEL2_Pos (11U) 1767 #define OPAMP_CSR_S5SEL2_Msk (0x1U << OPAMP_CSR_S5SEL2_Pos) /*!< 0x00000800 */ 1768 #define OPAMP_CSR_S5SEL2 OPAMP_CSR_S5SEL2_Msk /*!< Switch 5 for OPAMP2 Enable */ 1769 #define OPAMP_CSR_S6SEL2_Pos (12U) 1770 #define OPAMP_CSR_S6SEL2_Msk (0x1U << OPAMP_CSR_S6SEL2_Pos) /*!< 0x00001000 */ 1771 #define OPAMP_CSR_S6SEL2 OPAMP_CSR_S6SEL2_Msk /*!< Switch 6 for OPAMP2 Enable */ 1772 #define OPAMP_CSR_OPA2CAL_L_Pos (13U) 1773 #define OPAMP_CSR_OPA2CAL_L_Msk (0x1U << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */ 1774 #define OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_L_Msk /*!< OPAMP2 Offset calibration for P differential pair */ 1775 #define OPAMP_CSR_OPA2CAL_H_Pos (14U) 1776 #define OPAMP_CSR_OPA2CAL_H_Msk (0x1U << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */ 1777 #define OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2CAL_H_Msk /*!< OPAMP2 Offset calibration for N differential pair */ 1778 #define OPAMP_CSR_OPA2LPM_Pos (15U) 1779 #define OPAMP_CSR_OPA2LPM_Msk (0x1U << OPAMP_CSR_OPA2LPM_Pos) /*!< 0x00008000 */ 1780 #define OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA2LPM_Msk /*!< OPAMP2 Low power enable */ 1781 #define OPAMP_CSR_ANAWSEL1_Pos (24U) 1782 #define OPAMP_CSR_ANAWSEL1_Msk (0x1U << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */ 1783 #define OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL1_Msk /*!< Switch ANA Enable for OPAMP1 */ 1784 #define OPAMP_CSR_ANAWSEL2_Pos (25U) 1785 #define OPAMP_CSR_ANAWSEL2_Msk (0x1U << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */ 1786 #define OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL2_Msk /*!< Switch ANA Enable for OPAMP2 */ 1787 #define OPAMP_CSR_S7SEL2_Pos (27U) 1788 #define OPAMP_CSR_S7SEL2_Msk (0x1U << OPAMP_CSR_S7SEL2_Pos) /*!< 0x08000000 */ 1789 #define OPAMP_CSR_S7SEL2 OPAMP_CSR_S7SEL2_Msk /*!< Switch 7 for OPAMP2 Enable */ 1790 #define OPAMP_CSR_AOP_RANGE_Pos (28U) 1791 #define OPAMP_CSR_AOP_RANGE_Msk (0x1U << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */ 1792 #define OPAMP_CSR_AOP_RANGE OPAMP_CSR_AOP_RANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */ 1793 #define OPAMP_CSR_OPA1CALOUT_Pos (29U) 1794 #define OPAMP_CSR_OPA1CALOUT_Msk (0x1U << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */ 1795 #define OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA1CALOUT_Msk /*!< OPAMP1 calibration output */ 1796 #define OPAMP_CSR_OPA2CALOUT_Pos (30U) 1797 #define OPAMP_CSR_OPA2CALOUT_Msk (0x1U << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */ 1798 #define OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA2CALOUT_Msk /*!< OPAMP2 calibration output */ 1799 1800 /******************* Bit definition for OPAMP_OTR register ******************/ 1801 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U) 1802 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */ 1803 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ 1804 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U) 1805 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */ 1806 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ 1807 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U) 1808 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */ 1809 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ 1810 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U) 1811 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */ 1812 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ 1813 #define OPAMP_OTR_OT_USER_Pos (31U) 1814 #define OPAMP_OTR_OT_USER_Msk (0x1U << OPAMP_OTR_OT_USER_Pos) /*!< 0x80000000 */ 1815 #define OPAMP_OTR_OT_USER OPAMP_OTR_OT_USER_Msk /*!< Switch to OPAMP offset user trimmed values */ 1816 1817 /******************* Bit definition for OPAMP_LPOTR register ****************/ 1818 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U) 1819 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */ 1820 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */ 1821 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U) 1822 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */ 1823 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */ 1824 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U) 1825 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */ 1826 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */ 1827 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U) 1828 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */ 1829 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */ 1830 1831 /******************************************************************************/ 1832 /* */ 1833 /* CRC calculation unit (CRC) */ 1834 /* */ 1835 /******************************************************************************/ 1836 1837 /******************* Bit definition for CRC_DR register *********************/ 1838 #define CRC_DR_DR_Pos (0U) 1839 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 1840 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 1841 1842 /******************* Bit definition for CRC_IDR register ********************/ 1843 #define CRC_IDR_IDR_Pos (0U) 1844 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 1845 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ 1846 1847 /******************** Bit definition for CRC_CR register ********************/ 1848 #define CRC_CR_RESET_Pos (0U) 1849 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 1850 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ 1851 1852 /******************************************************************************/ 1853 /* */ 1854 /* Digital to Analog Converter (DAC) */ 1855 /* */ 1856 /******************************************************************************/ 1857 1858 /******************** Bit definition for DAC_CR register ********************/ 1859 #define DAC_CR_EN1_Pos (0U) 1860 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 1861 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ 1862 #define DAC_CR_BOFF1_Pos (1U) 1863 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ 1864 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */ 1865 #define DAC_CR_TEN1_Pos (2U) 1866 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ 1867 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ 1868 1869 #define DAC_CR_TSEL1_Pos (3U) 1870 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ 1871 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ 1872 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 1873 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 1874 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 1875 1876 #define DAC_CR_WAVE1_Pos (6U) 1877 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 1878 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 1879 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 1880 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 1881 1882 #define DAC_CR_MAMP1_Pos (8U) 1883 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 1884 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 1885 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 1886 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 1887 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 1888 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 1889 1890 #define DAC_CR_DMAEN1_Pos (12U) 1891 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 1892 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ 1893 #define DAC_CR_DMAUDRIE1_Pos (13U) 1894 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 1895 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA Interrupt enable */ 1896 #define DAC_CR_EN2_Pos (16U) 1897 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ 1898 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ 1899 #define DAC_CR_BOFF2_Pos (17U) 1900 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ 1901 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */ 1902 #define DAC_CR_TEN2_Pos (18U) 1903 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ 1904 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ 1905 1906 #define DAC_CR_TSEL2_Pos (19U) 1907 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ 1908 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ 1909 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ 1910 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ 1911 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ 1912 1913 #define DAC_CR_WAVE2_Pos (22U) 1914 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ 1915 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 1916 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ 1917 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ 1918 1919 #define DAC_CR_MAMP2_Pos (24U) 1920 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ 1921 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 1922 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ 1923 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ 1924 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ 1925 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ 1926 1927 #define DAC_CR_DMAEN2_Pos (28U) 1928 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ 1929 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ 1930 #define DAC_CR_DMAUDRIE2_Pos (29U) 1931 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ 1932 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */ 1933 /***************** Bit definition for DAC_SWTRIGR register ******************/ 1934 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 1935 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 1936 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ 1937 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 1938 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ 1939 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ 1940 1941 /***************** Bit definition for DAC_DHR12R1 register ******************/ 1942 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 1943 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 1944 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 1945 1946 /***************** Bit definition for DAC_DHR12L1 register ******************/ 1947 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 1948 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 1949 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 1950 1951 /****************** Bit definition for DAC_DHR8R1 register ******************/ 1952 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 1953 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 1954 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 1955 1956 /***************** Bit definition for DAC_DHR12R2 register ******************/ 1957 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 1958 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ 1959 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 1960 1961 /***************** Bit definition for DAC_DHR12L2 register ******************/ 1962 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 1963 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ 1964 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 1965 1966 /****************** Bit definition for DAC_DHR8R2 register ******************/ 1967 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 1968 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ 1969 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 1970 1971 /***************** Bit definition for DAC_DHR12RD register ******************/ 1972 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 1973 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 1974 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 1975 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 1976 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ 1977 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 1978 1979 /***************** Bit definition for DAC_DHR12LD register ******************/ 1980 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 1981 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 1982 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 1983 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 1984 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ 1985 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 1986 1987 /****************** Bit definition for DAC_DHR8RD register ******************/ 1988 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 1989 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 1990 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 1991 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 1992 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ 1993 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 1994 1995 /******************* Bit definition for DAC_DOR1 register *******************/ 1996 #define DAC_DOR1_DACC1DOR_Pos (0U) 1997 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 1998 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ 1999 2000 /******************* Bit definition for DAC_DOR2 register *******************/ 2001 #define DAC_DOR2_DACC2DOR_Pos (0U) 2002 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ 2003 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ 2004 2005 /******************** Bit definition for DAC_SR register ********************/ 2006 #define DAC_SR_DMAUDR1_Pos (13U) 2007 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 2008 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ 2009 #define DAC_SR_DMAUDR2_Pos (29U) 2010 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 2011 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ 2012 2013 /******************************************************************************/ 2014 /* */ 2015 /* Debug MCU (DBGMCU) */ 2016 /* */ 2017 /******************************************************************************/ 2018 2019 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 2020 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 2021 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 2022 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 2023 2024 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 2025 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 2026 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 2027 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 2028 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 2029 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 2030 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 2031 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 2032 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 2033 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 2034 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 2035 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 2036 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 2037 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 2038 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 2039 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 2040 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 2041 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 2042 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 2043 2044 /****************** Bit definition for DBGMCU_CR register *******************/ 2045 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 2046 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 2047 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ 2048 #define DBGMCU_CR_DBG_STOP_Pos (1U) 2049 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 2050 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 2051 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 2052 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 2053 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 2054 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 2055 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 2056 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ 2057 2058 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 2059 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 2060 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ 2061 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 2062 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 2063 2064 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 2065 2066 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 2067 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 2068 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 2069 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 2070 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 2071 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 2072 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) 2073 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ 2074 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ 2075 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) 2076 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ 2077 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */ 2078 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 2079 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 2080 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ 2081 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) 2082 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ 2083 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */ 2084 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 2085 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 2086 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */ 2087 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 2088 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 2089 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 2090 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 2091 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 2092 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 2093 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 2094 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ 2095 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 2096 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) 2097 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ 2098 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 2099 2100 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 2101 2102 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U) 2103 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */ 2104 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */ 2105 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U) 2106 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */ 2107 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */ 2108 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U) 2109 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */ 2110 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */ 2111 2112 /******************************************************************************/ 2113 /* */ 2114 /* DMA Controller (DMA) */ 2115 /* */ 2116 /******************************************************************************/ 2117 2118 /******************* Bit definition for DMA_ISR register ********************/ 2119 #define DMA_ISR_GIF1_Pos (0U) 2120 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 2121 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 2122 #define DMA_ISR_TCIF1_Pos (1U) 2123 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 2124 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 2125 #define DMA_ISR_HTIF1_Pos (2U) 2126 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 2127 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 2128 #define DMA_ISR_TEIF1_Pos (3U) 2129 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 2130 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 2131 #define DMA_ISR_GIF2_Pos (4U) 2132 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 2133 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 2134 #define DMA_ISR_TCIF2_Pos (5U) 2135 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 2136 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 2137 #define DMA_ISR_HTIF2_Pos (6U) 2138 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 2139 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 2140 #define DMA_ISR_TEIF2_Pos (7U) 2141 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 2142 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 2143 #define DMA_ISR_GIF3_Pos (8U) 2144 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 2145 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 2146 #define DMA_ISR_TCIF3_Pos (9U) 2147 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 2148 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 2149 #define DMA_ISR_HTIF3_Pos (10U) 2150 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 2151 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 2152 #define DMA_ISR_TEIF3_Pos (11U) 2153 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 2154 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 2155 #define DMA_ISR_GIF4_Pos (12U) 2156 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 2157 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 2158 #define DMA_ISR_TCIF4_Pos (13U) 2159 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 2160 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 2161 #define DMA_ISR_HTIF4_Pos (14U) 2162 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 2163 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 2164 #define DMA_ISR_TEIF4_Pos (15U) 2165 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 2166 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 2167 #define DMA_ISR_GIF5_Pos (16U) 2168 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 2169 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 2170 #define DMA_ISR_TCIF5_Pos (17U) 2171 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 2172 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 2173 #define DMA_ISR_HTIF5_Pos (18U) 2174 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 2175 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 2176 #define DMA_ISR_TEIF5_Pos (19U) 2177 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 2178 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 2179 #define DMA_ISR_GIF6_Pos (20U) 2180 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 2181 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 2182 #define DMA_ISR_TCIF6_Pos (21U) 2183 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 2184 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 2185 #define DMA_ISR_HTIF6_Pos (22U) 2186 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 2187 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 2188 #define DMA_ISR_TEIF6_Pos (23U) 2189 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 2190 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 2191 #define DMA_ISR_GIF7_Pos (24U) 2192 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 2193 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 2194 #define DMA_ISR_TCIF7_Pos (25U) 2195 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 2196 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 2197 #define DMA_ISR_HTIF7_Pos (26U) 2198 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 2199 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 2200 #define DMA_ISR_TEIF7_Pos (27U) 2201 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 2202 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 2203 2204 /******************* Bit definition for DMA_IFCR register *******************/ 2205 #define DMA_IFCR_CGIF1_Pos (0U) 2206 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 2207 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 2208 #define DMA_IFCR_CTCIF1_Pos (1U) 2209 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 2210 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 2211 #define DMA_IFCR_CHTIF1_Pos (2U) 2212 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 2213 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 2214 #define DMA_IFCR_CTEIF1_Pos (3U) 2215 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 2216 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 2217 #define DMA_IFCR_CGIF2_Pos (4U) 2218 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 2219 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 2220 #define DMA_IFCR_CTCIF2_Pos (5U) 2221 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 2222 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 2223 #define DMA_IFCR_CHTIF2_Pos (6U) 2224 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 2225 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 2226 #define DMA_IFCR_CTEIF2_Pos (7U) 2227 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 2228 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 2229 #define DMA_IFCR_CGIF3_Pos (8U) 2230 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 2231 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 2232 #define DMA_IFCR_CTCIF3_Pos (9U) 2233 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 2234 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 2235 #define DMA_IFCR_CHTIF3_Pos (10U) 2236 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 2237 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 2238 #define DMA_IFCR_CTEIF3_Pos (11U) 2239 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 2240 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 2241 #define DMA_IFCR_CGIF4_Pos (12U) 2242 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 2243 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 2244 #define DMA_IFCR_CTCIF4_Pos (13U) 2245 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 2246 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 2247 #define DMA_IFCR_CHTIF4_Pos (14U) 2248 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 2249 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 2250 #define DMA_IFCR_CTEIF4_Pos (15U) 2251 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 2252 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 2253 #define DMA_IFCR_CGIF5_Pos (16U) 2254 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 2255 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 2256 #define DMA_IFCR_CTCIF5_Pos (17U) 2257 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 2258 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 2259 #define DMA_IFCR_CHTIF5_Pos (18U) 2260 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 2261 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 2262 #define DMA_IFCR_CTEIF5_Pos (19U) 2263 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 2264 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 2265 #define DMA_IFCR_CGIF6_Pos (20U) 2266 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 2267 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 2268 #define DMA_IFCR_CTCIF6_Pos (21U) 2269 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 2270 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 2271 #define DMA_IFCR_CHTIF6_Pos (22U) 2272 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 2273 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 2274 #define DMA_IFCR_CTEIF6_Pos (23U) 2275 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 2276 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 2277 #define DMA_IFCR_CGIF7_Pos (24U) 2278 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 2279 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 2280 #define DMA_IFCR_CTCIF7_Pos (25U) 2281 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 2282 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 2283 #define DMA_IFCR_CHTIF7_Pos (26U) 2284 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 2285 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 2286 #define DMA_IFCR_CTEIF7_Pos (27U) 2287 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 2288 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 2289 2290 /******************* Bit definition for DMA_CCR register *******************/ 2291 #define DMA_CCR_EN_Pos (0U) 2292 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 2293 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable*/ 2294 #define DMA_CCR_TCIE_Pos (1U) 2295 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 2296 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 2297 #define DMA_CCR_HTIE_Pos (2U) 2298 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 2299 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 2300 #define DMA_CCR_TEIE_Pos (3U) 2301 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 2302 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 2303 #define DMA_CCR_DIR_Pos (4U) 2304 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 2305 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 2306 #define DMA_CCR_CIRC_Pos (5U) 2307 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 2308 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 2309 #define DMA_CCR_PINC_Pos (6U) 2310 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 2311 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 2312 #define DMA_CCR_MINC_Pos (7U) 2313 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 2314 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 2315 2316 #define DMA_CCR_PSIZE_Pos (8U) 2317 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 2318 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 2319 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 2320 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 2321 2322 #define DMA_CCR_MSIZE_Pos (10U) 2323 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 2324 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 2325 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 2326 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 2327 2328 #define DMA_CCR_PL_Pos (12U) 2329 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 2330 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ 2331 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 2332 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 2333 2334 #define DMA_CCR_MEM2MEM_Pos (14U) 2335 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 2336 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 2337 2338 /****************** Bit definition generic for DMA_CNDTR register *******************/ 2339 #define DMA_CNDTR_NDT_Pos (0U) 2340 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 2341 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 2342 2343 /****************** Bit definition for DMA_CNDTR1 register ******************/ 2344 #define DMA_CNDTR1_NDT_Pos (0U) 2345 #define DMA_CNDTR1_NDT_Msk (0xFFFFU << DMA_CNDTR1_NDT_Pos) /*!< 0x0000FFFF */ 2346 #define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /*!< Number of data to Transfer */ 2347 2348 /****************** Bit definition for DMA_CNDTR2 register ******************/ 2349 #define DMA_CNDTR2_NDT_Pos (0U) 2350 #define DMA_CNDTR2_NDT_Msk (0xFFFFU << DMA_CNDTR2_NDT_Pos) /*!< 0x0000FFFF */ 2351 #define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /*!< Number of data to Transfer */ 2352 2353 /****************** Bit definition for DMA_CNDTR3 register ******************/ 2354 #define DMA_CNDTR3_NDT_Pos (0U) 2355 #define DMA_CNDTR3_NDT_Msk (0xFFFFU << DMA_CNDTR3_NDT_Pos) /*!< 0x0000FFFF */ 2356 #define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /*!< Number of data to Transfer */ 2357 2358 /****************** Bit definition for DMA_CNDTR4 register ******************/ 2359 #define DMA_CNDTR4_NDT_Pos (0U) 2360 #define DMA_CNDTR4_NDT_Msk (0xFFFFU << DMA_CNDTR4_NDT_Pos) /*!< 0x0000FFFF */ 2361 #define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /*!< Number of data to Transfer */ 2362 2363 /****************** Bit definition for DMA_CNDTR5 register ******************/ 2364 #define DMA_CNDTR5_NDT_Pos (0U) 2365 #define DMA_CNDTR5_NDT_Msk (0xFFFFU << DMA_CNDTR5_NDT_Pos) /*!< 0x0000FFFF */ 2366 #define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /*!< Number of data to Transfer */ 2367 2368 /****************** Bit definition for DMA_CNDTR6 register ******************/ 2369 #define DMA_CNDTR6_NDT_Pos (0U) 2370 #define DMA_CNDTR6_NDT_Msk (0xFFFFU << DMA_CNDTR6_NDT_Pos) /*!< 0x0000FFFF */ 2371 #define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /*!< Number of data to Transfer */ 2372 2373 /****************** Bit definition for DMA_CNDTR7 register ******************/ 2374 #define DMA_CNDTR7_NDT_Pos (0U) 2375 #define DMA_CNDTR7_NDT_Msk (0xFFFFU << DMA_CNDTR7_NDT_Pos) /*!< 0x0000FFFF */ 2376 #define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /*!< Number of data to Transfer */ 2377 2378 /****************** Bit definition generic for DMA_CPAR register ********************/ 2379 #define DMA_CPAR_PA_Pos (0U) 2380 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 2381 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 2382 2383 /****************** Bit definition for DMA_CPAR1 register *******************/ 2384 #define DMA_CPAR1_PA_Pos (0U) 2385 #define DMA_CPAR1_PA_Msk (0xFFFFFFFFU << DMA_CPAR1_PA_Pos) /*!< 0xFFFFFFFF */ 2386 #define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /*!< Peripheral Address */ 2387 2388 /****************** Bit definition for DMA_CPAR2 register *******************/ 2389 #define DMA_CPAR2_PA_Pos (0U) 2390 #define DMA_CPAR2_PA_Msk (0xFFFFFFFFU << DMA_CPAR2_PA_Pos) /*!< 0xFFFFFFFF */ 2391 #define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /*!< Peripheral Address */ 2392 2393 /****************** Bit definition for DMA_CPAR3 register *******************/ 2394 #define DMA_CPAR3_PA_Pos (0U) 2395 #define DMA_CPAR3_PA_Msk (0xFFFFFFFFU << DMA_CPAR3_PA_Pos) /*!< 0xFFFFFFFF */ 2396 #define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /*!< Peripheral Address */ 2397 2398 2399 /****************** Bit definition for DMA_CPAR4 register *******************/ 2400 #define DMA_CPAR4_PA_Pos (0U) 2401 #define DMA_CPAR4_PA_Msk (0xFFFFFFFFU << DMA_CPAR4_PA_Pos) /*!< 0xFFFFFFFF */ 2402 #define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /*!< Peripheral Address */ 2403 2404 /****************** Bit definition for DMA_CPAR5 register *******************/ 2405 #define DMA_CPAR5_PA_Pos (0U) 2406 #define DMA_CPAR5_PA_Msk (0xFFFFFFFFU << DMA_CPAR5_PA_Pos) /*!< 0xFFFFFFFF */ 2407 #define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /*!< Peripheral Address */ 2408 2409 /****************** Bit definition for DMA_CPAR6 register *******************/ 2410 #define DMA_CPAR6_PA_Pos (0U) 2411 #define DMA_CPAR6_PA_Msk (0xFFFFFFFFU << DMA_CPAR6_PA_Pos) /*!< 0xFFFFFFFF */ 2412 #define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /*!< Peripheral Address */ 2413 2414 2415 /****************** Bit definition for DMA_CPAR7 register *******************/ 2416 #define DMA_CPAR7_PA_Pos (0U) 2417 #define DMA_CPAR7_PA_Msk (0xFFFFFFFFU << DMA_CPAR7_PA_Pos) /*!< 0xFFFFFFFF */ 2418 #define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /*!< Peripheral Address */ 2419 2420 /****************** Bit definition generic for DMA_CMAR register ********************/ 2421 #define DMA_CMAR_MA_Pos (0U) 2422 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 2423 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 2424 2425 /****************** Bit definition for DMA_CMAR1 register *******************/ 2426 #define DMA_CMAR1_MA_Pos (0U) 2427 #define DMA_CMAR1_MA_Msk (0xFFFFFFFFU << DMA_CMAR1_MA_Pos) /*!< 0xFFFFFFFF */ 2428 #define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /*!< Memory Address */ 2429 2430 /****************** Bit definition for DMA_CMAR2 register *******************/ 2431 #define DMA_CMAR2_MA_Pos (0U) 2432 #define DMA_CMAR2_MA_Msk (0xFFFFFFFFU << DMA_CMAR2_MA_Pos) /*!< 0xFFFFFFFF */ 2433 #define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /*!< Memory Address */ 2434 2435 /****************** Bit definition for DMA_CMAR3 register *******************/ 2436 #define DMA_CMAR3_MA_Pos (0U) 2437 #define DMA_CMAR3_MA_Msk (0xFFFFFFFFU << DMA_CMAR3_MA_Pos) /*!< 0xFFFFFFFF */ 2438 #define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /*!< Memory Address */ 2439 2440 2441 /****************** Bit definition for DMA_CMAR4 register *******************/ 2442 #define DMA_CMAR4_MA_Pos (0U) 2443 #define DMA_CMAR4_MA_Msk (0xFFFFFFFFU << DMA_CMAR4_MA_Pos) /*!< 0xFFFFFFFF */ 2444 #define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /*!< Memory Address */ 2445 2446 /****************** Bit definition for DMA_CMAR5 register *******************/ 2447 #define DMA_CMAR5_MA_Pos (0U) 2448 #define DMA_CMAR5_MA_Msk (0xFFFFFFFFU << DMA_CMAR5_MA_Pos) /*!< 0xFFFFFFFF */ 2449 #define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /*!< Memory Address */ 2450 2451 /****************** Bit definition for DMA_CMAR6 register *******************/ 2452 #define DMA_CMAR6_MA_Pos (0U) 2453 #define DMA_CMAR6_MA_Msk (0xFFFFFFFFU << DMA_CMAR6_MA_Pos) /*!< 0xFFFFFFFF */ 2454 #define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /*!< Memory Address */ 2455 2456 /****************** Bit definition for DMA_CMAR7 register *******************/ 2457 #define DMA_CMAR7_MA_Pos (0U) 2458 #define DMA_CMAR7_MA_Msk (0xFFFFFFFFU << DMA_CMAR7_MA_Pos) /*!< 0xFFFFFFFF */ 2459 #define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /*!< Memory Address */ 2460 2461 /******************************************************************************/ 2462 /* */ 2463 /* External Interrupt/Event Controller (EXTI) */ 2464 /* */ 2465 /******************************************************************************/ 2466 2467 /******************* Bit definition for EXTI_IMR register *******************/ 2468 #define EXTI_IMR_MR0_Pos (0U) 2469 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 2470 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 2471 #define EXTI_IMR_MR1_Pos (1U) 2472 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 2473 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 2474 #define EXTI_IMR_MR2_Pos (2U) 2475 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 2476 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 2477 #define EXTI_IMR_MR3_Pos (3U) 2478 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 2479 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 2480 #define EXTI_IMR_MR4_Pos (4U) 2481 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 2482 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 2483 #define EXTI_IMR_MR5_Pos (5U) 2484 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 2485 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 2486 #define EXTI_IMR_MR6_Pos (6U) 2487 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 2488 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 2489 #define EXTI_IMR_MR7_Pos (7U) 2490 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 2491 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 2492 #define EXTI_IMR_MR8_Pos (8U) 2493 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 2494 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 2495 #define EXTI_IMR_MR9_Pos (9U) 2496 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 2497 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 2498 #define EXTI_IMR_MR10_Pos (10U) 2499 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 2500 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 2501 #define EXTI_IMR_MR11_Pos (11U) 2502 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 2503 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 2504 #define EXTI_IMR_MR12_Pos (12U) 2505 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 2506 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 2507 #define EXTI_IMR_MR13_Pos (13U) 2508 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 2509 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 2510 #define EXTI_IMR_MR14_Pos (14U) 2511 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 2512 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 2513 #define EXTI_IMR_MR15_Pos (15U) 2514 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 2515 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 2516 #define EXTI_IMR_MR16_Pos (16U) 2517 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 2518 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 2519 #define EXTI_IMR_MR17_Pos (17U) 2520 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 2521 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 2522 #define EXTI_IMR_MR18_Pos (18U) 2523 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ 2524 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ 2525 #define EXTI_IMR_MR19_Pos (19U) 2526 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 2527 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 2528 #define EXTI_IMR_MR20_Pos (20U) 2529 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ 2530 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ 2531 #define EXTI_IMR_MR21_Pos (21U) 2532 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ 2533 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ 2534 #define EXTI_IMR_MR22_Pos (22U) 2535 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ 2536 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ 2537 #define EXTI_IMR_MR23_Pos (23U) 2538 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */ 2539 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */ 2540 2541 /* References Defines */ 2542 #define EXTI_IMR_IM0 EXTI_IMR_MR0 2543 #define EXTI_IMR_IM1 EXTI_IMR_MR1 2544 #define EXTI_IMR_IM2 EXTI_IMR_MR2 2545 #define EXTI_IMR_IM3 EXTI_IMR_MR3 2546 #define EXTI_IMR_IM4 EXTI_IMR_MR4 2547 #define EXTI_IMR_IM5 EXTI_IMR_MR5 2548 #define EXTI_IMR_IM6 EXTI_IMR_MR6 2549 #define EXTI_IMR_IM7 EXTI_IMR_MR7 2550 #define EXTI_IMR_IM8 EXTI_IMR_MR8 2551 #define EXTI_IMR_IM9 EXTI_IMR_MR9 2552 #define EXTI_IMR_IM10 EXTI_IMR_MR10 2553 #define EXTI_IMR_IM11 EXTI_IMR_MR11 2554 #define EXTI_IMR_IM12 EXTI_IMR_MR12 2555 #define EXTI_IMR_IM13 EXTI_IMR_MR13 2556 #define EXTI_IMR_IM14 EXTI_IMR_MR14 2557 #define EXTI_IMR_IM15 EXTI_IMR_MR15 2558 #define EXTI_IMR_IM16 EXTI_IMR_MR16 2559 #define EXTI_IMR_IM17 EXTI_IMR_MR17 2560 #define EXTI_IMR_IM18 EXTI_IMR_MR18 2561 #define EXTI_IMR_IM19 EXTI_IMR_MR19 2562 #define EXTI_IMR_IM20 EXTI_IMR_MR20 2563 #define EXTI_IMR_IM21 EXTI_IMR_MR21 2564 #define EXTI_IMR_IM22 EXTI_IMR_MR22 2565 /* Category 3, 4 & 5 */ 2566 #define EXTI_IMR_IM23 EXTI_IMR_MR23 2567 #define EXTI_IMR_IM_Pos (0U) 2568 #define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */ 2569 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 2570 2571 /******************* Bit definition for EXTI_EMR register *******************/ 2572 #define EXTI_EMR_MR0_Pos (0U) 2573 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 2574 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 2575 #define EXTI_EMR_MR1_Pos (1U) 2576 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 2577 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 2578 #define EXTI_EMR_MR2_Pos (2U) 2579 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 2580 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 2581 #define EXTI_EMR_MR3_Pos (3U) 2582 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 2583 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 2584 #define EXTI_EMR_MR4_Pos (4U) 2585 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 2586 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 2587 #define EXTI_EMR_MR5_Pos (5U) 2588 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 2589 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 2590 #define EXTI_EMR_MR6_Pos (6U) 2591 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 2592 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 2593 #define EXTI_EMR_MR7_Pos (7U) 2594 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 2595 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 2596 #define EXTI_EMR_MR8_Pos (8U) 2597 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 2598 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 2599 #define EXTI_EMR_MR9_Pos (9U) 2600 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 2601 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 2602 #define EXTI_EMR_MR10_Pos (10U) 2603 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 2604 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 2605 #define EXTI_EMR_MR11_Pos (11U) 2606 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 2607 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 2608 #define EXTI_EMR_MR12_Pos (12U) 2609 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 2610 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 2611 #define EXTI_EMR_MR13_Pos (13U) 2612 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 2613 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 2614 #define EXTI_EMR_MR14_Pos (14U) 2615 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 2616 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 2617 #define EXTI_EMR_MR15_Pos (15U) 2618 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 2619 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 2620 #define EXTI_EMR_MR16_Pos (16U) 2621 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 2622 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 2623 #define EXTI_EMR_MR17_Pos (17U) 2624 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 2625 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 2626 #define EXTI_EMR_MR18_Pos (18U) 2627 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ 2628 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ 2629 #define EXTI_EMR_MR19_Pos (19U) 2630 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 2631 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 2632 #define EXTI_EMR_MR20_Pos (20U) 2633 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ 2634 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ 2635 #define EXTI_EMR_MR21_Pos (21U) 2636 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ 2637 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ 2638 #define EXTI_EMR_MR22_Pos (22U) 2639 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ 2640 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ 2641 #define EXTI_EMR_MR23_Pos (23U) 2642 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */ 2643 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */ 2644 2645 /* References Defines */ 2646 #define EXTI_EMR_EM0 EXTI_EMR_MR0 2647 #define EXTI_EMR_EM1 EXTI_EMR_MR1 2648 #define EXTI_EMR_EM2 EXTI_EMR_MR2 2649 #define EXTI_EMR_EM3 EXTI_EMR_MR3 2650 #define EXTI_EMR_EM4 EXTI_EMR_MR4 2651 #define EXTI_EMR_EM5 EXTI_EMR_MR5 2652 #define EXTI_EMR_EM6 EXTI_EMR_MR6 2653 #define EXTI_EMR_EM7 EXTI_EMR_MR7 2654 #define EXTI_EMR_EM8 EXTI_EMR_MR8 2655 #define EXTI_EMR_EM9 EXTI_EMR_MR9 2656 #define EXTI_EMR_EM10 EXTI_EMR_MR10 2657 #define EXTI_EMR_EM11 EXTI_EMR_MR11 2658 #define EXTI_EMR_EM12 EXTI_EMR_MR12 2659 #define EXTI_EMR_EM13 EXTI_EMR_MR13 2660 #define EXTI_EMR_EM14 EXTI_EMR_MR14 2661 #define EXTI_EMR_EM15 EXTI_EMR_MR15 2662 #define EXTI_EMR_EM16 EXTI_EMR_MR16 2663 #define EXTI_EMR_EM17 EXTI_EMR_MR17 2664 #define EXTI_EMR_EM18 EXTI_EMR_MR18 2665 #define EXTI_EMR_EM19 EXTI_EMR_MR19 2666 #define EXTI_EMR_EM20 EXTI_EMR_MR20 2667 #define EXTI_EMR_EM21 EXTI_EMR_MR21 2668 #define EXTI_EMR_EM22 EXTI_EMR_MR22 2669 #define EXTI_EMR_EM23 EXTI_EMR_MR23 2670 2671 /****************** Bit definition for EXTI_RTSR register *******************/ 2672 #define EXTI_RTSR_TR0_Pos (0U) 2673 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 2674 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 2675 #define EXTI_RTSR_TR1_Pos (1U) 2676 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 2677 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 2678 #define EXTI_RTSR_TR2_Pos (2U) 2679 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 2680 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 2681 #define EXTI_RTSR_TR3_Pos (3U) 2682 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 2683 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 2684 #define EXTI_RTSR_TR4_Pos (4U) 2685 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 2686 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 2687 #define EXTI_RTSR_TR5_Pos (5U) 2688 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 2689 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 2690 #define EXTI_RTSR_TR6_Pos (6U) 2691 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 2692 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 2693 #define EXTI_RTSR_TR7_Pos (7U) 2694 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 2695 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 2696 #define EXTI_RTSR_TR8_Pos (8U) 2697 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 2698 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 2699 #define EXTI_RTSR_TR9_Pos (9U) 2700 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 2701 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 2702 #define EXTI_RTSR_TR10_Pos (10U) 2703 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 2704 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 2705 #define EXTI_RTSR_TR11_Pos (11U) 2706 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 2707 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 2708 #define EXTI_RTSR_TR12_Pos (12U) 2709 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 2710 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 2711 #define EXTI_RTSR_TR13_Pos (13U) 2712 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 2713 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 2714 #define EXTI_RTSR_TR14_Pos (14U) 2715 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 2716 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 2717 #define EXTI_RTSR_TR15_Pos (15U) 2718 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 2719 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 2720 #define EXTI_RTSR_TR16_Pos (16U) 2721 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 2722 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 2723 #define EXTI_RTSR_TR17_Pos (17U) 2724 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 2725 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 2726 #define EXTI_RTSR_TR18_Pos (18U) 2727 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ 2728 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ 2729 #define EXTI_RTSR_TR19_Pos (19U) 2730 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 2731 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 2732 #define EXTI_RTSR_TR20_Pos (20U) 2733 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ 2734 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ 2735 #define EXTI_RTSR_TR21_Pos (21U) 2736 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ 2737 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ 2738 #define EXTI_RTSR_TR22_Pos (22U) 2739 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ 2740 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ 2741 #define EXTI_RTSR_TR23_Pos (23U) 2742 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */ 2743 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */ 2744 2745 /* References Defines */ 2746 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 2747 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 2748 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 2749 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 2750 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 2751 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 2752 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 2753 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 2754 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 2755 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 2756 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 2757 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 2758 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 2759 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 2760 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 2761 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 2762 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 2763 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 2764 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 2765 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 2766 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20 2767 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21 2768 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22 2769 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23 2770 2771 /****************** Bit definition for EXTI_FTSR register *******************/ 2772 #define EXTI_FTSR_TR0_Pos (0U) 2773 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 2774 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 2775 #define EXTI_FTSR_TR1_Pos (1U) 2776 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 2777 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 2778 #define EXTI_FTSR_TR2_Pos (2U) 2779 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 2780 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 2781 #define EXTI_FTSR_TR3_Pos (3U) 2782 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 2783 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 2784 #define EXTI_FTSR_TR4_Pos (4U) 2785 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 2786 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 2787 #define EXTI_FTSR_TR5_Pos (5U) 2788 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 2789 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 2790 #define EXTI_FTSR_TR6_Pos (6U) 2791 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 2792 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 2793 #define EXTI_FTSR_TR7_Pos (7U) 2794 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 2795 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 2796 #define EXTI_FTSR_TR8_Pos (8U) 2797 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 2798 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 2799 #define EXTI_FTSR_TR9_Pos (9U) 2800 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 2801 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 2802 #define EXTI_FTSR_TR10_Pos (10U) 2803 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 2804 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 2805 #define EXTI_FTSR_TR11_Pos (11U) 2806 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 2807 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 2808 #define EXTI_FTSR_TR12_Pos (12U) 2809 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 2810 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 2811 #define EXTI_FTSR_TR13_Pos (13U) 2812 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 2813 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 2814 #define EXTI_FTSR_TR14_Pos (14U) 2815 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 2816 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 2817 #define EXTI_FTSR_TR15_Pos (15U) 2818 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 2819 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 2820 #define EXTI_FTSR_TR16_Pos (16U) 2821 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 2822 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 2823 #define EXTI_FTSR_TR17_Pos (17U) 2824 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 2825 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 2826 #define EXTI_FTSR_TR18_Pos (18U) 2827 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ 2828 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ 2829 #define EXTI_FTSR_TR19_Pos (19U) 2830 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 2831 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 2832 #define EXTI_FTSR_TR20_Pos (20U) 2833 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ 2834 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ 2835 #define EXTI_FTSR_TR21_Pos (21U) 2836 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ 2837 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ 2838 #define EXTI_FTSR_TR22_Pos (22U) 2839 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ 2840 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ 2841 #define EXTI_FTSR_TR23_Pos (23U) 2842 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */ 2843 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */ 2844 2845 /* References Defines */ 2846 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 2847 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 2848 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 2849 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 2850 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 2851 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 2852 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 2853 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 2854 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 2855 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 2856 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 2857 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 2858 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 2859 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 2860 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 2861 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 2862 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 2863 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 2864 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 2865 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 2866 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20 2867 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21 2868 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22 2869 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23 2870 2871 /****************** Bit definition for EXTI_SWIER register ******************/ 2872 #define EXTI_SWIER_SWIER0_Pos (0U) 2873 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 2874 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 2875 #define EXTI_SWIER_SWIER1_Pos (1U) 2876 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 2877 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 2878 #define EXTI_SWIER_SWIER2_Pos (2U) 2879 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 2880 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 2881 #define EXTI_SWIER_SWIER3_Pos (3U) 2882 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 2883 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 2884 #define EXTI_SWIER_SWIER4_Pos (4U) 2885 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 2886 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 2887 #define EXTI_SWIER_SWIER5_Pos (5U) 2888 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 2889 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 2890 #define EXTI_SWIER_SWIER6_Pos (6U) 2891 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 2892 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 2893 #define EXTI_SWIER_SWIER7_Pos (7U) 2894 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 2895 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 2896 #define EXTI_SWIER_SWIER8_Pos (8U) 2897 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 2898 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 2899 #define EXTI_SWIER_SWIER9_Pos (9U) 2900 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 2901 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 2902 #define EXTI_SWIER_SWIER10_Pos (10U) 2903 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 2904 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 2905 #define EXTI_SWIER_SWIER11_Pos (11U) 2906 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 2907 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 2908 #define EXTI_SWIER_SWIER12_Pos (12U) 2909 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 2910 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 2911 #define EXTI_SWIER_SWIER13_Pos (13U) 2912 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 2913 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 2914 #define EXTI_SWIER_SWIER14_Pos (14U) 2915 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 2916 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 2917 #define EXTI_SWIER_SWIER15_Pos (15U) 2918 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 2919 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 2920 #define EXTI_SWIER_SWIER16_Pos (16U) 2921 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 2922 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 2923 #define EXTI_SWIER_SWIER17_Pos (17U) 2924 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 2925 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 2926 #define EXTI_SWIER_SWIER18_Pos (18U) 2927 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ 2928 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ 2929 #define EXTI_SWIER_SWIER19_Pos (19U) 2930 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 2931 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 2932 #define EXTI_SWIER_SWIER20_Pos (20U) 2933 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ 2934 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ 2935 #define EXTI_SWIER_SWIER21_Pos (21U) 2936 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ 2937 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ 2938 #define EXTI_SWIER_SWIER22_Pos (22U) 2939 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ 2940 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ 2941 #define EXTI_SWIER_SWIER23_Pos (23U) 2942 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */ 2943 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */ 2944 2945 /* References Defines */ 2946 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 2947 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 2948 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 2949 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 2950 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 2951 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 2952 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 2953 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 2954 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 2955 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 2956 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 2957 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 2958 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 2959 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 2960 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 2961 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 2962 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 2963 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 2964 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 2965 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 2966 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20 2967 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21 2968 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22 2969 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23 2970 2971 /******************* Bit definition for EXTI_PR register ********************/ 2972 #define EXTI_PR_PR0_Pos (0U) 2973 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 2974 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ 2975 #define EXTI_PR_PR1_Pos (1U) 2976 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 2977 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ 2978 #define EXTI_PR_PR2_Pos (2U) 2979 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 2980 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ 2981 #define EXTI_PR_PR3_Pos (3U) 2982 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 2983 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ 2984 #define EXTI_PR_PR4_Pos (4U) 2985 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 2986 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ 2987 #define EXTI_PR_PR5_Pos (5U) 2988 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 2989 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ 2990 #define EXTI_PR_PR6_Pos (6U) 2991 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 2992 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ 2993 #define EXTI_PR_PR7_Pos (7U) 2994 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 2995 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ 2996 #define EXTI_PR_PR8_Pos (8U) 2997 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 2998 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ 2999 #define EXTI_PR_PR9_Pos (9U) 3000 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 3001 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ 3002 #define EXTI_PR_PR10_Pos (10U) 3003 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 3004 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ 3005 #define EXTI_PR_PR11_Pos (11U) 3006 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 3007 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ 3008 #define EXTI_PR_PR12_Pos (12U) 3009 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 3010 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ 3011 #define EXTI_PR_PR13_Pos (13U) 3012 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 3013 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ 3014 #define EXTI_PR_PR14_Pos (14U) 3015 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 3016 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ 3017 #define EXTI_PR_PR15_Pos (15U) 3018 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 3019 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ 3020 #define EXTI_PR_PR16_Pos (16U) 3021 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 3022 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ 3023 #define EXTI_PR_PR17_Pos (17U) 3024 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 3025 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ 3026 #define EXTI_PR_PR18_Pos (18U) 3027 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ 3028 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ 3029 #define EXTI_PR_PR19_Pos (19U) 3030 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 3031 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ 3032 #define EXTI_PR_PR20_Pos (20U) 3033 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ 3034 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ 3035 #define EXTI_PR_PR21_Pos (21U) 3036 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ 3037 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ 3038 #define EXTI_PR_PR22_Pos (22U) 3039 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ 3040 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ 3041 #define EXTI_PR_PR23_Pos (23U) 3042 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */ 3043 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */ 3044 3045 /* References Defines */ 3046 #define EXTI_PR_PIF0 EXTI_PR_PR0 3047 #define EXTI_PR_PIF1 EXTI_PR_PR1 3048 #define EXTI_PR_PIF2 EXTI_PR_PR2 3049 #define EXTI_PR_PIF3 EXTI_PR_PR3 3050 #define EXTI_PR_PIF4 EXTI_PR_PR4 3051 #define EXTI_PR_PIF5 EXTI_PR_PR5 3052 #define EXTI_PR_PIF6 EXTI_PR_PR6 3053 #define EXTI_PR_PIF7 EXTI_PR_PR7 3054 #define EXTI_PR_PIF8 EXTI_PR_PR8 3055 #define EXTI_PR_PIF9 EXTI_PR_PR9 3056 #define EXTI_PR_PIF10 EXTI_PR_PR10 3057 #define EXTI_PR_PIF11 EXTI_PR_PR11 3058 #define EXTI_PR_PIF12 EXTI_PR_PR12 3059 #define EXTI_PR_PIF13 EXTI_PR_PR13 3060 #define EXTI_PR_PIF14 EXTI_PR_PR14 3061 #define EXTI_PR_PIF15 EXTI_PR_PR15 3062 #define EXTI_PR_PIF16 EXTI_PR_PR16 3063 #define EXTI_PR_PIF17 EXTI_PR_PR17 3064 #define EXTI_PR_PIF18 EXTI_PR_PR18 3065 #define EXTI_PR_PIF19 EXTI_PR_PR19 3066 #define EXTI_PR_PIF20 EXTI_PR_PR20 3067 #define EXTI_PR_PIF21 EXTI_PR_PR21 3068 #define EXTI_PR_PIF22 EXTI_PR_PR22 3069 #define EXTI_PR_PIF23 EXTI_PR_PR23 3070 3071 /******************************************************************************/ 3072 /* */ 3073 /* FLASH, DATA EEPROM and Option Bytes Registers */ 3074 /* (FLASH, DATA_EEPROM, OB) */ 3075 /* */ 3076 /******************************************************************************/ 3077 3078 /******************* Bit definition for FLASH_ACR register ******************/ 3079 #define FLASH_ACR_LATENCY_Pos (0U) 3080 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 3081 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ 3082 #define FLASH_ACR_PRFTEN_Pos (1U) 3083 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ 3084 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ 3085 #define FLASH_ACR_ACC64_Pos (2U) 3086 #define FLASH_ACR_ACC64_Msk (0x1U << FLASH_ACR_ACC64_Pos) /*!< 0x00000004 */ 3087 #define FLASH_ACR_ACC64 FLASH_ACR_ACC64_Msk /*!< Access 64 bits */ 3088 #define FLASH_ACR_SLEEP_PD_Pos (3U) 3089 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ 3090 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ 3091 #define FLASH_ACR_RUN_PD_Pos (4U) 3092 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ 3093 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ 3094 3095 /******************* Bit definition for FLASH_PECR register ******************/ 3096 #define FLASH_PECR_PELOCK_Pos (0U) 3097 #define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ 3098 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ 3099 #define FLASH_PECR_PRGLOCK_Pos (1U) 3100 #define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ 3101 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ 3102 #define FLASH_PECR_OPTLOCK_Pos (2U) 3103 #define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ 3104 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ 3105 #define FLASH_PECR_PROG_Pos (3U) 3106 #define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ 3107 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ 3108 #define FLASH_PECR_DATA_Pos (4U) 3109 #define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ 3110 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ 3111 #define FLASH_PECR_FTDW_Pos (8U) 3112 #define FLASH_PECR_FTDW_Msk (0x1U << FLASH_PECR_FTDW_Pos) /*!< 0x00000100 */ 3113 #define FLASH_PECR_FTDW FLASH_PECR_FTDW_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ 3114 #define FLASH_PECR_ERASE_Pos (9U) 3115 #define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ 3116 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ 3117 #define FLASH_PECR_FPRG_Pos (10U) 3118 #define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ 3119 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ 3120 #define FLASH_PECR_PARALLBANK_Pos (15U) 3121 #define FLASH_PECR_PARALLBANK_Msk (0x1U << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */ 3122 #define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */ 3123 #define FLASH_PECR_EOPIE_Pos (16U) 3124 #define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ 3125 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ 3126 #define FLASH_PECR_ERRIE_Pos (17U) 3127 #define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ 3128 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ 3129 #define FLASH_PECR_OBL_LAUNCH_Pos (18U) 3130 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ 3131 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ 3132 3133 /****************** Bit definition for FLASH_PDKEYR register ******************/ 3134 #define FLASH_PDKEYR_PDKEYR_Pos (0U) 3135 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ 3136 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 3137 3138 /****************** Bit definition for FLASH_PEKEYR register ******************/ 3139 #define FLASH_PEKEYR_PEKEYR_Pos (0U) 3140 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ 3141 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 3142 3143 /****************** Bit definition for FLASH_PRGKEYR register ******************/ 3144 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U) 3145 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ 3146 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ 3147 3148 /****************** Bit definition for FLASH_OPTKEYR register ******************/ 3149 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 3150 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 3151 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ 3152 3153 /****************** Bit definition for FLASH_SR register *******************/ 3154 #define FLASH_SR_BSY_Pos (0U) 3155 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 3156 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 3157 #define FLASH_SR_EOP_Pos (1U) 3158 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ 3159 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ 3160 #define FLASH_SR_ENDHV_Pos (2U) 3161 #define FLASH_SR_ENDHV_Msk (0x1U << FLASH_SR_ENDHV_Pos) /*!< 0x00000004 */ 3162 #define FLASH_SR_ENDHV FLASH_SR_ENDHV_Msk /*!< End of high voltage */ 3163 #define FLASH_SR_READY_Pos (3U) 3164 #define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */ 3165 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ 3166 3167 #define FLASH_SR_WRPERR_Pos (8U) 3168 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ 3169 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protected error */ 3170 #define FLASH_SR_PGAERR_Pos (9U) 3171 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ 3172 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ 3173 #define FLASH_SR_SIZERR_Pos (10U) 3174 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ 3175 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ 3176 #define FLASH_SR_OPTVERR_Pos (11U) 3177 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ 3178 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */ 3179 #define FLASH_SR_OPTVERRUSR_Pos (12U) 3180 #define FLASH_SR_OPTVERRUSR_Msk (0x1U << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */ 3181 #define FLASH_SR_OPTVERRUSR FLASH_SR_OPTVERRUSR_Msk /*!< Option User validity error */ 3182 3183 /****************** Bit definition for FLASH_OBR register *******************/ 3184 #define FLASH_OBR_RDPRT_Pos (0U) 3185 #define FLASH_OBR_RDPRT_Msk (0xFFU << FLASH_OBR_RDPRT_Pos) /*!< 0x000000FF */ 3186 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read Protection */ 3187 #define FLASH_OBR_BOR_LEV_Pos (16U) 3188 #define FLASH_OBR_BOR_LEV_Msk (0xFU << FLASH_OBR_BOR_LEV_Pos) /*!< 0x000F0000 */ 3189 #define FLASH_OBR_BOR_LEV FLASH_OBR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ 3190 #define FLASH_OBR_USER_Pos (20U) 3191 #define FLASH_OBR_USER_Msk (0xFU << FLASH_OBR_USER_Pos) /*!< 0x00F00000 */ 3192 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 3193 #define FLASH_OBR_IWDG_SW_Pos (20U) 3194 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00100000 */ 3195 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG_SW */ 3196 #define FLASH_OBR_nRST_STOP_Pos (21U) 3197 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */ 3198 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 3199 #define FLASH_OBR_nRST_STDBY_Pos (22U) 3200 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */ 3201 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 3202 #define FLASH_OBR_nRST_BFB2_Pos (23U) 3203 #define FLASH_OBR_nRST_BFB2_Msk (0x1U << FLASH_OBR_nRST_BFB2_Pos) /*!< 0x00800000 */ 3204 #define FLASH_OBR_nRST_BFB2 FLASH_OBR_nRST_BFB2_Msk /*!< BFB2 */ 3205 3206 /****************** Bit definition for FLASH_WRPR register ******************/ 3207 #define FLASH_WRPR1_WRP_Pos (0U) 3208 #define FLASH_WRPR1_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */ 3209 #define FLASH_WRPR1_WRP FLASH_WRPR1_WRP_Msk /*!< Write Protect sectors 0 to 31 */ 3210 #define FLASH_WRPR2_WRP_Pos (0U) 3211 #define FLASH_WRPR2_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */ 3212 #define FLASH_WRPR2_WRP FLASH_WRPR2_WRP_Msk /*!< Write Protect sectors 32 to 63 */ 3213 #define FLASH_WRPR3_WRP_Pos (0U) 3214 #define FLASH_WRPR3_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR3_WRP_Pos) /*!< 0xFFFFFFFF */ 3215 #define FLASH_WRPR3_WRP FLASH_WRPR3_WRP_Msk /*!< Write Protect sectors 64 to 95 */ 3216 #define FLASH_WRPR4_WRP_Pos (0U) 3217 #define FLASH_WRPR4_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR4_WRP_Pos) /*!< 0xFFFFFFFF */ 3218 #define FLASH_WRPR4_WRP FLASH_WRPR4_WRP_Msk /*!< Write Protect sectors 96 to 127 */ 3219 3220 /******************************************************************************/ 3221 /* */ 3222 /* General Purpose I/O */ 3223 /* */ 3224 /******************************************************************************/ 3225 /****************** Bits definition for GPIO_MODER register *****************/ 3226 #define GPIO_MODER_MODER0_Pos (0U) 3227 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ 3228 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 3229 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ 3230 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ 3231 3232 #define GPIO_MODER_MODER1_Pos (2U) 3233 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ 3234 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 3235 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ 3236 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ 3237 3238 #define GPIO_MODER_MODER2_Pos (4U) 3239 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ 3240 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 3241 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ 3242 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ 3243 3244 #define GPIO_MODER_MODER3_Pos (6U) 3245 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ 3246 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 3247 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ 3248 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ 3249 3250 #define GPIO_MODER_MODER4_Pos (8U) 3251 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ 3252 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 3253 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ 3254 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ 3255 3256 #define GPIO_MODER_MODER5_Pos (10U) 3257 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ 3258 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 3259 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ 3260 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ 3261 3262 #define GPIO_MODER_MODER6_Pos (12U) 3263 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ 3264 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 3265 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ 3266 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ 3267 3268 #define GPIO_MODER_MODER7_Pos (14U) 3269 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ 3270 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 3271 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ 3272 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ 3273 3274 #define GPIO_MODER_MODER8_Pos (16U) 3275 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ 3276 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 3277 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ 3278 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ 3279 3280 #define GPIO_MODER_MODER9_Pos (18U) 3281 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ 3282 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 3283 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ 3284 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ 3285 3286 #define GPIO_MODER_MODER10_Pos (20U) 3287 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ 3288 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 3289 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ 3290 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ 3291 3292 #define GPIO_MODER_MODER11_Pos (22U) 3293 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ 3294 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 3295 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ 3296 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ 3297 3298 #define GPIO_MODER_MODER12_Pos (24U) 3299 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ 3300 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 3301 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ 3302 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ 3303 3304 #define GPIO_MODER_MODER13_Pos (26U) 3305 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ 3306 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 3307 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ 3308 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ 3309 3310 #define GPIO_MODER_MODER14_Pos (28U) 3311 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ 3312 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 3313 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ 3314 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ 3315 3316 #define GPIO_MODER_MODER15_Pos (30U) 3317 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ 3318 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 3319 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ 3320 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ 3321 3322 /****************** Bits definition for GPIO_OTYPER register ****************/ 3323 #define GPIO_OTYPER_OT_0 (0x00000001U) 3324 #define GPIO_OTYPER_OT_1 (0x00000002U) 3325 #define GPIO_OTYPER_OT_2 (0x00000004U) 3326 #define GPIO_OTYPER_OT_3 (0x00000008U) 3327 #define GPIO_OTYPER_OT_4 (0x00000010U) 3328 #define GPIO_OTYPER_OT_5 (0x00000020U) 3329 #define GPIO_OTYPER_OT_6 (0x00000040U) 3330 #define GPIO_OTYPER_OT_7 (0x00000080U) 3331 #define GPIO_OTYPER_OT_8 (0x00000100U) 3332 #define GPIO_OTYPER_OT_9 (0x00000200U) 3333 #define GPIO_OTYPER_OT_10 (0x00000400U) 3334 #define GPIO_OTYPER_OT_11 (0x00000800U) 3335 #define GPIO_OTYPER_OT_12 (0x00001000U) 3336 #define GPIO_OTYPER_OT_13 (0x00002000U) 3337 #define GPIO_OTYPER_OT_14 (0x00004000U) 3338 #define GPIO_OTYPER_OT_15 (0x00008000U) 3339 3340 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 3341 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) 3342 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */ 3343 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk 3344 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */ 3345 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */ 3346 3347 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) 3348 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */ 3349 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk 3350 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */ 3351 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */ 3352 3353 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) 3354 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */ 3355 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk 3356 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */ 3357 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */ 3358 3359 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) 3360 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */ 3361 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk 3362 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */ 3363 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */ 3364 3365 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) 3366 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */ 3367 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk 3368 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */ 3369 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */ 3370 3371 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) 3372 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */ 3373 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk 3374 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */ 3375 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */ 3376 3377 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) 3378 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */ 3379 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk 3380 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */ 3381 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */ 3382 3383 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) 3384 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */ 3385 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk 3386 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */ 3387 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */ 3388 3389 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) 3390 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */ 3391 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk 3392 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */ 3393 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */ 3394 3395 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) 3396 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */ 3397 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk 3398 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */ 3399 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */ 3400 3401 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) 3402 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */ 3403 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk 3404 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */ 3405 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */ 3406 3407 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) 3408 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */ 3409 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk 3410 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */ 3411 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */ 3412 3413 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) 3414 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */ 3415 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk 3416 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */ 3417 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */ 3418 3419 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) 3420 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */ 3421 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk 3422 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */ 3423 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */ 3424 3425 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) 3426 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */ 3427 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk 3428 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */ 3429 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */ 3430 3431 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) 3432 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */ 3433 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk 3434 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */ 3435 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */ 3436 3437 /****************** Bits definition for GPIO_PUPDR register *****************/ 3438 #define GPIO_PUPDR_PUPDR0_Pos (0U) 3439 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */ 3440 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk 3441 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */ 3442 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */ 3443 3444 #define GPIO_PUPDR_PUPDR1_Pos (2U) 3445 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */ 3446 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk 3447 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */ 3448 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */ 3449 3450 #define GPIO_PUPDR_PUPDR2_Pos (4U) 3451 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */ 3452 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk 3453 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */ 3454 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */ 3455 3456 #define GPIO_PUPDR_PUPDR3_Pos (6U) 3457 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */ 3458 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk 3459 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */ 3460 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */ 3461 3462 #define GPIO_PUPDR_PUPDR4_Pos (8U) 3463 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */ 3464 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk 3465 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */ 3466 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */ 3467 3468 #define GPIO_PUPDR_PUPDR5_Pos (10U) 3469 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */ 3470 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk 3471 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */ 3472 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */ 3473 3474 #define GPIO_PUPDR_PUPDR6_Pos (12U) 3475 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */ 3476 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk 3477 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */ 3478 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */ 3479 3480 #define GPIO_PUPDR_PUPDR7_Pos (14U) 3481 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */ 3482 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk 3483 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */ 3484 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */ 3485 3486 #define GPIO_PUPDR_PUPDR8_Pos (16U) 3487 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */ 3488 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk 3489 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */ 3490 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */ 3491 3492 #define GPIO_PUPDR_PUPDR9_Pos (18U) 3493 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */ 3494 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk 3495 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */ 3496 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */ 3497 3498 #define GPIO_PUPDR_PUPDR10_Pos (20U) 3499 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */ 3500 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk 3501 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */ 3502 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */ 3503 3504 #define GPIO_PUPDR_PUPDR11_Pos (22U) 3505 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */ 3506 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk 3507 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */ 3508 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */ 3509 3510 #define GPIO_PUPDR_PUPDR12_Pos (24U) 3511 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */ 3512 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk 3513 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */ 3514 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */ 3515 3516 #define GPIO_PUPDR_PUPDR13_Pos (26U) 3517 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */ 3518 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk 3519 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */ 3520 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */ 3521 3522 #define GPIO_PUPDR_PUPDR14_Pos (28U) 3523 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */ 3524 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk 3525 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */ 3526 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */ 3527 #define GPIO_PUPDR_PUPDR15_Pos (30U) 3528 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */ 3529 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk 3530 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */ 3531 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */ 3532 3533 /****************** Bits definition for GPIO_IDR register *******************/ 3534 #define GPIO_IDR_IDR_0 (0x00000001U) 3535 #define GPIO_IDR_IDR_1 (0x00000002U) 3536 #define GPIO_IDR_IDR_2 (0x00000004U) 3537 #define GPIO_IDR_IDR_3 (0x00000008U) 3538 #define GPIO_IDR_IDR_4 (0x00000010U) 3539 #define GPIO_IDR_IDR_5 (0x00000020U) 3540 #define GPIO_IDR_IDR_6 (0x00000040U) 3541 #define GPIO_IDR_IDR_7 (0x00000080U) 3542 #define GPIO_IDR_IDR_8 (0x00000100U) 3543 #define GPIO_IDR_IDR_9 (0x00000200U) 3544 #define GPIO_IDR_IDR_10 (0x00000400U) 3545 #define GPIO_IDR_IDR_11 (0x00000800U) 3546 #define GPIO_IDR_IDR_12 (0x00001000U) 3547 #define GPIO_IDR_IDR_13 (0x00002000U) 3548 #define GPIO_IDR_IDR_14 (0x00004000U) 3549 #define GPIO_IDR_IDR_15 (0x00008000U) 3550 3551 /****************** Bits definition for GPIO_ODR register *******************/ 3552 #define GPIO_ODR_ODR_0 (0x00000001U) 3553 #define GPIO_ODR_ODR_1 (0x00000002U) 3554 #define GPIO_ODR_ODR_2 (0x00000004U) 3555 #define GPIO_ODR_ODR_3 (0x00000008U) 3556 #define GPIO_ODR_ODR_4 (0x00000010U) 3557 #define GPIO_ODR_ODR_5 (0x00000020U) 3558 #define GPIO_ODR_ODR_6 (0x00000040U) 3559 #define GPIO_ODR_ODR_7 (0x00000080U) 3560 #define GPIO_ODR_ODR_8 (0x00000100U) 3561 #define GPIO_ODR_ODR_9 (0x00000200U) 3562 #define GPIO_ODR_ODR_10 (0x00000400U) 3563 #define GPIO_ODR_ODR_11 (0x00000800U) 3564 #define GPIO_ODR_ODR_12 (0x00001000U) 3565 #define GPIO_ODR_ODR_13 (0x00002000U) 3566 #define GPIO_ODR_ODR_14 (0x00004000U) 3567 #define GPIO_ODR_ODR_15 (0x00008000U) 3568 3569 /****************** Bits definition for GPIO_BSRR register ******************/ 3570 #define GPIO_BSRR_BS_0 (0x00000001U) 3571 #define GPIO_BSRR_BS_1 (0x00000002U) 3572 #define GPIO_BSRR_BS_2 (0x00000004U) 3573 #define GPIO_BSRR_BS_3 (0x00000008U) 3574 #define GPIO_BSRR_BS_4 (0x00000010U) 3575 #define GPIO_BSRR_BS_5 (0x00000020U) 3576 #define GPIO_BSRR_BS_6 (0x00000040U) 3577 #define GPIO_BSRR_BS_7 (0x00000080U) 3578 #define GPIO_BSRR_BS_8 (0x00000100U) 3579 #define GPIO_BSRR_BS_9 (0x00000200U) 3580 #define GPIO_BSRR_BS_10 (0x00000400U) 3581 #define GPIO_BSRR_BS_11 (0x00000800U) 3582 #define GPIO_BSRR_BS_12 (0x00001000U) 3583 #define GPIO_BSRR_BS_13 (0x00002000U) 3584 #define GPIO_BSRR_BS_14 (0x00004000U) 3585 #define GPIO_BSRR_BS_15 (0x00008000U) 3586 #define GPIO_BSRR_BR_0 (0x00010000U) 3587 #define GPIO_BSRR_BR_1 (0x00020000U) 3588 #define GPIO_BSRR_BR_2 (0x00040000U) 3589 #define GPIO_BSRR_BR_3 (0x00080000U) 3590 #define GPIO_BSRR_BR_4 (0x00100000U) 3591 #define GPIO_BSRR_BR_5 (0x00200000U) 3592 #define GPIO_BSRR_BR_6 (0x00400000U) 3593 #define GPIO_BSRR_BR_7 (0x00800000U) 3594 #define GPIO_BSRR_BR_8 (0x01000000U) 3595 #define GPIO_BSRR_BR_9 (0x02000000U) 3596 #define GPIO_BSRR_BR_10 (0x04000000U) 3597 #define GPIO_BSRR_BR_11 (0x08000000U) 3598 #define GPIO_BSRR_BR_12 (0x10000000U) 3599 #define GPIO_BSRR_BR_13 (0x20000000U) 3600 #define GPIO_BSRR_BR_14 (0x40000000U) 3601 #define GPIO_BSRR_BR_15 (0x80000000U) 3602 3603 /****************** Bit definition for GPIO_LCKR register ********************/ 3604 #define GPIO_LCKR_LCK0_Pos (0U) 3605 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 3606 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 3607 #define GPIO_LCKR_LCK1_Pos (1U) 3608 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 3609 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 3610 #define GPIO_LCKR_LCK2_Pos (2U) 3611 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 3612 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 3613 #define GPIO_LCKR_LCK3_Pos (3U) 3614 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 3615 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 3616 #define GPIO_LCKR_LCK4_Pos (4U) 3617 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 3618 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 3619 #define GPIO_LCKR_LCK5_Pos (5U) 3620 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 3621 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 3622 #define GPIO_LCKR_LCK6_Pos (6U) 3623 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 3624 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 3625 #define GPIO_LCKR_LCK7_Pos (7U) 3626 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 3627 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 3628 #define GPIO_LCKR_LCK8_Pos (8U) 3629 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 3630 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 3631 #define GPIO_LCKR_LCK9_Pos (9U) 3632 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 3633 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 3634 #define GPIO_LCKR_LCK10_Pos (10U) 3635 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 3636 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 3637 #define GPIO_LCKR_LCK11_Pos (11U) 3638 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 3639 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 3640 #define GPIO_LCKR_LCK12_Pos (12U) 3641 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 3642 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 3643 #define GPIO_LCKR_LCK13_Pos (13U) 3644 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 3645 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 3646 #define GPIO_LCKR_LCK14_Pos (14U) 3647 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 3648 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 3649 #define GPIO_LCKR_LCK15_Pos (15U) 3650 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 3651 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 3652 #define GPIO_LCKR_LCKK_Pos (16U) 3653 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 3654 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 3655 3656 /****************** Bit definition for GPIO_AFRL register ********************/ 3657 #define GPIO_AFRL_AFSEL0_Pos (0U) 3658 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 3659 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 3660 #define GPIO_AFRL_AFSEL1_Pos (4U) 3661 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 3662 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 3663 #define GPIO_AFRL_AFSEL2_Pos (8U) 3664 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 3665 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 3666 #define GPIO_AFRL_AFSEL3_Pos (12U) 3667 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 3668 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 3669 #define GPIO_AFRL_AFSEL4_Pos (16U) 3670 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 3671 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 3672 #define GPIO_AFRL_AFSEL5_Pos (20U) 3673 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 3674 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 3675 #define GPIO_AFRL_AFSEL6_Pos (24U) 3676 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 3677 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 3678 #define GPIO_AFRL_AFSEL7_Pos (28U) 3679 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 3680 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 3681 3682 /****************** Bit definition for GPIO_AFRH register ********************/ 3683 #define GPIO_AFRH_AFSEL8_Pos (0U) 3684 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 3685 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 3686 #define GPIO_AFRH_AFSEL9_Pos (4U) 3687 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 3688 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 3689 #define GPIO_AFRH_AFSEL10_Pos (8U) 3690 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 3691 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 3692 #define GPIO_AFRH_AFSEL11_Pos (12U) 3693 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 3694 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 3695 #define GPIO_AFRH_AFSEL12_Pos (16U) 3696 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 3697 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 3698 #define GPIO_AFRH_AFSEL13_Pos (20U) 3699 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 3700 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 3701 #define GPIO_AFRH_AFSEL14_Pos (24U) 3702 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 3703 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 3704 #define GPIO_AFRH_AFSEL15_Pos (28U) 3705 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 3706 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 3707 3708 /****************** Bit definition for GPIO_BRR register *********************/ 3709 #define GPIO_BRR_BR_0 (0x00000001U) 3710 #define GPIO_BRR_BR_1 (0x00000002U) 3711 #define GPIO_BRR_BR_2 (0x00000004U) 3712 #define GPIO_BRR_BR_3 (0x00000008U) 3713 #define GPIO_BRR_BR_4 (0x00000010U) 3714 #define GPIO_BRR_BR_5 (0x00000020U) 3715 #define GPIO_BRR_BR_6 (0x00000040U) 3716 #define GPIO_BRR_BR_7 (0x00000080U) 3717 #define GPIO_BRR_BR_8 (0x00000100U) 3718 #define GPIO_BRR_BR_9 (0x00000200U) 3719 #define GPIO_BRR_BR_10 (0x00000400U) 3720 #define GPIO_BRR_BR_11 (0x00000800U) 3721 #define GPIO_BRR_BR_12 (0x00001000U) 3722 #define GPIO_BRR_BR_13 (0x00002000U) 3723 #define GPIO_BRR_BR_14 (0x00004000U) 3724 #define GPIO_BRR_BR_15 (0x00008000U) 3725 3726 /******************************************************************************/ 3727 /* */ 3728 /* Inter-integrated Circuit Interface (I2C) */ 3729 /* */ 3730 /******************************************************************************/ 3731 3732 /******************* Bit definition for I2C_CR1 register ********************/ 3733 #define I2C_CR1_PE_Pos (0U) 3734 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 3735 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ 3736 #define I2C_CR1_SMBUS_Pos (1U) 3737 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ 3738 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ 3739 #define I2C_CR1_SMBTYPE_Pos (3U) 3740 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ 3741 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ 3742 #define I2C_CR1_ENARP_Pos (4U) 3743 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ 3744 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ 3745 #define I2C_CR1_ENPEC_Pos (5U) 3746 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ 3747 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ 3748 #define I2C_CR1_ENGC_Pos (6U) 3749 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ 3750 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ 3751 #define I2C_CR1_NOSTRETCH_Pos (7U) 3752 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ 3753 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ 3754 #define I2C_CR1_START_Pos (8U) 3755 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */ 3756 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ 3757 #define I2C_CR1_STOP_Pos (9U) 3758 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ 3759 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ 3760 #define I2C_CR1_ACK_Pos (10U) 3761 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ 3762 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ 3763 #define I2C_CR1_POS_Pos (11U) 3764 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */ 3765 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ 3766 #define I2C_CR1_PEC_Pos (12U) 3767 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ 3768 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ 3769 #define I2C_CR1_ALERT_Pos (13U) 3770 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ 3771 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ 3772 #define I2C_CR1_SWRST_Pos (15U) 3773 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ 3774 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ 3775 3776 /******************* Bit definition for I2C_CR2 register ********************/ 3777 #define I2C_CR2_FREQ_Pos (0U) 3778 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ 3779 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ 3780 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ 3781 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ 3782 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ 3783 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ 3784 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ 3785 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ 3786 3787 #define I2C_CR2_ITERREN_Pos (8U) 3788 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ 3789 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ 3790 #define I2C_CR2_ITEVTEN_Pos (9U) 3791 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ 3792 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ 3793 #define I2C_CR2_ITBUFEN_Pos (10U) 3794 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ 3795 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ 3796 #define I2C_CR2_DMAEN_Pos (11U) 3797 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ 3798 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ 3799 #define I2C_CR2_LAST_Pos (12U) 3800 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ 3801 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ 3802 3803 /******************* Bit definition for I2C_OAR1 register *******************/ 3804 #define I2C_OAR1_ADD1_7 (0x000000FEU) /*!< Interface Address */ 3805 #define I2C_OAR1_ADD8_9 (0x00000300U) /*!< Interface Address */ 3806 3807 #define I2C_OAR1_ADD0_Pos (0U) 3808 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ 3809 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ 3810 #define I2C_OAR1_ADD1_Pos (1U) 3811 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ 3812 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ 3813 #define I2C_OAR1_ADD2_Pos (2U) 3814 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ 3815 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ 3816 #define I2C_OAR1_ADD3_Pos (3U) 3817 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ 3818 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ 3819 #define I2C_OAR1_ADD4_Pos (4U) 3820 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ 3821 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ 3822 #define I2C_OAR1_ADD5_Pos (5U) 3823 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ 3824 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ 3825 #define I2C_OAR1_ADD6_Pos (6U) 3826 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ 3827 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ 3828 #define I2C_OAR1_ADD7_Pos (7U) 3829 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ 3830 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ 3831 #define I2C_OAR1_ADD8_Pos (8U) 3832 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ 3833 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ 3834 #define I2C_OAR1_ADD9_Pos (9U) 3835 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ 3836 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ 3837 3838 #define I2C_OAR1_ADDMODE_Pos (15U) 3839 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ 3840 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ 3841 3842 /******************* Bit definition for I2C_OAR2 register *******************/ 3843 #define I2C_OAR2_ENDUAL_Pos (0U) 3844 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ 3845 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ 3846 #define I2C_OAR2_ADD2_Pos (1U) 3847 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ 3848 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ 3849 3850 /******************** Bit definition for I2C_DR register ********************/ 3851 #define I2C_DR_DR_Pos (0U) 3852 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */ 3853 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ 3854 3855 /******************* Bit definition for I2C_SR1 register ********************/ 3856 #define I2C_SR1_SB_Pos (0U) 3857 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */ 3858 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ 3859 #define I2C_SR1_ADDR_Pos (1U) 3860 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ 3861 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ 3862 #define I2C_SR1_BTF_Pos (2U) 3863 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ 3864 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ 3865 #define I2C_SR1_ADD10_Pos (3U) 3866 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ 3867 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ 3868 #define I2C_SR1_STOPF_Pos (4U) 3869 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ 3870 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ 3871 #define I2C_SR1_RXNE_Pos (6U) 3872 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ 3873 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ 3874 #define I2C_SR1_TXE_Pos (7U) 3875 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ 3876 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ 3877 #define I2C_SR1_BERR_Pos (8U) 3878 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ 3879 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ 3880 #define I2C_SR1_ARLO_Pos (9U) 3881 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ 3882 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ 3883 #define I2C_SR1_AF_Pos (10U) 3884 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */ 3885 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ 3886 #define I2C_SR1_OVR_Pos (11U) 3887 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ 3888 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ 3889 #define I2C_SR1_PECERR_Pos (12U) 3890 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ 3891 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ 3892 #define I2C_SR1_TIMEOUT_Pos (14U) 3893 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ 3894 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ 3895 #define I2C_SR1_SMBALERT_Pos (15U) 3896 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ 3897 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ 3898 3899 /******************* Bit definition for I2C_SR2 register ********************/ 3900 #define I2C_SR2_MSL_Pos (0U) 3901 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ 3902 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ 3903 #define I2C_SR2_BUSY_Pos (1U) 3904 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ 3905 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ 3906 #define I2C_SR2_TRA_Pos (2U) 3907 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ 3908 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ 3909 #define I2C_SR2_GENCALL_Pos (4U) 3910 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ 3911 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ 3912 #define I2C_SR2_SMBDEFAULT_Pos (5U) 3913 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ 3914 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ 3915 #define I2C_SR2_SMBHOST_Pos (6U) 3916 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ 3917 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ 3918 #define I2C_SR2_DUALF_Pos (7U) 3919 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ 3920 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ 3921 #define I2C_SR2_PEC_Pos (8U) 3922 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ 3923 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ 3924 3925 /******************* Bit definition for I2C_CCR register ********************/ 3926 #define I2C_CCR_CCR_Pos (0U) 3927 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ 3928 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ 3929 #define I2C_CCR_DUTY_Pos (14U) 3930 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ 3931 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ 3932 #define I2C_CCR_FS_Pos (15U) 3933 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */ 3934 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ 3935 3936 /****************** Bit definition for I2C_TRISE register *******************/ 3937 #define I2C_TRISE_TRISE_Pos (0U) 3938 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ 3939 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ 3940 3941 /******************************************************************************/ 3942 /* */ 3943 /* Independent WATCHDOG (IWDG) */ 3944 /* */ 3945 /******************************************************************************/ 3946 3947 /******************* Bit definition for IWDG_KR register ********************/ 3948 #define IWDG_KR_KEY_Pos (0U) 3949 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 3950 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 3951 3952 /******************* Bit definition for IWDG_PR register ********************/ 3953 #define IWDG_PR_PR_Pos (0U) 3954 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 3955 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 3956 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 3957 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 3958 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 3959 3960 /******************* Bit definition for IWDG_RLR register *******************/ 3961 #define IWDG_RLR_RL_Pos (0U) 3962 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 3963 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 3964 3965 /******************* Bit definition for IWDG_SR register ********************/ 3966 #define IWDG_SR_PVU_Pos (0U) 3967 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 3968 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 3969 #define IWDG_SR_RVU_Pos (1U) 3970 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 3971 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 3972 3973 /******************************************************************************/ 3974 /* */ 3975 /* LCD Controller (LCD) */ 3976 /* */ 3977 /******************************************************************************/ 3978 3979 /******************* Bit definition for LCD_CR register *********************/ 3980 #define LCD_CR_LCDEN_Pos (0U) 3981 #define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */ 3982 #define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */ 3983 #define LCD_CR_VSEL_Pos (1U) 3984 #define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */ 3985 #define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */ 3986 3987 #define LCD_CR_DUTY_Pos (2U) 3988 #define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */ 3989 #define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */ 3990 #define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */ 3991 #define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */ 3992 #define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */ 3993 3994 #define LCD_CR_BIAS_Pos (5U) 3995 #define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */ 3996 #define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */ 3997 #define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */ 3998 #define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */ 3999 4000 #define LCD_CR_MUX_SEG_Pos (7U) 4001 #define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */ 4002 #define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */ 4003 4004 /******************* Bit definition for LCD_FCR register ********************/ 4005 #define LCD_FCR_HD_Pos (0U) 4006 #define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */ 4007 #define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */ 4008 #define LCD_FCR_SOFIE_Pos (1U) 4009 #define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */ 4010 #define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */ 4011 #define LCD_FCR_UDDIE_Pos (3U) 4012 #define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */ 4013 #define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */ 4014 4015 #define LCD_FCR_PON_Pos (4U) 4016 #define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */ 4017 #define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ 4018 #define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */ 4019 #define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */ 4020 #define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */ 4021 4022 #define LCD_FCR_DEAD_Pos (7U) 4023 #define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */ 4024 #define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */ 4025 #define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */ 4026 #define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */ 4027 #define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */ 4028 4029 #define LCD_FCR_CC_Pos (10U) 4030 #define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */ 4031 #define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */ 4032 #define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */ 4033 #define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */ 4034 #define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */ 4035 4036 #define LCD_FCR_BLINKF_Pos (13U) 4037 #define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */ 4038 #define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */ 4039 #define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */ 4040 #define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */ 4041 #define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */ 4042 4043 #define LCD_FCR_BLINK_Pos (16U) 4044 #define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */ 4045 #define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */ 4046 #define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */ 4047 #define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */ 4048 4049 #define LCD_FCR_DIV_Pos (18U) 4050 #define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */ 4051 #define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */ 4052 #define LCD_FCR_PS_Pos (22U) 4053 #define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */ 4054 #define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */ 4055 4056 /******************* Bit definition for LCD_SR register *********************/ 4057 #define LCD_SR_ENS_Pos (0U) 4058 #define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */ 4059 #define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */ 4060 #define LCD_SR_SOF_Pos (1U) 4061 #define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */ 4062 #define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */ 4063 #define LCD_SR_UDR_Pos (2U) 4064 #define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */ 4065 #define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */ 4066 #define LCD_SR_UDD_Pos (3U) 4067 #define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */ 4068 #define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */ 4069 #define LCD_SR_RDY_Pos (4U) 4070 #define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */ 4071 #define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */ 4072 #define LCD_SR_FCRSR_Pos (5U) 4073 #define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */ 4074 #define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */ 4075 4076 /******************* Bit definition for LCD_CLR register ********************/ 4077 #define LCD_CLR_SOFC_Pos (1U) 4078 #define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */ 4079 #define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */ 4080 #define LCD_CLR_UDDC_Pos (3U) 4081 #define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */ 4082 #define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */ 4083 4084 /******************* Bit definition for LCD_RAM register ********************/ 4085 #define LCD_RAM_SEGMENT_DATA_Pos (0U) 4086 #define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */ 4087 #define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */ 4088 4089 /******************************************************************************/ 4090 /* */ 4091 /* Power Control (PWR) */ 4092 /* */ 4093 /******************************************************************************/ 4094 4095 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */ 4096 4097 /******************** Bit definition for PWR_CR register ********************/ 4098 #define PWR_CR_LPSDSR_Pos (0U) 4099 #define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ 4100 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ 4101 #define PWR_CR_PDDS_Pos (1U) 4102 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 4103 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 4104 #define PWR_CR_CWUF_Pos (2U) 4105 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 4106 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 4107 #define PWR_CR_CSBF_Pos (3U) 4108 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 4109 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 4110 #define PWR_CR_PVDE_Pos (4U) 4111 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 4112 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 4113 4114 #define PWR_CR_PLS_Pos (5U) 4115 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 4116 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 4117 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 4118 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 4119 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 4120 4121 /*!< PVD level configuration */ 4122 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ 4123 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ 4124 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ 4125 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ 4126 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ 4127 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ 4128 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ 4129 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ 4130 4131 #define PWR_CR_DBP_Pos (8U) 4132 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 4133 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 4134 #define PWR_CR_ULP_Pos (9U) 4135 #define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */ 4136 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ 4137 #define PWR_CR_FWU_Pos (10U) 4138 #define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */ 4139 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ 4140 4141 #define PWR_CR_VOS_Pos (11U) 4142 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */ 4143 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ 4144 #define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */ 4145 #define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */ 4146 #define PWR_CR_LPRUN_Pos (14U) 4147 #define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ 4148 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ 4149 4150 /******************* Bit definition for PWR_CSR register ********************/ 4151 #define PWR_CSR_WUF_Pos (0U) 4152 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 4153 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 4154 #define PWR_CSR_SBF_Pos (1U) 4155 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 4156 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 4157 #define PWR_CSR_PVDO_Pos (2U) 4158 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 4159 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 4160 #define PWR_CSR_VREFINTRDYF_Pos (3U) 4161 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ 4162 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ 4163 #define PWR_CSR_VOSF_Pos (4U) 4164 #define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ 4165 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ 4166 #define PWR_CSR_REGLPF_Pos (5U) 4167 #define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ 4168 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ 4169 4170 #define PWR_CSR_EWUP1_Pos (8U) 4171 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 4172 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 4173 #define PWR_CSR_EWUP2_Pos (9U) 4174 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 4175 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 4176 #define PWR_CSR_EWUP3_Pos (10U) 4177 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ 4178 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ 4179 4180 /******************************************************************************/ 4181 /* */ 4182 /* Reset and Clock Control (RCC) */ 4183 /* */ 4184 /******************************************************************************/ 4185 /* 4186 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) 4187 */ 4188 #define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */ 4189 4190 /******************** Bit definition for RCC_CR register ********************/ 4191 #define RCC_CR_HSION_Pos (0U) 4192 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 4193 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 4194 #define RCC_CR_HSIRDY_Pos (1U) 4195 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 4196 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 4197 4198 #define RCC_CR_MSION_Pos (8U) 4199 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */ 4200 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ 4201 #define RCC_CR_MSIRDY_Pos (9U) 4202 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ 4203 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ 4204 4205 #define RCC_CR_HSEON_Pos (16U) 4206 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 4207 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 4208 #define RCC_CR_HSERDY_Pos (17U) 4209 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 4210 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 4211 #define RCC_CR_HSEBYP_Pos (18U) 4212 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 4213 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 4214 4215 #define RCC_CR_PLLON_Pos (24U) 4216 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 4217 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 4218 #define RCC_CR_PLLRDY_Pos (25U) 4219 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 4220 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 4221 #define RCC_CR_CSSON_Pos (28U) 4222 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x10000000 */ 4223 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 4224 4225 #define RCC_CR_RTCPRE_Pos (29U) 4226 #define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x60000000 */ 4227 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD Prescaler */ 4228 #define RCC_CR_RTCPRE_0 (0x20000000U) /*!< Bit0 */ 4229 #define RCC_CR_RTCPRE_1 (0x40000000U) /*!< Bit1 */ 4230 4231 /******************** Bit definition for RCC_ICSCR register *****************/ 4232 #define RCC_ICSCR_HSICAL_Pos (0U) 4233 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ 4234 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 4235 #define RCC_ICSCR_HSITRIM_Pos (8U) 4236 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ 4237 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 4238 4239 #define RCC_ICSCR_MSIRANGE_Pos (13U) 4240 #define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ 4241 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ 4242 #define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ 4243 #define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ 4244 #define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ 4245 #define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ 4246 #define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ 4247 #define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ 4248 #define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ 4249 #define RCC_ICSCR_MSICAL_Pos (16U) 4250 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ 4251 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ 4252 #define RCC_ICSCR_MSITRIM_Pos (24U) 4253 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ 4254 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ 4255 4256 /******************** Bit definition for RCC_CFGR register ******************/ 4257 #define RCC_CFGR_SW_Pos (0U) 4258 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 4259 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 4260 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 4261 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 4262 4263 /*!< SW configuration */ 4264 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ 4265 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ 4266 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ 4267 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ 4268 4269 #define RCC_CFGR_SWS_Pos (2U) 4270 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 4271 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 4272 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 4273 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 4274 4275 /*!< SWS configuration */ 4276 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ 4277 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ 4278 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ 4279 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ 4280 4281 #define RCC_CFGR_HPRE_Pos (4U) 4282 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 4283 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 4284 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 4285 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 4286 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 4287 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 4288 4289 /*!< HPRE configuration */ 4290 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 4291 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 4292 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 4293 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 4294 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 4295 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 4296 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 4297 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 4298 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 4299 4300 #define RCC_CFGR_PPRE1_Pos (8U) 4301 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 4302 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 4303 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 4304 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 4305 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 4306 4307 /*!< PPRE1 configuration */ 4308 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ 4309 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ 4310 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ 4311 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ 4312 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ 4313 4314 #define RCC_CFGR_PPRE2_Pos (11U) 4315 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 4316 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 4317 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 4318 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 4319 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 4320 4321 /*!< PPRE2 configuration */ 4322 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ 4323 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ 4324 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ 4325 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ 4326 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ 4327 4328 /*!< PLL entry clock source*/ 4329 #define RCC_CFGR_PLLSRC_Pos (16U) 4330 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 4331 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 4332 4333 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ 4334 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ 4335 4336 4337 /*!< PLLMUL configuration */ 4338 #define RCC_CFGR_PLLMUL_Pos (18U) 4339 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 4340 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 4341 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 4342 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 4343 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 4344 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 4345 4346 /*!< PLLMUL configuration */ 4347 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ 4348 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ 4349 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ 4350 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ 4351 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ 4352 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ 4353 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ 4354 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ 4355 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ 4356 4357 /*!< PLLDIV configuration */ 4358 #define RCC_CFGR_PLLDIV_Pos (22U) 4359 #define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ 4360 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ 4361 #define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ 4362 #define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ 4363 4364 4365 /*!< PLLDIV configuration */ 4366 #define RCC_CFGR_PLLDIV1 (0x00000000U) /*!< PLL clock output = CKVCO / 1 */ 4367 #define RCC_CFGR_PLLDIV2_Pos (22U) 4368 #define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ 4369 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ 4370 #define RCC_CFGR_PLLDIV3_Pos (23U) 4371 #define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ 4372 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ 4373 #define RCC_CFGR_PLLDIV4_Pos (22U) 4374 #define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ 4375 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ 4376 4377 4378 #define RCC_CFGR_MCOSEL_Pos (24U) 4379 #define RCC_CFGR_MCOSEL_Msk (0x7U << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */ 4380 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 4381 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 4382 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 4383 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 4384 4385 /*!< MCO configuration */ 4386 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ 4387 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) 4388 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ 4389 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected */ 4390 #define RCC_CFGR_MCOSEL_HSI_Pos (25U) 4391 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ 4392 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ 4393 #define RCC_CFGR_MCOSEL_MSI_Pos (24U) 4394 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ 4395 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ 4396 #define RCC_CFGR_MCOSEL_HSE_Pos (26U) 4397 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ 4398 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ 4399 #define RCC_CFGR_MCOSEL_PLL_Pos (24U) 4400 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ 4401 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ 4402 #define RCC_CFGR_MCOSEL_LSI_Pos (25U) 4403 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ 4404 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ 4405 #define RCC_CFGR_MCOSEL_LSE_Pos (24U) 4406 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ 4407 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ 4408 4409 #define RCC_CFGR_MCOPRE_Pos (28U) 4410 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 4411 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */ 4412 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 4413 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 4414 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 4415 4416 /*!< MCO Prescaler configuration */ 4417 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 4418 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 4419 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 4420 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 4421 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 4422 4423 /* Legacy aliases */ 4424 #define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1 4425 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2 4426 #define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4 4427 #define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8 4428 #define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16 4429 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK 4430 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK 4431 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI 4432 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI 4433 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE 4434 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL 4435 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI 4436 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE 4437 4438 /*!<****************** Bit definition for RCC_CIR register ********************/ 4439 #define RCC_CIR_LSIRDYF_Pos (0U) 4440 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 4441 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 4442 #define RCC_CIR_LSERDYF_Pos (1U) 4443 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 4444 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 4445 #define RCC_CIR_HSIRDYF_Pos (2U) 4446 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 4447 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 4448 #define RCC_CIR_HSERDYF_Pos (3U) 4449 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 4450 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 4451 #define RCC_CIR_PLLRDYF_Pos (4U) 4452 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 4453 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 4454 #define RCC_CIR_MSIRDYF_Pos (5U) 4455 #define RCC_CIR_MSIRDYF_Msk (0x1U << RCC_CIR_MSIRDYF_Pos) /*!< 0x00000020 */ 4456 #define RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ 4457 #define RCC_CIR_LSECSSF_Pos (6U) 4458 #define RCC_CIR_LSECSSF_Msk (0x1U << RCC_CIR_LSECSSF_Pos) /*!< 0x00000040 */ 4459 #define RCC_CIR_LSECSSF RCC_CIR_LSECSSF_Msk /*!< LSE CSS Interrupt flag */ 4460 #define RCC_CIR_CSSF_Pos (7U) 4461 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 4462 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 4463 4464 #define RCC_CIR_LSIRDYIE_Pos (8U) 4465 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 4466 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 4467 #define RCC_CIR_LSERDYIE_Pos (9U) 4468 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 4469 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 4470 #define RCC_CIR_HSIRDYIE_Pos (10U) 4471 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 4472 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 4473 #define RCC_CIR_HSERDYIE_Pos (11U) 4474 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 4475 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 4476 #define RCC_CIR_PLLRDYIE_Pos (12U) 4477 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 4478 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 4479 #define RCC_CIR_MSIRDYIE_Pos (13U) 4480 #define RCC_CIR_MSIRDYIE_Msk (0x1U << RCC_CIR_MSIRDYIE_Pos) /*!< 0x00002000 */ 4481 #define RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ 4482 #define RCC_CIR_LSECSSIE_Pos (14U) 4483 #define RCC_CIR_LSECSSIE_Msk (0x1U << RCC_CIR_LSECSSIE_Pos) /*!< 0x00004000 */ 4484 #define RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE_Msk /*!< LSE CSS Interrupt Enable */ 4485 4486 #define RCC_CIR_LSIRDYC_Pos (16U) 4487 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 4488 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 4489 #define RCC_CIR_LSERDYC_Pos (17U) 4490 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 4491 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 4492 #define RCC_CIR_HSIRDYC_Pos (18U) 4493 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 4494 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 4495 #define RCC_CIR_HSERDYC_Pos (19U) 4496 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 4497 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 4498 #define RCC_CIR_PLLRDYC_Pos (20U) 4499 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 4500 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 4501 #define RCC_CIR_MSIRDYC_Pos (21U) 4502 #define RCC_CIR_MSIRDYC_Msk (0x1U << RCC_CIR_MSIRDYC_Pos) /*!< 0x00200000 */ 4503 #define RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ 4504 #define RCC_CIR_LSECSSC_Pos (22U) 4505 #define RCC_CIR_LSECSSC_Msk (0x1U << RCC_CIR_LSECSSC_Pos) /*!< 0x00400000 */ 4506 #define RCC_CIR_LSECSSC RCC_CIR_LSECSSC_Msk /*!< LSE CSS Interrupt Clear */ 4507 #define RCC_CIR_CSSC_Pos (23U) 4508 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 4509 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 4510 4511 /***************** Bit definition for RCC_AHBRSTR register ******************/ 4512 #define RCC_AHBRSTR_GPIOARST_Pos (0U) 4513 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */ 4514 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIO port A reset */ 4515 #define RCC_AHBRSTR_GPIOBRST_Pos (1U) 4516 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */ 4517 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIO port B reset */ 4518 #define RCC_AHBRSTR_GPIOCRST_Pos (2U) 4519 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */ 4520 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIO port C reset */ 4521 #define RCC_AHBRSTR_GPIODRST_Pos (3U) 4522 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */ 4523 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIO port D reset */ 4524 #define RCC_AHBRSTR_GPIOERST_Pos (4U) 4525 #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */ 4526 #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIO port E reset */ 4527 #define RCC_AHBRSTR_GPIOHRST_Pos (5U) 4528 #define RCC_AHBRSTR_GPIOHRST_Msk (0x1U << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */ 4529 #define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /*!< GPIO port H reset */ 4530 #define RCC_AHBRSTR_GPIOFRST_Pos (6U) 4531 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00000040 */ 4532 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIO port F reset */ 4533 #define RCC_AHBRSTR_GPIOGRST_Pos (7U) 4534 #define RCC_AHBRSTR_GPIOGRST_Msk (0x1U << RCC_AHBRSTR_GPIOGRST_Pos) /*!< 0x00000080 */ 4535 #define RCC_AHBRSTR_GPIOGRST RCC_AHBRSTR_GPIOGRST_Msk /*!< GPIO port G reset */ 4536 #define RCC_AHBRSTR_CRCRST_Pos (12U) 4537 #define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ 4538 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ 4539 #define RCC_AHBRSTR_FLITFRST_Pos (15U) 4540 #define RCC_AHBRSTR_FLITFRST_Msk (0x1U << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */ 4541 #define RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_FLITFRST_Msk /*!< FLITF reset */ 4542 #define RCC_AHBRSTR_DMA1RST_Pos (24U) 4543 #define RCC_AHBRSTR_DMA1RST_Msk (0x1U << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x01000000 */ 4544 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk /*!< DMA1 reset */ 4545 #define RCC_AHBRSTR_DMA2RST_Pos (25U) 4546 #define RCC_AHBRSTR_DMA2RST_Msk (0x1U << RCC_AHBRSTR_DMA2RST_Pos) /*!< 0x02000000 */ 4547 #define RCC_AHBRSTR_DMA2RST RCC_AHBRSTR_DMA2RST_Msk /*!< DMA2 reset */ 4548 4549 /***************** Bit definition for RCC_APB2RSTR register *****************/ 4550 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 4551 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 4552 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< System Configuration SYSCFG reset */ 4553 #define RCC_APB2RSTR_TIM9RST_Pos (2U) 4554 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */ 4555 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */ 4556 #define RCC_APB2RSTR_TIM10RST_Pos (3U) 4557 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */ 4558 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /*!< TIM10 reset */ 4559 #define RCC_APB2RSTR_TIM11RST_Pos (4U) 4560 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */ 4561 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /*!< TIM11 reset */ 4562 #define RCC_APB2RSTR_ADC1RST_Pos (9U) 4563 #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ 4564 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC1 reset */ 4565 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 4566 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 4567 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */ 4568 #define RCC_APB2RSTR_USART1RST_Pos (14U) 4569 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 4570 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 4571 4572 /***************** Bit definition for RCC_APB1RSTR register *****************/ 4573 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 4574 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 4575 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 4576 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 4577 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 4578 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 4579 #define RCC_APB1RSTR_TIM4RST_Pos (2U) 4580 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ 4581 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ 4582 #define RCC_APB1RSTR_TIM5RST_Pos (3U) 4583 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ 4584 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */ 4585 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 4586 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 4587 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 4588 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 4589 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ 4590 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ 4591 #define RCC_APB1RSTR_LCDRST_Pos (9U) 4592 #define RCC_APB1RSTR_LCDRST_Msk (0x1U << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */ 4593 #define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD reset */ 4594 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 4595 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 4596 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 4597 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 4598 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 4599 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ 4600 #define RCC_APB1RSTR_SPI3RST_Pos (15U) 4601 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ 4602 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */ 4603 #define RCC_APB1RSTR_USART2RST_Pos (17U) 4604 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 4605 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 4606 #define RCC_APB1RSTR_USART3RST_Pos (18U) 4607 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ 4608 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ 4609 #define RCC_APB1RSTR_UART4RST_Pos (19U) 4610 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ 4611 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */ 4612 #define RCC_APB1RSTR_UART5RST_Pos (20U) 4613 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ 4614 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */ 4615 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 4616 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 4617 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 4618 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 4619 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 4620 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 4621 #define RCC_APB1RSTR_USBRST_Pos (23U) 4622 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ 4623 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */ 4624 #define RCC_APB1RSTR_PWRRST_Pos (28U) 4625 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 4626 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ 4627 #define RCC_APB1RSTR_DACRST_Pos (29U) 4628 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ 4629 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ 4630 #define RCC_APB1RSTR_COMPRST_Pos (31U) 4631 #define RCC_APB1RSTR_COMPRST_Msk (0x1U << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */ 4632 #define RCC_APB1RSTR_COMPRST RCC_APB1RSTR_COMPRST_Msk /*!< Comparator interface reset */ 4633 4634 /****************** Bit definition for RCC_AHBENR register ******************/ 4635 #define RCC_AHBENR_GPIOAEN_Pos (0U) 4636 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00000001 */ 4637 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIO port A clock enable */ 4638 #define RCC_AHBENR_GPIOBEN_Pos (1U) 4639 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00000002 */ 4640 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIO port B clock enable */ 4641 #define RCC_AHBENR_GPIOCEN_Pos (2U) 4642 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00000004 */ 4643 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIO port C clock enable */ 4644 #define RCC_AHBENR_GPIODEN_Pos (3U) 4645 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00000008 */ 4646 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIO port D clock enable */ 4647 #define RCC_AHBENR_GPIOEEN_Pos (4U) 4648 #define RCC_AHBENR_GPIOEEN_Msk (0x1U << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00000010 */ 4649 #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIO port E clock enable */ 4650 #define RCC_AHBENR_GPIOHEN_Pos (5U) 4651 #define RCC_AHBENR_GPIOHEN_Msk (0x1U << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00000020 */ 4652 #define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /*!< GPIO port H clock enable */ 4653 #define RCC_AHBENR_GPIOFEN_Pos (6U) 4654 #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00000040 */ 4655 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIO port F clock enable */ 4656 #define RCC_AHBENR_GPIOGEN_Pos (7U) 4657 #define RCC_AHBENR_GPIOGEN_Msk (0x1U << RCC_AHBENR_GPIOGEN_Pos) /*!< 0x00000080 */ 4658 #define RCC_AHBENR_GPIOGEN RCC_AHBENR_GPIOGEN_Msk /*!< GPIO port G clock enable */ 4659 #define RCC_AHBENR_CRCEN_Pos (12U) 4660 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ 4661 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 4662 #define RCC_AHBENR_FLITFEN_Pos (15U) 4663 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00008000 */ 4664 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable (has effect only when 4665 the Flash memory is in power down mode) */ 4666 #define RCC_AHBENR_DMA1EN_Pos (24U) 4667 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x01000000 */ 4668 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ 4669 #define RCC_AHBENR_DMA2EN_Pos (25U) 4670 #define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x02000000 */ 4671 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ 4672 4673 /****************** Bit definition for RCC_APB2ENR register *****************/ 4674 #define RCC_APB2ENR_SYSCFGEN_Pos (0U) 4675 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ 4676 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< System Configuration SYSCFG clock enable */ 4677 #define RCC_APB2ENR_TIM9EN_Pos (2U) 4678 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00000004 */ 4679 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 interface clock enable */ 4680 #define RCC_APB2ENR_TIM10EN_Pos (3U) 4681 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00000008 */ 4682 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface clock enable */ 4683 #define RCC_APB2ENR_TIM11EN_Pos (4U) 4684 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00000010 */ 4685 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /*!< TIM11 Timer clock enable */ 4686 #define RCC_APB2ENR_ADC1EN_Pos (9U) 4687 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ 4688 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC1 clock enable */ 4689 #define RCC_APB2ENR_SPI1EN_Pos (12U) 4690 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 4691 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 4692 #define RCC_APB2ENR_USART1EN_Pos (14U) 4693 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 4694 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 4695 4696 /***************** Bit definition for RCC_APB1ENR register ******************/ 4697 #define RCC_APB1ENR_TIM2EN_Pos (0U) 4698 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 4699 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ 4700 #define RCC_APB1ENR_TIM3EN_Pos (1U) 4701 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 4702 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 4703 #define RCC_APB1ENR_TIM4EN_Pos (2U) 4704 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ 4705 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ 4706 #define RCC_APB1ENR_TIM5EN_Pos (3U) 4707 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ 4708 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */ 4709 #define RCC_APB1ENR_TIM6EN_Pos (4U) 4710 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 4711 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 4712 #define RCC_APB1ENR_TIM7EN_Pos (5U) 4713 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ 4714 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ 4715 #define RCC_APB1ENR_LCDEN_Pos (9U) 4716 #define RCC_APB1ENR_LCDEN_Msk (0x1U << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */ 4717 #define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */ 4718 #define RCC_APB1ENR_WWDGEN_Pos (11U) 4719 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 4720 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 4721 #define RCC_APB1ENR_SPI2EN_Pos (14U) 4722 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 4723 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ 4724 #define RCC_APB1ENR_SPI3EN_Pos (15U) 4725 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ 4726 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */ 4727 #define RCC_APB1ENR_USART2EN_Pos (17U) 4728 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 4729 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ 4730 #define RCC_APB1ENR_USART3EN_Pos (18U) 4731 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ 4732 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ 4733 #define RCC_APB1ENR_UART4EN_Pos (19U) 4734 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ 4735 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */ 4736 #define RCC_APB1ENR_UART5EN_Pos (20U) 4737 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ 4738 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */ 4739 #define RCC_APB1ENR_I2C1EN_Pos (21U) 4740 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 4741 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ 4742 #define RCC_APB1ENR_I2C2EN_Pos (22U) 4743 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 4744 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ 4745 #define RCC_APB1ENR_USBEN_Pos (23U) 4746 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ 4747 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */ 4748 #define RCC_APB1ENR_PWREN_Pos (28U) 4749 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 4750 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ 4751 #define RCC_APB1ENR_DACEN_Pos (29U) 4752 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ 4753 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ 4754 #define RCC_APB1ENR_COMPEN_Pos (31U) 4755 #define RCC_APB1ENR_COMPEN_Msk (0x1U << RCC_APB1ENR_COMPEN_Pos) /*!< 0x80000000 */ 4756 #define RCC_APB1ENR_COMPEN RCC_APB1ENR_COMPEN_Msk /*!< Comparator interface clock enable */ 4757 4758 /****************** Bit definition for RCC_AHBLPENR register ****************/ 4759 #define RCC_AHBLPENR_GPIOALPEN_Pos (0U) 4760 #define RCC_AHBLPENR_GPIOALPEN_Msk (0x1U << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ 4761 #define RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOALPEN_Msk /*!< GPIO port A clock enabled in sleep mode */ 4762 #define RCC_AHBLPENR_GPIOBLPEN_Pos (1U) 4763 #define RCC_AHBLPENR_GPIOBLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ 4764 #define RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOBLPEN_Msk /*!< GPIO port B clock enabled in sleep mode */ 4765 #define RCC_AHBLPENR_GPIOCLPEN_Pos (2U) 4766 #define RCC_AHBLPENR_GPIOCLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ 4767 #define RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIOCLPEN_Msk /*!< GPIO port C clock enabled in sleep mode */ 4768 #define RCC_AHBLPENR_GPIODLPEN_Pos (3U) 4769 #define RCC_AHBLPENR_GPIODLPEN_Msk (0x1U << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ 4770 #define RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIODLPEN_Msk /*!< GPIO port D clock enabled in sleep mode */ 4771 #define RCC_AHBLPENR_GPIOELPEN_Pos (4U) 4772 #define RCC_AHBLPENR_GPIOELPEN_Msk (0x1U << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ 4773 #define RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOELPEN_Msk /*!< GPIO port E clock enabled in sleep mode */ 4774 #define RCC_AHBLPENR_GPIOHLPEN_Pos (5U) 4775 #define RCC_AHBLPENR_GPIOHLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */ 4776 #define RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOHLPEN_Msk /*!< GPIO port H clock enabled in sleep mode */ 4777 #define RCC_AHBLPENR_GPIOFLPEN_Pos (6U) 4778 #define RCC_AHBLPENR_GPIOFLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOFLPEN_Pos) /*!< 0x00000040 */ 4779 #define RCC_AHBLPENR_GPIOFLPEN RCC_AHBLPENR_GPIOFLPEN_Msk /*!< GPIO port F clock enabled in sleep mode */ 4780 #define RCC_AHBLPENR_GPIOGLPEN_Pos (7U) 4781 #define RCC_AHBLPENR_GPIOGLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOGLPEN_Pos) /*!< 0x00000080 */ 4782 #define RCC_AHBLPENR_GPIOGLPEN RCC_AHBLPENR_GPIOGLPEN_Msk /*!< GPIO port G clock enabled in sleep mode */ 4783 #define RCC_AHBLPENR_CRCLPEN_Pos (12U) 4784 #define RCC_AHBLPENR_CRCLPEN_Msk (0x1U << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */ 4785 #define RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_CRCLPEN_Msk /*!< CRC clock enabled in sleep mode */ 4786 #define RCC_AHBLPENR_FLITFLPEN_Pos (15U) 4787 #define RCC_AHBLPENR_FLITFLPEN_Msk (0x1U << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */ 4788 #define RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_FLITFLPEN_Msk /*!< Flash Interface clock enabled in sleep mode 4789 (has effect only when the Flash memory is 4790 in power down mode) */ 4791 #define RCC_AHBLPENR_SRAMLPEN_Pos (16U) 4792 #define RCC_AHBLPENR_SRAMLPEN_Msk (0x1U << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */ 4793 #define RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_SRAMLPEN_Msk /*!< SRAM clock enabled in sleep mode */ 4794 #define RCC_AHBLPENR_DMA1LPEN_Pos (24U) 4795 #define RCC_AHBLPENR_DMA1LPEN_Msk (0x1U << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */ 4796 #define RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA1LPEN_Msk /*!< DMA1 clock enabled in sleep mode */ 4797 #define RCC_AHBLPENR_DMA2LPEN_Pos (25U) 4798 #define RCC_AHBLPENR_DMA2LPEN_Msk (0x1U << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */ 4799 #define RCC_AHBLPENR_DMA2LPEN RCC_AHBLPENR_DMA2LPEN_Msk /*!< DMA2 clock enabled in sleep mode */ 4800 4801 /****************** Bit definition for RCC_APB2LPENR register ***************/ 4802 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (0U) 4803 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */ 4804 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk /*!< System Configuration SYSCFG clock enabled in sleep mode */ 4805 #define RCC_APB2LPENR_TIM9LPEN_Pos (2U) 4806 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */ 4807 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 interface clock enabled in sleep mode */ 4808 #define RCC_APB2LPENR_TIM10LPEN_Pos (3U) 4809 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */ 4810 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk /*!< TIM10 interface clock enabled in sleep mode */ 4811 #define RCC_APB2LPENR_TIM11LPEN_Pos (4U) 4812 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */ 4813 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk /*!< TIM11 Timer clock enabled in sleep mode */ 4814 #define RCC_APB2LPENR_ADC1LPEN_Pos (9U) 4815 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */ 4816 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk /*!< ADC1 clock enabled in sleep mode */ 4817 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U) 4818 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ 4819 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enabled in sleep mode */ 4820 #define RCC_APB2LPENR_USART1LPEN_Pos (14U) 4821 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */ 4822 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enabled in sleep mode */ 4823 4824 /***************** Bit definition for RCC_APB1LPENR register ****************/ 4825 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U) 4826 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ 4827 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk /*!< Timer 2 clock enabled in sleep mode */ 4828 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U) 4829 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ 4830 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk /*!< Timer 3 clock enabled in sleep mode */ 4831 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U) 4832 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ 4833 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk /*!< Timer 4 clock enabled in sleep mode */ 4834 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U) 4835 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ 4836 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk /*!< Timer 5 clock enabled in sleep mode */ 4837 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U) 4838 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ 4839 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk /*!< Timer 6 clock enabled in sleep mode */ 4840 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U) 4841 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ 4842 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk /*!< Timer 7 clock enabled in sleep mode */ 4843 #define RCC_APB1LPENR_LCDLPEN_Pos (9U) 4844 #define RCC_APB1LPENR_LCDLPEN_Msk (0x1U << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */ 4845 #define RCC_APB1LPENR_LCDLPEN RCC_APB1LPENR_LCDLPEN_Msk /*!< LCD clock enabled in sleep mode */ 4846 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U) 4847 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ 4848 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ 4849 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U) 4850 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ 4851 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk /*!< SPI 2 clock enabled in sleep mode */ 4852 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U) 4853 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ 4854 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk /*!< SPI 3 clock enabled in sleep mode */ 4855 #define RCC_APB1LPENR_USART2LPEN_Pos (17U) 4856 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */ 4857 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk /*!< USART 2 clock enabled in sleep mode */ 4858 #define RCC_APB1LPENR_USART3LPEN_Pos (18U) 4859 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */ 4860 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk /*!< USART 3 clock enabled in sleep mode */ 4861 #define RCC_APB1LPENR_UART4LPEN_Pos (19U) 4862 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */ 4863 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk /*!< UART 4 clock enabled in sleep mode */ 4864 #define RCC_APB1LPENR_UART5LPEN_Pos (20U) 4865 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */ 4866 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk /*!< UART 5 clock enabled in sleep mode */ 4867 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U) 4868 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ 4869 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk /*!< I2C 1 clock enabled in sleep mode */ 4870 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U) 4871 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ 4872 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk /*!< I2C 2 clock enabled in sleep mode */ 4873 #define RCC_APB1LPENR_USBLPEN_Pos (23U) 4874 #define RCC_APB1LPENR_USBLPEN_Msk (0x1U << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */ 4875 #define RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_USBLPEN_Msk /*!< USB clock enabled in sleep mode */ 4876 #define RCC_APB1LPENR_PWRLPEN_Pos (28U) 4877 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */ 4878 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /*!< Power interface clock enabled in sleep mode */ 4879 #define RCC_APB1LPENR_DACLPEN_Pos (29U) 4880 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */ 4881 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk /*!< DAC interface clock enabled in sleep mode */ 4882 #define RCC_APB1LPENR_COMPLPEN_Pos (31U) 4883 #define RCC_APB1LPENR_COMPLPEN_Msk (0x1U << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */ 4884 #define RCC_APB1LPENR_COMPLPEN RCC_APB1LPENR_COMPLPEN_Msk /*!< Comparator interface clock enabled in sleep mode*/ 4885 4886 /******************* Bit definition for RCC_CSR register ********************/ 4887 #define RCC_CSR_LSION_Pos (0U) 4888 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 4889 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 4890 #define RCC_CSR_LSIRDY_Pos (1U) 4891 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 4892 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 4893 4894 #define RCC_CSR_LSEON_Pos (8U) 4895 #define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ 4896 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ 4897 #define RCC_CSR_LSERDY_Pos (9U) 4898 #define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ 4899 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 4900 #define RCC_CSR_LSEBYP_Pos (10U) 4901 #define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ 4902 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 4903 4904 #define RCC_CSR_LSECSSON_Pos (11U) 4905 #define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00000800 */ 4906 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ 4907 #define RCC_CSR_LSECSSD_Pos (12U) 4908 #define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00001000 */ 4909 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ 4910 4911 #define RCC_CSR_RTCSEL_Pos (16U) 4912 #define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ 4913 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 4914 #define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ 4915 #define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ 4916 4917 /*!< RTC congiguration */ 4918 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 4919 #define RCC_CSR_RTCSEL_LSE_Pos (16U) 4920 #define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ 4921 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ 4922 #define RCC_CSR_RTCSEL_LSI_Pos (17U) 4923 #define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ 4924 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ 4925 #define RCC_CSR_RTCSEL_HSE_Pos (16U) 4926 #define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ 4927 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */ 4928 4929 #define RCC_CSR_RTCEN_Pos (22U) 4930 #define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00400000 */ 4931 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ 4932 #define RCC_CSR_RTCRST_Pos (23U) 4933 #define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00800000 */ 4934 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC reset */ 4935 4936 #define RCC_CSR_RMVF_Pos (24U) 4937 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 4938 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 4939 #define RCC_CSR_OBLRSTF_Pos (25U) 4940 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 4941 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< Option Bytes Loader reset flag */ 4942 #define RCC_CSR_PINRSTF_Pos (26U) 4943 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 4944 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 4945 #define RCC_CSR_PORRSTF_Pos (27U) 4946 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 4947 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 4948 #define RCC_CSR_SFTRSTF_Pos (28U) 4949 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 4950 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 4951 #define RCC_CSR_IWDGRSTF_Pos (29U) 4952 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 4953 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 4954 #define RCC_CSR_WWDGRSTF_Pos (30U) 4955 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 4956 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 4957 #define RCC_CSR_LPWRRSTF_Pos (31U) 4958 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 4959 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 4960 4961 /******************************************************************************/ 4962 /* */ 4963 /* Real-Time Clock (RTC) */ 4964 /* */ 4965 /******************************************************************************/ 4966 /* 4967 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie) 4968 */ 4969 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */ 4970 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ 4971 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */ 4972 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */ 4973 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */ 4974 #define RTC_SMOOTHCALIB_SUPPORT /*!< Smooth digital calibration feature support */ 4975 #define RTC_SUBSECOND_SUPPORT /*!< Sub-second feature support */ 4976 4977 /******************** Bits definition for RTC_TR register *******************/ 4978 #define RTC_TR_PM_Pos (22U) 4979 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ 4980 #define RTC_TR_PM RTC_TR_PM_Msk 4981 #define RTC_TR_HT_Pos (20U) 4982 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ 4983 #define RTC_TR_HT RTC_TR_HT_Msk 4984 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ 4985 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ 4986 #define RTC_TR_HU_Pos (16U) 4987 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 4988 #define RTC_TR_HU RTC_TR_HU_Msk 4989 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ 4990 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ 4991 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ 4992 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ 4993 #define RTC_TR_MNT_Pos (12U) 4994 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 4995 #define RTC_TR_MNT RTC_TR_MNT_Msk 4996 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 4997 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 4998 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 4999 #define RTC_TR_MNU_Pos (8U) 5000 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 5001 #define RTC_TR_MNU RTC_TR_MNU_Msk 5002 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 5003 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 5004 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 5005 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 5006 #define RTC_TR_ST_Pos (4U) 5007 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ 5008 #define RTC_TR_ST RTC_TR_ST_Msk 5009 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ 5010 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ 5011 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ 5012 #define RTC_TR_SU_Pos (0U) 5013 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ 5014 #define RTC_TR_SU RTC_TR_SU_Msk 5015 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ 5016 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ 5017 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ 5018 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ 5019 5020 /******************** Bits definition for RTC_DR register *******************/ 5021 #define RTC_DR_YT_Pos (20U) 5022 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 5023 #define RTC_DR_YT RTC_DR_YT_Msk 5024 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ 5025 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ 5026 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ 5027 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ 5028 #define RTC_DR_YU_Pos (16U) 5029 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 5030 #define RTC_DR_YU RTC_DR_YU_Msk 5031 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ 5032 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ 5033 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ 5034 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ 5035 #define RTC_DR_WDU_Pos (13U) 5036 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 5037 #define RTC_DR_WDU RTC_DR_WDU_Msk 5038 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 5039 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 5040 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 5041 #define RTC_DR_MT_Pos (12U) 5042 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ 5043 #define RTC_DR_MT RTC_DR_MT_Msk 5044 #define RTC_DR_MU_Pos (8U) 5045 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 5046 #define RTC_DR_MU RTC_DR_MU_Msk 5047 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ 5048 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ 5049 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ 5050 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ 5051 #define RTC_DR_DT_Pos (4U) 5052 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ 5053 #define RTC_DR_DT RTC_DR_DT_Msk 5054 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ 5055 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ 5056 #define RTC_DR_DU_Pos (0U) 5057 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ 5058 #define RTC_DR_DU RTC_DR_DU_Msk 5059 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ 5060 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ 5061 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ 5062 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ 5063 5064 /******************** Bits definition for RTC_CR register *******************/ 5065 #define RTC_CR_COE_Pos (23U) 5066 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ 5067 #define RTC_CR_COE RTC_CR_COE_Msk 5068 #define RTC_CR_OSEL_Pos (21U) 5069 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 5070 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 5071 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 5072 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 5073 #define RTC_CR_POL_Pos (20U) 5074 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ 5075 #define RTC_CR_POL RTC_CR_POL_Msk 5076 #define RTC_CR_COSEL_Pos (19U) 5077 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 5078 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 5079 #define RTC_CR_BKP_Pos (18U) 5080 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 5081 #define RTC_CR_BKP RTC_CR_BKP_Msk 5082 #define RTC_CR_SUB1H_Pos (17U) 5083 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 5084 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 5085 #define RTC_CR_ADD1H_Pos (16U) 5086 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 5087 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 5088 #define RTC_CR_TSIE_Pos (15U) 5089 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 5090 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 5091 #define RTC_CR_WUTIE_Pos (14U) 5092 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 5093 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 5094 #define RTC_CR_ALRBIE_Pos (13U) 5095 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 5096 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 5097 #define RTC_CR_ALRAIE_Pos (12U) 5098 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 5099 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 5100 #define RTC_CR_TSE_Pos (11U) 5101 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 5102 #define RTC_CR_TSE RTC_CR_TSE_Msk 5103 #define RTC_CR_WUTE_Pos (10U) 5104 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 5105 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 5106 #define RTC_CR_ALRBE_Pos (9U) 5107 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 5108 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 5109 #define RTC_CR_ALRAE_Pos (8U) 5110 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 5111 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 5112 #define RTC_CR_DCE_Pos (7U) 5113 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */ 5114 #define RTC_CR_DCE RTC_CR_DCE_Msk 5115 #define RTC_CR_FMT_Pos (6U) 5116 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 5117 #define RTC_CR_FMT RTC_CR_FMT_Msk 5118 #define RTC_CR_BYPSHAD_Pos (5U) 5119 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 5120 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 5121 #define RTC_CR_REFCKON_Pos (4U) 5122 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 5123 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 5124 #define RTC_CR_TSEDGE_Pos (3U) 5125 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 5126 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 5127 #define RTC_CR_WUCKSEL_Pos (0U) 5128 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 5129 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 5130 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 5131 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 5132 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 5133 5134 /* Legacy defines */ 5135 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos 5136 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk 5137 #define RTC_CR_BCK RTC_CR_BKP 5138 5139 /******************** Bits definition for RTC_ISR register ******************/ 5140 #define RTC_ISR_RECALPF_Pos (16U) 5141 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 5142 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk 5143 #define RTC_ISR_TAMP3F_Pos (15U) 5144 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ 5145 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk 5146 #define RTC_ISR_TAMP2F_Pos (14U) 5147 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 5148 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk 5149 #define RTC_ISR_TAMP1F_Pos (13U) 5150 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 5151 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 5152 #define RTC_ISR_TSOVF_Pos (12U) 5153 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 5154 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 5155 #define RTC_ISR_TSF_Pos (11U) 5156 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 5157 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 5158 #define RTC_ISR_WUTF_Pos (10U) 5159 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 5160 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk 5161 #define RTC_ISR_ALRBF_Pos (9U) 5162 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 5163 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk 5164 #define RTC_ISR_ALRAF_Pos (8U) 5165 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 5166 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 5167 #define RTC_ISR_INIT_Pos (7U) 5168 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 5169 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 5170 #define RTC_ISR_INITF_Pos (6U) 5171 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 5172 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 5173 #define RTC_ISR_RSF_Pos (5U) 5174 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 5175 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 5176 #define RTC_ISR_INITS_Pos (4U) 5177 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 5178 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 5179 #define RTC_ISR_SHPF_Pos (3U) 5180 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 5181 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk 5182 #define RTC_ISR_WUTWF_Pos (2U) 5183 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 5184 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk 5185 #define RTC_ISR_ALRBWF_Pos (1U) 5186 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 5187 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk 5188 #define RTC_ISR_ALRAWF_Pos (0U) 5189 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 5190 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 5191 5192 /******************** Bits definition for RTC_PRER register *****************/ 5193 #define RTC_PRER_PREDIV_A_Pos (16U) 5194 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 5195 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 5196 #define RTC_PRER_PREDIV_S_Pos (0U) 5197 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 5198 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 5199 5200 /******************** Bits definition for RTC_WUTR register *****************/ 5201 #define RTC_WUTR_WUT_Pos (0U) 5202 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 5203 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 5204 5205 /******************** Bits definition for RTC_CALIBR register ***************/ 5206 #define RTC_CALIBR_DCS_Pos (7U) 5207 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */ 5208 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk 5209 #define RTC_CALIBR_DC_Pos (0U) 5210 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */ 5211 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk 5212 5213 /******************** Bits definition for RTC_ALRMAR register ***************/ 5214 #define RTC_ALRMAR_MSK4_Pos (31U) 5215 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 5216 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 5217 #define RTC_ALRMAR_WDSEL_Pos (30U) 5218 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 5219 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 5220 #define RTC_ALRMAR_DT_Pos (28U) 5221 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 5222 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 5223 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 5224 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 5225 #define RTC_ALRMAR_DU_Pos (24U) 5226 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 5227 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 5228 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 5229 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 5230 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 5231 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 5232 #define RTC_ALRMAR_MSK3_Pos (23U) 5233 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 5234 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 5235 #define RTC_ALRMAR_PM_Pos (22U) 5236 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 5237 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 5238 #define RTC_ALRMAR_HT_Pos (20U) 5239 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 5240 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 5241 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 5242 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 5243 #define RTC_ALRMAR_HU_Pos (16U) 5244 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 5245 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 5246 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 5247 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 5248 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 5249 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 5250 #define RTC_ALRMAR_MSK2_Pos (15U) 5251 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 5252 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 5253 #define RTC_ALRMAR_MNT_Pos (12U) 5254 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 5255 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 5256 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 5257 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 5258 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 5259 #define RTC_ALRMAR_MNU_Pos (8U) 5260 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 5261 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 5262 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 5263 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 5264 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 5265 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 5266 #define RTC_ALRMAR_MSK1_Pos (7U) 5267 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 5268 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 5269 #define RTC_ALRMAR_ST_Pos (4U) 5270 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 5271 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 5272 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 5273 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 5274 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 5275 #define RTC_ALRMAR_SU_Pos (0U) 5276 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 5277 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 5278 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 5279 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 5280 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 5281 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 5282 5283 /******************** Bits definition for RTC_ALRMBR register ***************/ 5284 #define RTC_ALRMBR_MSK4_Pos (31U) 5285 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 5286 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 5287 #define RTC_ALRMBR_WDSEL_Pos (30U) 5288 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 5289 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 5290 #define RTC_ALRMBR_DT_Pos (28U) 5291 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 5292 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 5293 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 5294 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 5295 #define RTC_ALRMBR_DU_Pos (24U) 5296 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 5297 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 5298 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 5299 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 5300 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 5301 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 5302 #define RTC_ALRMBR_MSK3_Pos (23U) 5303 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 5304 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 5305 #define RTC_ALRMBR_PM_Pos (22U) 5306 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 5307 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 5308 #define RTC_ALRMBR_HT_Pos (20U) 5309 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 5310 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 5311 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 5312 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 5313 #define RTC_ALRMBR_HU_Pos (16U) 5314 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 5315 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 5316 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 5317 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 5318 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 5319 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 5320 #define RTC_ALRMBR_MSK2_Pos (15U) 5321 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 5322 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 5323 #define RTC_ALRMBR_MNT_Pos (12U) 5324 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 5325 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 5326 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 5327 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 5328 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 5329 #define RTC_ALRMBR_MNU_Pos (8U) 5330 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 5331 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 5332 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 5333 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 5334 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 5335 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 5336 #define RTC_ALRMBR_MSK1_Pos (7U) 5337 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 5338 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 5339 #define RTC_ALRMBR_ST_Pos (4U) 5340 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 5341 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 5342 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 5343 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 5344 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 5345 #define RTC_ALRMBR_SU_Pos (0U) 5346 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 5347 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 5348 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 5349 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 5350 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 5351 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 5352 5353 /******************** Bits definition for RTC_WPR register ******************/ 5354 #define RTC_WPR_KEY_Pos (0U) 5355 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 5356 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 5357 5358 /******************** Bits definition for RTC_SSR register ******************/ 5359 #define RTC_SSR_SS_Pos (0U) 5360 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 5361 #define RTC_SSR_SS RTC_SSR_SS_Msk 5362 5363 /******************** Bits definition for RTC_SHIFTR register ***************/ 5364 #define RTC_SHIFTR_SUBFS_Pos (0U) 5365 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 5366 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 5367 #define RTC_SHIFTR_ADD1S_Pos (31U) 5368 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 5369 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 5370 5371 /******************** Bits definition for RTC_TSTR register *****************/ 5372 #define RTC_TSTR_PM_Pos (22U) 5373 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 5374 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 5375 #define RTC_TSTR_HT_Pos (20U) 5376 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 5377 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 5378 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 5379 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 5380 #define RTC_TSTR_HU_Pos (16U) 5381 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 5382 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 5383 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 5384 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 5385 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 5386 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 5387 #define RTC_TSTR_MNT_Pos (12U) 5388 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 5389 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 5390 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 5391 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 5392 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 5393 #define RTC_TSTR_MNU_Pos (8U) 5394 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 5395 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 5396 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 5397 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 5398 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 5399 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 5400 #define RTC_TSTR_ST_Pos (4U) 5401 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 5402 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 5403 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 5404 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 5405 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 5406 #define RTC_TSTR_SU_Pos (0U) 5407 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 5408 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 5409 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 5410 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 5411 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 5412 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 5413 5414 /******************** Bits definition for RTC_TSDR register *****************/ 5415 #define RTC_TSDR_WDU_Pos (13U) 5416 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 5417 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 5418 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 5419 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 5420 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 5421 #define RTC_TSDR_MT_Pos (12U) 5422 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 5423 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 5424 #define RTC_TSDR_MU_Pos (8U) 5425 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 5426 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 5427 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 5428 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 5429 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 5430 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 5431 #define RTC_TSDR_DT_Pos (4U) 5432 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 5433 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 5434 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 5435 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 5436 #define RTC_TSDR_DU_Pos (0U) 5437 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 5438 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 5439 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 5440 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 5441 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 5442 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 5443 5444 /******************** Bits definition for RTC_TSSSR register ****************/ 5445 #define RTC_TSSSR_SS_Pos (0U) 5446 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 5447 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 5448 5449 /******************** Bits definition for RTC_CAL register *****************/ 5450 #define RTC_CALR_CALP_Pos (15U) 5451 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 5452 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 5453 #define RTC_CALR_CALW8_Pos (14U) 5454 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 5455 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 5456 #define RTC_CALR_CALW16_Pos (13U) 5457 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 5458 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 5459 #define RTC_CALR_CALM_Pos (0U) 5460 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 5461 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 5462 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 5463 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 5464 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 5465 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 5466 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 5467 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 5468 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 5469 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 5470 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 5471 5472 /******************** Bits definition for RTC_TAFCR register ****************/ 5473 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U) 5474 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */ 5475 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk 5476 #define RTC_TAFCR_TAMPPUDIS_Pos (15U) 5477 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 5478 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk 5479 #define RTC_TAFCR_TAMPPRCH_Pos (13U) 5480 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 5481 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk 5482 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 5483 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 5484 #define RTC_TAFCR_TAMPFLT_Pos (11U) 5485 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ 5486 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk 5487 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ 5488 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ 5489 #define RTC_TAFCR_TAMPFREQ_Pos (8U) 5490 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 5491 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk 5492 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 5493 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 5494 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 5495 #define RTC_TAFCR_TAMPTS_Pos (7U) 5496 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ 5497 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk 5498 #define RTC_TAFCR_TAMP3TRG_Pos (6U) 5499 #define RTC_TAFCR_TAMP3TRG_Msk (0x1U << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */ 5500 #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk 5501 #define RTC_TAFCR_TAMP3E_Pos (5U) 5502 #define RTC_TAFCR_TAMP3E_Msk (0x1U << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */ 5503 #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk 5504 #define RTC_TAFCR_TAMP2TRG_Pos (4U) 5505 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 5506 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk 5507 #define RTC_TAFCR_TAMP2E_Pos (3U) 5508 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ 5509 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk 5510 #define RTC_TAFCR_TAMPIE_Pos (2U) 5511 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ 5512 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk 5513 #define RTC_TAFCR_TAMP1TRG_Pos (1U) 5514 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 5515 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk 5516 #define RTC_TAFCR_TAMP1E_Pos (0U) 5517 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ 5518 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk 5519 5520 /******************** Bits definition for RTC_ALRMASSR register *************/ 5521 #define RTC_ALRMASSR_MASKSS_Pos (24U) 5522 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 5523 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 5524 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 5525 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 5526 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 5527 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 5528 #define RTC_ALRMASSR_SS_Pos (0U) 5529 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 5530 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 5531 5532 /******************** Bits definition for RTC_ALRMBSSR register *************/ 5533 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 5534 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 5535 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 5536 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 5537 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 5538 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 5539 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 5540 #define RTC_ALRMBSSR_SS_Pos (0U) 5541 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 5542 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 5543 5544 /******************** Bits definition for RTC_BKP0R register ****************/ 5545 #define RTC_BKP0R_Pos (0U) 5546 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 5547 #define RTC_BKP0R RTC_BKP0R_Msk 5548 5549 /******************** Bits definition for RTC_BKP1R register ****************/ 5550 #define RTC_BKP1R_Pos (0U) 5551 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 5552 #define RTC_BKP1R RTC_BKP1R_Msk 5553 5554 /******************** Bits definition for RTC_BKP2R register ****************/ 5555 #define RTC_BKP2R_Pos (0U) 5556 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 5557 #define RTC_BKP2R RTC_BKP2R_Msk 5558 5559 /******************** Bits definition for RTC_BKP3R register ****************/ 5560 #define RTC_BKP3R_Pos (0U) 5561 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 5562 #define RTC_BKP3R RTC_BKP3R_Msk 5563 5564 /******************** Bits definition for RTC_BKP4R register ****************/ 5565 #define RTC_BKP4R_Pos (0U) 5566 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 5567 #define RTC_BKP4R RTC_BKP4R_Msk 5568 5569 /******************** Bits definition for RTC_BKP5R register ****************/ 5570 #define RTC_BKP5R_Pos (0U) 5571 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ 5572 #define RTC_BKP5R RTC_BKP5R_Msk 5573 5574 /******************** Bits definition for RTC_BKP6R register ****************/ 5575 #define RTC_BKP6R_Pos (0U) 5576 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ 5577 #define RTC_BKP6R RTC_BKP6R_Msk 5578 5579 /******************** Bits definition for RTC_BKP7R register ****************/ 5580 #define RTC_BKP7R_Pos (0U) 5581 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ 5582 #define RTC_BKP7R RTC_BKP7R_Msk 5583 5584 /******************** Bits definition for RTC_BKP8R register ****************/ 5585 #define RTC_BKP8R_Pos (0U) 5586 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ 5587 #define RTC_BKP8R RTC_BKP8R_Msk 5588 5589 /******************** Bits definition for RTC_BKP9R register ****************/ 5590 #define RTC_BKP9R_Pos (0U) 5591 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ 5592 #define RTC_BKP9R RTC_BKP9R_Msk 5593 5594 /******************** Bits definition for RTC_BKP10R register ***************/ 5595 #define RTC_BKP10R_Pos (0U) 5596 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ 5597 #define RTC_BKP10R RTC_BKP10R_Msk 5598 5599 /******************** Bits definition for RTC_BKP11R register ***************/ 5600 #define RTC_BKP11R_Pos (0U) 5601 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ 5602 #define RTC_BKP11R RTC_BKP11R_Msk 5603 5604 /******************** Bits definition for RTC_BKP12R register ***************/ 5605 #define RTC_BKP12R_Pos (0U) 5606 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ 5607 #define RTC_BKP12R RTC_BKP12R_Msk 5608 5609 /******************** Bits definition for RTC_BKP13R register ***************/ 5610 #define RTC_BKP13R_Pos (0U) 5611 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ 5612 #define RTC_BKP13R RTC_BKP13R_Msk 5613 5614 /******************** Bits definition for RTC_BKP14R register ***************/ 5615 #define RTC_BKP14R_Pos (0U) 5616 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ 5617 #define RTC_BKP14R RTC_BKP14R_Msk 5618 5619 /******************** Bits definition for RTC_BKP15R register ***************/ 5620 #define RTC_BKP15R_Pos (0U) 5621 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ 5622 #define RTC_BKP15R RTC_BKP15R_Msk 5623 5624 /******************** Bits definition for RTC_BKP16R register ***************/ 5625 #define RTC_BKP16R_Pos (0U) 5626 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ 5627 #define RTC_BKP16R RTC_BKP16R_Msk 5628 5629 /******************** Bits definition for RTC_BKP17R register ***************/ 5630 #define RTC_BKP17R_Pos (0U) 5631 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ 5632 #define RTC_BKP17R RTC_BKP17R_Msk 5633 5634 /******************** Bits definition for RTC_BKP18R register ***************/ 5635 #define RTC_BKP18R_Pos (0U) 5636 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ 5637 #define RTC_BKP18R RTC_BKP18R_Msk 5638 5639 /******************** Bits definition for RTC_BKP19R register ***************/ 5640 #define RTC_BKP19R_Pos (0U) 5641 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ 5642 #define RTC_BKP19R RTC_BKP19R_Msk 5643 5644 /******************** Bits definition for RTC_BKP20R register ***************/ 5645 #define RTC_BKP20R_Pos (0U) 5646 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */ 5647 #define RTC_BKP20R RTC_BKP20R_Msk 5648 5649 /******************** Bits definition for RTC_BKP21R register ***************/ 5650 #define RTC_BKP21R_Pos (0U) 5651 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */ 5652 #define RTC_BKP21R RTC_BKP21R_Msk 5653 5654 /******************** Bits definition for RTC_BKP22R register ***************/ 5655 #define RTC_BKP22R_Pos (0U) 5656 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */ 5657 #define RTC_BKP22R RTC_BKP22R_Msk 5658 5659 /******************** Bits definition for RTC_BKP23R register ***************/ 5660 #define RTC_BKP23R_Pos (0U) 5661 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */ 5662 #define RTC_BKP23R RTC_BKP23R_Msk 5663 5664 /******************** Bits definition for RTC_BKP24R register ***************/ 5665 #define RTC_BKP24R_Pos (0U) 5666 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */ 5667 #define RTC_BKP24R RTC_BKP24R_Msk 5668 5669 /******************** Bits definition for RTC_BKP25R register ***************/ 5670 #define RTC_BKP25R_Pos (0U) 5671 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */ 5672 #define RTC_BKP25R RTC_BKP25R_Msk 5673 5674 /******************** Bits definition for RTC_BKP26R register ***************/ 5675 #define RTC_BKP26R_Pos (0U) 5676 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */ 5677 #define RTC_BKP26R RTC_BKP26R_Msk 5678 5679 /******************** Bits definition for RTC_BKP27R register ***************/ 5680 #define RTC_BKP27R_Pos (0U) 5681 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */ 5682 #define RTC_BKP27R RTC_BKP27R_Msk 5683 5684 /******************** Bits definition for RTC_BKP28R register ***************/ 5685 #define RTC_BKP28R_Pos (0U) 5686 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */ 5687 #define RTC_BKP28R RTC_BKP28R_Msk 5688 5689 /******************** Bits definition for RTC_BKP29R register ***************/ 5690 #define RTC_BKP29R_Pos (0U) 5691 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */ 5692 #define RTC_BKP29R RTC_BKP29R_Msk 5693 5694 /******************** Bits definition for RTC_BKP30R register ***************/ 5695 #define RTC_BKP30R_Pos (0U) 5696 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */ 5697 #define RTC_BKP30R RTC_BKP30R_Msk 5698 5699 /******************** Bits definition for RTC_BKP31R register ***************/ 5700 #define RTC_BKP31R_Pos (0U) 5701 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */ 5702 #define RTC_BKP31R RTC_BKP31R_Msk 5703 5704 /******************** Number of backup registers ******************************/ 5705 #define RTC_BKP_NUMBER 32 5706 5707 /******************************************************************************/ 5708 /* */ 5709 /* Serial Peripheral Interface (SPI) */ 5710 /* */ 5711 /******************************************************************************/ 5712 5713 /* 5714 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie) 5715 */ 5716 #define SPI_I2S_SUPPORT 5717 5718 /******************* Bit definition for SPI_CR1 register ********************/ 5719 #define SPI_CR1_CPHA_Pos (0U) 5720 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 5721 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 5722 #define SPI_CR1_CPOL_Pos (1U) 5723 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 5724 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 5725 #define SPI_CR1_MSTR_Pos (2U) 5726 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 5727 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 5728 5729 #define SPI_CR1_BR_Pos (3U) 5730 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 5731 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 5732 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 5733 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 5734 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 5735 5736 #define SPI_CR1_SPE_Pos (6U) 5737 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 5738 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 5739 #define SPI_CR1_LSBFIRST_Pos (7U) 5740 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 5741 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 5742 #define SPI_CR1_SSI_Pos (8U) 5743 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 5744 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 5745 #define SPI_CR1_SSM_Pos (9U) 5746 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 5747 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 5748 #define SPI_CR1_RXONLY_Pos (10U) 5749 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 5750 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 5751 #define SPI_CR1_DFF_Pos (11U) 5752 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 5753 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ 5754 #define SPI_CR1_CRCNEXT_Pos (12U) 5755 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 5756 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 5757 #define SPI_CR1_CRCEN_Pos (13U) 5758 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 5759 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 5760 #define SPI_CR1_BIDIOE_Pos (14U) 5761 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 5762 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 5763 #define SPI_CR1_BIDIMODE_Pos (15U) 5764 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 5765 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 5766 5767 /******************* Bit definition for SPI_CR2 register ********************/ 5768 #define SPI_CR2_RXDMAEN_Pos (0U) 5769 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 5770 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 5771 #define SPI_CR2_TXDMAEN_Pos (1U) 5772 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 5773 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 5774 #define SPI_CR2_SSOE_Pos (2U) 5775 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 5776 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 5777 #define SPI_CR2_FRF_Pos (4U) 5778 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 5779 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame format */ 5780 #define SPI_CR2_ERRIE_Pos (5U) 5781 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 5782 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 5783 #define SPI_CR2_RXNEIE_Pos (6U) 5784 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 5785 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 5786 #define SPI_CR2_TXEIE_Pos (7U) 5787 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 5788 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 5789 5790 /******************** Bit definition for SPI_SR register ********************/ 5791 #define SPI_SR_RXNE_Pos (0U) 5792 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 5793 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 5794 #define SPI_SR_TXE_Pos (1U) 5795 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 5796 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 5797 #define SPI_SR_CHSIDE_Pos (2U) 5798 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 5799 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 5800 #define SPI_SR_UDR_Pos (3U) 5801 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 5802 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 5803 #define SPI_SR_CRCERR_Pos (4U) 5804 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 5805 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 5806 #define SPI_SR_MODF_Pos (5U) 5807 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 5808 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 5809 #define SPI_SR_OVR_Pos (6U) 5810 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 5811 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 5812 #define SPI_SR_BSY_Pos (7U) 5813 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 5814 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 5815 #define SPI_SR_FRE_Pos (8U) 5816 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 5817 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */ 5818 5819 /******************** Bit definition for SPI_DR register ********************/ 5820 #define SPI_DR_DR_Pos (0U) 5821 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 5822 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 5823 5824 /******************* Bit definition for SPI_CRCPR register ******************/ 5825 #define SPI_CRCPR_CRCPOLY_Pos (0U) 5826 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 5827 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 5828 5829 /****************** Bit definition for SPI_RXCRCR register ******************/ 5830 #define SPI_RXCRCR_RXCRC_Pos (0U) 5831 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 5832 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 5833 5834 /****************** Bit definition for SPI_TXCRCR register ******************/ 5835 #define SPI_TXCRCR_TXCRC_Pos (0U) 5836 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 5837 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 5838 5839 /****************** Bit definition for SPI_I2SCFGR register *****************/ 5840 #define SPI_I2SCFGR_CHLEN_Pos (0U) 5841 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 5842 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 5843 5844 #define SPI_I2SCFGR_DATLEN_Pos (1U) 5845 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 5846 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 5847 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 5848 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 5849 5850 #define SPI_I2SCFGR_CKPOL_Pos (3U) 5851 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 5852 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 5853 5854 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 5855 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 5856 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 5857 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 5858 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 5859 5860 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 5861 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 5862 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 5863 5864 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 5865 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 5866 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 5867 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 5868 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 5869 5870 #define SPI_I2SCFGR_I2SE_Pos (10U) 5871 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 5872 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 5873 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 5874 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 5875 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 5876 5877 /****************** Bit definition for SPI_I2SPR register *******************/ 5878 #define SPI_I2SPR_I2SDIV_Pos (0U) 5879 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 5880 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 5881 #define SPI_I2SPR_ODD_Pos (8U) 5882 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 5883 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 5884 #define SPI_I2SPR_MCKOE_Pos (9U) 5885 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 5886 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 5887 5888 /******************************************************************************/ 5889 /* */ 5890 /* System Configuration (SYSCFG) */ 5891 /* */ 5892 /******************************************************************************/ 5893 /***************** Bit definition for SYSCFG_MEMRMP register ****************/ 5894 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) 5895 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */ 5896 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 5897 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ 5898 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ 5899 #define SYSCFG_MEMRMP_BOOT_MODE_Pos (8U) 5900 #define SYSCFG_MEMRMP_BOOT_MODE_Msk (0x3U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000300 */ 5901 #define SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_Msk /*!< Boot mode Config */ 5902 #define SYSCFG_MEMRMP_BOOT_MODE_0 (0x1U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000100 */ 5903 #define SYSCFG_MEMRMP_BOOT_MODE_1 (0x2U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000200 */ 5904 5905 /***************** Bit definition for SYSCFG_PMC register *******************/ 5906 #define SYSCFG_PMC_USB_PU_Pos (0U) 5907 #define SYSCFG_PMC_USB_PU_Msk (0x1U << SYSCFG_PMC_USB_PU_Pos) /*!< 0x00000001 */ 5908 #define SYSCFG_PMC_USB_PU SYSCFG_PMC_USB_PU_Msk /*!< SYSCFG PMC */ 5909 #define SYSCFG_PMC_LCD_CAPA_Pos (1U) 5910 #define SYSCFG_PMC_LCD_CAPA_Msk (0x1FU << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x0000003E */ 5911 #define SYSCFG_PMC_LCD_CAPA SYSCFG_PMC_LCD_CAPA_Msk /*!< LCD_CAPA decoupling capacitance connection */ 5912 #define SYSCFG_PMC_LCD_CAPA_0 (0x01U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000002 */ 5913 #define SYSCFG_PMC_LCD_CAPA_1 (0x02U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000004 */ 5914 #define SYSCFG_PMC_LCD_CAPA_2 (0x04U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000008 */ 5915 #define SYSCFG_PMC_LCD_CAPA_3 (0x08U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000010 */ 5916 #define SYSCFG_PMC_LCD_CAPA_4 (0x10U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000020 */ 5917 5918 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 5919 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 5920 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 5921 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 5922 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 5923 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 5924 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 5925 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 5926 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 5927 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 5928 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 5929 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 5930 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 5931 5932 /** 5933 * @brief EXTI0 configuration 5934 */ 5935 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 5936 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 5937 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 5938 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 5939 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */ 5940 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */ 5941 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */ 5942 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */ 5943 5944 /** 5945 * @brief EXTI1 configuration 5946 */ 5947 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 5948 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 5949 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 5950 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 5951 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */ 5952 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */ 5953 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */ 5954 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */ 5955 5956 /** 5957 * @brief EXTI2 configuration 5958 */ 5959 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 5960 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 5961 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 5962 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 5963 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */ 5964 #define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */ 5965 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */ 5966 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */ 5967 5968 /** 5969 * @brief EXTI3 configuration 5970 */ 5971 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 5972 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 5973 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 5974 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 5975 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ 5976 #define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */ 5977 #define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */ 5978 5979 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ 5980 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 5981 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 5982 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 5983 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 5984 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 5985 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 5986 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 5987 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 5988 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 5989 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 5990 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 5991 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 5992 5993 /** 5994 * @brief EXTI4 configuration 5995 */ 5996 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 5997 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 5998 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 5999 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 6000 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */ 6001 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */ 6002 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */ 6003 6004 /** 6005 * @brief EXTI5 configuration 6006 */ 6007 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 6008 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 6009 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 6010 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 6011 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */ 6012 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */ 6013 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */ 6014 6015 /** 6016 * @brief EXTI6 configuration 6017 */ 6018 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 6019 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 6020 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 6021 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 6022 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */ 6023 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */ 6024 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */ 6025 6026 /** 6027 * @brief EXTI7 configuration 6028 */ 6029 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 6030 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 6031 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 6032 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 6033 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */ 6034 #define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */ 6035 #define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */ 6036 6037 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ 6038 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 6039 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 6040 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 6041 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 6042 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 6043 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 6044 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 6045 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 6046 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 6047 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 6048 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 6049 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 6050 6051 /** 6052 * @brief EXTI8 configuration 6053 */ 6054 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 6055 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 6056 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 6057 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 6058 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */ 6059 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */ 6060 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */ 6061 6062 /** 6063 * @brief EXTI9 configuration 6064 */ 6065 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 6066 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 6067 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 6068 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 6069 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */ 6070 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */ 6071 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */ 6072 6073 /** 6074 * @brief EXTI10 configuration 6075 */ 6076 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 6077 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 6078 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 6079 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 6080 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */ 6081 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */ 6082 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */ 6083 6084 /** 6085 * @brief EXTI11 configuration 6086 */ 6087 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 6088 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 6089 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 6090 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 6091 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */ 6092 #define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */ 6093 #define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */ 6094 6095 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 6096 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 6097 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 6098 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 6099 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 6100 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 6101 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 6102 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 6103 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 6104 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 6105 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 6106 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 6107 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 6108 6109 /** 6110 * @brief EXTI12 configuration 6111 */ 6112 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 6113 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 6114 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 6115 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 6116 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */ 6117 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */ 6118 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */ 6119 6120 /** 6121 * @brief EXTI13 configuration 6122 */ 6123 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 6124 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 6125 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 6126 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 6127 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */ 6128 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */ 6129 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */ 6130 6131 /** 6132 * @brief EXTI14 configuration 6133 */ 6134 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 6135 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 6136 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 6137 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 6138 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */ 6139 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */ 6140 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */ 6141 6142 /** 6143 * @brief EXTI15 configuration 6144 */ 6145 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 6146 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 6147 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 6148 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 6149 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ 6150 #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */ 6151 #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */ 6152 6153 /******************************************************************************/ 6154 /* */ 6155 /* Routing Interface (RI) */ 6156 /* */ 6157 /******************************************************************************/ 6158 6159 /******************** Bit definition for RI_ICR register ********************/ 6160 #define RI_ICR_IC1OS_Pos (0U) 6161 #define RI_ICR_IC1OS_Msk (0xFU << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */ 6162 #define RI_ICR_IC1OS RI_ICR_IC1OS_Msk /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */ 6163 #define RI_ICR_IC1OS_0 (0x1U << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */ 6164 #define RI_ICR_IC1OS_1 (0x2U << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */ 6165 #define RI_ICR_IC1OS_2 (0x4U << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */ 6166 #define RI_ICR_IC1OS_3 (0x8U << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */ 6167 6168 #define RI_ICR_IC2OS_Pos (4U) 6169 #define RI_ICR_IC2OS_Msk (0xFU << RI_ICR_IC2OS_Pos) /*!< 0x000000F0 */ 6170 #define RI_ICR_IC2OS RI_ICR_IC2OS_Msk /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */ 6171 #define RI_ICR_IC2OS_0 (0x1U << RI_ICR_IC2OS_Pos) /*!< 0x00000010 */ 6172 #define RI_ICR_IC2OS_1 (0x2U << RI_ICR_IC2OS_Pos) /*!< 0x00000020 */ 6173 #define RI_ICR_IC2OS_2 (0x4U << RI_ICR_IC2OS_Pos) /*!< 0x00000040 */ 6174 #define RI_ICR_IC2OS_3 (0x8U << RI_ICR_IC2OS_Pos) /*!< 0x00000080 */ 6175 6176 #define RI_ICR_IC3OS_Pos (8U) 6177 #define RI_ICR_IC3OS_Msk (0xFU << RI_ICR_IC3OS_Pos) /*!< 0x00000F00 */ 6178 #define RI_ICR_IC3OS RI_ICR_IC3OS_Msk /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */ 6179 #define RI_ICR_IC3OS_0 (0x1U << RI_ICR_IC3OS_Pos) /*!< 0x00000100 */ 6180 #define RI_ICR_IC3OS_1 (0x2U << RI_ICR_IC3OS_Pos) /*!< 0x00000200 */ 6181 #define RI_ICR_IC3OS_2 (0x4U << RI_ICR_IC3OS_Pos) /*!< 0x00000400 */ 6182 #define RI_ICR_IC3OS_3 (0x8U << RI_ICR_IC3OS_Pos) /*!< 0x00000800 */ 6183 6184 #define RI_ICR_IC4OS_Pos (12U) 6185 #define RI_ICR_IC4OS_Msk (0xFU << RI_ICR_IC4OS_Pos) /*!< 0x0000F000 */ 6186 #define RI_ICR_IC4OS RI_ICR_IC4OS_Msk /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */ 6187 #define RI_ICR_IC4OS_0 (0x1U << RI_ICR_IC4OS_Pos) /*!< 0x00001000 */ 6188 #define RI_ICR_IC4OS_1 (0x2U << RI_ICR_IC4OS_Pos) /*!< 0x00002000 */ 6189 #define RI_ICR_IC4OS_2 (0x4U << RI_ICR_IC4OS_Pos) /*!< 0x00004000 */ 6190 #define RI_ICR_IC4OS_3 (0x8U << RI_ICR_IC4OS_Pos) /*!< 0x00008000 */ 6191 6192 #define RI_ICR_TIM_Pos (16U) 6193 #define RI_ICR_TIM_Msk (0x3U << RI_ICR_TIM_Pos) /*!< 0x00030000 */ 6194 #define RI_ICR_TIM RI_ICR_TIM_Msk /*!< TIM[3:0] bits (Timers select bits) */ 6195 #define RI_ICR_TIM_0 (0x1U << RI_ICR_TIM_Pos) /*!< 0x00010000 */ 6196 #define RI_ICR_TIM_1 (0x2U << RI_ICR_TIM_Pos) /*!< 0x00020000 */ 6197 6198 #define RI_ICR_IC1_Pos (18U) 6199 #define RI_ICR_IC1_Msk (0x1U << RI_ICR_IC1_Pos) /*!< 0x00040000 */ 6200 #define RI_ICR_IC1 RI_ICR_IC1_Msk /*!< Input capture 1 */ 6201 #define RI_ICR_IC2_Pos (19U) 6202 #define RI_ICR_IC2_Msk (0x1U << RI_ICR_IC2_Pos) /*!< 0x00080000 */ 6203 #define RI_ICR_IC2 RI_ICR_IC2_Msk /*!< Input capture 2 */ 6204 #define RI_ICR_IC3_Pos (20U) 6205 #define RI_ICR_IC3_Msk (0x1U << RI_ICR_IC3_Pos) /*!< 0x00100000 */ 6206 #define RI_ICR_IC3 RI_ICR_IC3_Msk /*!< Input capture 3 */ 6207 #define RI_ICR_IC4_Pos (21U) 6208 #define RI_ICR_IC4_Msk (0x1U << RI_ICR_IC4_Pos) /*!< 0x00200000 */ 6209 #define RI_ICR_IC4 RI_ICR_IC4_Msk /*!< Input capture 4 */ 6210 6211 /******************** Bit definition for RI_ASCR1 register ********************/ 6212 #define RI_ASCR1_CH_Pos (0U) 6213 #define RI_ASCR1_CH_Msk (0x7BFDFFFFU << RI_ASCR1_CH_Pos) /*!< 0x7BFDFFFF */ 6214 #define RI_ASCR1_CH RI_ASCR1_CH_Msk /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */ 6215 #define RI_ASCR1_CH_0 (0x00000001U) /*!< Bit 0 */ 6216 #define RI_ASCR1_CH_1 (0x00000002U) /*!< Bit 1 */ 6217 #define RI_ASCR1_CH_2 (0x00000004U) /*!< Bit 2 */ 6218 #define RI_ASCR1_CH_3 (0x00000008U) /*!< Bit 3 */ 6219 #define RI_ASCR1_CH_4 (0x00000010U) /*!< Bit 4 */ 6220 #define RI_ASCR1_CH_5 (0x00000020U) /*!< Bit 5 */ 6221 #define RI_ASCR1_CH_6 (0x00000040U) /*!< Bit 6 */ 6222 #define RI_ASCR1_CH_7 (0x00000080U) /*!< Bit 7 */ 6223 #define RI_ASCR1_CH_8 (0x00000100U) /*!< Bit 8 */ 6224 #define RI_ASCR1_CH_9 (0x00000200U) /*!< Bit 9 */ 6225 #define RI_ASCR1_CH_10 (0x00000400U) /*!< Bit 10 */ 6226 #define RI_ASCR1_CH_11 (0x00000800U) /*!< Bit 11 */ 6227 #define RI_ASCR1_CH_12 (0x00001000U) /*!< Bit 12 */ 6228 #define RI_ASCR1_CH_13 (0x00002000U) /*!< Bit 13 */ 6229 #define RI_ASCR1_CH_14 (0x00004000U) /*!< Bit 14 */ 6230 #define RI_ASCR1_CH_15 (0x00008000U) /*!< Bit 15 */ 6231 #define RI_ASCR1_CH_31 (0x00010000U) /*!< Bit 16 */ 6232 #define RI_ASCR1_CH_18 (0x00040000U) /*!< Bit 18 */ 6233 #define RI_ASCR1_CH_19 (0x00080000U) /*!< Bit 19 */ 6234 #define RI_ASCR1_CH_20 (0x00100000U) /*!< Bit 20 */ 6235 #define RI_ASCR1_CH_21 (0x00200000U) /*!< Bit 21 */ 6236 #define RI_ASCR1_CH_22 (0x00400000U) /*!< Bit 22 */ 6237 #define RI_ASCR1_CH_23 (0x00800000U) /*!< Bit 23 */ 6238 #define RI_ASCR1_CH_24 (0x01000000U) /*!< Bit 24 */ 6239 #define RI_ASCR1_CH_25 (0x02000000U) /*!< Bit 25 */ 6240 #define RI_ASCR1_VCOMP_Pos (26U) 6241 #define RI_ASCR1_VCOMP_Msk (0x1U << RI_ASCR1_VCOMP_Pos) /*!< 0x04000000 */ 6242 #define RI_ASCR1_VCOMP RI_ASCR1_VCOMP_Msk /*!< ADC analog switch selection for internal node to COMP1 */ 6243 #define RI_ASCR1_CH_27 (0x08000000U) /*!< Bit 27 */ 6244 #define RI_ASCR1_CH_28 (0x10000000U) /*!< Bit 28 */ 6245 #define RI_ASCR1_CH_29 (0x20000000U) /*!< Bit 29 */ 6246 #define RI_ASCR1_CH_30 (0x40000000U) /*!< Bit 30 */ 6247 #define RI_ASCR1_SCM_Pos (31U) 6248 #define RI_ASCR1_SCM_Msk (0x1U << RI_ASCR1_SCM_Pos) /*!< 0x80000000 */ 6249 #define RI_ASCR1_SCM RI_ASCR1_SCM_Msk /*!< I/O Switch control mode */ 6250 6251 /******************** Bit definition for RI_ASCR2 register ********************/ 6252 #define RI_ASCR2_GR10_1 (0x00000001U) /*!< GR10-1 selection bit */ 6253 #define RI_ASCR2_GR10_2 (0x00000002U) /*!< GR10-2 selection bit */ 6254 #define RI_ASCR2_GR10_3 (0x00000004U) /*!< GR10-3 selection bit */ 6255 #define RI_ASCR2_GR10_4 (0x00000008U) /*!< GR10-4 selection bit */ 6256 #define RI_ASCR2_GR6_Pos (4U) 6257 #define RI_ASCR2_GR6_Msk (0x1800003U << RI_ASCR2_GR6_Pos) /*!< 0x18000030 */ 6258 #define RI_ASCR2_GR6 RI_ASCR2_GR6_Msk /*!< GR6 selection bits */ 6259 #define RI_ASCR2_GR6_1 (0x0000001U << RI_ASCR2_GR6_Pos) /*!< 0x00000010 */ 6260 #define RI_ASCR2_GR6_2 (0x0000002U << RI_ASCR2_GR6_Pos) /*!< 0x00000020 */ 6261 #define RI_ASCR2_GR6_3 (0x0800000U << RI_ASCR2_GR6_Pos) /*!< 0x08000000 */ 6262 #define RI_ASCR2_GR6_4 (0x1000000U << RI_ASCR2_GR6_Pos) /*!< 0x10000000 */ 6263 #define RI_ASCR2_GR5_1 (0x00000040U) /*!< GR5-1 selection bit */ 6264 #define RI_ASCR2_GR5_2 (0x00000080U) /*!< GR5-2 selection bit */ 6265 #define RI_ASCR2_GR5_3 (0x00000100U) /*!< GR5-3 selection bit */ 6266 #define RI_ASCR2_GR4_1 (0x00000200U) /*!< GR4-1 selection bit */ 6267 #define RI_ASCR2_GR4_2 (0x00000400U) /*!< GR4-2 selection bit */ 6268 #define RI_ASCR2_GR4_3 (0x00000800U) /*!< GR4-3 selection bit */ 6269 #define RI_ASCR2_GR4_4 (0x00008000U) /*!< GR4-4 selection bit */ 6270 #define RI_ASCR2_CH0b_Pos (16U) 6271 #define RI_ASCR2_CH0b_Msk (0x1U << RI_ASCR2_CH0b_Pos) /*!< 0x00010000 */ 6272 #define RI_ASCR2_CH0b RI_ASCR2_CH0b_Msk /*!< CH0b selection bit */ 6273 #define RI_ASCR2_CH1b_Pos (17U) 6274 #define RI_ASCR2_CH1b_Msk (0x1U << RI_ASCR2_CH1b_Pos) /*!< 0x00020000 */ 6275 #define RI_ASCR2_CH1b RI_ASCR2_CH1b_Msk /*!< CH1b selection bit */ 6276 #define RI_ASCR2_CH2b_Pos (18U) 6277 #define RI_ASCR2_CH2b_Msk (0x1U << RI_ASCR2_CH2b_Pos) /*!< 0x00040000 */ 6278 #define RI_ASCR2_CH2b RI_ASCR2_CH2b_Msk /*!< CH2b selection bit */ 6279 #define RI_ASCR2_CH3b_Pos (19U) 6280 #define RI_ASCR2_CH3b_Msk (0x1U << RI_ASCR2_CH3b_Pos) /*!< 0x00080000 */ 6281 #define RI_ASCR2_CH3b RI_ASCR2_CH3b_Msk /*!< CH3b selection bit */ 6282 #define RI_ASCR2_CH6b_Pos (20U) 6283 #define RI_ASCR2_CH6b_Msk (0x1U << RI_ASCR2_CH6b_Pos) /*!< 0x00100000 */ 6284 #define RI_ASCR2_CH6b RI_ASCR2_CH6b_Msk /*!< CH6b selection bit */ 6285 #define RI_ASCR2_CH7b_Pos (21U) 6286 #define RI_ASCR2_CH7b_Msk (0x1U << RI_ASCR2_CH7b_Pos) /*!< 0x00200000 */ 6287 #define RI_ASCR2_CH7b RI_ASCR2_CH7b_Msk /*!< CH7b selection bit */ 6288 #define RI_ASCR2_CH8b_Pos (22U) 6289 #define RI_ASCR2_CH8b_Msk (0x1U << RI_ASCR2_CH8b_Pos) /*!< 0x00400000 */ 6290 #define RI_ASCR2_CH8b RI_ASCR2_CH8b_Msk /*!< CH8b selection bit */ 6291 #define RI_ASCR2_CH9b_Pos (23U) 6292 #define RI_ASCR2_CH9b_Msk (0x1U << RI_ASCR2_CH9b_Pos) /*!< 0x00800000 */ 6293 #define RI_ASCR2_CH9b RI_ASCR2_CH9b_Msk /*!< CH9b selection bit */ 6294 #define RI_ASCR2_CH10b_Pos (24U) 6295 #define RI_ASCR2_CH10b_Msk (0x1U << RI_ASCR2_CH10b_Pos) /*!< 0x01000000 */ 6296 #define RI_ASCR2_CH10b RI_ASCR2_CH10b_Msk /*!< CH10b selection bit */ 6297 #define RI_ASCR2_CH11b_Pos (25U) 6298 #define RI_ASCR2_CH11b_Msk (0x1U << RI_ASCR2_CH11b_Pos) /*!< 0x02000000 */ 6299 #define RI_ASCR2_CH11b RI_ASCR2_CH11b_Msk /*!< CH11b selection bit */ 6300 #define RI_ASCR2_CH12b_Pos (26U) 6301 #define RI_ASCR2_CH12b_Msk (0x1U << RI_ASCR2_CH12b_Pos) /*!< 0x04000000 */ 6302 #define RI_ASCR2_CH12b RI_ASCR2_CH12b_Msk /*!< CH12b selection bit */ 6303 6304 /******************** Bit definition for RI_HYSCR1 register ********************/ 6305 #define RI_HYSCR1_PA_Pos (0U) 6306 #define RI_HYSCR1_PA_Msk (0xFFFFU << RI_HYSCR1_PA_Pos) /*!< 0x0000FFFF */ 6307 #define RI_HYSCR1_PA RI_HYSCR1_PA_Msk /*!< PA[15:0] Port A Hysteresis selection */ 6308 #define RI_HYSCR1_PA_0 (0x0001U << RI_HYSCR1_PA_Pos) /*!< 0x00000001 */ 6309 #define RI_HYSCR1_PA_1 (0x0002U << RI_HYSCR1_PA_Pos) /*!< 0x00000002 */ 6310 #define RI_HYSCR1_PA_2 (0x0004U << RI_HYSCR1_PA_Pos) /*!< 0x00000004 */ 6311 #define RI_HYSCR1_PA_3 (0x0008U << RI_HYSCR1_PA_Pos) /*!< 0x00000008 */ 6312 #define RI_HYSCR1_PA_4 (0x0010U << RI_HYSCR1_PA_Pos) /*!< 0x00000010 */ 6313 #define RI_HYSCR1_PA_5 (0x0020U << RI_HYSCR1_PA_Pos) /*!< 0x00000020 */ 6314 #define RI_HYSCR1_PA_6 (0x0040U << RI_HYSCR1_PA_Pos) /*!< 0x00000040 */ 6315 #define RI_HYSCR1_PA_7 (0x0080U << RI_HYSCR1_PA_Pos) /*!< 0x00000080 */ 6316 #define RI_HYSCR1_PA_8 (0x0100U << RI_HYSCR1_PA_Pos) /*!< 0x00000100 */ 6317 #define RI_HYSCR1_PA_9 (0x0200U << RI_HYSCR1_PA_Pos) /*!< 0x00000200 */ 6318 #define RI_HYSCR1_PA_10 (0x0400U << RI_HYSCR1_PA_Pos) /*!< 0x00000400 */ 6319 #define RI_HYSCR1_PA_11 (0x0800U << RI_HYSCR1_PA_Pos) /*!< 0x00000800 */ 6320 #define RI_HYSCR1_PA_12 (0x1000U << RI_HYSCR1_PA_Pos) /*!< 0x00001000 */ 6321 #define RI_HYSCR1_PA_13 (0x2000U << RI_HYSCR1_PA_Pos) /*!< 0x00002000 */ 6322 #define RI_HYSCR1_PA_14 (0x4000U << RI_HYSCR1_PA_Pos) /*!< 0x00004000 */ 6323 #define RI_HYSCR1_PA_15 (0x8000U << RI_HYSCR1_PA_Pos) /*!< 0x00008000 */ 6324 6325 #define RI_HYSCR1_PB_Pos (16U) 6326 #define RI_HYSCR1_PB_Msk (0xFFFFU << RI_HYSCR1_PB_Pos) /*!< 0xFFFF0000 */ 6327 #define RI_HYSCR1_PB RI_HYSCR1_PB_Msk /*!< PB[15:0] Port B Hysteresis selection */ 6328 #define RI_HYSCR1_PB_0 (0x0001U << RI_HYSCR1_PB_Pos) /*!< 0x00010000 */ 6329 #define RI_HYSCR1_PB_1 (0x0002U << RI_HYSCR1_PB_Pos) /*!< 0x00020000 */ 6330 #define RI_HYSCR1_PB_2 (0x0004U << RI_HYSCR1_PB_Pos) /*!< 0x00040000 */ 6331 #define RI_HYSCR1_PB_3 (0x0008U << RI_HYSCR1_PB_Pos) /*!< 0x00080000 */ 6332 #define RI_HYSCR1_PB_4 (0x0010U << RI_HYSCR1_PB_Pos) /*!< 0x00100000 */ 6333 #define RI_HYSCR1_PB_5 (0x0020U << RI_HYSCR1_PB_Pos) /*!< 0x00200000 */ 6334 #define RI_HYSCR1_PB_6 (0x0040U << RI_HYSCR1_PB_Pos) /*!< 0x00400000 */ 6335 #define RI_HYSCR1_PB_7 (0x0080U << RI_HYSCR1_PB_Pos) /*!< 0x00800000 */ 6336 #define RI_HYSCR1_PB_8 (0x0100U << RI_HYSCR1_PB_Pos) /*!< 0x01000000 */ 6337 #define RI_HYSCR1_PB_9 (0x0200U << RI_HYSCR1_PB_Pos) /*!< 0x02000000 */ 6338 #define RI_HYSCR1_PB_10 (0x0400U << RI_HYSCR1_PB_Pos) /*!< 0x04000000 */ 6339 #define RI_HYSCR1_PB_11 (0x0800U << RI_HYSCR1_PB_Pos) /*!< 0x08000000 */ 6340 #define RI_HYSCR1_PB_12 (0x1000U << RI_HYSCR1_PB_Pos) /*!< 0x10000000 */ 6341 #define RI_HYSCR1_PB_13 (0x2000U << RI_HYSCR1_PB_Pos) /*!< 0x20000000 */ 6342 #define RI_HYSCR1_PB_14 (0x4000U << RI_HYSCR1_PB_Pos) /*!< 0x40000000 */ 6343 #define RI_HYSCR1_PB_15 (0x8000U << RI_HYSCR1_PB_Pos) /*!< 0x80000000 */ 6344 6345 /******************** Bit definition for RI_HYSCR2 register ********************/ 6346 #define RI_HYSCR2_PC_Pos (0U) 6347 #define RI_HYSCR2_PC_Msk (0xFFFFU << RI_HYSCR2_PC_Pos) /*!< 0x0000FFFF */ 6348 #define RI_HYSCR2_PC RI_HYSCR2_PC_Msk /*!< PC[15:0] Port C Hysteresis selection */ 6349 #define RI_HYSCR2_PC_0 (0x0001U << RI_HYSCR2_PC_Pos) /*!< 0x00000001 */ 6350 #define RI_HYSCR2_PC_1 (0x0002U << RI_HYSCR2_PC_Pos) /*!< 0x00000002 */ 6351 #define RI_HYSCR2_PC_2 (0x0004U << RI_HYSCR2_PC_Pos) /*!< 0x00000004 */ 6352 #define RI_HYSCR2_PC_3 (0x0008U << RI_HYSCR2_PC_Pos) /*!< 0x00000008 */ 6353 #define RI_HYSCR2_PC_4 (0x0010U << RI_HYSCR2_PC_Pos) /*!< 0x00000010 */ 6354 #define RI_HYSCR2_PC_5 (0x0020U << RI_HYSCR2_PC_Pos) /*!< 0x00000020 */ 6355 #define RI_HYSCR2_PC_6 (0x0040U << RI_HYSCR2_PC_Pos) /*!< 0x00000040 */ 6356 #define RI_HYSCR2_PC_7 (0x0080U << RI_HYSCR2_PC_Pos) /*!< 0x00000080 */ 6357 #define RI_HYSCR2_PC_8 (0x0100U << RI_HYSCR2_PC_Pos) /*!< 0x00000100 */ 6358 #define RI_HYSCR2_PC_9 (0x0200U << RI_HYSCR2_PC_Pos) /*!< 0x00000200 */ 6359 #define RI_HYSCR2_PC_10 (0x0400U << RI_HYSCR2_PC_Pos) /*!< 0x00000400 */ 6360 #define RI_HYSCR2_PC_11 (0x0800U << RI_HYSCR2_PC_Pos) /*!< 0x00000800 */ 6361 #define RI_HYSCR2_PC_12 (0x1000U << RI_HYSCR2_PC_Pos) /*!< 0x00001000 */ 6362 #define RI_HYSCR2_PC_13 (0x2000U << RI_HYSCR2_PC_Pos) /*!< 0x00002000 */ 6363 #define RI_HYSCR2_PC_14 (0x4000U << RI_HYSCR2_PC_Pos) /*!< 0x00004000 */ 6364 #define RI_HYSCR2_PC_15 (0x8000U << RI_HYSCR2_PC_Pos) /*!< 0x00008000 */ 6365 6366 #define RI_HYSCR2_PD_Pos (16U) 6367 #define RI_HYSCR2_PD_Msk (0xFFFFU << RI_HYSCR2_PD_Pos) /*!< 0xFFFF0000 */ 6368 #define RI_HYSCR2_PD RI_HYSCR2_PD_Msk /*!< PD[15:0] Port D Hysteresis selection */ 6369 #define RI_HYSCR2_PD_0 (0x0001U << RI_HYSCR2_PD_Pos) /*!< 0x00010000 */ 6370 #define RI_HYSCR2_PD_1 (0x0002U << RI_HYSCR2_PD_Pos) /*!< 0x00020000 */ 6371 #define RI_HYSCR2_PD_2 (0x0004U << RI_HYSCR2_PD_Pos) /*!< 0x00040000 */ 6372 #define RI_HYSCR2_PD_3 (0x0008U << RI_HYSCR2_PD_Pos) /*!< 0x00080000 */ 6373 #define RI_HYSCR2_PD_4 (0x0010U << RI_HYSCR2_PD_Pos) /*!< 0x00100000 */ 6374 #define RI_HYSCR2_PD_5 (0x0020U << RI_HYSCR2_PD_Pos) /*!< 0x00200000 */ 6375 #define RI_HYSCR2_PD_6 (0x0040U << RI_HYSCR2_PD_Pos) /*!< 0x00400000 */ 6376 #define RI_HYSCR2_PD_7 (0x0080U << RI_HYSCR2_PD_Pos) /*!< 0x00800000 */ 6377 #define RI_HYSCR2_PD_8 (0x0100U << RI_HYSCR2_PD_Pos) /*!< 0x01000000 */ 6378 #define RI_HYSCR2_PD_9 (0x0200U << RI_HYSCR2_PD_Pos) /*!< 0x02000000 */ 6379 #define RI_HYSCR2_PD_10 (0x0400U << RI_HYSCR2_PD_Pos) /*!< 0x04000000 */ 6380 #define RI_HYSCR2_PD_11 (0x0800U << RI_HYSCR2_PD_Pos) /*!< 0x08000000 */ 6381 #define RI_HYSCR2_PD_12 (0x1000U << RI_HYSCR2_PD_Pos) /*!< 0x10000000 */ 6382 #define RI_HYSCR2_PD_13 (0x2000U << RI_HYSCR2_PD_Pos) /*!< 0x20000000 */ 6383 #define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */ 6384 #define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */ 6385 6386 /******************** Bit definition for RI_HYSCR3 register ********************/ 6387 #define RI_HYSCR3_PE_Pos (0U) 6388 #define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */ 6389 #define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */ 6390 #define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */ 6391 #define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */ 6392 #define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */ 6393 #define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */ 6394 #define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */ 6395 #define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */ 6396 #define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */ 6397 #define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */ 6398 #define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */ 6399 #define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */ 6400 #define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */ 6401 #define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */ 6402 #define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */ 6403 #define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */ 6404 #define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */ 6405 #define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */ 6406 #define RI_HYSCR3_PF_Pos (16U) 6407 #define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */ 6408 #define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */ 6409 #define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */ 6410 #define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */ 6411 #define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */ 6412 #define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */ 6413 #define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */ 6414 #define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */ 6415 #define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */ 6416 #define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */ 6417 #define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */ 6418 #define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */ 6419 #define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */ 6420 #define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */ 6421 #define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */ 6422 #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */ 6423 #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */ 6424 #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */ 6425 6426 /******************** Bit definition for RI_HYSCR4 register ********************/ 6427 #define RI_HYSCR4_PG_Pos (0U) 6428 #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */ 6429 #define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */ 6430 #define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */ 6431 #define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */ 6432 #define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */ 6433 #define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */ 6434 #define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */ 6435 #define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */ 6436 #define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */ 6437 #define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */ 6438 #define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */ 6439 #define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */ 6440 #define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */ 6441 #define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */ 6442 #define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */ 6443 #define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */ 6444 #define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */ 6445 #define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */ 6446 6447 /******************** Bit definition for RI_ASMR1 register ********************/ 6448 #define RI_ASMR1_PA_Pos (0U) 6449 #define RI_ASMR1_PA_Msk (0xFFFFU << RI_ASMR1_PA_Pos) /*!< 0x0000FFFF */ 6450 #define RI_ASMR1_PA RI_ASMR1_PA_Msk /*!< PA[15:0] Port A selection*/ 6451 #define RI_ASMR1_PA_0 (0x0001U << RI_ASMR1_PA_Pos) /*!< 0x00000001 */ 6452 #define RI_ASMR1_PA_1 (0x0002U << RI_ASMR1_PA_Pos) /*!< 0x00000002 */ 6453 #define RI_ASMR1_PA_2 (0x0004U << RI_ASMR1_PA_Pos) /*!< 0x00000004 */ 6454 #define RI_ASMR1_PA_3 (0x0008U << RI_ASMR1_PA_Pos) /*!< 0x00000008 */ 6455 #define RI_ASMR1_PA_4 (0x0010U << RI_ASMR1_PA_Pos) /*!< 0x00000010 */ 6456 #define RI_ASMR1_PA_5 (0x0020U << RI_ASMR1_PA_Pos) /*!< 0x00000020 */ 6457 #define RI_ASMR1_PA_6 (0x0040U << RI_ASMR1_PA_Pos) /*!< 0x00000040 */ 6458 #define RI_ASMR1_PA_7 (0x0080U << RI_ASMR1_PA_Pos) /*!< 0x00000080 */ 6459 #define RI_ASMR1_PA_8 (0x0100U << RI_ASMR1_PA_Pos) /*!< 0x00000100 */ 6460 #define RI_ASMR1_PA_9 (0x0200U << RI_ASMR1_PA_Pos) /*!< 0x00000200 */ 6461 #define RI_ASMR1_PA_10 (0x0400U << RI_ASMR1_PA_Pos) /*!< 0x00000400 */ 6462 #define RI_ASMR1_PA_11 (0x0800U << RI_ASMR1_PA_Pos) /*!< 0x00000800 */ 6463 #define RI_ASMR1_PA_12 (0x1000U << RI_ASMR1_PA_Pos) /*!< 0x00001000 */ 6464 #define RI_ASMR1_PA_13 (0x2000U << RI_ASMR1_PA_Pos) /*!< 0x00002000 */ 6465 #define RI_ASMR1_PA_14 (0x4000U << RI_ASMR1_PA_Pos) /*!< 0x00004000 */ 6466 #define RI_ASMR1_PA_15 (0x8000U << RI_ASMR1_PA_Pos) /*!< 0x00008000 */ 6467 6468 /******************** Bit definition for RI_CMR1 register ********************/ 6469 #define RI_CMR1_PA_Pos (0U) 6470 #define RI_CMR1_PA_Msk (0xFFFFU << RI_CMR1_PA_Pos) /*!< 0x0000FFFF */ 6471 #define RI_CMR1_PA RI_CMR1_PA_Msk /*!< PA[15:0] Port A selection*/ 6472 #define RI_CMR1_PA_0 (0x0001U << RI_CMR1_PA_Pos) /*!< 0x00000001 */ 6473 #define RI_CMR1_PA_1 (0x0002U << RI_CMR1_PA_Pos) /*!< 0x00000002 */ 6474 #define RI_CMR1_PA_2 (0x0004U << RI_CMR1_PA_Pos) /*!< 0x00000004 */ 6475 #define RI_CMR1_PA_3 (0x0008U << RI_CMR1_PA_Pos) /*!< 0x00000008 */ 6476 #define RI_CMR1_PA_4 (0x0010U << RI_CMR1_PA_Pos) /*!< 0x00000010 */ 6477 #define RI_CMR1_PA_5 (0x0020U << RI_CMR1_PA_Pos) /*!< 0x00000020 */ 6478 #define RI_CMR1_PA_6 (0x0040U << RI_CMR1_PA_Pos) /*!< 0x00000040 */ 6479 #define RI_CMR1_PA_7 (0x0080U << RI_CMR1_PA_Pos) /*!< 0x00000080 */ 6480 #define RI_CMR1_PA_8 (0x0100U << RI_CMR1_PA_Pos) /*!< 0x00000100 */ 6481 #define RI_CMR1_PA_9 (0x0200U << RI_CMR1_PA_Pos) /*!< 0x00000200 */ 6482 #define RI_CMR1_PA_10 (0x0400U << RI_CMR1_PA_Pos) /*!< 0x00000400 */ 6483 #define RI_CMR1_PA_11 (0x0800U << RI_CMR1_PA_Pos) /*!< 0x00000800 */ 6484 #define RI_CMR1_PA_12 (0x1000U << RI_CMR1_PA_Pos) /*!< 0x00001000 */ 6485 #define RI_CMR1_PA_13 (0x2000U << RI_CMR1_PA_Pos) /*!< 0x00002000 */ 6486 #define RI_CMR1_PA_14 (0x4000U << RI_CMR1_PA_Pos) /*!< 0x00004000 */ 6487 #define RI_CMR1_PA_15 (0x8000U << RI_CMR1_PA_Pos) /*!< 0x00008000 */ 6488 6489 /******************** Bit definition for RI_CICR1 register ********************/ 6490 #define RI_CICR1_PA_Pos (0U) 6491 #define RI_CICR1_PA_Msk (0xFFFFU << RI_CICR1_PA_Pos) /*!< 0x0000FFFF */ 6492 #define RI_CICR1_PA RI_CICR1_PA_Msk /*!< PA[15:0] Port A selection*/ 6493 #define RI_CICR1_PA_0 (0x0001U << RI_CICR1_PA_Pos) /*!< 0x00000001 */ 6494 #define RI_CICR1_PA_1 (0x0002U << RI_CICR1_PA_Pos) /*!< 0x00000002 */ 6495 #define RI_CICR1_PA_2 (0x0004U << RI_CICR1_PA_Pos) /*!< 0x00000004 */ 6496 #define RI_CICR1_PA_3 (0x0008U << RI_CICR1_PA_Pos) /*!< 0x00000008 */ 6497 #define RI_CICR1_PA_4 (0x0010U << RI_CICR1_PA_Pos) /*!< 0x00000010 */ 6498 #define RI_CICR1_PA_5 (0x0020U << RI_CICR1_PA_Pos) /*!< 0x00000020 */ 6499 #define RI_CICR1_PA_6 (0x0040U << RI_CICR1_PA_Pos) /*!< 0x00000040 */ 6500 #define RI_CICR1_PA_7 (0x0080U << RI_CICR1_PA_Pos) /*!< 0x00000080 */ 6501 #define RI_CICR1_PA_8 (0x0100U << RI_CICR1_PA_Pos) /*!< 0x00000100 */ 6502 #define RI_CICR1_PA_9 (0x0200U << RI_CICR1_PA_Pos) /*!< 0x00000200 */ 6503 #define RI_CICR1_PA_10 (0x0400U << RI_CICR1_PA_Pos) /*!< 0x00000400 */ 6504 #define RI_CICR1_PA_11 (0x0800U << RI_CICR1_PA_Pos) /*!< 0x00000800 */ 6505 #define RI_CICR1_PA_12 (0x1000U << RI_CICR1_PA_Pos) /*!< 0x00001000 */ 6506 #define RI_CICR1_PA_13 (0x2000U << RI_CICR1_PA_Pos) /*!< 0x00002000 */ 6507 #define RI_CICR1_PA_14 (0x4000U << RI_CICR1_PA_Pos) /*!< 0x00004000 */ 6508 #define RI_CICR1_PA_15 (0x8000U << RI_CICR1_PA_Pos) /*!< 0x00008000 */ 6509 6510 /******************** Bit definition for RI_ASMR2 register ********************/ 6511 #define RI_ASMR2_PB_Pos (0U) 6512 #define RI_ASMR2_PB_Msk (0xFFFFU << RI_ASMR2_PB_Pos) /*!< 0x0000FFFF */ 6513 #define RI_ASMR2_PB RI_ASMR2_PB_Msk /*!< PB[15:0] Port B selection */ 6514 #define RI_ASMR2_PB_0 (0x0001U << RI_ASMR2_PB_Pos) /*!< 0x00000001 */ 6515 #define RI_ASMR2_PB_1 (0x0002U << RI_ASMR2_PB_Pos) /*!< 0x00000002 */ 6516 #define RI_ASMR2_PB_2 (0x0004U << RI_ASMR2_PB_Pos) /*!< 0x00000004 */ 6517 #define RI_ASMR2_PB_3 (0x0008U << RI_ASMR2_PB_Pos) /*!< 0x00000008 */ 6518 #define RI_ASMR2_PB_4 (0x0010U << RI_ASMR2_PB_Pos) /*!< 0x00000010 */ 6519 #define RI_ASMR2_PB_5 (0x0020U << RI_ASMR2_PB_Pos) /*!< 0x00000020 */ 6520 #define RI_ASMR2_PB_6 (0x0040U << RI_ASMR2_PB_Pos) /*!< 0x00000040 */ 6521 #define RI_ASMR2_PB_7 (0x0080U << RI_ASMR2_PB_Pos) /*!< 0x00000080 */ 6522 #define RI_ASMR2_PB_8 (0x0100U << RI_ASMR2_PB_Pos) /*!< 0x00000100 */ 6523 #define RI_ASMR2_PB_9 (0x0200U << RI_ASMR2_PB_Pos) /*!< 0x00000200 */ 6524 #define RI_ASMR2_PB_10 (0x0400U << RI_ASMR2_PB_Pos) /*!< 0x00000400 */ 6525 #define RI_ASMR2_PB_11 (0x0800U << RI_ASMR2_PB_Pos) /*!< 0x00000800 */ 6526 #define RI_ASMR2_PB_12 (0x1000U << RI_ASMR2_PB_Pos) /*!< 0x00001000 */ 6527 #define RI_ASMR2_PB_13 (0x2000U << RI_ASMR2_PB_Pos) /*!< 0x00002000 */ 6528 #define RI_ASMR2_PB_14 (0x4000U << RI_ASMR2_PB_Pos) /*!< 0x00004000 */ 6529 #define RI_ASMR2_PB_15 (0x8000U << RI_ASMR2_PB_Pos) /*!< 0x00008000 */ 6530 6531 /******************** Bit definition for RI_CMR2 register ********************/ 6532 #define RI_CMR2_PB_Pos (0U) 6533 #define RI_CMR2_PB_Msk (0xFFFFU << RI_CMR2_PB_Pos) /*!< 0x0000FFFF */ 6534 #define RI_CMR2_PB RI_CMR2_PB_Msk /*!< PB[15:0] Port B selection */ 6535 #define RI_CMR2_PB_0 (0x0001U << RI_CMR2_PB_Pos) /*!< 0x00000001 */ 6536 #define RI_CMR2_PB_1 (0x0002U << RI_CMR2_PB_Pos) /*!< 0x00000002 */ 6537 #define RI_CMR2_PB_2 (0x0004U << RI_CMR2_PB_Pos) /*!< 0x00000004 */ 6538 #define RI_CMR2_PB_3 (0x0008U << RI_CMR2_PB_Pos) /*!< 0x00000008 */ 6539 #define RI_CMR2_PB_4 (0x0010U << RI_CMR2_PB_Pos) /*!< 0x00000010 */ 6540 #define RI_CMR2_PB_5 (0x0020U << RI_CMR2_PB_Pos) /*!< 0x00000020 */ 6541 #define RI_CMR2_PB_6 (0x0040U << RI_CMR2_PB_Pos) /*!< 0x00000040 */ 6542 #define RI_CMR2_PB_7 (0x0080U << RI_CMR2_PB_Pos) /*!< 0x00000080 */ 6543 #define RI_CMR2_PB_8 (0x0100U << RI_CMR2_PB_Pos) /*!< 0x00000100 */ 6544 #define RI_CMR2_PB_9 (0x0200U << RI_CMR2_PB_Pos) /*!< 0x00000200 */ 6545 #define RI_CMR2_PB_10 (0x0400U << RI_CMR2_PB_Pos) /*!< 0x00000400 */ 6546 #define RI_CMR2_PB_11 (0x0800U << RI_CMR2_PB_Pos) /*!< 0x00000800 */ 6547 #define RI_CMR2_PB_12 (0x1000U << RI_CMR2_PB_Pos) /*!< 0x00001000 */ 6548 #define RI_CMR2_PB_13 (0x2000U << RI_CMR2_PB_Pos) /*!< 0x00002000 */ 6549 #define RI_CMR2_PB_14 (0x4000U << RI_CMR2_PB_Pos) /*!< 0x00004000 */ 6550 #define RI_CMR2_PB_15 (0x8000U << RI_CMR2_PB_Pos) /*!< 0x00008000 */ 6551 6552 /******************** Bit definition for RI_CICR2 register ********************/ 6553 #define RI_CICR2_PB_Pos (0U) 6554 #define RI_CICR2_PB_Msk (0xFFFFU << RI_CICR2_PB_Pos) /*!< 0x0000FFFF */ 6555 #define RI_CICR2_PB RI_CICR2_PB_Msk /*!< PB[15:0] Port B selection */ 6556 #define RI_CICR2_PB_0 (0x0001U << RI_CICR2_PB_Pos) /*!< 0x00000001 */ 6557 #define RI_CICR2_PB_1 (0x0002U << RI_CICR2_PB_Pos) /*!< 0x00000002 */ 6558 #define RI_CICR2_PB_2 (0x0004U << RI_CICR2_PB_Pos) /*!< 0x00000004 */ 6559 #define RI_CICR2_PB_3 (0x0008U << RI_CICR2_PB_Pos) /*!< 0x00000008 */ 6560 #define RI_CICR2_PB_4 (0x0010U << RI_CICR2_PB_Pos) /*!< 0x00000010 */ 6561 #define RI_CICR2_PB_5 (0x0020U << RI_CICR2_PB_Pos) /*!< 0x00000020 */ 6562 #define RI_CICR2_PB_6 (0x0040U << RI_CICR2_PB_Pos) /*!< 0x00000040 */ 6563 #define RI_CICR2_PB_7 (0x0080U << RI_CICR2_PB_Pos) /*!< 0x00000080 */ 6564 #define RI_CICR2_PB_8 (0x0100U << RI_CICR2_PB_Pos) /*!< 0x00000100 */ 6565 #define RI_CICR2_PB_9 (0x0200U << RI_CICR2_PB_Pos) /*!< 0x00000200 */ 6566 #define RI_CICR2_PB_10 (0x0400U << RI_CICR2_PB_Pos) /*!< 0x00000400 */ 6567 #define RI_CICR2_PB_11 (0x0800U << RI_CICR2_PB_Pos) /*!< 0x00000800 */ 6568 #define RI_CICR2_PB_12 (0x1000U << RI_CICR2_PB_Pos) /*!< 0x00001000 */ 6569 #define RI_CICR2_PB_13 (0x2000U << RI_CICR2_PB_Pos) /*!< 0x00002000 */ 6570 #define RI_CICR2_PB_14 (0x4000U << RI_CICR2_PB_Pos) /*!< 0x00004000 */ 6571 #define RI_CICR2_PB_15 (0x8000U << RI_CICR2_PB_Pos) /*!< 0x00008000 */ 6572 6573 /******************** Bit definition for RI_ASMR3 register ********************/ 6574 #define RI_ASMR3_PC_Pos (0U) 6575 #define RI_ASMR3_PC_Msk (0xFFFFU << RI_ASMR3_PC_Pos) /*!< 0x0000FFFF */ 6576 #define RI_ASMR3_PC RI_ASMR3_PC_Msk /*!< PC[15:0] Port C selection */ 6577 #define RI_ASMR3_PC_0 (0x0001U << RI_ASMR3_PC_Pos) /*!< 0x00000001 */ 6578 #define RI_ASMR3_PC_1 (0x0002U << RI_ASMR3_PC_Pos) /*!< 0x00000002 */ 6579 #define RI_ASMR3_PC_2 (0x0004U << RI_ASMR3_PC_Pos) /*!< 0x00000004 */ 6580 #define RI_ASMR3_PC_3 (0x0008U << RI_ASMR3_PC_Pos) /*!< 0x00000008 */ 6581 #define RI_ASMR3_PC_4 (0x0010U << RI_ASMR3_PC_Pos) /*!< 0x00000010 */ 6582 #define RI_ASMR3_PC_5 (0x0020U << RI_ASMR3_PC_Pos) /*!< 0x00000020 */ 6583 #define RI_ASMR3_PC_6 (0x0040U << RI_ASMR3_PC_Pos) /*!< 0x00000040 */ 6584 #define RI_ASMR3_PC_7 (0x0080U << RI_ASMR3_PC_Pos) /*!< 0x00000080 */ 6585 #define RI_ASMR3_PC_8 (0x0100U << RI_ASMR3_PC_Pos) /*!< 0x00000100 */ 6586 #define RI_ASMR3_PC_9 (0x0200U << RI_ASMR3_PC_Pos) /*!< 0x00000200 */ 6587 #define RI_ASMR3_PC_10 (0x0400U << RI_ASMR3_PC_Pos) /*!< 0x00000400 */ 6588 #define RI_ASMR3_PC_11 (0x0800U << RI_ASMR3_PC_Pos) /*!< 0x00000800 */ 6589 #define RI_ASMR3_PC_12 (0x1000U << RI_ASMR3_PC_Pos) /*!< 0x00001000 */ 6590 #define RI_ASMR3_PC_13 (0x2000U << RI_ASMR3_PC_Pos) /*!< 0x00002000 */ 6591 #define RI_ASMR3_PC_14 (0x4000U << RI_ASMR3_PC_Pos) /*!< 0x00004000 */ 6592 #define RI_ASMR3_PC_15 (0x8000U << RI_ASMR3_PC_Pos) /*!< 0x00008000 */ 6593 6594 /******************** Bit definition for RI_CMR3 register ********************/ 6595 #define RI_CMR3_PC_Pos (0U) 6596 #define RI_CMR3_PC_Msk (0xFFFFU << RI_CMR3_PC_Pos) /*!< 0x0000FFFF */ 6597 #define RI_CMR3_PC RI_CMR3_PC_Msk /*!< PC[15:0] Port C selection */ 6598 #define RI_CMR3_PC_0 (0x0001U << RI_CMR3_PC_Pos) /*!< 0x00000001 */ 6599 #define RI_CMR3_PC_1 (0x0002U << RI_CMR3_PC_Pos) /*!< 0x00000002 */ 6600 #define RI_CMR3_PC_2 (0x0004U << RI_CMR3_PC_Pos) /*!< 0x00000004 */ 6601 #define RI_CMR3_PC_3 (0x0008U << RI_CMR3_PC_Pos) /*!< 0x00000008 */ 6602 #define RI_CMR3_PC_4 (0x0010U << RI_CMR3_PC_Pos) /*!< 0x00000010 */ 6603 #define RI_CMR3_PC_5 (0x0020U << RI_CMR3_PC_Pos) /*!< 0x00000020 */ 6604 #define RI_CMR3_PC_6 (0x0040U << RI_CMR3_PC_Pos) /*!< 0x00000040 */ 6605 #define RI_CMR3_PC_7 (0x0080U << RI_CMR3_PC_Pos) /*!< 0x00000080 */ 6606 #define RI_CMR3_PC_8 (0x0100U << RI_CMR3_PC_Pos) /*!< 0x00000100 */ 6607 #define RI_CMR3_PC_9 (0x0200U << RI_CMR3_PC_Pos) /*!< 0x00000200 */ 6608 #define RI_CMR3_PC_10 (0x0400U << RI_CMR3_PC_Pos) /*!< 0x00000400 */ 6609 #define RI_CMR3_PC_11 (0x0800U << RI_CMR3_PC_Pos) /*!< 0x00000800 */ 6610 #define RI_CMR3_PC_12 (0x1000U << RI_CMR3_PC_Pos) /*!< 0x00001000 */ 6611 #define RI_CMR3_PC_13 (0x2000U << RI_CMR3_PC_Pos) /*!< 0x00002000 */ 6612 #define RI_CMR3_PC_14 (0x4000U << RI_CMR3_PC_Pos) /*!< 0x00004000 */ 6613 #define RI_CMR3_PC_15 (0x8000U << RI_CMR3_PC_Pos) /*!< 0x00008000 */ 6614 6615 /******************** Bit definition for RI_CICR3 register ********************/ 6616 #define RI_CICR3_PC_Pos (0U) 6617 #define RI_CICR3_PC_Msk (0xFFFFU << RI_CICR3_PC_Pos) /*!< 0x0000FFFF */ 6618 #define RI_CICR3_PC RI_CICR3_PC_Msk /*!< PC[15:0] Port C selection */ 6619 #define RI_CICR3_PC_0 (0x0001U << RI_CICR3_PC_Pos) /*!< 0x00000001 */ 6620 #define RI_CICR3_PC_1 (0x0002U << RI_CICR3_PC_Pos) /*!< 0x00000002 */ 6621 #define RI_CICR3_PC_2 (0x0004U << RI_CICR3_PC_Pos) /*!< 0x00000004 */ 6622 #define RI_CICR3_PC_3 (0x0008U << RI_CICR3_PC_Pos) /*!< 0x00000008 */ 6623 #define RI_CICR3_PC_4 (0x0010U << RI_CICR3_PC_Pos) /*!< 0x00000010 */ 6624 #define RI_CICR3_PC_5 (0x0020U << RI_CICR3_PC_Pos) /*!< 0x00000020 */ 6625 #define RI_CICR3_PC_6 (0x0040U << RI_CICR3_PC_Pos) /*!< 0x00000040 */ 6626 #define RI_CICR3_PC_7 (0x0080U << RI_CICR3_PC_Pos) /*!< 0x00000080 */ 6627 #define RI_CICR3_PC_8 (0x0100U << RI_CICR3_PC_Pos) /*!< 0x00000100 */ 6628 #define RI_CICR3_PC_9 (0x0200U << RI_CICR3_PC_Pos) /*!< 0x00000200 */ 6629 #define RI_CICR3_PC_10 (0x0400U << RI_CICR3_PC_Pos) /*!< 0x00000400 */ 6630 #define RI_CICR3_PC_11 (0x0800U << RI_CICR3_PC_Pos) /*!< 0x00000800 */ 6631 #define RI_CICR3_PC_12 (0x1000U << RI_CICR3_PC_Pos) /*!< 0x00001000 */ 6632 #define RI_CICR3_PC_13 (0x2000U << RI_CICR3_PC_Pos) /*!< 0x00002000 */ 6633 #define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */ 6634 #define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */ 6635 6636 /******************** Bit definition for RI_ASMR4 register ********************/ 6637 #define RI_ASMR4_PF_Pos (0U) 6638 #define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */ 6639 #define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */ 6640 #define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */ 6641 #define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */ 6642 #define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */ 6643 #define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */ 6644 #define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */ 6645 #define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */ 6646 #define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */ 6647 #define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */ 6648 #define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */ 6649 #define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */ 6650 #define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */ 6651 #define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */ 6652 #define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */ 6653 #define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */ 6654 #define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */ 6655 #define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */ 6656 6657 /******************** Bit definition for RI_CMR4 register ********************/ 6658 #define RI_CMR4_PF_Pos (0U) 6659 #define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */ 6660 #define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */ 6661 #define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */ 6662 #define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */ 6663 #define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */ 6664 #define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */ 6665 #define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */ 6666 #define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */ 6667 #define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */ 6668 #define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */ 6669 #define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */ 6670 #define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */ 6671 #define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */ 6672 #define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */ 6673 #define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */ 6674 #define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */ 6675 #define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */ 6676 #define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */ 6677 6678 /******************** Bit definition for RI_CICR4 register ********************/ 6679 #define RI_CICR4_PF_Pos (0U) 6680 #define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */ 6681 #define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */ 6682 #define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */ 6683 #define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */ 6684 #define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */ 6685 #define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */ 6686 #define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */ 6687 #define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */ 6688 #define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */ 6689 #define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */ 6690 #define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */ 6691 #define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */ 6692 #define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */ 6693 #define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */ 6694 #define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */ 6695 #define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */ 6696 #define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */ 6697 #define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */ 6698 6699 /******************** Bit definition for RI_ASMR5 register ********************/ 6700 #define RI_ASMR5_PG_Pos (0U) 6701 #define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */ 6702 #define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */ 6703 #define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */ 6704 #define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */ 6705 #define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */ 6706 #define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */ 6707 #define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */ 6708 #define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */ 6709 #define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */ 6710 #define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */ 6711 #define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */ 6712 #define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */ 6713 #define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */ 6714 #define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */ 6715 #define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */ 6716 #define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */ 6717 #define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */ 6718 #define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */ 6719 6720 /******************** Bit definition for RI_CMR5 register ********************/ 6721 #define RI_CMR5_PG_Pos (0U) 6722 #define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */ 6723 #define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */ 6724 #define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */ 6725 #define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */ 6726 #define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */ 6727 #define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */ 6728 #define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */ 6729 #define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */ 6730 #define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */ 6731 #define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */ 6732 #define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */ 6733 #define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */ 6734 #define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */ 6735 #define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */ 6736 #define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */ 6737 #define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */ 6738 #define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */ 6739 #define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */ 6740 6741 /******************** Bit definition for RI_CICR5 register ********************/ 6742 #define RI_CICR5_PG_Pos (0U) 6743 #define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */ 6744 #define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */ 6745 #define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */ 6746 #define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */ 6747 #define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */ 6748 #define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */ 6749 #define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */ 6750 #define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */ 6751 #define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */ 6752 #define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */ 6753 #define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */ 6754 #define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */ 6755 #define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */ 6756 #define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */ 6757 #define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */ 6758 #define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */ 6759 #define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */ 6760 #define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */ 6761 6762 /******************************************************************************/ 6763 /* */ 6764 /* Timers (TIM) */ 6765 /* */ 6766 /******************************************************************************/ 6767 6768 /******************* Bit definition for TIM_CR1 register ********************/ 6769 #define TIM_CR1_CEN_Pos (0U) 6770 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 6771 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 6772 #define TIM_CR1_UDIS_Pos (1U) 6773 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 6774 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 6775 #define TIM_CR1_URS_Pos (2U) 6776 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 6777 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 6778 #define TIM_CR1_OPM_Pos (3U) 6779 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 6780 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 6781 #define TIM_CR1_DIR_Pos (4U) 6782 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 6783 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 6784 6785 #define TIM_CR1_CMS_Pos (5U) 6786 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 6787 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 6788 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 6789 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 6790 6791 #define TIM_CR1_ARPE_Pos (7U) 6792 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 6793 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 6794 6795 #define TIM_CR1_CKD_Pos (8U) 6796 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 6797 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 6798 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 6799 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 6800 6801 /******************* Bit definition for TIM_CR2 register ********************/ 6802 #define TIM_CR2_CCDS_Pos (3U) 6803 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 6804 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 6805 6806 #define TIM_CR2_MMS_Pos (4U) 6807 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 6808 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 6809 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 6810 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 6811 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 6812 6813 #define TIM_CR2_TI1S_Pos (7U) 6814 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 6815 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 6816 6817 /******************* Bit definition for TIM_SMCR register *******************/ 6818 #define TIM_SMCR_SMS_Pos (0U) 6819 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 6820 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 6821 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 6822 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 6823 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 6824 6825 #define TIM_SMCR_OCCS_Pos (3U) 6826 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 6827 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 6828 6829 #define TIM_SMCR_TS_Pos (4U) 6830 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 6831 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 6832 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 6833 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 6834 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 6835 6836 #define TIM_SMCR_MSM_Pos (7U) 6837 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 6838 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 6839 6840 #define TIM_SMCR_ETF_Pos (8U) 6841 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 6842 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 6843 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 6844 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 6845 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 6846 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 6847 6848 #define TIM_SMCR_ETPS_Pos (12U) 6849 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 6850 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 6851 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 6852 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 6853 6854 #define TIM_SMCR_ECE_Pos (14U) 6855 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 6856 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 6857 #define TIM_SMCR_ETP_Pos (15U) 6858 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 6859 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 6860 6861 /******************* Bit definition for TIM_DIER register *******************/ 6862 #define TIM_DIER_UIE_Pos (0U) 6863 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 6864 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 6865 #define TIM_DIER_CC1IE_Pos (1U) 6866 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 6867 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 6868 #define TIM_DIER_CC2IE_Pos (2U) 6869 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 6870 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 6871 #define TIM_DIER_CC3IE_Pos (3U) 6872 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 6873 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 6874 #define TIM_DIER_CC4IE_Pos (4U) 6875 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 6876 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 6877 #define TIM_DIER_TIE_Pos (6U) 6878 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 6879 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 6880 #define TIM_DIER_UDE_Pos (8U) 6881 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 6882 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 6883 #define TIM_DIER_CC1DE_Pos (9U) 6884 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 6885 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 6886 #define TIM_DIER_CC2DE_Pos (10U) 6887 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 6888 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 6889 #define TIM_DIER_CC3DE_Pos (11U) 6890 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 6891 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 6892 #define TIM_DIER_CC4DE_Pos (12U) 6893 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 6894 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 6895 #define TIM_DIER_COMDE ((uint16_t)0x2000U) /*!<COM DMA request enable */ 6896 #define TIM_DIER_TDE_Pos (14U) 6897 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 6898 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 6899 6900 /******************** Bit definition for TIM_SR register ********************/ 6901 #define TIM_SR_UIF_Pos (0U) 6902 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 6903 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 6904 #define TIM_SR_CC1IF_Pos (1U) 6905 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 6906 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 6907 #define TIM_SR_CC2IF_Pos (2U) 6908 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 6909 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 6910 #define TIM_SR_CC3IF_Pos (3U) 6911 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 6912 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 6913 #define TIM_SR_CC4IF_Pos (4U) 6914 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 6915 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 6916 #define TIM_SR_TIF_Pos (6U) 6917 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 6918 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 6919 #define TIM_SR_CC1OF_Pos (9U) 6920 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 6921 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 6922 #define TIM_SR_CC2OF_Pos (10U) 6923 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 6924 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 6925 #define TIM_SR_CC3OF_Pos (11U) 6926 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 6927 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 6928 #define TIM_SR_CC4OF_Pos (12U) 6929 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 6930 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 6931 6932 /******************* Bit definition for TIM_EGR register ********************/ 6933 #define TIM_EGR_UG_Pos (0U) 6934 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 6935 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 6936 #define TIM_EGR_CC1G_Pos (1U) 6937 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 6938 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 6939 #define TIM_EGR_CC2G_Pos (2U) 6940 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 6941 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 6942 #define TIM_EGR_CC3G_Pos (3U) 6943 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 6944 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 6945 #define TIM_EGR_CC4G_Pos (4U) 6946 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 6947 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 6948 #define TIM_EGR_TG_Pos (6U) 6949 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 6950 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 6951 6952 /****************** Bit definition for TIM_CCMR1 register *******************/ 6953 #define TIM_CCMR1_CC1S_Pos (0U) 6954 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 6955 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 6956 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 6957 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 6958 6959 #define TIM_CCMR1_OC1FE_Pos (2U) 6960 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 6961 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 6962 #define TIM_CCMR1_OC1PE_Pos (3U) 6963 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 6964 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 6965 6966 #define TIM_CCMR1_OC1M_Pos (4U) 6967 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 6968 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 6969 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 6970 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 6971 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 6972 6973 #define TIM_CCMR1_OC1CE_Pos (7U) 6974 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 6975 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 6976 6977 #define TIM_CCMR1_CC2S_Pos (8U) 6978 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 6979 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 6980 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 6981 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 6982 6983 #define TIM_CCMR1_OC2FE_Pos (10U) 6984 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 6985 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 6986 #define TIM_CCMR1_OC2PE_Pos (11U) 6987 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 6988 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 6989 6990 #define TIM_CCMR1_OC2M_Pos (12U) 6991 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 6992 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 6993 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 6994 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 6995 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 6996 6997 #define TIM_CCMR1_OC2CE_Pos (15U) 6998 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 6999 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 7000 7001 /*----------------------------------------------------------------------------*/ 7002 7003 #define TIM_CCMR1_IC1PSC_Pos (2U) 7004 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 7005 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 7006 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 7007 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 7008 7009 #define TIM_CCMR1_IC1F_Pos (4U) 7010 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 7011 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 7012 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 7013 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 7014 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 7015 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 7016 7017 #define TIM_CCMR1_IC2PSC_Pos (10U) 7018 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 7019 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 7020 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 7021 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 7022 7023 #define TIM_CCMR1_IC2F_Pos (12U) 7024 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 7025 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 7026 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 7027 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 7028 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 7029 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 7030 7031 /****************** Bit definition for TIM_CCMR2 register *******************/ 7032 #define TIM_CCMR2_CC3S_Pos (0U) 7033 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 7034 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 7035 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 7036 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 7037 7038 #define TIM_CCMR2_OC3FE_Pos (2U) 7039 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 7040 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 7041 #define TIM_CCMR2_OC3PE_Pos (3U) 7042 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 7043 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 7044 7045 #define TIM_CCMR2_OC3M_Pos (4U) 7046 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 7047 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 7048 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 7049 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 7050 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 7051 7052 #define TIM_CCMR2_OC3CE_Pos (7U) 7053 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 7054 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 7055 7056 #define TIM_CCMR2_CC4S_Pos (8U) 7057 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 7058 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 7059 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 7060 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 7061 7062 #define TIM_CCMR2_OC4FE_Pos (10U) 7063 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 7064 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 7065 #define TIM_CCMR2_OC4PE_Pos (11U) 7066 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 7067 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 7068 7069 #define TIM_CCMR2_OC4M_Pos (12U) 7070 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 7071 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 7072 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 7073 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 7074 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 7075 7076 #define TIM_CCMR2_OC4CE_Pos (15U) 7077 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 7078 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 7079 7080 /*----------------------------------------------------------------------------*/ 7081 7082 #define TIM_CCMR2_IC3PSC_Pos (2U) 7083 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 7084 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 7085 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 7086 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 7087 7088 #define TIM_CCMR2_IC3F_Pos (4U) 7089 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 7090 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 7091 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 7092 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 7093 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 7094 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 7095 7096 #define TIM_CCMR2_IC4PSC_Pos (10U) 7097 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 7098 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 7099 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 7100 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 7101 7102 #define TIM_CCMR2_IC4F_Pos (12U) 7103 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 7104 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 7105 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 7106 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 7107 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 7108 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 7109 7110 /******************* Bit definition for TIM_CCER register *******************/ 7111 #define TIM_CCER_CC1E_Pos (0U) 7112 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 7113 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 7114 #define TIM_CCER_CC1P_Pos (1U) 7115 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 7116 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 7117 #define TIM_CCER_CC1NP_Pos (3U) 7118 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 7119 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 7120 #define TIM_CCER_CC2E_Pos (4U) 7121 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 7122 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 7123 #define TIM_CCER_CC2P_Pos (5U) 7124 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 7125 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 7126 #define TIM_CCER_CC2NP_Pos (7U) 7127 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 7128 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 7129 #define TIM_CCER_CC3E_Pos (8U) 7130 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 7131 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 7132 #define TIM_CCER_CC3P_Pos (9U) 7133 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 7134 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 7135 #define TIM_CCER_CC3NP_Pos (11U) 7136 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 7137 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 7138 #define TIM_CCER_CC4E_Pos (12U) 7139 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 7140 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 7141 #define TIM_CCER_CC4P_Pos (13U) 7142 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 7143 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 7144 #define TIM_CCER_CC4NP_Pos (15U) 7145 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 7146 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 7147 7148 /******************* Bit definition for TIM_CNT register ********************/ 7149 #define TIM_CNT_CNT_Pos (0U) 7150 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 7151 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 7152 7153 /******************* Bit definition for TIM_PSC register ********************/ 7154 #define TIM_PSC_PSC_Pos (0U) 7155 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 7156 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 7157 7158 /******************* Bit definition for TIM_ARR register ********************/ 7159 #define TIM_ARR_ARR_Pos (0U) 7160 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 7161 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 7162 7163 /******************* Bit definition for TIM_CCR1 register *******************/ 7164 #define TIM_CCR1_CCR1_Pos (0U) 7165 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 7166 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 7167 7168 /******************* Bit definition for TIM_CCR2 register *******************/ 7169 #define TIM_CCR2_CCR2_Pos (0U) 7170 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 7171 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 7172 7173 /******************* Bit definition for TIM_CCR3 register *******************/ 7174 #define TIM_CCR3_CCR3_Pos (0U) 7175 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 7176 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 7177 7178 /******************* Bit definition for TIM_CCR4 register *******************/ 7179 #define TIM_CCR4_CCR4_Pos (0U) 7180 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 7181 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 7182 7183 /******************* Bit definition for TIM_DCR register ********************/ 7184 #define TIM_DCR_DBA_Pos (0U) 7185 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 7186 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 7187 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 7188 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 7189 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 7190 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 7191 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 7192 7193 #define TIM_DCR_DBL_Pos (8U) 7194 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 7195 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 7196 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 7197 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 7198 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 7199 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 7200 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 7201 7202 /******************* Bit definition for TIM_DMAR register *******************/ 7203 #define TIM_DMAR_DMAB_Pos (0U) 7204 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 7205 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 7206 7207 /******************* Bit definition for TIM_OR register *********************/ 7208 #define TIM_OR_TI1RMP_Pos (0U) 7209 #define TIM_OR_TI1RMP_Msk (0x3U << TIM_OR_TI1RMP_Pos) /*!< 0x00000003 */ 7210 #define TIM_OR_TI1RMP TIM_OR_TI1RMP_Msk /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */ 7211 #define TIM_OR_TI1RMP_0 (0x1U << TIM_OR_TI1RMP_Pos) /*!< 0x00000001 */ 7212 #define TIM_OR_TI1RMP_1 (0x2U << TIM_OR_TI1RMP_Pos) /*!< 0x00000002 */ 7213 7214 #define TIM_OR_ETR_RMP_Pos (2U) 7215 #define TIM_OR_ETR_RMP_Msk (0x1U << TIM_OR_ETR_RMP_Pos) /*!< 0x00000004 */ 7216 #define TIM_OR_ETR_RMP TIM_OR_ETR_RMP_Msk /*!<ETR_RMP bit (TIM10/11 ETR remap)*/ 7217 #define TIM_OR_TI1_RMP_RI_Pos (3U) 7218 #define TIM_OR_TI1_RMP_RI_Msk (0x1U << TIM_OR_TI1_RMP_RI_Pos) /*!< 0x00000008 */ 7219 #define TIM_OR_TI1_RMP_RI TIM_OR_TI1_RMP_RI_Msk /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */ 7220 7221 /*----------------------------------------------------------------------------*/ 7222 #define TIM9_OR_ITR1_RMP_Pos (2U) 7223 #define TIM9_OR_ITR1_RMP_Msk (0x1U << TIM9_OR_ITR1_RMP_Pos) /*!< 0x00000004 */ 7224 #define TIM9_OR_ITR1_RMP TIM9_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */ 7225 7226 /*----------------------------------------------------------------------------*/ 7227 #define TIM2_OR_ITR1_RMP_Pos (0U) 7228 #define TIM2_OR_ITR1_RMP_Msk (0x1U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000001 */ 7229 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */ 7230 7231 /*----------------------------------------------------------------------------*/ 7232 #define TIM3_OR_ITR2_RMP_Pos (0U) 7233 #define TIM3_OR_ITR2_RMP_Msk (0x1U << TIM3_OR_ITR2_RMP_Pos) /*!< 0x00000001 */ 7234 #define TIM3_OR_ITR2_RMP TIM3_OR_ITR2_RMP_Msk /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */ 7235 7236 /*----------------------------------------------------------------------------*/ 7237 7238 /******************************************************************************/ 7239 /* */ 7240 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 7241 /* */ 7242 /******************************************************************************/ 7243 7244 /******************* Bit definition for USART_SR register *******************/ 7245 #define USART_SR_PE_Pos (0U) 7246 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */ 7247 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ 7248 #define USART_SR_FE_Pos (1U) 7249 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */ 7250 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ 7251 #define USART_SR_NE_Pos (2U) 7252 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */ 7253 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ 7254 #define USART_SR_ORE_Pos (3U) 7255 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */ 7256 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ 7257 #define USART_SR_IDLE_Pos (4U) 7258 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */ 7259 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ 7260 #define USART_SR_RXNE_Pos (5U) 7261 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */ 7262 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ 7263 #define USART_SR_TC_Pos (6U) 7264 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */ 7265 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ 7266 #define USART_SR_TXE_Pos (7U) 7267 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */ 7268 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ 7269 #define USART_SR_LBD_Pos (8U) 7270 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */ 7271 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ 7272 #define USART_SR_CTS_Pos (9U) 7273 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */ 7274 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ 7275 7276 /******************* Bit definition for USART_DR register *******************/ 7277 #define USART_DR_DR_Pos (0U) 7278 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */ 7279 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ 7280 7281 /****************** Bit definition for USART_BRR register *******************/ 7282 #define USART_BRR_DIV_FRACTION_Pos (0U) 7283 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 7284 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 7285 #define USART_BRR_DIV_MANTISSA_Pos (4U) 7286 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 7287 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 7288 7289 /****************** Bit definition for USART_CR1 register *******************/ 7290 #define USART_CR1_SBK_Pos (0U) 7291 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */ 7292 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ 7293 #define USART_CR1_RWU_Pos (1U) 7294 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */ 7295 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ 7296 #define USART_CR1_RE_Pos (2U) 7297 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ 7298 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 7299 #define USART_CR1_TE_Pos (3U) 7300 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ 7301 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 7302 #define USART_CR1_IDLEIE_Pos (4U) 7303 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 7304 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 7305 #define USART_CR1_RXNEIE_Pos (5U) 7306 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 7307 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 7308 #define USART_CR1_TCIE_Pos (6U) 7309 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 7310 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 7311 #define USART_CR1_TXEIE_Pos (7U) 7312 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 7313 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ 7314 #define USART_CR1_PEIE_Pos (8U) 7315 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 7316 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 7317 #define USART_CR1_PS_Pos (9U) 7318 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ 7319 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 7320 #define USART_CR1_PCE_Pos (10U) 7321 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 7322 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 7323 #define USART_CR1_WAKE_Pos (11U) 7324 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 7325 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ 7326 #define USART_CR1_M_Pos (12U) 7327 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */ 7328 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 7329 #define USART_CR1_UE_Pos (13U) 7330 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */ 7331 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 7332 #define USART_CR1_OVER8_Pos (15U) 7333 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 7334 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit mode */ 7335 7336 /****************** Bit definition for USART_CR2 register *******************/ 7337 #define USART_CR2_ADD_Pos (0U) 7338 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */ 7339 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 7340 #define USART_CR2_LBDL_Pos (5U) 7341 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 7342 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 7343 #define USART_CR2_LBDIE_Pos (6U) 7344 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 7345 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 7346 #define USART_CR2_LBCL_Pos (8U) 7347 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 7348 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 7349 #define USART_CR2_CPHA_Pos (9U) 7350 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 7351 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 7352 #define USART_CR2_CPOL_Pos (10U) 7353 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 7354 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 7355 #define USART_CR2_CLKEN_Pos (11U) 7356 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 7357 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 7358 7359 #define USART_CR2_STOP_Pos (12U) 7360 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 7361 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 7362 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 7363 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 7364 7365 #define USART_CR2_LINEN_Pos (14U) 7366 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 7367 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 7368 7369 /****************** Bit definition for USART_CR3 register *******************/ 7370 #define USART_CR3_EIE_Pos (0U) 7371 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 7372 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 7373 #define USART_CR3_IREN_Pos (1U) 7374 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 7375 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 7376 #define USART_CR3_IRLP_Pos (2U) 7377 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 7378 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 7379 #define USART_CR3_HDSEL_Pos (3U) 7380 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 7381 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 7382 #define USART_CR3_NACK_Pos (4U) 7383 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 7384 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ 7385 #define USART_CR3_SCEN_Pos (5U) 7386 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 7387 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ 7388 #define USART_CR3_DMAR_Pos (6U) 7389 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 7390 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 7391 #define USART_CR3_DMAT_Pos (7U) 7392 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 7393 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 7394 #define USART_CR3_RTSE_Pos (8U) 7395 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 7396 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 7397 #define USART_CR3_CTSE_Pos (9U) 7398 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 7399 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 7400 #define USART_CR3_CTSIE_Pos (10U) 7401 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 7402 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 7403 #define USART_CR3_ONEBIT_Pos (11U) 7404 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 7405 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 7406 7407 /****************** Bit definition for USART_GTPR register ******************/ 7408 #define USART_GTPR_PSC_Pos (0U) 7409 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 7410 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 7411 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ 7412 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ 7413 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ 7414 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ 7415 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ 7416 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ 7417 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ 7418 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ 7419 7420 #define USART_GTPR_GT_Pos (8U) 7421 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 7422 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ 7423 7424 /******************************************************************************/ 7425 /* */ 7426 /* Universal Serial Bus (USB) */ 7427 /* */ 7428 /******************************************************************************/ 7429 7430 /*!<Endpoint-specific registers */ 7431 7432 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */ 7433 #define USB_EP1R (USB_BASE + 0x00000004U) /*!< endpoint 1 register address */ 7434 #define USB_EP2R (USB_BASE + 0x00000008U) /*!< endpoint 2 register address */ 7435 #define USB_EP3R (USB_BASE + 0x0000000CU) /*!< endpoint 3 register address */ 7436 #define USB_EP4R (USB_BASE + 0x00000010U) /*!< endpoint 4 register address */ 7437 #define USB_EP5R (USB_BASE + 0x00000014U) /*!< endpoint 5 register address */ 7438 #define USB_EP6R (USB_BASE + 0x00000018U) /*!< endpoint 6 register address */ 7439 #define USB_EP7R (USB_BASE + 0x0000001CU) /*!< endpoint 7 register address */ 7440 7441 /* bit positions */ 7442 #define USB_EP_CTR_RX_Pos (15U) 7443 #define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ 7444 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ 7445 #define USB_EP_DTOG_RX_Pos (14U) 7446 #define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ 7447 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ 7448 #define USB_EPRX_STAT_Pos (12U) 7449 #define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ 7450 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ 7451 #define USB_EP_SETUP_Pos (11U) 7452 #define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */ 7453 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ 7454 #define USB_EP_T_FIELD_Pos (9U) 7455 #define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ 7456 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ 7457 #define USB_EP_KIND_Pos (8U) 7458 #define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */ 7459 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ 7460 #define USB_EP_CTR_TX_Pos (7U) 7461 #define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ 7462 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ 7463 #define USB_EP_DTOG_TX_Pos (6U) 7464 #define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ 7465 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ 7466 #define USB_EPTX_STAT_Pos (4U) 7467 #define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ 7468 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ 7469 #define USB_EPADDR_FIELD_Pos (0U) 7470 #define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ 7471 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ 7472 7473 /* EndPoint REGister MASK (no toggle fields) */ 7474 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) 7475 /*!< EP_TYPE[1:0] EndPoint TYPE */ 7476 #define USB_EP_TYPE_MASK_Pos (9U) 7477 #define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ 7478 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ 7479 #define USB_EP_BULK (0x00000000U) /*!< EndPoint BULK */ 7480 #define USB_EP_CONTROL (0x00000200U) /*!< EndPoint CONTROL */ 7481 #define USB_EP_ISOCHRONOUS (0x00000400U) /*!< EndPoint ISOCHRONOUS */ 7482 #define USB_EP_INTERRUPT (0x00000600U) /*!< EndPoint INTERRUPT */ 7483 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) 7484 7485 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ 7486 /*!< STAT_TX[1:0] STATus for TX transfer */ 7487 #define USB_EP_TX_DIS (0x00000000U) /*!< EndPoint TX DISabled */ 7488 #define USB_EP_TX_STALL (0x00000010U) /*!< EndPoint TX STALLed */ 7489 #define USB_EP_TX_NAK (0x00000020U) /*!< EndPoint TX NAKed */ 7490 #define USB_EP_TX_VALID (0x00000030U) /*!< EndPoint TX VALID */ 7491 #define USB_EPTX_DTOG1 (0x00000010U) /*!< EndPoint TX Data TOGgle bit1 */ 7492 #define USB_EPTX_DTOG2 (0x00000020U) /*!< EndPoint TX Data TOGgle bit2 */ 7493 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) 7494 /*!< STAT_RX[1:0] STATus for RX transfer */ 7495 #define USB_EP_RX_DIS (0x00000000U) /*!< EndPoint RX DISabled */ 7496 #define USB_EP_RX_STALL (0x00001000U) /*!< EndPoint RX STALLed */ 7497 #define USB_EP_RX_NAK (0x00002000U) /*!< EndPoint RX NAKed */ 7498 #define USB_EP_RX_VALID (0x00003000U) /*!< EndPoint RX VALID */ 7499 #define USB_EPRX_DTOG1 (0x00001000U) /*!< EndPoint RX Data TOGgle bit1 */ 7500 #define USB_EPRX_DTOG2 (0x00002000U) /*!< EndPoint RX Data TOGgle bit1 */ 7501 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) 7502 7503 /******************* Bit definition for USB_EP0R register *******************/ 7504 #define USB_EP0R_EA_Pos (0U) 7505 #define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */ 7506 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!<Endpoint Address */ 7507 7508 #define USB_EP0R_STAT_TX_Pos (4U) 7509 #define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ 7510 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 7511 #define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ 7512 #define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ 7513 7514 #define USB_EP0R_DTOG_TX_Pos (6U) 7515 #define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ 7516 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 7517 #define USB_EP0R_CTR_TX_Pos (7U) 7518 #define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ 7519 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 7520 #define USB_EP0R_EP_KIND_Pos (8U) 7521 #define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ 7522 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!<Endpoint Kind */ 7523 7524 #define USB_EP0R_EP_TYPE_Pos (9U) 7525 #define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ 7526 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 7527 #define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ 7528 #define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ 7529 7530 #define USB_EP0R_SETUP_Pos (11U) 7531 #define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ 7532 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!<Setup transaction completed */ 7533 7534 #define USB_EP0R_STAT_RX_Pos (12U) 7535 #define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ 7536 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 7537 #define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ 7538 #define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ 7539 7540 #define USB_EP0R_DTOG_RX_Pos (14U) 7541 #define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ 7542 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 7543 #define USB_EP0R_CTR_RX_Pos (15U) 7544 #define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ 7545 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!<Correct Transfer for reception */ 7546 7547 /******************* Bit definition for USB_EP1R register *******************/ 7548 #define USB_EP1R_EA_Pos (0U) 7549 #define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */ 7550 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!<Endpoint Address */ 7551 7552 #define USB_EP1R_STAT_TX_Pos (4U) 7553 #define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ 7554 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 7555 #define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ 7556 #define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ 7557 7558 #define USB_EP1R_DTOG_TX_Pos (6U) 7559 #define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ 7560 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 7561 #define USB_EP1R_CTR_TX_Pos (7U) 7562 #define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ 7563 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 7564 #define USB_EP1R_EP_KIND_Pos (8U) 7565 #define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ 7566 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!<Endpoint Kind */ 7567 7568 #define USB_EP1R_EP_TYPE_Pos (9U) 7569 #define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ 7570 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 7571 #define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ 7572 #define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ 7573 7574 #define USB_EP1R_SETUP_Pos (11U) 7575 #define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ 7576 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!<Setup transaction completed */ 7577 7578 #define USB_EP1R_STAT_RX_Pos (12U) 7579 #define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ 7580 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 7581 #define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ 7582 #define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ 7583 7584 #define USB_EP1R_DTOG_RX_Pos (14U) 7585 #define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ 7586 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 7587 #define USB_EP1R_CTR_RX_Pos (15U) 7588 #define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ 7589 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!<Correct Transfer for reception */ 7590 7591 /******************* Bit definition for USB_EP2R register *******************/ 7592 #define USB_EP2R_EA_Pos (0U) 7593 #define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */ 7594 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!<Endpoint Address */ 7595 7596 #define USB_EP2R_STAT_TX_Pos (4U) 7597 #define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ 7598 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 7599 #define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ 7600 #define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ 7601 7602 #define USB_EP2R_DTOG_TX_Pos (6U) 7603 #define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ 7604 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 7605 #define USB_EP2R_CTR_TX_Pos (7U) 7606 #define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ 7607 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 7608 #define USB_EP2R_EP_KIND_Pos (8U) 7609 #define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ 7610 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!<Endpoint Kind */ 7611 7612 #define USB_EP2R_EP_TYPE_Pos (9U) 7613 #define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ 7614 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 7615 #define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ 7616 #define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ 7617 7618 #define USB_EP2R_SETUP_Pos (11U) 7619 #define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ 7620 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!<Setup transaction completed */ 7621 7622 #define USB_EP2R_STAT_RX_Pos (12U) 7623 #define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ 7624 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 7625 #define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ 7626 #define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ 7627 7628 #define USB_EP2R_DTOG_RX_Pos (14U) 7629 #define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ 7630 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 7631 #define USB_EP2R_CTR_RX_Pos (15U) 7632 #define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ 7633 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!<Correct Transfer for reception */ 7634 7635 /******************* Bit definition for USB_EP3R register *******************/ 7636 #define USB_EP3R_EA_Pos (0U) 7637 #define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */ 7638 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!<Endpoint Address */ 7639 7640 #define USB_EP3R_STAT_TX_Pos (4U) 7641 #define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ 7642 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 7643 #define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ 7644 #define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ 7645 7646 #define USB_EP3R_DTOG_TX_Pos (6U) 7647 #define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ 7648 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 7649 #define USB_EP3R_CTR_TX_Pos (7U) 7650 #define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ 7651 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 7652 #define USB_EP3R_EP_KIND_Pos (8U) 7653 #define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ 7654 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!<Endpoint Kind */ 7655 7656 #define USB_EP3R_EP_TYPE_Pos (9U) 7657 #define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ 7658 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 7659 #define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ 7660 #define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ 7661 7662 #define USB_EP3R_SETUP_Pos (11U) 7663 #define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ 7664 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!<Setup transaction completed */ 7665 7666 #define USB_EP3R_STAT_RX_Pos (12U) 7667 #define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ 7668 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 7669 #define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ 7670 #define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ 7671 7672 #define USB_EP3R_DTOG_RX_Pos (14U) 7673 #define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ 7674 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 7675 #define USB_EP3R_CTR_RX_Pos (15U) 7676 #define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ 7677 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!<Correct Transfer for reception */ 7678 7679 /******************* Bit definition for USB_EP4R register *******************/ 7680 #define USB_EP4R_EA_Pos (0U) 7681 #define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */ 7682 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!<Endpoint Address */ 7683 7684 #define USB_EP4R_STAT_TX_Pos (4U) 7685 #define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ 7686 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 7687 #define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ 7688 #define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ 7689 7690 #define USB_EP4R_DTOG_TX_Pos (6U) 7691 #define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ 7692 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 7693 #define USB_EP4R_CTR_TX_Pos (7U) 7694 #define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ 7695 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 7696 #define USB_EP4R_EP_KIND_Pos (8U) 7697 #define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ 7698 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!<Endpoint Kind */ 7699 7700 #define USB_EP4R_EP_TYPE_Pos (9U) 7701 #define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ 7702 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 7703 #define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ 7704 #define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ 7705 7706 #define USB_EP4R_SETUP_Pos (11U) 7707 #define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ 7708 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!<Setup transaction completed */ 7709 7710 #define USB_EP4R_STAT_RX_Pos (12U) 7711 #define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ 7712 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 7713 #define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ 7714 #define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ 7715 7716 #define USB_EP4R_DTOG_RX_Pos (14U) 7717 #define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ 7718 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 7719 #define USB_EP4R_CTR_RX_Pos (15U) 7720 #define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ 7721 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!<Correct Transfer for reception */ 7722 7723 /******************* Bit definition for USB_EP5R register *******************/ 7724 #define USB_EP5R_EA_Pos (0U) 7725 #define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */ 7726 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!<Endpoint Address */ 7727 7728 #define USB_EP5R_STAT_TX_Pos (4U) 7729 #define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ 7730 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 7731 #define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ 7732 #define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ 7733 7734 #define USB_EP5R_DTOG_TX_Pos (6U) 7735 #define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ 7736 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 7737 #define USB_EP5R_CTR_TX_Pos (7U) 7738 #define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ 7739 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 7740 #define USB_EP5R_EP_KIND_Pos (8U) 7741 #define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ 7742 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!<Endpoint Kind */ 7743 7744 #define USB_EP5R_EP_TYPE_Pos (9U) 7745 #define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ 7746 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 7747 #define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ 7748 #define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ 7749 7750 #define USB_EP5R_SETUP_Pos (11U) 7751 #define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ 7752 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!<Setup transaction completed */ 7753 7754 #define USB_EP5R_STAT_RX_Pos (12U) 7755 #define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ 7756 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 7757 #define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ 7758 #define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ 7759 7760 #define USB_EP5R_DTOG_RX_Pos (14U) 7761 #define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ 7762 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 7763 #define USB_EP5R_CTR_RX_Pos (15U) 7764 #define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ 7765 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!<Correct Transfer for reception */ 7766 7767 /******************* Bit definition for USB_EP6R register *******************/ 7768 #define USB_EP6R_EA_Pos (0U) 7769 #define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */ 7770 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!<Endpoint Address */ 7771 7772 #define USB_EP6R_STAT_TX_Pos (4U) 7773 #define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ 7774 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 7775 #define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ 7776 #define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ 7777 7778 #define USB_EP6R_DTOG_TX_Pos (6U) 7779 #define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ 7780 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 7781 #define USB_EP6R_CTR_TX_Pos (7U) 7782 #define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ 7783 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 7784 #define USB_EP6R_EP_KIND_Pos (8U) 7785 #define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ 7786 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!<Endpoint Kind */ 7787 7788 #define USB_EP6R_EP_TYPE_Pos (9U) 7789 #define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ 7790 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 7791 #define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ 7792 #define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ 7793 7794 #define USB_EP6R_SETUP_Pos (11U) 7795 #define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ 7796 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!<Setup transaction completed */ 7797 7798 #define USB_EP6R_STAT_RX_Pos (12U) 7799 #define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ 7800 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 7801 #define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ 7802 #define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ 7803 7804 #define USB_EP6R_DTOG_RX_Pos (14U) 7805 #define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ 7806 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 7807 #define USB_EP6R_CTR_RX_Pos (15U) 7808 #define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ 7809 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!<Correct Transfer for reception */ 7810 7811 /******************* Bit definition for USB_EP7R register *******************/ 7812 #define USB_EP7R_EA_Pos (0U) 7813 #define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */ 7814 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!<Endpoint Address */ 7815 7816 #define USB_EP7R_STAT_TX_Pos (4U) 7817 #define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ 7818 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 7819 #define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ 7820 #define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ 7821 7822 #define USB_EP7R_DTOG_TX_Pos (6U) 7823 #define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ 7824 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */ 7825 #define USB_EP7R_CTR_TX_Pos (7U) 7826 #define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ 7827 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!<Correct Transfer for transmission */ 7828 #define USB_EP7R_EP_KIND_Pos (8U) 7829 #define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ 7830 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!<Endpoint Kind */ 7831 7832 #define USB_EP7R_EP_TYPE_Pos (9U) 7833 #define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ 7834 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */ 7835 #define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ 7836 #define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ 7837 7838 #define USB_EP7R_SETUP_Pos (11U) 7839 #define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ 7840 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!<Setup transaction completed */ 7841 7842 #define USB_EP7R_STAT_RX_Pos (12U) 7843 #define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ 7844 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */ 7845 #define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ 7846 #define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ 7847 7848 #define USB_EP7R_DTOG_RX_Pos (14U) 7849 #define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ 7850 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */ 7851 #define USB_EP7R_CTR_RX_Pos (15U) 7852 #define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ 7853 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!<Correct Transfer for reception */ 7854 7855 /*!<Common registers */ 7856 7857 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */ 7858 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */ 7859 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */ 7860 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */ 7861 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */ 7862 7863 7864 7865 /******************* Bit definition for USB_CNTR register *******************/ 7866 #define USB_CNTR_FRES_Pos (0U) 7867 #define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ 7868 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!<Force USB Reset */ 7869 #define USB_CNTR_PDWN_Pos (1U) 7870 #define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ 7871 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!<Power down */ 7872 #define USB_CNTR_LPMODE_Pos (2U) 7873 #define USB_CNTR_LPMODE_Msk (0x1U << USB_CNTR_LPMODE_Pos) /*!< 0x00000004 */ 7874 #define USB_CNTR_LPMODE USB_CNTR_LPMODE_Msk /*!<Low-power mode */ 7875 #define USB_CNTR_FSUSP_Pos (3U) 7876 #define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ 7877 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!<Force suspend */ 7878 #define USB_CNTR_RESUME_Pos (4U) 7879 #define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ 7880 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!<Resume request */ 7881 #define USB_CNTR_ESOFM_Pos (8U) 7882 #define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ 7883 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!<Expected Start Of Frame Interrupt Mask */ 7884 #define USB_CNTR_SOFM_Pos (9U) 7885 #define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ 7886 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!<Start Of Frame Interrupt Mask */ 7887 #define USB_CNTR_RESETM_Pos (10U) 7888 #define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ 7889 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!<RESET Interrupt Mask */ 7890 #define USB_CNTR_SUSPM_Pos (11U) 7891 #define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ 7892 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!<Suspend mode Interrupt Mask */ 7893 #define USB_CNTR_WKUPM_Pos (12U) 7894 #define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ 7895 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!<Wakeup Interrupt Mask */ 7896 #define USB_CNTR_ERRM_Pos (13U) 7897 #define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ 7898 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!<Error Interrupt Mask */ 7899 #define USB_CNTR_PMAOVRM_Pos (14U) 7900 #define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ 7901 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!<Packet Memory Area Over / Underrun Interrupt Mask */ 7902 #define USB_CNTR_CTRM_Pos (15U) 7903 #define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ 7904 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!<Correct Transfer Interrupt Mask */ 7905 7906 /******************* Bit definition for USB_ISTR register *******************/ 7907 #define USB_ISTR_EP_ID_Pos (0U) 7908 #define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ 7909 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!<Endpoint Identifier */ 7910 #define USB_ISTR_DIR_Pos (4U) 7911 #define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ 7912 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!<Direction of transaction */ 7913 #define USB_ISTR_ESOF_Pos (8U) 7914 #define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ 7915 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!<Expected Start Of Frame */ 7916 #define USB_ISTR_SOF_Pos (9U) 7917 #define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ 7918 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!<Start Of Frame */ 7919 #define USB_ISTR_RESET_Pos (10U) 7920 #define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ 7921 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!<USB RESET request */ 7922 #define USB_ISTR_SUSP_Pos (11U) 7923 #define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ 7924 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!<Suspend mode request */ 7925 #define USB_ISTR_WKUP_Pos (12U) 7926 #define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ 7927 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!<Wake up */ 7928 #define USB_ISTR_ERR_Pos (13U) 7929 #define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ 7930 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!<Error */ 7931 #define USB_ISTR_PMAOVR_Pos (14U) 7932 #define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ 7933 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!<Packet Memory Area Over / Underrun */ 7934 #define USB_ISTR_CTR_Pos (15U) 7935 #define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ 7936 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!<Correct Transfer */ 7937 7938 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ 7939 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ 7940 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ 7941 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ 7942 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ 7943 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ 7944 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ 7945 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ 7946 7947 7948 /******************* Bit definition for USB_FNR register ********************/ 7949 #define USB_FNR_FN_Pos (0U) 7950 #define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */ 7951 #define USB_FNR_FN USB_FNR_FN_Msk /*!<Frame Number */ 7952 #define USB_FNR_LSOF_Pos (11U) 7953 #define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ 7954 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!<Lost SOF */ 7955 #define USB_FNR_LCK_Pos (13U) 7956 #define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */ 7957 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!<Locked */ 7958 #define USB_FNR_RXDM_Pos (14U) 7959 #define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ 7960 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!<Receive Data - Line Status */ 7961 #define USB_FNR_RXDP_Pos (15U) 7962 #define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ 7963 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!<Receive Data + Line Status */ 7964 7965 /****************** Bit definition for USB_DADDR register *******************/ 7966 #define USB_DADDR_ADD_Pos (0U) 7967 #define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ 7968 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!<ADD[6:0] bits (Device Address) */ 7969 #define USB_DADDR_ADD0_Pos (0U) 7970 #define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ 7971 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!<Bit 0 */ 7972 #define USB_DADDR_ADD1_Pos (1U) 7973 #define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ 7974 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!<Bit 1 */ 7975 #define USB_DADDR_ADD2_Pos (2U) 7976 #define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ 7977 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!<Bit 2 */ 7978 #define USB_DADDR_ADD3_Pos (3U) 7979 #define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ 7980 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!<Bit 3 */ 7981 #define USB_DADDR_ADD4_Pos (4U) 7982 #define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ 7983 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!<Bit 4 */ 7984 #define USB_DADDR_ADD5_Pos (5U) 7985 #define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ 7986 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!<Bit 5 */ 7987 #define USB_DADDR_ADD6_Pos (6U) 7988 #define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ 7989 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!<Bit 6 */ 7990 7991 #define USB_DADDR_EF_Pos (7U) 7992 #define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */ 7993 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!<Enable Function */ 7994 7995 /****************** Bit definition for USB_BTABLE register ******************/ 7996 #define USB_BTABLE_BTABLE_Pos (3U) 7997 #define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ 7998 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!<Buffer Table */ 7999 8000 /*!< Buffer descriptor table */ 8001 /***************** Bit definition for USB_ADDR0_TX register *****************/ 8002 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U) 8003 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ 8004 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ 8005 8006 /***************** Bit definition for USB_ADDR1_TX register *****************/ 8007 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U) 8008 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ 8009 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ 8010 8011 /***************** Bit definition for USB_ADDR2_TX register *****************/ 8012 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U) 8013 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ 8014 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ 8015 8016 /***************** Bit definition for USB_ADDR3_TX register *****************/ 8017 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U) 8018 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ 8019 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ 8020 8021 /***************** Bit definition for USB_ADDR4_TX register *****************/ 8022 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U) 8023 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ 8024 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ 8025 8026 /***************** Bit definition for USB_ADDR5_TX register *****************/ 8027 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U) 8028 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ 8029 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ 8030 8031 /***************** Bit definition for USB_ADDR6_TX register *****************/ 8032 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U) 8033 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ 8034 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ 8035 8036 /***************** Bit definition for USB_ADDR7_TX register *****************/ 8037 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U) 8038 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ 8039 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ 8040 8041 /*----------------------------------------------------------------------------*/ 8042 8043 /***************** Bit definition for USB_COUNT0_TX register ****************/ 8044 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U) 8045 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ 8046 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ 8047 8048 /***************** Bit definition for USB_COUNT1_TX register ****************/ 8049 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U) 8050 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ 8051 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ 8052 8053 /***************** Bit definition for USB_COUNT2_TX register ****************/ 8054 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U) 8055 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ 8056 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ 8057 8058 /***************** Bit definition for USB_COUNT3_TX register ****************/ 8059 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U) 8060 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ 8061 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ 8062 8063 /***************** Bit definition for USB_COUNT4_TX register ****************/ 8064 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U) 8065 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ 8066 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ 8067 8068 /***************** Bit definition for USB_COUNT5_TX register ****************/ 8069 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U) 8070 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ 8071 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ 8072 8073 /***************** Bit definition for USB_COUNT6_TX register ****************/ 8074 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U) 8075 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ 8076 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ 8077 8078 /***************** Bit definition for USB_COUNT7_TX register ****************/ 8079 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U) 8080 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ 8081 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ 8082 8083 /*----------------------------------------------------------------------------*/ 8084 8085 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ 8086 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */ 8087 8088 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ 8089 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */ 8090 8091 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ 8092 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */ 8093 8094 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ 8095 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */ 8096 8097 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ 8098 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */ 8099 8100 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ 8101 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */ 8102 8103 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ 8104 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x00000000U03FF) /*!< Transmission Byte Count 3 (low) */ 8105 8106 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ 8107 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FFU0000) /*!< Transmission Byte Count 3 (high) */ 8108 8109 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ 8110 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */ 8111 8112 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ 8113 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */ 8114 8115 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ 8116 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */ 8117 8118 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ 8119 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */ 8120 8121 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ 8122 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */ 8123 8124 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ 8125 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */ 8126 8127 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ 8128 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */ 8129 8130 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ 8131 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */ 8132 8133 /*----------------------------------------------------------------------------*/ 8134 8135 /***************** Bit definition for USB_ADDR0_RX register *****************/ 8136 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U) 8137 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ 8138 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ 8139 8140 /***************** Bit definition for USB_ADDR1_RX register *****************/ 8141 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U) 8142 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ 8143 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ 8144 8145 /***************** Bit definition for USB_ADDR2_RX register *****************/ 8146 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U) 8147 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ 8148 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ 8149 8150 /***************** Bit definition for USB_ADDR3_RX register *****************/ 8151 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U) 8152 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ 8153 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ 8154 8155 /***************** Bit definition for USB_ADDR4_RX register *****************/ 8156 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U) 8157 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ 8158 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ 8159 8160 /***************** Bit definition for USB_ADDR5_RX register *****************/ 8161 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U) 8162 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ 8163 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ 8164 8165 /***************** Bit definition for USB_ADDR6_RX register *****************/ 8166 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U) 8167 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ 8168 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ 8169 8170 /***************** Bit definition for USB_ADDR7_RX register *****************/ 8171 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U) 8172 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ 8173 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ 8174 8175 /*----------------------------------------------------------------------------*/ 8176 8177 /***************** Bit definition for USB_COUNT0_RX register ****************/ 8178 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U) 8179 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ 8180 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ 8181 8182 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) 8183 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8184 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8185 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8186 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8187 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8188 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8189 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8190 8191 #define USB_COUNT0_RX_BLSIZE_Pos (15U) 8192 #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8193 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ 8194 8195 /***************** Bit definition for USB_COUNT1_RX register ****************/ 8196 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U) 8197 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ 8198 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ 8199 8200 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) 8201 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8202 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8203 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8204 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8205 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8206 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8207 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8208 8209 #define USB_COUNT1_RX_BLSIZE_Pos (15U) 8210 #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8211 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ 8212 8213 /***************** Bit definition for USB_COUNT2_RX register ****************/ 8214 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U) 8215 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ 8216 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ 8217 8218 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) 8219 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8220 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8221 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8222 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8223 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8224 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8225 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8226 8227 #define USB_COUNT2_RX_BLSIZE_Pos (15U) 8228 #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8229 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ 8230 8231 /***************** Bit definition for USB_COUNT3_RX register ****************/ 8232 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U) 8233 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ 8234 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ 8235 8236 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) 8237 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8238 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8239 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8240 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8241 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8242 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8243 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8244 8245 #define USB_COUNT3_RX_BLSIZE_Pos (15U) 8246 #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8247 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ 8248 8249 /***************** Bit definition for USB_COUNT4_RX register ****************/ 8250 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U) 8251 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ 8252 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ 8253 8254 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) 8255 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8256 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8257 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8258 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8259 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8260 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8261 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8262 8263 #define USB_COUNT4_RX_BLSIZE_Pos (15U) 8264 #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8265 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ 8266 8267 /***************** Bit definition for USB_COUNT5_RX register ****************/ 8268 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U) 8269 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ 8270 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ 8271 8272 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) 8273 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8274 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8275 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8276 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8277 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8278 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8279 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8280 8281 #define USB_COUNT5_RX_BLSIZE_Pos (15U) 8282 #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8283 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ 8284 8285 /***************** Bit definition for USB_COUNT6_RX register ****************/ 8286 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U) 8287 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ 8288 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ 8289 8290 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) 8291 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8292 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8293 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8294 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8295 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8296 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8297 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8298 8299 #define USB_COUNT6_RX_BLSIZE_Pos (15U) 8300 #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8301 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ 8302 8303 /***************** Bit definition for USB_COUNT7_RX register ****************/ 8304 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U) 8305 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ 8306 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ 8307 8308 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) 8309 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 8310 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 8311 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 8312 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 8313 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 8314 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 8315 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 8316 8317 #define USB_COUNT7_RX_BLSIZE_Pos (15U) 8318 #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ 8319 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ 8320 8321 /*----------------------------------------------------------------------------*/ 8322 8323 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ 8324 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8325 8326 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8327 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8328 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8329 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8330 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8331 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8332 8333 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8334 8335 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ 8336 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8337 8338 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8339 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */ 8340 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8341 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8342 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8343 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8344 8345 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8346 8347 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ 8348 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8349 8350 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8351 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8352 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8353 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8354 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8355 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8356 8357 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8358 8359 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ 8360 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8361 8362 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8363 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8364 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8365 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8366 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8367 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8368 8369 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8370 8371 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ 8372 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8373 8374 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8375 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8376 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8377 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8378 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8379 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8380 8381 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8382 8383 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ 8384 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8385 8386 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8387 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8388 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8389 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8390 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8391 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8392 8393 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8394 8395 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ 8396 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8397 8398 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8399 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8400 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8401 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8402 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8403 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8404 8405 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8406 8407 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ 8408 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8409 8410 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8411 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8412 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8413 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8414 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8415 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8416 8417 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8418 8419 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ 8420 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8421 8422 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8423 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8424 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8425 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8426 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8427 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8428 8429 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8430 8431 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ 8432 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8433 8434 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8435 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8436 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8437 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8438 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8439 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8440 8441 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8442 8443 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ 8444 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8445 8446 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8447 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8448 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8449 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8450 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8451 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8452 8453 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8454 8455 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ 8456 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8457 8458 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8459 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8460 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8461 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8462 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8463 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8464 8465 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8466 8467 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ 8468 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8469 8470 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8471 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8472 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8473 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8474 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8475 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8476 8477 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8478 8479 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ 8480 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8481 8482 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8483 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8484 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8485 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8486 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8487 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8488 8489 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8490 8491 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ 8492 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 8493 8494 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 8495 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 8496 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 8497 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 8498 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 8499 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 8500 8501 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 8502 8503 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ 8504 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 8505 8506 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 8507 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 8508 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 8509 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 8510 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 8511 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 8512 8513 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 8514 8515 /******************************************************************************/ 8516 /* */ 8517 /* Window WATCHDOG (WWDG) */ 8518 /* */ 8519 /******************************************************************************/ 8520 8521 /******************* Bit definition for WWDG_CR register ********************/ 8522 #define WWDG_CR_T_Pos (0U) 8523 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ 8524 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 8525 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */ 8526 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */ 8527 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */ 8528 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */ 8529 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */ 8530 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */ 8531 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */ 8532 8533 /* Legacy defines */ 8534 #define WWDG_CR_T0 WWDG_CR_T_0 8535 #define WWDG_CR_T1 WWDG_CR_T_1 8536 #define WWDG_CR_T2 WWDG_CR_T_2 8537 #define WWDG_CR_T3 WWDG_CR_T_3 8538 #define WWDG_CR_T4 WWDG_CR_T_4 8539 #define WWDG_CR_T5 WWDG_CR_T_5 8540 #define WWDG_CR_T6 WWDG_CR_T_6 8541 8542 #define WWDG_CR_WDGA_Pos (7U) 8543 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 8544 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 8545 8546 /******************* Bit definition for WWDG_CFR register *******************/ 8547 #define WWDG_CFR_W_Pos (0U) 8548 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 8549 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 8550 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 8551 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 8552 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 8553 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 8554 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 8555 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 8556 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 8557 8558 /* Legacy defines */ 8559 #define WWDG_CFR_W0 WWDG_CFR_W_0 8560 #define WWDG_CFR_W1 WWDG_CFR_W_1 8561 #define WWDG_CFR_W2 WWDG_CFR_W_2 8562 #define WWDG_CFR_W3 WWDG_CFR_W_3 8563 #define WWDG_CFR_W4 WWDG_CFR_W_4 8564 #define WWDG_CFR_W5 WWDG_CFR_W_5 8565 #define WWDG_CFR_W6 WWDG_CFR_W_6 8566 8567 #define WWDG_CFR_WDGTB_Pos (7U) 8568 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 8569 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 8570 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 8571 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 8572 8573 /* Legacy defines */ 8574 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 8575 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 8576 8577 #define WWDG_CFR_EWI_Pos (9U) 8578 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 8579 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 8580 8581 /******************* Bit definition for WWDG_SR register ********************/ 8582 #define WWDG_SR_EWIF_Pos (0U) 8583 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 8584 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 8585 8586 /******************************************************************************/ 8587 /* */ 8588 /* SystemTick (SysTick) */ 8589 /* */ 8590 /******************************************************************************/ 8591 8592 /***************** Bit definition for SysTick_CTRL register *****************/ 8593 #define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */ 8594 #define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */ 8595 #define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */ 8596 #define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */ 8597 8598 /***************** Bit definition for SysTick_LOAD register *****************/ 8599 #define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ 8600 8601 /***************** Bit definition for SysTick_VAL register ******************/ 8602 #define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */ 8603 8604 /***************** Bit definition for SysTick_CALIB register ****************/ 8605 #define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */ 8606 #define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */ 8607 #define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */ 8608 8609 /******************************************************************************/ 8610 /* */ 8611 /* Nested Vectored Interrupt Controller (NVIC) */ 8612 /* */ 8613 /******************************************************************************/ 8614 8615 /****************** Bit definition for NVIC_ISER register *******************/ 8616 #define NVIC_ISER_SETENA_Pos (0U) 8617 #define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ 8618 #define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ 8619 #define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ 8620 #define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ 8621 #define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ 8622 #define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ 8623 #define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ 8624 #define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ 8625 #define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ 8626 #define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ 8627 #define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ 8628 #define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ 8629 #define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ 8630 #define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ 8631 #define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ 8632 #define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ 8633 #define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ 8634 #define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ 8635 #define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ 8636 #define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ 8637 #define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ 8638 #define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ 8639 #define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ 8640 #define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ 8641 #define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ 8642 #define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ 8643 #define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ 8644 #define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ 8645 #define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ 8646 #define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ 8647 #define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ 8648 #define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ 8649 #define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ 8650 #define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ 8651 8652 /****************** Bit definition for NVIC_ICER register *******************/ 8653 #define NVIC_ICER_CLRENA_Pos (0U) 8654 #define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ 8655 #define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ 8656 #define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ 8657 #define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ 8658 #define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ 8659 #define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ 8660 #define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ 8661 #define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ 8662 #define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ 8663 #define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ 8664 #define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ 8665 #define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ 8666 #define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ 8667 #define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ 8668 #define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ 8669 #define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ 8670 #define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ 8671 #define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ 8672 #define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ 8673 #define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ 8674 #define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ 8675 #define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ 8676 #define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ 8677 #define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ 8678 #define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ 8679 #define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ 8680 #define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ 8681 #define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ 8682 #define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ 8683 #define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ 8684 #define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ 8685 #define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ 8686 #define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ 8687 #define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ 8688 8689 /****************** Bit definition for NVIC_ISPR register *******************/ 8690 #define NVIC_ISPR_SETPEND_Pos (0U) 8691 #define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ 8692 #define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ 8693 #define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ 8694 #define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ 8695 #define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ 8696 #define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ 8697 #define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ 8698 #define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ 8699 #define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ 8700 #define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ 8701 #define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ 8702 #define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ 8703 #define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ 8704 #define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ 8705 #define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ 8706 #define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ 8707 #define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ 8708 #define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ 8709 #define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ 8710 #define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ 8711 #define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ 8712 #define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ 8713 #define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ 8714 #define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ 8715 #define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ 8716 #define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ 8717 #define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ 8718 #define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ 8719 #define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ 8720 #define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ 8721 #define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ 8722 #define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ 8723 #define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ 8724 #define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ 8725 8726 /****************** Bit definition for NVIC_ICPR register *******************/ 8727 #define NVIC_ICPR_CLRPEND_Pos (0U) 8728 #define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ 8729 #define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ 8730 #define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ 8731 #define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ 8732 #define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ 8733 #define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ 8734 #define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ 8735 #define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ 8736 #define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ 8737 #define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ 8738 #define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ 8739 #define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ 8740 #define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ 8741 #define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ 8742 #define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ 8743 #define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ 8744 #define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ 8745 #define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ 8746 #define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ 8747 #define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ 8748 #define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ 8749 #define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ 8750 #define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ 8751 #define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ 8752 #define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ 8753 #define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ 8754 #define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ 8755 #define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ 8756 #define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ 8757 #define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ 8758 #define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ 8759 #define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ 8760 #define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ 8761 #define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ 8762 8763 /****************** Bit definition for NVIC_IABR register *******************/ 8764 #define NVIC_IABR_ACTIVE_Pos (0U) 8765 #define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ 8766 #define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ 8767 #define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ 8768 #define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ 8769 #define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ 8770 #define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ 8771 #define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ 8772 #define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ 8773 #define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ 8774 #define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ 8775 #define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ 8776 #define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ 8777 #define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ 8778 #define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ 8779 #define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ 8780 #define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ 8781 #define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ 8782 #define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ 8783 #define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ 8784 #define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ 8785 #define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ 8786 #define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ 8787 #define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ 8788 #define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ 8789 #define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ 8790 #define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ 8791 #define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ 8792 #define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ 8793 #define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ 8794 #define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ 8795 #define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ 8796 #define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ 8797 #define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ 8798 #define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ 8799 8800 /****************** Bit definition for NVIC_PRI0 register *******************/ 8801 #define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */ 8802 #define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */ 8803 #define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */ 8804 #define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */ 8805 8806 /****************** Bit definition for NVIC_PRI1 register *******************/ 8807 #define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */ 8808 #define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */ 8809 #define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */ 8810 #define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */ 8811 8812 /****************** Bit definition for NVIC_PRI2 register *******************/ 8813 #define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */ 8814 #define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */ 8815 #define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */ 8816 #define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */ 8817 8818 /****************** Bit definition for NVIC_PRI3 register *******************/ 8819 #define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */ 8820 #define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */ 8821 #define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */ 8822 #define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */ 8823 8824 /****************** Bit definition for NVIC_PRI4 register *******************/ 8825 #define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */ 8826 #define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */ 8827 #define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */ 8828 #define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */ 8829 8830 /****************** Bit definition for NVIC_PRI5 register *******************/ 8831 #define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */ 8832 #define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */ 8833 #define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */ 8834 #define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */ 8835 8836 /****************** Bit definition for NVIC_PRI6 register *******************/ 8837 #define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */ 8838 #define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */ 8839 #define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */ 8840 #define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */ 8841 8842 /****************** Bit definition for NVIC_PRI7 register *******************/ 8843 #define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */ 8844 #define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */ 8845 #define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */ 8846 #define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */ 8847 8848 /****************** Bit definition for SCB_CPUID register *******************/ 8849 #define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */ 8850 #define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */ 8851 #define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */ 8852 #define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */ 8853 #define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */ 8854 8855 /******************* Bit definition for SCB_ICSR register *******************/ 8856 #define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */ 8857 #define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ 8858 #define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */ 8859 #define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */ 8860 #define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ 8861 #define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */ 8862 #define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */ 8863 #define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */ 8864 #define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */ 8865 #define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */ 8866 8867 /******************* Bit definition for SCB_VTOR register *******************/ 8868 #define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */ 8869 #define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */ 8870 8871 /*!<***************** Bit definition for SCB_AIRCR register *******************/ 8872 #define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */ 8873 #define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */ 8874 #define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */ 8875 8876 #define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */ 8877 #define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */ 8878 #define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */ 8879 #define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */ 8880 8881 /* prority group configuration */ 8882 #define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ 8883 #define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ 8884 #define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ 8885 #define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ 8886 #define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ 8887 #define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ 8888 #define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ 8889 #define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ 8890 8891 #define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */ 8892 #define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ 8893 8894 /******************* Bit definition for SCB_SCR register ********************/ 8895 #define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */ 8896 #define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */ 8897 #define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */ 8898 8899 /******************** Bit definition for SCB_CCR register *******************/ 8900 #define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ 8901 #define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ 8902 #define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */ 8903 #define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */ 8904 #define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */ 8905 #define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ 8906 8907 /******************* Bit definition for SCB_SHPR register ********************/ 8908 #define SCB_SHPR_PRI_N_Pos (0U) 8909 #define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ 8910 #define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ 8911 #define SCB_SHPR_PRI_N1_Pos (8U) 8912 #define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ 8913 #define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ 8914 #define SCB_SHPR_PRI_N2_Pos (16U) 8915 #define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ 8916 #define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ 8917 #define SCB_SHPR_PRI_N3_Pos (24U) 8918 #define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ 8919 #define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ 8920 8921 /****************** Bit definition for SCB_SHCSR register *******************/ 8922 #define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */ 8923 #define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */ 8924 #define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */ 8925 #define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */ 8926 #define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */ 8927 #define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */ 8928 #define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */ 8929 #define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */ 8930 #define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */ 8931 #define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */ 8932 #define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */ 8933 #define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */ 8934 #define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */ 8935 #define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */ 8936 8937 /******************* Bit definition for SCB_CFSR register *******************/ 8938 /*!< MFSR */ 8939 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 8940 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 8941 #define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ 8942 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 8943 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 8944 #define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ 8945 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 8946 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 8947 #define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ 8948 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 8949 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 8950 #define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ 8951 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 8952 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 8953 #define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ 8954 /*!< BFSR */ 8955 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 8956 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 8957 #define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ 8958 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 8959 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 8960 #define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ 8961 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 8962 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 8963 #define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ 8964 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 8965 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 8966 #define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ 8967 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 8968 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 8969 #define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ 8970 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 8971 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 8972 #define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ 8973 /*!< UFSR */ 8974 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 8975 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 8976 #define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */ 8977 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 8978 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 8979 #define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ 8980 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 8981 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 8982 #define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ 8983 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 8984 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 8985 #define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ 8986 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 8987 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 8988 #define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ 8989 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 8990 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 8991 #define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ 8992 8993 /******************* Bit definition for SCB_HFSR register *******************/ 8994 #define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */ 8995 #define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ 8996 #define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */ 8997 8998 /******************* Bit definition for SCB_DFSR register *******************/ 8999 #define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */ 9000 #define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */ 9001 #define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */ 9002 #define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */ 9003 #define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */ 9004 9005 /******************* Bit definition for SCB_MMFAR register ******************/ 9006 #define SCB_MMFAR_ADDRESS_Pos (0U) 9007 #define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ 9008 #define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ 9009 9010 /******************* Bit definition for SCB_BFAR register *******************/ 9011 #define SCB_BFAR_ADDRESS_Pos (0U) 9012 #define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ 9013 #define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ 9014 9015 /******************* Bit definition for SCB_afsr register *******************/ 9016 #define SCB_AFSR_IMPDEF_Pos (0U) 9017 #define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ 9018 #define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ 9019 /** 9020 * @} 9021 */ 9022 9023 /** 9024 * @} 9025 */ 9026 /** @addtogroup Exported_macro 9027 * @{ 9028 */ 9029 9030 /****************************** ADC Instances *********************************/ 9031 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 9032 9033 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 9034 9035 /******************************** COMP Instances ******************************/ 9036 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ 9037 ((INSTANCE) == COMP2)) 9038 9039 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) 9040 9041 /****************************** CRC Instances *********************************/ 9042 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 9043 9044 /****************************** DAC Instances *********************************/ 9045 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC) 9046 9047 /****************************** DMA Instances *********************************/ 9048 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 9049 ((INSTANCE) == DMA1_Channel2) || \ 9050 ((INSTANCE) == DMA1_Channel3) || \ 9051 ((INSTANCE) == DMA1_Channel4) || \ 9052 ((INSTANCE) == DMA1_Channel5) || \ 9053 ((INSTANCE) == DMA1_Channel6) || \ 9054 ((INSTANCE) == DMA1_Channel7) || \ 9055 ((INSTANCE) == DMA2_Channel1) || \ 9056 ((INSTANCE) == DMA2_Channel2) || \ 9057 ((INSTANCE) == DMA2_Channel3) || \ 9058 ((INSTANCE) == DMA2_Channel4) || \ 9059 ((INSTANCE) == DMA2_Channel5)) 9060 9061 /******************************* GPIO Instances *******************************/ 9062 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 9063 ((INSTANCE) == GPIOB) || \ 9064 ((INSTANCE) == GPIOC) || \ 9065 ((INSTANCE) == GPIOD) || \ 9066 ((INSTANCE) == GPIOE) || \ 9067 ((INSTANCE) == GPIOF) || \ 9068 ((INSTANCE) == GPIOG) || \ 9069 ((INSTANCE) == GPIOH)) 9070 9071 /**************************** GPIO Alternate Function Instances ***************/ 9072 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 9073 9074 /**************************** GPIO Lock Instances *****************************/ 9075 /* On L1, all GPIO Bank support the Lock mechanism */ 9076 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 9077 9078 /******************************** I2C Instances *******************************/ 9079 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 9080 ((INSTANCE) == I2C2)) 9081 9082 /****************************** SMBUS Instances *******************************/ 9083 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 9084 9085 /******************************** I2S Instances *******************************/ 9086 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ 9087 ((INSTANCE) == SPI3)) 9088 /****************************** IWDG Instances ********************************/ 9089 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 9090 9091 /****************************** OPAMP Instances *******************************/ 9092 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \ 9093 ((INSTANCE) == OPAMP2)) 9094 9095 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) 9096 9097 /****************************** RTC Instances *********************************/ 9098 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 9099 9100 /******************************** SPI Instances *******************************/ 9101 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 9102 ((INSTANCE) == SPI2) || \ 9103 ((INSTANCE) == SPI3)) 9104 9105 /****************************** TIM Instances *********************************/ 9106 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9107 ((INSTANCE) == TIM3) || \ 9108 ((INSTANCE) == TIM4) || \ 9109 ((INSTANCE) == TIM5) || \ 9110 ((INSTANCE) == TIM6) || \ 9111 ((INSTANCE) == TIM7) || \ 9112 ((INSTANCE) == TIM9) || \ 9113 ((INSTANCE) == TIM10) || \ 9114 ((INSTANCE) == TIM11)) 9115 9116 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9117 ((INSTANCE) == TIM3) || \ 9118 ((INSTANCE) == TIM4) || \ 9119 ((INSTANCE) == TIM5) || \ 9120 ((INSTANCE) == TIM9) || \ 9121 ((INSTANCE) == TIM10) || \ 9122 ((INSTANCE) == TIM11)) 9123 9124 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9125 ((INSTANCE) == TIM3) || \ 9126 ((INSTANCE) == TIM4) || \ 9127 ((INSTANCE) == TIM5) || \ 9128 ((INSTANCE) == TIM9)) 9129 9130 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9131 ((INSTANCE) == TIM3) || \ 9132 ((INSTANCE) == TIM4) || \ 9133 ((INSTANCE) == TIM5)) 9134 9135 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9136 ((INSTANCE) == TIM3) || \ 9137 ((INSTANCE) == TIM4) || \ 9138 ((INSTANCE) == TIM5)) 9139 9140 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9141 ((INSTANCE) == TIM3) || \ 9142 ((INSTANCE) == TIM4) || \ 9143 ((INSTANCE) == TIM5) || \ 9144 ((INSTANCE) == TIM9)) 9145 9146 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9147 ((INSTANCE) == TIM3) || \ 9148 ((INSTANCE) == TIM4) || \ 9149 ((INSTANCE) == TIM5) || \ 9150 ((INSTANCE) == TIM9) || \ 9151 ((INSTANCE) == TIM10) || \ 9152 ((INSTANCE) == TIM11)) 9153 9154 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9155 ((INSTANCE) == TIM3) || \ 9156 ((INSTANCE) == TIM4) || \ 9157 ((INSTANCE) == TIM5) || \ 9158 ((INSTANCE) == TIM9)) 9159 9160 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9161 ((INSTANCE) == TIM3) || \ 9162 ((INSTANCE) == TIM4) || \ 9163 ((INSTANCE) == TIM5) || \ 9164 ((INSTANCE) == TIM9)) 9165 9166 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9167 ((INSTANCE) == TIM3) || \ 9168 ((INSTANCE) == TIM4)) 9169 9170 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9171 ((INSTANCE) == TIM3) || \ 9172 ((INSTANCE) == TIM4) || \ 9173 ((INSTANCE) == TIM5)) 9174 9175 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9176 ((INSTANCE) == TIM3) || \ 9177 ((INSTANCE) == TIM4) || \ 9178 ((INSTANCE) == TIM5)) 9179 9180 9181 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9182 ((INSTANCE) == TIM3) || \ 9183 ((INSTANCE) == TIM4) || \ 9184 ((INSTANCE) == TIM5) || \ 9185 ((INSTANCE) == TIM6) || \ 9186 ((INSTANCE) == TIM7) || \ 9187 ((INSTANCE) == TIM9)) 9188 9189 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9190 ((INSTANCE) == TIM3) || \ 9191 ((INSTANCE) == TIM4) || \ 9192 ((INSTANCE) == TIM5) || \ 9193 ((INSTANCE) == TIM9)) 9194 9195 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5) 9196 9197 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9198 ((INSTANCE) == TIM3) || \ 9199 ((INSTANCE) == TIM4) || \ 9200 ((INSTANCE) == TIM5)) 9201 9202 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 9203 ((((INSTANCE) == TIM2) && \ 9204 (((CHANNEL) == TIM_CHANNEL_1) || \ 9205 ((CHANNEL) == TIM_CHANNEL_2) || \ 9206 ((CHANNEL) == TIM_CHANNEL_3) || \ 9207 ((CHANNEL) == TIM_CHANNEL_4))) \ 9208 || \ 9209 (((INSTANCE) == TIM3) && \ 9210 (((CHANNEL) == TIM_CHANNEL_1) || \ 9211 ((CHANNEL) == TIM_CHANNEL_2) || \ 9212 ((CHANNEL) == TIM_CHANNEL_3) || \ 9213 ((CHANNEL) == TIM_CHANNEL_4))) \ 9214 || \ 9215 (((INSTANCE) == TIM4) && \ 9216 (((CHANNEL) == TIM_CHANNEL_1) || \ 9217 ((CHANNEL) == TIM_CHANNEL_2) || \ 9218 ((CHANNEL) == TIM_CHANNEL_3) || \ 9219 ((CHANNEL) == TIM_CHANNEL_4))) \ 9220 || \ 9221 (((INSTANCE) == TIM5) && \ 9222 (((CHANNEL) == TIM_CHANNEL_1) || \ 9223 ((CHANNEL) == TIM_CHANNEL_2) || \ 9224 ((CHANNEL) == TIM_CHANNEL_3) || \ 9225 ((CHANNEL) == TIM_CHANNEL_4))) \ 9226 || \ 9227 (((INSTANCE) == TIM9) && \ 9228 (((CHANNEL) == TIM_CHANNEL_1) || \ 9229 ((CHANNEL) == TIM_CHANNEL_2))) \ 9230 || \ 9231 (((INSTANCE) == TIM10) && \ 9232 (((CHANNEL) == TIM_CHANNEL_1))) \ 9233 || \ 9234 (((INSTANCE) == TIM11) && \ 9235 (((CHANNEL) == TIM_CHANNEL_1)))) 9236 9237 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9238 ((INSTANCE) == TIM3) || \ 9239 ((INSTANCE) == TIM4) || \ 9240 ((INSTANCE) == TIM5) || \ 9241 ((INSTANCE) == TIM9) || \ 9242 ((INSTANCE) == TIM10) || \ 9243 ((INSTANCE) == TIM11)) 9244 9245 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9246 ((INSTANCE) == TIM3) || \ 9247 ((INSTANCE) == TIM4) || \ 9248 ((INSTANCE) == TIM5) || \ 9249 ((INSTANCE) == TIM6) || \ 9250 ((INSTANCE) == TIM7)) 9251 9252 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9253 ((INSTANCE) == TIM3) || \ 9254 ((INSTANCE) == TIM4) || \ 9255 ((INSTANCE) == TIM5)) 9256 9257 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9258 ((INSTANCE) == TIM3) || \ 9259 ((INSTANCE) == TIM4) || \ 9260 ((INSTANCE) == TIM5) || \ 9261 ((INSTANCE) == TIM9)) 9262 9263 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9264 ((INSTANCE) == TIM3) || \ 9265 ((INSTANCE) == TIM4) || \ 9266 ((INSTANCE) == TIM5) || \ 9267 ((INSTANCE) == TIM9)) 9268 9269 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 9270 ((INSTANCE) == TIM3) || \ 9271 ((INSTANCE) == TIM9) || \ 9272 ((INSTANCE) == TIM10) || \ 9273 ((INSTANCE) == TIM11)) 9274 9275 /******************** USART Instances : Synchronous mode **********************/ 9276 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9277 ((INSTANCE) == USART2) || \ 9278 ((INSTANCE) == USART3)) 9279 9280 /******************** UART Instances : Asynchronous mode **********************/ 9281 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9282 ((INSTANCE) == USART2) || \ 9283 ((INSTANCE) == USART3) || \ 9284 ((INSTANCE) == UART4) || \ 9285 ((INSTANCE) == UART5)) 9286 9287 /******************** UART Instances : Half-Duplex mode **********************/ 9288 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9289 ((INSTANCE) == USART2) || \ 9290 ((INSTANCE) == USART3) || \ 9291 ((INSTANCE) == UART4) || \ 9292 ((INSTANCE) == UART5)) 9293 9294 /******************** UART Instances : LIN mode **********************/ 9295 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9296 ((INSTANCE) == USART2) || \ 9297 ((INSTANCE) == USART3) || \ 9298 ((INSTANCE) == UART4) || \ 9299 ((INSTANCE) == UART5)) 9300 9301 /****************** UART Instances : Hardware Flow control ********************/ 9302 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9303 ((INSTANCE) == USART2) || \ 9304 ((INSTANCE) == USART3)) 9305 9306 /********************* UART Instances : Smard card mode ***********************/ 9307 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9308 ((INSTANCE) == USART2) || \ 9309 ((INSTANCE) == USART3)) 9310 9311 /*********************** UART Instances : IRDA mode ***************************/ 9312 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9313 ((INSTANCE) == USART2) || \ 9314 ((INSTANCE) == USART3) || \ 9315 ((INSTANCE) == UART4) || \ 9316 ((INSTANCE) == UART5)) 9317 9318 /***************** UART Instances : Multi-Processor mode **********************/ 9319 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 9320 ((INSTANCE) == USART2) || \ 9321 ((INSTANCE) == USART3) || \ 9322 ((INSTANCE) == UART4) || \ 9323 ((INSTANCE) == UART5)) 9324 9325 /****************************** WWDG Instances ********************************/ 9326 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 9327 9328 9329 /****************************** LCD Instances ********************************/ 9330 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD) 9331 9332 /****************************** USB Instances ********************************/ 9333 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) 9334 9335 /** 9336 * @} 9337 */ 9338 9339 /******************************************************************************/ 9340 /* For a painless codes migration between the STM32L1xx device product */ 9341 /* lines, the aliases defined below are put in place to overcome the */ 9342 /* differences in the interrupt handlers and IRQn definitions. */ 9343 /* No need to update developed interrupt code when moving across */ 9344 /* product lines within the same STM32L1 Family */ 9345 /******************************************************************************/ 9346 9347 /* Aliases for __IRQn */ 9348 9349 /* Aliases for __IRQHandler */ 9350 9351 /** 9352 * @} 9353 */ 9354 9355 /** 9356 * @} 9357 */ 9358 9359 #ifdef __cplusplus 9360 } 9361 #endif /* __cplusplus */ 9362 9363 #endif /* __STM32L152xE_H */ 9364 9365 9366 9367 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 9368
