Searched refs:pllmul (Results 1 – 8 of 8) sorted by relevance
| /loramac-node-3.6.0-3.5.0/src/boards/SKiM881AXL/cmsis/ |
| D | system_stm32l0xx.c | 222 uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; in SystemCoreClockUpdate() local
241 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
243 pllmul = PLLMulTable[(pllmul >> 18U)]; in SystemCoreClockUpdate()
251 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
256 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
|
| /loramac-node-3.6.0-3.5.0/src/boards/NucleoL073/cmsis/ |
| D | system_stm32l0xx.c | 222 uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; in SystemCoreClockUpdate() local
241 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
243 pllmul = PLLMulTable[(pllmul >> 18U)]; in SystemCoreClockUpdate()
251 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
256 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
|
| /loramac-node-3.6.0-3.5.0/src/boards/B-L072Z-LRWAN1/cmsis/ |
| D | system_stm32l0xx.c | 222 uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; in SystemCoreClockUpdate() local
241 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
243 pllmul = PLLMulTable[(pllmul >> 18U)]; in SystemCoreClockUpdate()
251 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
256 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
|
| /loramac-node-3.6.0-3.5.0/src/boards/NucleoL152/cmsis/ |
| D | system_stm32l1xx.c | 229 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; in SystemCoreClockUpdate() local
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
250 pllmul = PLLMulTable[(pllmul >> 18)]; in SystemCoreClockUpdate()
258 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
263 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
|
| /loramac-node-3.6.0-3.5.0/src/boards/SKiM980A/cmsis/ |
| D | system_stm32l1xx.c | 229 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; in SystemCoreClockUpdate() local
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
250 pllmul = PLLMulTable[(pllmul >> 18)]; in SystemCoreClockUpdate()
258 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
263 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
|
| /loramac-node-3.6.0-3.5.0/src/boards/NAMote72/cmsis/ |
| D | system_stm32l1xx.c | 229 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; in SystemCoreClockUpdate() local
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
250 pllmul = PLLMulTable[(pllmul >> 18)]; in SystemCoreClockUpdate()
258 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
263 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
|
| /loramac-node-3.6.0-3.5.0/src/boards/SKiM880B/cmsis/ |
| D | system_stm32l1xx.c | 229 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; in SystemCoreClockUpdate() local
248 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in SystemCoreClockUpdate()
250 pllmul = PLLMulTable[(pllmul >> 18)]; in SystemCoreClockUpdate()
258 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
263 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
|
| /loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/ |
| D | stm32l0xx_hal_rcc_ex.c | 400 uint32_t pllmul = 0U, plldiv = 0U, pllvco = 0U; in HAL_RCCEx_GetPeriphCLKFreq() local
475 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; in HAL_RCCEx_GetPeriphCLKFreq()
477 pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)]; in HAL_RCCEx_GetPeriphCLKFreq()
497 pllvco = (pllvco * pllmul); in HAL_RCCEx_GetPeriphCLKFreq()
|
