Searched refs:plldiv (Results 1 – 8 of 8) sorted by relevance
| /loramac-node-3.6.0-3.5.0/src/boards/SKiM881AXL/cmsis/ |
| D | system_stm32l0xx.c | 222 uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; in SystemCoreClockUpdate() local
242 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
244 plldiv = (plldiv >> 22U) + 1U; in SystemCoreClockUpdate()
251 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
256 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
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| /loramac-node-3.6.0-3.5.0/src/boards/NucleoL073/cmsis/ |
| D | system_stm32l0xx.c | 222 uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; in SystemCoreClockUpdate() local
242 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
244 plldiv = (plldiv >> 22U) + 1U; in SystemCoreClockUpdate()
251 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
256 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
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| /loramac-node-3.6.0-3.5.0/src/boards/B-L072Z-LRWAN1/cmsis/ |
| D | system_stm32l0xx.c | 222 uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; in SystemCoreClockUpdate() local
242 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
244 plldiv = (plldiv >> 22U) + 1U; in SystemCoreClockUpdate()
251 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
256 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
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| /loramac-node-3.6.0-3.5.0/src/boards/NucleoL152/cmsis/ |
| D | system_stm32l1xx.c | 229 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; in SystemCoreClockUpdate() local
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
251 plldiv = (plldiv >> 22) + 1; in SystemCoreClockUpdate()
258 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
263 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
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| /loramac-node-3.6.0-3.5.0/src/boards/SKiM980A/cmsis/ |
| D | system_stm32l1xx.c | 229 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; in SystemCoreClockUpdate() local
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
251 plldiv = (plldiv >> 22) + 1; in SystemCoreClockUpdate()
258 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
263 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
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| /loramac-node-3.6.0-3.5.0/src/boards/NAMote72/cmsis/ |
| D | system_stm32l1xx.c | 229 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; in SystemCoreClockUpdate() local
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
251 plldiv = (plldiv >> 22) + 1; in SystemCoreClockUpdate()
258 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
263 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
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| /loramac-node-3.6.0-3.5.0/src/boards/SKiM880B/cmsis/ |
| D | system_stm32l1xx.c | 229 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; in SystemCoreClockUpdate() local
249 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in SystemCoreClockUpdate()
251 plldiv = (plldiv >> 22) + 1; in SystemCoreClockUpdate()
258 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
263 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); in SystemCoreClockUpdate()
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| /loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/ |
| D | stm32l0xx_hal_rcc_ex.c | 400 uint32_t pllmul = 0U, plldiv = 0U, pllvco = 0U; in HAL_RCCEx_GetPeriphCLKFreq() local
476 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; in HAL_RCCEx_GetPeriphCLKFreq()
478 plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U; in HAL_RCCEx_GetPeriphCLKFreq()
498 frequency = (pllvco/ plldiv); in HAL_RCCEx_GetPeriphCLKFreq()
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