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/loramac-node-3.6.0-3.5.0/src/boards/mcu/saml21/hri/
Dhri_gclk_l21.h136 static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) in hri_gclk_set_GENCTRL_GENEN_bit() argument
139 ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; in hri_gclk_set_GENCTRL_GENEN_bit()
143 static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) in hri_gclk_get_GENCTRL_GENEN_bit() argument
146 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
151 static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) in hri_gclk_write_GENCTRL_GENEN_bit() argument
155 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()
158 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()
162 static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) in hri_gclk_clear_GENCTRL_GENEN_bit() argument
165 ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; in hri_gclk_clear_GENCTRL_GENEN_bit()
169 static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) in hri_gclk_toggle_GENCTRL_GENEN_bit() argument
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Dhri_ccl_l21.h202 static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqct… in hri_ccl_set_SEQCTRL_SEQSEL_bf() argument
205 ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); in hri_ccl_set_SEQCTRL_SEQSEL_bf()
209 …tic inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, in hri_ccl_get_SEQCTRL_SEQSEL_bf() argument
213 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_get_SEQCTRL_SEQSEL_bf()
218 static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seq… in hri_ccl_write_SEQCTRL_SEQSEL_bf() argument
222 tmp = ((Ccl *)hw)->SEQCTRL[index].reg; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
225 ((Ccl *)hw)->SEQCTRL[index].reg = tmp; in hri_ccl_write_SEQCTRL_SEQSEL_bf()
229 static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seq… in hri_ccl_clear_SEQCTRL_SEQSEL_bf() argument
232 ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); in hri_ccl_clear_SEQCTRL_SEQSEL_bf()
236 static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_se… in hri_ccl_toggle_SEQCTRL_SEQSEL_bf() argument
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Dhri_opamp_l21.h202 static inline void hri_opamp_set_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) in hri_opamp_set_OPAMPCTRL_ENABLE_bit() argument
205 ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_ENABLE; in hri_opamp_set_OPAMPCTRL_ENABLE_bit()
209 static inline bool hri_opamp_get_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) in hri_opamp_get_OPAMPCTRL_ENABLE_bit() argument
212 tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; in hri_opamp_get_OPAMPCTRL_ENABLE_bit()
217 static inline void hri_opamp_write_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool v… in hri_opamp_write_OPAMPCTRL_ENABLE_bit() argument
221 tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; in hri_opamp_write_OPAMPCTRL_ENABLE_bit()
224 ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; in hri_opamp_write_OPAMPCTRL_ENABLE_bit()
228 static inline void hri_opamp_clear_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) in hri_opamp_clear_OPAMPCTRL_ENABLE_bit() argument
231 ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_ENABLE; in hri_opamp_clear_OPAMPCTRL_ENABLE_bit()
235 static inline void hri_opamp_toggle_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) in hri_opamp_toggle_OPAMPCTRL_ENABLE_bit() argument
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Dhri_eic_l21.h684 static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) in hri_eic_set_CONFIG_FILTEN0_bit() argument
687 ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; in hri_eic_set_CONFIG_FILTEN0_bit()
691 static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) in hri_eic_get_CONFIG_FILTEN0_bit() argument
694 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_get_CONFIG_FILTEN0_bit()
699 static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) in hri_eic_write_CONFIG_FILTEN0_bit() argument
703 tmp = ((Eic *)hw)->CONFIG[index].reg; in hri_eic_write_CONFIG_FILTEN0_bit()
706 ((Eic *)hw)->CONFIG[index].reg = tmp; in hri_eic_write_CONFIG_FILTEN0_bit()
710 static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) in hri_eic_clear_CONFIG_FILTEN0_bit() argument
713 ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; in hri_eic_clear_CONFIG_FILTEN0_bit()
717 static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) in hri_eic_toggle_CONFIG_FILTEN0_bit() argument
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Dhri_ac_l21.h914 static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_re… in hri_ac_set_SCALER_VALUE_bf() argument
917 ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); in hri_ac_set_SCALER_VALUE_bf()
921 static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, in hri_ac_get_SCALER_VALUE_bf() argument
925 tmp = ((Ac *)hw)->SCALER[index].reg; in hri_ac_get_SCALER_VALUE_bf()
930 static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_… in hri_ac_write_SCALER_VALUE_bf() argument
934 tmp = ((Ac *)hw)->SCALER[index].reg; in hri_ac_write_SCALER_VALUE_bf()
937 ((Ac *)hw)->SCALER[index].reg = tmp; in hri_ac_write_SCALER_VALUE_bf()
941 static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_… in hri_ac_clear_SCALER_VALUE_bf() argument
944 ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); in hri_ac_clear_SCALER_VALUE_bf()
948 static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler… in hri_ac_toggle_SCALER_VALUE_bf() argument
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Dhri_dac_l21.h308 static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t d… in hri_dac_write_DATA_reg() argument
311 ((Dac *)hw)->DATA[index].reg = data; in hri_dac_write_DATA_reg()
315 static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_r… in hri_dac_write_DATABUF_reg() argument
318 ((Dac *)hw)->DATABUF[index].reg = data; in hri_dac_write_DATABUF_reg()
835 static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) in hri_dac_set_DACCTRL_LEFTADJ_bit() argument
839 ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; in hri_dac_set_DACCTRL_LEFTADJ_bit()
843 static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) in hri_dac_get_DACCTRL_LEFTADJ_bit() argument
846 tmp = ((Dac *)hw)->DACCTRL[index].reg; in hri_dac_get_DACCTRL_LEFTADJ_bit()
851 static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool valu… in hri_dac_write_DACCTRL_LEFTADJ_bit() argument
856 tmp = ((Dac *)hw)->DACCTRL[index].reg; in hri_dac_write_DACCTRL_LEFTADJ_bit()
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Dhri_port_l21.h902 static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pm… in hri_portgroup_set_PMUX_PMUXE_bf() argument
905 ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); in hri_portgroup_set_PMUX_PMUXE_bf()
909 …tic inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, in hri_portgroup_get_PMUX_PMUXE_bf() argument
913 tmp = ((PortGroup *)hw)->PMUX[index].reg; in hri_portgroup_get_PMUX_PMUXE_bf()
918 static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_… in hri_portgroup_write_PMUX_PMUXE_bf() argument
922 tmp = ((PortGroup *)hw)->PMUX[index].reg; in hri_portgroup_write_PMUX_PMUXE_bf()
925 ((PortGroup *)hw)->PMUX[index].reg = tmp; in hri_portgroup_write_PMUX_PMUXE_bf()
929 static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_… in hri_portgroup_clear_PMUX_PMUXE_bf() argument
932 ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); in hri_portgroup_clear_PMUX_PMUXE_bf()
936 static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port… in hri_portgroup_toggle_PMUX_PMUXE_bf() argument
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Dhri_evsys_l21.h1236 static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) in hri_evsys_set_CHANNEL_RUNSTDBY_bit() argument
1239 ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_RUNSTDBY; in hri_evsys_set_CHANNEL_RUNSTDBY_bit()
1243 static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) in hri_evsys_get_CHANNEL_RUNSTDBY_bit() argument
1246 tmp = ((Evsys *)hw)->CHANNEL[index].reg; in hri_evsys_get_CHANNEL_RUNSTDBY_bit()
1251 static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool v… in hri_evsys_write_CHANNEL_RUNSTDBY_bit() argument
1255 tmp = ((Evsys *)hw)->CHANNEL[index].reg; in hri_evsys_write_CHANNEL_RUNSTDBY_bit()
1258 ((Evsys *)hw)->CHANNEL[index].reg = tmp; in hri_evsys_write_CHANNEL_RUNSTDBY_bit()
1262 static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) in hri_evsys_clear_CHANNEL_RUNSTDBY_bit() argument
1265 ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_RUNSTDBY; in hri_evsys_clear_CHANNEL_RUNSTDBY_bit()
1269 static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) in hri_evsys_toggle_CHANNEL_RUNSTDBY_bit() argument
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Dhri_dsu_l21.h409 static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t m… in hri_dsu_set_DCC_DATA_bf() argument
412 ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); in hri_dsu_set_DCC_DATA_bf()
416 static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_ds… in hri_dsu_get_DCC_DATA_bf() argument
419 tmp = ((Dsu *)hw)->DCC[index].reg; in hri_dsu_get_DCC_DATA_bf()
424 static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t… in hri_dsu_write_DCC_DATA_bf() argument
428 tmp = ((Dsu *)hw)->DCC[index].reg; in hri_dsu_write_DCC_DATA_bf()
431 ((Dsu *)hw)->DCC[index].reg = tmp; in hri_dsu_write_DCC_DATA_bf()
435 static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t… in hri_dsu_clear_DCC_DATA_bf() argument
438 ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); in hri_dsu_clear_DCC_DATA_bf()
442 static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_… in hri_dsu_toggle_DCC_DATA_bf() argument
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Dhri_tc_l21.h184 static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_… in hri_tccount16_set_CC_CC_bf() argument
187 ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); in hri_tccount16_set_CC_CC_bf()
191 static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, hri… in hri_tccount16_get_CC_CC_bf() argument
194 tmp = ((Tc *)hw)->COUNT16.CC[index].reg; in hri_tccount16_get_CC_CC_bf()
199 static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_re… in hri_tccount16_write_CC_CC_bf() argument
203 tmp = ((Tc *)hw)->COUNT16.CC[index].reg; in hri_tccount16_write_CC_CC_bf()
206 ((Tc *)hw)->COUNT16.CC[index].reg = tmp; in hri_tccount16_write_CC_CC_bf()
210 static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_re… in hri_tccount16_clear_CC_CC_bf() argument
213 ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); in hri_tccount16_clear_CC_CC_bf()
217 static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_r… in hri_tccount16_toggle_CC_CC_bf() argument
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Dhri_tcc_l21.h950 static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_r… in hri_tcc_set_CC_DITH4_DITHER_bf() argument
953 ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); in hri_tcc_set_CC_DITH4_DITHER_bf()
957 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, in hri_tcc_get_CC_DITH4_DITHER_bf() argument
961 tmp = ((Tcc *)hw)->CC[index].reg; in hri_tcc_get_CC_DITH4_DITHER_bf()
966 static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc… in hri_tcc_write_CC_DITH4_DITHER_bf() argument
970 tmp = ((Tcc *)hw)->CC[index].reg; in hri_tcc_write_CC_DITH4_DITHER_bf()
973 ((Tcc *)hw)->CC[index].reg = tmp; in hri_tcc_write_CC_DITH4_DITHER_bf()
977 static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc… in hri_tcc_clear_CC_DITH4_DITHER_bf() argument
980 ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); in hri_tcc_clear_CC_DITH4_DITHER_bf()
984 static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_c… in hri_tcc_toggle_CC_DITH4_DITHER_bf() argument
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Dhri_aes_l21.h218 static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_r… in hri_aes_write_KEYWORD_reg() argument
221 ((Aes *)hw)->KEYWORD[index].reg = data; in hri_aes_write_KEYWORD_reg()
225 static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv… in hri_aes_write_INTVECTV_reg() argument
228 ((Aes *)hw)->INTVECTV[index].reg = data; in hri_aes_write_INTVECTV_reg()
1052 static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg… in hri_aes_set_HASHKEY_reg() argument
1055 ((Aes *)hw)->HASHKEY[index].reg |= mask; in hri_aes_set_HASHKEY_reg()
1059 static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, in hri_aes_get_HASHKEY_reg() argument
1063 tmp = ((Aes *)hw)->HASHKEY[index].reg; in hri_aes_get_HASHKEY_reg()
1068 static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_r… in hri_aes_write_HASHKEY_reg() argument
1071 ((Aes *)hw)->HASHKEY[index].reg = data; in hri_aes_write_HASHKEY_reg()
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Dhri_rtc_l21.h2921 static inline void hri_rtcmode2_set_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg… in hri_rtcmode2_set_GP_reg() argument
2924 ((Rtc *)hw)->MODE2.GP[index].reg |= mask; in hri_rtcmode2_set_GP_reg()
2928 static inline hri_rtcmode2_gp_reg_t hri_rtcmode2_get_GP_reg(const void *const hw, uint8_t index, in hri_rtcmode2_get_GP_reg() argument
2932 tmp = ((Rtc *)hw)->MODE2.GP[index].reg; in hri_rtcmode2_get_GP_reg()
2937 static inline void hri_rtcmode2_write_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_r… in hri_rtcmode2_write_GP_reg() argument
2940 ((Rtc *)hw)->MODE2.GP[index].reg = data; in hri_rtcmode2_write_GP_reg()
2944 static inline void hri_rtcmode2_clear_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_r… in hri_rtcmode2_clear_GP_reg() argument
2947 ((Rtc *)hw)->MODE2.GP[index].reg &= ~mask; in hri_rtcmode2_clear_GP_reg()
2951 static inline void hri_rtcmode2_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_… in hri_rtcmode2_toggle_GP_reg() argument
2954 ((Rtc *)hw)->MODE2.GP[index].reg ^= mask; in hri_rtcmode2_toggle_GP_reg()
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/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_crc.c240 uint32_t index = 0; in HAL_CRC_Accumulate() local
249 for(index = 0; index < BufferLength; index++) in HAL_CRC_Accumulate()
251 hcrc->Instance->DR = pBuffer[index]; in HAL_CRC_Accumulate()
275 uint32_t index = 0; in HAL_CRC_Calculate() local
287 for(index = 0; index < BufferLength; index++) in HAL_CRC_Calculate()
289 hcrc->Instance->DR = pBuffer[index]; in HAL_CRC_Calculate()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_cryp_ex.c450 uint32_t index ; in HAL_CRYPEx_AES_Auth() local
572 for(index=0U ; (index < Size); index += 16U) in HAL_CRYPEx_AES_Auth()
595 index_test = (uint64_t)index + 16U; in HAL_CRYPEx_AES_Auth()
629 for(index=0U ; index < headerlength; index += 16U) in HAL_CRYPEx_AES_Auth()
653 index_temp = (uint64_t)index + 16U; in HAL_CRYPEx_AES_Auth()
716 for(index=0U ; index < payloadlength; index += 16U) in HAL_CRYPEx_AES_Auth()
752 index_temp = (uint64_t)index + 16U; in HAL_CRYPEx_AES_Auth()
965 uint32_t index ; in HAL_CRYPEx_AES_Auth_IT() local
1165 for(index=0U ; index < (difflength/4U); index ++) in HAL_CRYPEx_AES_Auth_IT()
1178 for(index=0U; index < (4U - ((difflength+3U)/4U)); index ++) in HAL_CRYPEx_AES_Auth_IT()
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Dstm32l4xx_hal_crc.c305 uint32_t index; /* CRC input data buffer index */ in HAL_CRC_Accumulate() local
315 for (index = 0U; index < BufferLength; index++) in HAL_CRC_Accumulate()
317 hcrc->Instance->DR = pBuffer[index]; in HAL_CRC_Accumulate()
357 uint32_t index; /* CRC input data buffer index */ in HAL_CRC_Calculate() local
371 for (index = 0U; index < BufferLength; index++) in HAL_CRC_Calculate()
373 hcrc->Instance->DR = pBuffer[index]; in HAL_CRC_Calculate()
Dstm32l4xx_hal_nand.c447 __IO uint32_t index = 0; in HAL_NAND_Read_Page_8b() local
555 for(; index < size; index++) in HAL_NAND_Read_Page_8b()
590 __IO uint32_t index = 0; in HAL_NAND_Read_Page_16b() local
697 for (; index < size; index++) in HAL_NAND_Read_Page_16b()
732 __IO uint32_t index = 0; in HAL_NAND_Write_Page_8b() local
819 for (; index < size; index++) in HAL_NAND_Write_Page_8b()
870 __IO uint32_t index = 0; in HAL_NAND_Write_Page_16b() local
957 for(; index < size; index++) in HAL_NAND_Write_Page_16b()
1008 __IO uint32_t index = 0; in HAL_NAND_Read_SpareArea_8b() local
1122 for (; index < size; index++) in HAL_NAND_Read_SpareArea_8b()
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Dstm32l4xx_hal_ospi.c2468 uint8_t index, ospi_enabled = 0U, other_instance; in HAL_OSPIM_Config() local
2493 for (index = 0U; index < OSPI_NB_INSTANCE; index++) in HAL_OSPIM_Config()
2495 if (OSPIM_GetConfig(index+1U, &(IOM_cfg[index])) != HAL_OK) in HAL_OSPIM_Config()
2931 uint32_t index; in OSPIM_GetConfig() local
2953 for (index = 0U; index < OSPI_IOM_NB_PORTS; index ++) in OSPIM_GetConfig()
2955 reg = OCTOSPIM->PCR[index]; in OSPIM_GetConfig()
2963 cfg->ClkPort = index+1U; in OSPIM_GetConfig()
2973 cfg->DQSPort = index+1U; in OSPIM_GetConfig()
2983 cfg->NCSPort = index+1U; in OSPIM_GetConfig()
2995 cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1U)); in OSPIM_GetConfig()
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/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_hal_crc.c319 uint32_t index = 0U; /* CRC input data buffer index */ in HAL_CRC_Accumulate() local
332 for(index = 0U; index < BufferLength; index++) in HAL_CRC_Accumulate()
334 hcrc->Instance->DR = pBuffer[index]; in HAL_CRC_Accumulate()
378 uint32_t index = 0U; /* CRC input data buffer index */ in HAL_CRC_Calculate() local
395 for(index = 0U; index < BufferLength; index++) in HAL_CRC_Calculate()
397 hcrc->Instance->DR = pBuffer[index]; in HAL_CRC_Calculate()
/loramac-node-3.6.0-3.5.0/src/boards/SAMR34/
Dsx1276-board.c134 static void DioIrqHanlderProcess( uint8_t index ) in DioIrqHanlderProcess() argument
136 if( ( DioIrqs[index] != NULL ) && ( DioIrqs[index]->IrqHandler != NULL ) ) in DioIrqHanlderProcess()
138 DioIrqs[index]->IrqHandler( DioIrqs[index]->Context ); in DioIrqHanlderProcess()
162 static void IoIrqInit( uint8_t index, DioIrqHandler *irqHandler ) in IoIrqInit() argument
164 DioIrqs[index]->IrqHandler = irqHandler; in IoIrqInit()
165 ext_irq_register( DioIrqs[index]->pin, ExtIrqHandlers[index] ); in IoIrqInit()
/loramac-node-3.6.0-3.5.0/src/apps/LoRaMac/common/LmHandler/packages/
DFragDecoder.c121 static uint8_t GetParity( uint16_t index, uint8_t *matrixRow );
130 static void SetParity( uint16_t index, uint8_t *matrixRow, uint8_t parity );
522 static uint8_t GetParity( uint16_t index, uint8_t *matrixRow ) in GetParity() argument
525 parity = matrixRow[index >> 3]; in GetParity()
526 parity = ( parity >> ( 7 - ( index % 8 ) ) ) & 0x01; in GetParity()
530 static void SetParity( uint16_t index, uint8_t *matrixRow, uint8_t parity ) in SetParity() argument
532 uint8_t mask = 0xFF - ( 1 << ( 7 - ( index % 8 ) ) ); in SetParity()
533 parity = parity << ( 7 - ( index % 8 ) ); in SetParity()
534 matrixRow[index >> 3] = ( matrixRow[index >> 3] & mask ) + parity; in SetParity()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/cmsis/
Darm_math.h570 uint32_t index, i; in arm_recip_q31() local
586 index = (uint32_t)(in >> 24); in arm_recip_q31()
587 index = (index & INDEX_MASK); in arm_recip_q31()
590 out = pRecipTable[index]; in arm_recip_q31()
621 uint32_t index = 0, i = 0; in arm_recip_q15() local
637 index = (uint32_t)(in >> 8); in arm_recip_q15()
638 index = (index & INDEX_MASK); in arm_recip_q15()
641 out = pRecipTable[index]; in arm_recip_q15()
5498 int32_t index; /* Index to read nearest output values */ in arm_linear_interp_q31() local
5503 index = ((x & (q31_t)0xFFF00000) >> 20); in arm_linear_interp_q31()
[all …]
/loramac-node-3.6.0-3.5.0/src/boards/mcu/saml21/cmsis/
Darm_math.h554 uint32_t index, i; in arm_recip_q31() local
570 index = (uint32_t) (in >> 24u); in arm_recip_q31()
571 index = (index & INDEX_MASK); in arm_recip_q31()
574 out = pRecipTable[index]; in arm_recip_q31()
605 uint32_t index = 0, i = 0; in arm_recip_q15() local
621 index = in >> 8; in arm_recip_q15()
622 index = (index & INDEX_MASK); in arm_recip_q15()
625 out = pRecipTable[index]; in arm_recip_q15()
5836 int32_t index; /* Index to read nearest output values */ in arm_linear_interp_q31() local
5841 index = ((x & 0xFFF00000) >> 20); in arm_linear_interp_q31()
[all …]
/loramac-node-3.6.0-3.5.0/src/system/
Dfifo.c25 static uint16_t FifoNext( Fifo_t *fifo, uint16_t index ) in FifoNext() argument
27 return ( index + 1 ) % fifo->Size; in FifoNext()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/EEPROM_Emul/Core/
Deeprom_emul.c1469 uint32_t index = 0U; in VerifyPagesFullWriteVariable() local
1472 for (index = 0U; index < 31U; index++) in VerifyPagesFullWriteVariable()
1474 if (puhVirtAdd[index] == VirtAddress) in VerifyPagesFullWriteVariable()
1476 LL_RTC_BAK_SetRegister(RTC, index, Data); in VerifyPagesFullWriteVariable()

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