1 /**
2 * \file
3 *
4 * \brief SAM PORT
5 *
6 * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 */
42
43 #ifdef _SAML21_PORT_COMPONENT_
44 #ifndef _HRI_PORT_L21_H_INCLUDED_
45 #define _HRI_PORT_L21_H_INCLUDED_
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53
54 #if defined(ENABLE_PORT_CRITICAL_SECTIONS)
55 #define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define PORT_CRITICAL_SECTION_ENTER()
59 #define PORT_CRITICAL_SECTION_LEAVE()
60 #endif
61
62 typedef uint32_t hri_port_ctrl_reg_t;
63 typedef uint32_t hri_port_dir_reg_t;
64 typedef uint32_t hri_port_evctrl_reg_t;
65 typedef uint32_t hri_port_in_reg_t;
66 typedef uint32_t hri_port_out_reg_t;
67 typedef uint32_t hri_port_wrconfig_reg_t;
68 typedef uint32_t hri_portgroup_ctrl_reg_t;
69 typedef uint32_t hri_portgroup_dir_reg_t;
70 typedef uint32_t hri_portgroup_evctrl_reg_t;
71 typedef uint32_t hri_portgroup_in_reg_t;
72 typedef uint32_t hri_portgroup_out_reg_t;
73 typedef uint32_t hri_portgroup_wrconfig_reg_t;
74 typedef uint8_t hri_port_pincfg_reg_t;
75 typedef uint8_t hri_port_pmux_reg_t;
76 typedef uint8_t hri_portgroup_pincfg_reg_t;
77 typedef uint8_t hri_portgroup_pmux_reg_t;
78
hri_portgroup_set_DIR_DIR_bf(const void * const hw,hri_port_dir_reg_t mask)79 static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
80 {
81 ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask);
82 }
83
hri_portgroup_get_DIR_DIR_bf(const void * const hw,hri_port_dir_reg_t mask)84 static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
85 {
86 uint32_t tmp;
87 tmp = ((PortGroup *)hw)->DIR.reg;
88 tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
89 return tmp;
90 }
91
hri_portgroup_read_DIR_DIR_bf(const void * const hw)92 static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw)
93 {
94 uint32_t tmp;
95 tmp = ((PortGroup *)hw)->DIR.reg;
96 tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
97 return tmp;
98 }
99
hri_portgroup_write_DIR_DIR_bf(const void * const hw,hri_port_dir_reg_t data)100 static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data)
101 {
102 ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data);
103 ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data);
104 }
105
hri_portgroup_clear_DIR_DIR_bf(const void * const hw,hri_port_dir_reg_t mask)106 static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
107 {
108 ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask);
109 }
110
hri_portgroup_toggle_DIR_DIR_bf(const void * const hw,hri_port_dir_reg_t mask)111 static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask)
112 {
113 ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask);
114 }
115
hri_portgroup_set_DIR_reg(const void * const hw,hri_port_dir_reg_t mask)116 static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
117 {
118 ((PortGroup *)hw)->DIRSET.reg = mask;
119 }
120
hri_portgroup_get_DIR_reg(const void * const hw,hri_port_dir_reg_t mask)121 static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
122 {
123 uint32_t tmp;
124 tmp = ((PortGroup *)hw)->DIR.reg;
125 tmp &= mask;
126 return tmp;
127 }
128
hri_portgroup_read_DIR_reg(const void * const hw)129 static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw)
130 {
131 return ((PortGroup *)hw)->DIR.reg;
132 }
133
hri_portgroup_write_DIR_reg(const void * const hw,hri_port_dir_reg_t data)134 static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data)
135 {
136 ((PortGroup *)hw)->DIRSET.reg = data;
137 ((PortGroup *)hw)->DIRCLR.reg = ~data;
138 }
139
hri_portgroup_clear_DIR_reg(const void * const hw,hri_port_dir_reg_t mask)140 static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
141 {
142 ((PortGroup *)hw)->DIRCLR.reg = mask;
143 }
144
hri_portgroup_toggle_DIR_reg(const void * const hw,hri_port_dir_reg_t mask)145 static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask)
146 {
147 ((PortGroup *)hw)->DIRTGL.reg = mask;
148 }
149
hri_portgroup_set_OUT_OUT_bf(const void * const hw,hri_port_out_reg_t mask)150 static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
151 {
152 ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask);
153 }
154
hri_portgroup_get_OUT_OUT_bf(const void * const hw,hri_port_out_reg_t mask)155 static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
156 {
157 uint32_t tmp;
158 tmp = ((PortGroup *)hw)->OUT.reg;
159 tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
160 return tmp;
161 }
162
hri_portgroup_read_OUT_OUT_bf(const void * const hw)163 static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw)
164 {
165 uint32_t tmp;
166 tmp = ((PortGroup *)hw)->OUT.reg;
167 tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
168 return tmp;
169 }
170
hri_portgroup_write_OUT_OUT_bf(const void * const hw,hri_port_out_reg_t data)171 static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data)
172 {
173 ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data);
174 ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data);
175 }
176
hri_portgroup_clear_OUT_OUT_bf(const void * const hw,hri_port_out_reg_t mask)177 static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
178 {
179 ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask);
180 }
181
hri_portgroup_toggle_OUT_OUT_bf(const void * const hw,hri_port_out_reg_t mask)182 static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask)
183 {
184 ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask);
185 }
186
hri_portgroup_set_OUT_reg(const void * const hw,hri_port_out_reg_t mask)187 static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
188 {
189 ((PortGroup *)hw)->OUTSET.reg = mask;
190 }
191
hri_portgroup_get_OUT_reg(const void * const hw,hri_port_out_reg_t mask)192 static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
193 {
194 uint32_t tmp;
195 tmp = ((PortGroup *)hw)->OUT.reg;
196 tmp &= mask;
197 return tmp;
198 }
199
hri_portgroup_read_OUT_reg(const void * const hw)200 static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw)
201 {
202 return ((PortGroup *)hw)->OUT.reg;
203 }
204
hri_portgroup_write_OUT_reg(const void * const hw,hri_port_out_reg_t data)205 static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data)
206 {
207 ((PortGroup *)hw)->OUTSET.reg = data;
208 ((PortGroup *)hw)->OUTCLR.reg = ~data;
209 }
210
hri_portgroup_clear_OUT_reg(const void * const hw,hri_port_out_reg_t mask)211 static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
212 {
213 ((PortGroup *)hw)->OUTCLR.reg = mask;
214 }
215
hri_portgroup_toggle_OUT_reg(const void * const hw,hri_port_out_reg_t mask)216 static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask)
217 {
218 ((PortGroup *)hw)->OUTTGL.reg = mask;
219 }
220
hri_portgroup_write_WRCONFIG_reg(const void * const hw,hri_port_wrconfig_reg_t data)221 static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data)
222 {
223 PORT_CRITICAL_SECTION_ENTER();
224 ((PortGroup *)hw)->WRCONFIG.reg = data;
225 PORT_CRITICAL_SECTION_LEAVE();
226 }
227
hri_portgroup_set_CTRL_SAMPLING_bf(const void * const hw,hri_port_ctrl_reg_t mask)228 static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
229 {
230 PORT_CRITICAL_SECTION_ENTER();
231 ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask);
232 PORT_CRITICAL_SECTION_LEAVE();
233 }
234
hri_portgroup_get_CTRL_SAMPLING_bf(const void * const hw,hri_port_ctrl_reg_t mask)235 static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
236 {
237 uint32_t tmp;
238 tmp = ((PortGroup *)hw)->CTRL.reg;
239 tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
240 return tmp;
241 }
242
hri_portgroup_write_CTRL_SAMPLING_bf(const void * const hw,hri_port_ctrl_reg_t data)243 static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data)
244 {
245 uint32_t tmp;
246 PORT_CRITICAL_SECTION_ENTER();
247 tmp = ((PortGroup *)hw)->CTRL.reg;
248 tmp &= ~PORT_CTRL_SAMPLING_Msk;
249 tmp |= PORT_CTRL_SAMPLING(data);
250 ((PortGroup *)hw)->CTRL.reg = tmp;
251 PORT_CRITICAL_SECTION_LEAVE();
252 }
253
hri_portgroup_clear_CTRL_SAMPLING_bf(const void * const hw,hri_port_ctrl_reg_t mask)254 static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
255 {
256 PORT_CRITICAL_SECTION_ENTER();
257 ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
258 PORT_CRITICAL_SECTION_LEAVE();
259 }
260
hri_portgroup_toggle_CTRL_SAMPLING_bf(const void * const hw,hri_port_ctrl_reg_t mask)261 static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask)
262 {
263 PORT_CRITICAL_SECTION_ENTER();
264 ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
265 PORT_CRITICAL_SECTION_LEAVE();
266 }
267
hri_portgroup_read_CTRL_SAMPLING_bf(const void * const hw)268 static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw)
269 {
270 uint32_t tmp;
271 tmp = ((PortGroup *)hw)->CTRL.reg;
272 tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
273 return tmp;
274 }
275
hri_portgroup_set_CTRL_reg(const void * const hw,hri_port_ctrl_reg_t mask)276 static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
277 {
278 PORT_CRITICAL_SECTION_ENTER();
279 ((PortGroup *)hw)->CTRL.reg |= mask;
280 PORT_CRITICAL_SECTION_LEAVE();
281 }
282
hri_portgroup_get_CTRL_reg(const void * const hw,hri_port_ctrl_reg_t mask)283 static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
284 {
285 uint32_t tmp;
286 tmp = ((PortGroup *)hw)->CTRL.reg;
287 tmp &= mask;
288 return tmp;
289 }
290
hri_portgroup_write_CTRL_reg(const void * const hw,hri_port_ctrl_reg_t data)291 static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data)
292 {
293 PORT_CRITICAL_SECTION_ENTER();
294 ((PortGroup *)hw)->CTRL.reg = data;
295 PORT_CRITICAL_SECTION_LEAVE();
296 }
297
hri_portgroup_clear_CTRL_reg(const void * const hw,hri_port_ctrl_reg_t mask)298 static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
299 {
300 PORT_CRITICAL_SECTION_ENTER();
301 ((PortGroup *)hw)->CTRL.reg &= ~mask;
302 PORT_CRITICAL_SECTION_LEAVE();
303 }
304
hri_portgroup_toggle_CTRL_reg(const void * const hw,hri_port_ctrl_reg_t mask)305 static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask)
306 {
307 PORT_CRITICAL_SECTION_ENTER();
308 ((PortGroup *)hw)->CTRL.reg ^= mask;
309 PORT_CRITICAL_SECTION_LEAVE();
310 }
311
hri_portgroup_read_CTRL_reg(const void * const hw)312 static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw)
313 {
314 return ((PortGroup *)hw)->CTRL.reg;
315 }
316
hri_portgroup_set_EVCTRL_PORTEI0_bit(const void * const hw)317 static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw)
318 {
319 PORT_CRITICAL_SECTION_ENTER();
320 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
321 PORT_CRITICAL_SECTION_LEAVE();
322 }
323
hri_portgroup_get_EVCTRL_PORTEI0_bit(const void * const hw)324 static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw)
325 {
326 uint32_t tmp;
327 tmp = ((PortGroup *)hw)->EVCTRL.reg;
328 tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
329 return (bool)tmp;
330 }
331
hri_portgroup_write_EVCTRL_PORTEI0_bit(const void * const hw,bool value)332 static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value)
333 {
334 uint32_t tmp;
335 PORT_CRITICAL_SECTION_ENTER();
336 tmp = ((PortGroup *)hw)->EVCTRL.reg;
337 tmp &= ~PORT_EVCTRL_PORTEI0;
338 tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
339 ((PortGroup *)hw)->EVCTRL.reg = tmp;
340 PORT_CRITICAL_SECTION_LEAVE();
341 }
342
hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void * const hw)343 static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw)
344 {
345 PORT_CRITICAL_SECTION_ENTER();
346 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
347 PORT_CRITICAL_SECTION_LEAVE();
348 }
349
hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void * const hw)350 static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw)
351 {
352 PORT_CRITICAL_SECTION_ENTER();
353 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
354 PORT_CRITICAL_SECTION_LEAVE();
355 }
356
hri_portgroup_set_EVCTRL_PORTEI1_bit(const void * const hw)357 static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw)
358 {
359 PORT_CRITICAL_SECTION_ENTER();
360 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
361 PORT_CRITICAL_SECTION_LEAVE();
362 }
363
hri_portgroup_get_EVCTRL_PORTEI1_bit(const void * const hw)364 static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw)
365 {
366 uint32_t tmp;
367 tmp = ((PortGroup *)hw)->EVCTRL.reg;
368 tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
369 return (bool)tmp;
370 }
371
hri_portgroup_write_EVCTRL_PORTEI1_bit(const void * const hw,bool value)372 static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value)
373 {
374 uint32_t tmp;
375 PORT_CRITICAL_SECTION_ENTER();
376 tmp = ((PortGroup *)hw)->EVCTRL.reg;
377 tmp &= ~PORT_EVCTRL_PORTEI1;
378 tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
379 ((PortGroup *)hw)->EVCTRL.reg = tmp;
380 PORT_CRITICAL_SECTION_LEAVE();
381 }
382
hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void * const hw)383 static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw)
384 {
385 PORT_CRITICAL_SECTION_ENTER();
386 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
387 PORT_CRITICAL_SECTION_LEAVE();
388 }
389
hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void * const hw)390 static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw)
391 {
392 PORT_CRITICAL_SECTION_ENTER();
393 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
394 PORT_CRITICAL_SECTION_LEAVE();
395 }
396
hri_portgroup_set_EVCTRL_PORTEI2_bit(const void * const hw)397 static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw)
398 {
399 PORT_CRITICAL_SECTION_ENTER();
400 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
401 PORT_CRITICAL_SECTION_LEAVE();
402 }
403
hri_portgroup_get_EVCTRL_PORTEI2_bit(const void * const hw)404 static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw)
405 {
406 uint32_t tmp;
407 tmp = ((PortGroup *)hw)->EVCTRL.reg;
408 tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
409 return (bool)tmp;
410 }
411
hri_portgroup_write_EVCTRL_PORTEI2_bit(const void * const hw,bool value)412 static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value)
413 {
414 uint32_t tmp;
415 PORT_CRITICAL_SECTION_ENTER();
416 tmp = ((PortGroup *)hw)->EVCTRL.reg;
417 tmp &= ~PORT_EVCTRL_PORTEI2;
418 tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
419 ((PortGroup *)hw)->EVCTRL.reg = tmp;
420 PORT_CRITICAL_SECTION_LEAVE();
421 }
422
hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void * const hw)423 static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw)
424 {
425 PORT_CRITICAL_SECTION_ENTER();
426 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
427 PORT_CRITICAL_SECTION_LEAVE();
428 }
429
hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void * const hw)430 static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw)
431 {
432 PORT_CRITICAL_SECTION_ENTER();
433 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
434 PORT_CRITICAL_SECTION_LEAVE();
435 }
436
hri_portgroup_set_EVCTRL_PORTEI3_bit(const void * const hw)437 static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw)
438 {
439 PORT_CRITICAL_SECTION_ENTER();
440 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
441 PORT_CRITICAL_SECTION_LEAVE();
442 }
443
hri_portgroup_get_EVCTRL_PORTEI3_bit(const void * const hw)444 static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw)
445 {
446 uint32_t tmp;
447 tmp = ((PortGroup *)hw)->EVCTRL.reg;
448 tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
449 return (bool)tmp;
450 }
451
hri_portgroup_write_EVCTRL_PORTEI3_bit(const void * const hw,bool value)452 static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value)
453 {
454 uint32_t tmp;
455 PORT_CRITICAL_SECTION_ENTER();
456 tmp = ((PortGroup *)hw)->EVCTRL.reg;
457 tmp &= ~PORT_EVCTRL_PORTEI3;
458 tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
459 ((PortGroup *)hw)->EVCTRL.reg = tmp;
460 PORT_CRITICAL_SECTION_LEAVE();
461 }
462
hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void * const hw)463 static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw)
464 {
465 PORT_CRITICAL_SECTION_ENTER();
466 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
467 PORT_CRITICAL_SECTION_LEAVE();
468 }
469
hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void * const hw)470 static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw)
471 {
472 PORT_CRITICAL_SECTION_ENTER();
473 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
474 PORT_CRITICAL_SECTION_LEAVE();
475 }
476
hri_portgroup_set_EVCTRL_PID0_bf(const void * const hw,hri_port_evctrl_reg_t mask)477 static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
478 {
479 PORT_CRITICAL_SECTION_ENTER();
480 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
481 PORT_CRITICAL_SECTION_LEAVE();
482 }
483
hri_portgroup_get_EVCTRL_PID0_bf(const void * const hw,hri_port_evctrl_reg_t mask)484 static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
485 {
486 uint32_t tmp;
487 tmp = ((PortGroup *)hw)->EVCTRL.reg;
488 tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
489 return tmp;
490 }
491
hri_portgroup_write_EVCTRL_PID0_bf(const void * const hw,hri_port_evctrl_reg_t data)492 static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data)
493 {
494 uint32_t tmp;
495 PORT_CRITICAL_SECTION_ENTER();
496 tmp = ((PortGroup *)hw)->EVCTRL.reg;
497 tmp &= ~PORT_EVCTRL_PID0_Msk;
498 tmp |= PORT_EVCTRL_PID0(data);
499 ((PortGroup *)hw)->EVCTRL.reg = tmp;
500 PORT_CRITICAL_SECTION_LEAVE();
501 }
502
hri_portgroup_clear_EVCTRL_PID0_bf(const void * const hw,hri_port_evctrl_reg_t mask)503 static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
504 {
505 PORT_CRITICAL_SECTION_ENTER();
506 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
507 PORT_CRITICAL_SECTION_LEAVE();
508 }
509
hri_portgroup_toggle_EVCTRL_PID0_bf(const void * const hw,hri_port_evctrl_reg_t mask)510 static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
511 {
512 PORT_CRITICAL_SECTION_ENTER();
513 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
514 PORT_CRITICAL_SECTION_LEAVE();
515 }
516
hri_portgroup_read_EVCTRL_PID0_bf(const void * const hw)517 static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw)
518 {
519 uint32_t tmp;
520 tmp = ((PortGroup *)hw)->EVCTRL.reg;
521 tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
522 return tmp;
523 }
524
hri_portgroup_set_EVCTRL_EVACT0_bf(const void * const hw,hri_port_evctrl_reg_t mask)525 static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
526 {
527 PORT_CRITICAL_SECTION_ENTER();
528 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
529 PORT_CRITICAL_SECTION_LEAVE();
530 }
531
hri_portgroup_get_EVCTRL_EVACT0_bf(const void * const hw,hri_port_evctrl_reg_t mask)532 static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
533 {
534 uint32_t tmp;
535 tmp = ((PortGroup *)hw)->EVCTRL.reg;
536 tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
537 return tmp;
538 }
539
hri_portgroup_write_EVCTRL_EVACT0_bf(const void * const hw,hri_port_evctrl_reg_t data)540 static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data)
541 {
542 uint32_t tmp;
543 PORT_CRITICAL_SECTION_ENTER();
544 tmp = ((PortGroup *)hw)->EVCTRL.reg;
545 tmp &= ~PORT_EVCTRL_EVACT0_Msk;
546 tmp |= PORT_EVCTRL_EVACT0(data);
547 ((PortGroup *)hw)->EVCTRL.reg = tmp;
548 PORT_CRITICAL_SECTION_LEAVE();
549 }
550
hri_portgroup_clear_EVCTRL_EVACT0_bf(const void * const hw,hri_port_evctrl_reg_t mask)551 static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
552 {
553 PORT_CRITICAL_SECTION_ENTER();
554 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
555 PORT_CRITICAL_SECTION_LEAVE();
556 }
557
hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void * const hw,hri_port_evctrl_reg_t mask)558 static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask)
559 {
560 PORT_CRITICAL_SECTION_ENTER();
561 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
562 PORT_CRITICAL_SECTION_LEAVE();
563 }
564
hri_portgroup_read_EVCTRL_EVACT0_bf(const void * const hw)565 static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw)
566 {
567 uint32_t tmp;
568 tmp = ((PortGroup *)hw)->EVCTRL.reg;
569 tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
570 return tmp;
571 }
572
hri_portgroup_set_EVCTRL_PID1_bf(const void * const hw,hri_port_evctrl_reg_t mask)573 static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
574 {
575 PORT_CRITICAL_SECTION_ENTER();
576 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
577 PORT_CRITICAL_SECTION_LEAVE();
578 }
579
hri_portgroup_get_EVCTRL_PID1_bf(const void * const hw,hri_port_evctrl_reg_t mask)580 static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
581 {
582 uint32_t tmp;
583 tmp = ((PortGroup *)hw)->EVCTRL.reg;
584 tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
585 return tmp;
586 }
587
hri_portgroup_write_EVCTRL_PID1_bf(const void * const hw,hri_port_evctrl_reg_t data)588 static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data)
589 {
590 uint32_t tmp;
591 PORT_CRITICAL_SECTION_ENTER();
592 tmp = ((PortGroup *)hw)->EVCTRL.reg;
593 tmp &= ~PORT_EVCTRL_PID1_Msk;
594 tmp |= PORT_EVCTRL_PID1(data);
595 ((PortGroup *)hw)->EVCTRL.reg = tmp;
596 PORT_CRITICAL_SECTION_LEAVE();
597 }
598
hri_portgroup_clear_EVCTRL_PID1_bf(const void * const hw,hri_port_evctrl_reg_t mask)599 static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
600 {
601 PORT_CRITICAL_SECTION_ENTER();
602 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
603 PORT_CRITICAL_SECTION_LEAVE();
604 }
605
hri_portgroup_toggle_EVCTRL_PID1_bf(const void * const hw,hri_port_evctrl_reg_t mask)606 static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
607 {
608 PORT_CRITICAL_SECTION_ENTER();
609 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
610 PORT_CRITICAL_SECTION_LEAVE();
611 }
612
hri_portgroup_read_EVCTRL_PID1_bf(const void * const hw)613 static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw)
614 {
615 uint32_t tmp;
616 tmp = ((PortGroup *)hw)->EVCTRL.reg;
617 tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
618 return tmp;
619 }
620
hri_portgroup_set_EVCTRL_EVACT1_bf(const void * const hw,hri_port_evctrl_reg_t mask)621 static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
622 {
623 PORT_CRITICAL_SECTION_ENTER();
624 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
625 PORT_CRITICAL_SECTION_LEAVE();
626 }
627
hri_portgroup_get_EVCTRL_EVACT1_bf(const void * const hw,hri_port_evctrl_reg_t mask)628 static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
629 {
630 uint32_t tmp;
631 tmp = ((PortGroup *)hw)->EVCTRL.reg;
632 tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
633 return tmp;
634 }
635
hri_portgroup_write_EVCTRL_EVACT1_bf(const void * const hw,hri_port_evctrl_reg_t data)636 static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data)
637 {
638 uint32_t tmp;
639 PORT_CRITICAL_SECTION_ENTER();
640 tmp = ((PortGroup *)hw)->EVCTRL.reg;
641 tmp &= ~PORT_EVCTRL_EVACT1_Msk;
642 tmp |= PORT_EVCTRL_EVACT1(data);
643 ((PortGroup *)hw)->EVCTRL.reg = tmp;
644 PORT_CRITICAL_SECTION_LEAVE();
645 }
646
hri_portgroup_clear_EVCTRL_EVACT1_bf(const void * const hw,hri_port_evctrl_reg_t mask)647 static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
648 {
649 PORT_CRITICAL_SECTION_ENTER();
650 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
651 PORT_CRITICAL_SECTION_LEAVE();
652 }
653
hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void * const hw,hri_port_evctrl_reg_t mask)654 static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask)
655 {
656 PORT_CRITICAL_SECTION_ENTER();
657 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
658 PORT_CRITICAL_SECTION_LEAVE();
659 }
660
hri_portgroup_read_EVCTRL_EVACT1_bf(const void * const hw)661 static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw)
662 {
663 uint32_t tmp;
664 tmp = ((PortGroup *)hw)->EVCTRL.reg;
665 tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
666 return tmp;
667 }
668
hri_portgroup_set_EVCTRL_PID2_bf(const void * const hw,hri_port_evctrl_reg_t mask)669 static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
670 {
671 PORT_CRITICAL_SECTION_ENTER();
672 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
673 PORT_CRITICAL_SECTION_LEAVE();
674 }
675
hri_portgroup_get_EVCTRL_PID2_bf(const void * const hw,hri_port_evctrl_reg_t mask)676 static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
677 {
678 uint32_t tmp;
679 tmp = ((PortGroup *)hw)->EVCTRL.reg;
680 tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
681 return tmp;
682 }
683
hri_portgroup_write_EVCTRL_PID2_bf(const void * const hw,hri_port_evctrl_reg_t data)684 static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data)
685 {
686 uint32_t tmp;
687 PORT_CRITICAL_SECTION_ENTER();
688 tmp = ((PortGroup *)hw)->EVCTRL.reg;
689 tmp &= ~PORT_EVCTRL_PID2_Msk;
690 tmp |= PORT_EVCTRL_PID2(data);
691 ((PortGroup *)hw)->EVCTRL.reg = tmp;
692 PORT_CRITICAL_SECTION_LEAVE();
693 }
694
hri_portgroup_clear_EVCTRL_PID2_bf(const void * const hw,hri_port_evctrl_reg_t mask)695 static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
696 {
697 PORT_CRITICAL_SECTION_ENTER();
698 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
699 PORT_CRITICAL_SECTION_LEAVE();
700 }
701
hri_portgroup_toggle_EVCTRL_PID2_bf(const void * const hw,hri_port_evctrl_reg_t mask)702 static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
703 {
704 PORT_CRITICAL_SECTION_ENTER();
705 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
706 PORT_CRITICAL_SECTION_LEAVE();
707 }
708
hri_portgroup_read_EVCTRL_PID2_bf(const void * const hw)709 static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw)
710 {
711 uint32_t tmp;
712 tmp = ((PortGroup *)hw)->EVCTRL.reg;
713 tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
714 return tmp;
715 }
716
hri_portgroup_set_EVCTRL_EVACT2_bf(const void * const hw,hri_port_evctrl_reg_t mask)717 static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
718 {
719 PORT_CRITICAL_SECTION_ENTER();
720 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
721 PORT_CRITICAL_SECTION_LEAVE();
722 }
723
hri_portgroup_get_EVCTRL_EVACT2_bf(const void * const hw,hri_port_evctrl_reg_t mask)724 static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
725 {
726 uint32_t tmp;
727 tmp = ((PortGroup *)hw)->EVCTRL.reg;
728 tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
729 return tmp;
730 }
731
hri_portgroup_write_EVCTRL_EVACT2_bf(const void * const hw,hri_port_evctrl_reg_t data)732 static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data)
733 {
734 uint32_t tmp;
735 PORT_CRITICAL_SECTION_ENTER();
736 tmp = ((PortGroup *)hw)->EVCTRL.reg;
737 tmp &= ~PORT_EVCTRL_EVACT2_Msk;
738 tmp |= PORT_EVCTRL_EVACT2(data);
739 ((PortGroup *)hw)->EVCTRL.reg = tmp;
740 PORT_CRITICAL_SECTION_LEAVE();
741 }
742
hri_portgroup_clear_EVCTRL_EVACT2_bf(const void * const hw,hri_port_evctrl_reg_t mask)743 static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
744 {
745 PORT_CRITICAL_SECTION_ENTER();
746 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
747 PORT_CRITICAL_SECTION_LEAVE();
748 }
749
hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void * const hw,hri_port_evctrl_reg_t mask)750 static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask)
751 {
752 PORT_CRITICAL_SECTION_ENTER();
753 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
754 PORT_CRITICAL_SECTION_LEAVE();
755 }
756
hri_portgroup_read_EVCTRL_EVACT2_bf(const void * const hw)757 static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw)
758 {
759 uint32_t tmp;
760 tmp = ((PortGroup *)hw)->EVCTRL.reg;
761 tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
762 return tmp;
763 }
764
hri_portgroup_set_EVCTRL_PID3_bf(const void * const hw,hri_port_evctrl_reg_t mask)765 static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
766 {
767 PORT_CRITICAL_SECTION_ENTER();
768 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
769 PORT_CRITICAL_SECTION_LEAVE();
770 }
771
hri_portgroup_get_EVCTRL_PID3_bf(const void * const hw,hri_port_evctrl_reg_t mask)772 static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
773 {
774 uint32_t tmp;
775 tmp = ((PortGroup *)hw)->EVCTRL.reg;
776 tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
777 return tmp;
778 }
779
hri_portgroup_write_EVCTRL_PID3_bf(const void * const hw,hri_port_evctrl_reg_t data)780 static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data)
781 {
782 uint32_t tmp;
783 PORT_CRITICAL_SECTION_ENTER();
784 tmp = ((PortGroup *)hw)->EVCTRL.reg;
785 tmp &= ~PORT_EVCTRL_PID3_Msk;
786 tmp |= PORT_EVCTRL_PID3(data);
787 ((PortGroup *)hw)->EVCTRL.reg = tmp;
788 PORT_CRITICAL_SECTION_LEAVE();
789 }
790
hri_portgroup_clear_EVCTRL_PID3_bf(const void * const hw,hri_port_evctrl_reg_t mask)791 static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
792 {
793 PORT_CRITICAL_SECTION_ENTER();
794 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
795 PORT_CRITICAL_SECTION_LEAVE();
796 }
797
hri_portgroup_toggle_EVCTRL_PID3_bf(const void * const hw,hri_port_evctrl_reg_t mask)798 static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
799 {
800 PORT_CRITICAL_SECTION_ENTER();
801 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
802 PORT_CRITICAL_SECTION_LEAVE();
803 }
804
hri_portgroup_read_EVCTRL_PID3_bf(const void * const hw)805 static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw)
806 {
807 uint32_t tmp;
808 tmp = ((PortGroup *)hw)->EVCTRL.reg;
809 tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
810 return tmp;
811 }
812
hri_portgroup_set_EVCTRL_EVACT3_bf(const void * const hw,hri_port_evctrl_reg_t mask)813 static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
814 {
815 PORT_CRITICAL_SECTION_ENTER();
816 ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
817 PORT_CRITICAL_SECTION_LEAVE();
818 }
819
hri_portgroup_get_EVCTRL_EVACT3_bf(const void * const hw,hri_port_evctrl_reg_t mask)820 static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
821 {
822 uint32_t tmp;
823 tmp = ((PortGroup *)hw)->EVCTRL.reg;
824 tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
825 return tmp;
826 }
827
hri_portgroup_write_EVCTRL_EVACT3_bf(const void * const hw,hri_port_evctrl_reg_t data)828 static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data)
829 {
830 uint32_t tmp;
831 PORT_CRITICAL_SECTION_ENTER();
832 tmp = ((PortGroup *)hw)->EVCTRL.reg;
833 tmp &= ~PORT_EVCTRL_EVACT3_Msk;
834 tmp |= PORT_EVCTRL_EVACT3(data);
835 ((PortGroup *)hw)->EVCTRL.reg = tmp;
836 PORT_CRITICAL_SECTION_LEAVE();
837 }
838
hri_portgroup_clear_EVCTRL_EVACT3_bf(const void * const hw,hri_port_evctrl_reg_t mask)839 static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
840 {
841 PORT_CRITICAL_SECTION_ENTER();
842 ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
843 PORT_CRITICAL_SECTION_LEAVE();
844 }
845
hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void * const hw,hri_port_evctrl_reg_t mask)846 static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask)
847 {
848 PORT_CRITICAL_SECTION_ENTER();
849 ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
850 PORT_CRITICAL_SECTION_LEAVE();
851 }
852
hri_portgroup_read_EVCTRL_EVACT3_bf(const void * const hw)853 static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw)
854 {
855 uint32_t tmp;
856 tmp = ((PortGroup *)hw)->EVCTRL.reg;
857 tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
858 return tmp;
859 }
860
hri_portgroup_set_EVCTRL_reg(const void * const hw,hri_port_evctrl_reg_t mask)861 static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
862 {
863 PORT_CRITICAL_SECTION_ENTER();
864 ((PortGroup *)hw)->EVCTRL.reg |= mask;
865 PORT_CRITICAL_SECTION_LEAVE();
866 }
867
hri_portgroup_get_EVCTRL_reg(const void * const hw,hri_port_evctrl_reg_t mask)868 static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
869 {
870 uint32_t tmp;
871 tmp = ((PortGroup *)hw)->EVCTRL.reg;
872 tmp &= mask;
873 return tmp;
874 }
875
hri_portgroup_write_EVCTRL_reg(const void * const hw,hri_port_evctrl_reg_t data)876 static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data)
877 {
878 PORT_CRITICAL_SECTION_ENTER();
879 ((PortGroup *)hw)->EVCTRL.reg = data;
880 PORT_CRITICAL_SECTION_LEAVE();
881 }
882
hri_portgroup_clear_EVCTRL_reg(const void * const hw,hri_port_evctrl_reg_t mask)883 static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
884 {
885 PORT_CRITICAL_SECTION_ENTER();
886 ((PortGroup *)hw)->EVCTRL.reg &= ~mask;
887 PORT_CRITICAL_SECTION_LEAVE();
888 }
889
hri_portgroup_toggle_EVCTRL_reg(const void * const hw,hri_port_evctrl_reg_t mask)890 static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask)
891 {
892 PORT_CRITICAL_SECTION_ENTER();
893 ((PortGroup *)hw)->EVCTRL.reg ^= mask;
894 PORT_CRITICAL_SECTION_LEAVE();
895 }
896
hri_portgroup_read_EVCTRL_reg(const void * const hw)897 static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw)
898 {
899 return ((PortGroup *)hw)->EVCTRL.reg;
900 }
901
hri_portgroup_set_PMUX_PMUXE_bf(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)902 static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
903 {
904 PORT_CRITICAL_SECTION_ENTER();
905 ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
906 PORT_CRITICAL_SECTION_LEAVE();
907 }
908
hri_portgroup_get_PMUX_PMUXE_bf(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)909 static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index,
910 hri_port_pmux_reg_t mask)
911 {
912 uint8_t tmp;
913 tmp = ((PortGroup *)hw)->PMUX[index].reg;
914 tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
915 return tmp;
916 }
917
hri_portgroup_write_PMUX_PMUXE_bf(const void * const hw,uint8_t index,hri_port_pmux_reg_t data)918 static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
919 {
920 uint8_t tmp;
921 PORT_CRITICAL_SECTION_ENTER();
922 tmp = ((PortGroup *)hw)->PMUX[index].reg;
923 tmp &= ~PORT_PMUX_PMUXE_Msk;
924 tmp |= PORT_PMUX_PMUXE(data);
925 ((PortGroup *)hw)->PMUX[index].reg = tmp;
926 PORT_CRITICAL_SECTION_LEAVE();
927 }
928
hri_portgroup_clear_PMUX_PMUXE_bf(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)929 static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
930 {
931 PORT_CRITICAL_SECTION_ENTER();
932 ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
933 PORT_CRITICAL_SECTION_LEAVE();
934 }
935
hri_portgroup_toggle_PMUX_PMUXE_bf(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)936 static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
937 {
938 PORT_CRITICAL_SECTION_ENTER();
939 ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
940 PORT_CRITICAL_SECTION_LEAVE();
941 }
942
hri_portgroup_read_PMUX_PMUXE_bf(const void * const hw,uint8_t index)943 static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index)
944 {
945 uint8_t tmp;
946 tmp = ((PortGroup *)hw)->PMUX[index].reg;
947 tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
948 return tmp;
949 }
950
hri_portgroup_set_PMUX_PMUXO_bf(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)951 static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
952 {
953 PORT_CRITICAL_SECTION_ENTER();
954 ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
955 PORT_CRITICAL_SECTION_LEAVE();
956 }
957
hri_portgroup_get_PMUX_PMUXO_bf(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)958 static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index,
959 hri_port_pmux_reg_t mask)
960 {
961 uint8_t tmp;
962 tmp = ((PortGroup *)hw)->PMUX[index].reg;
963 tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
964 return tmp;
965 }
966
hri_portgroup_write_PMUX_PMUXO_bf(const void * const hw,uint8_t index,hri_port_pmux_reg_t data)967 static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
968 {
969 uint8_t tmp;
970 PORT_CRITICAL_SECTION_ENTER();
971 tmp = ((PortGroup *)hw)->PMUX[index].reg;
972 tmp &= ~PORT_PMUX_PMUXO_Msk;
973 tmp |= PORT_PMUX_PMUXO(data);
974 ((PortGroup *)hw)->PMUX[index].reg = tmp;
975 PORT_CRITICAL_SECTION_LEAVE();
976 }
977
hri_portgroup_clear_PMUX_PMUXO_bf(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)978 static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
979 {
980 PORT_CRITICAL_SECTION_ENTER();
981 ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
982 PORT_CRITICAL_SECTION_LEAVE();
983 }
984
hri_portgroup_toggle_PMUX_PMUXO_bf(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)985 static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
986 {
987 PORT_CRITICAL_SECTION_ENTER();
988 ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
989 PORT_CRITICAL_SECTION_LEAVE();
990 }
991
hri_portgroup_read_PMUX_PMUXO_bf(const void * const hw,uint8_t index)992 static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index)
993 {
994 uint8_t tmp;
995 tmp = ((PortGroup *)hw)->PMUX[index].reg;
996 tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
997 return tmp;
998 }
999
hri_portgroup_set_PMUX_reg(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)1000 static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
1001 {
1002 PORT_CRITICAL_SECTION_ENTER();
1003 ((PortGroup *)hw)->PMUX[index].reg |= mask;
1004 PORT_CRITICAL_SECTION_LEAVE();
1005 }
1006
hri_portgroup_get_PMUX_reg(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)1007 static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index,
1008 hri_port_pmux_reg_t mask)
1009 {
1010 uint8_t tmp;
1011 tmp = ((PortGroup *)hw)->PMUX[index].reg;
1012 tmp &= mask;
1013 return tmp;
1014 }
1015
hri_portgroup_write_PMUX_reg(const void * const hw,uint8_t index,hri_port_pmux_reg_t data)1016 static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data)
1017 {
1018 PORT_CRITICAL_SECTION_ENTER();
1019 ((PortGroup *)hw)->PMUX[index].reg = data;
1020 PORT_CRITICAL_SECTION_LEAVE();
1021 }
1022
hri_portgroup_clear_PMUX_reg(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)1023 static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
1024 {
1025 PORT_CRITICAL_SECTION_ENTER();
1026 ((PortGroup *)hw)->PMUX[index].reg &= ~mask;
1027 PORT_CRITICAL_SECTION_LEAVE();
1028 }
1029
hri_portgroup_toggle_PMUX_reg(const void * const hw,uint8_t index,hri_port_pmux_reg_t mask)1030 static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask)
1031 {
1032 PORT_CRITICAL_SECTION_ENTER();
1033 ((PortGroup *)hw)->PMUX[index].reg ^= mask;
1034 PORT_CRITICAL_SECTION_LEAVE();
1035 }
1036
hri_portgroup_read_PMUX_reg(const void * const hw,uint8_t index)1037 static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index)
1038 {
1039 return ((PortGroup *)hw)->PMUX[index].reg;
1040 }
1041
hri_portgroup_set_PINCFG_PMUXEN_bit(const void * const hw,uint8_t index)1042 static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
1043 {
1044 PORT_CRITICAL_SECTION_ENTER();
1045 ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
1046 PORT_CRITICAL_SECTION_LEAVE();
1047 }
1048
hri_portgroup_get_PINCFG_PMUXEN_bit(const void * const hw,uint8_t index)1049 static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
1050 {
1051 uint8_t tmp;
1052 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1053 tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
1054 return (bool)tmp;
1055 }
1056
hri_portgroup_write_PINCFG_PMUXEN_bit(const void * const hw,uint8_t index,bool value)1057 static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value)
1058 {
1059 uint8_t tmp;
1060 PORT_CRITICAL_SECTION_ENTER();
1061 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1062 tmp &= ~PORT_PINCFG_PMUXEN;
1063 tmp |= value << PORT_PINCFG_PMUXEN_Pos;
1064 ((PortGroup *)hw)->PINCFG[index].reg = tmp;
1065 PORT_CRITICAL_SECTION_LEAVE();
1066 }
1067
hri_portgroup_clear_PINCFG_PMUXEN_bit(const void * const hw,uint8_t index)1068 static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
1069 {
1070 PORT_CRITICAL_SECTION_ENTER();
1071 ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
1072 PORT_CRITICAL_SECTION_LEAVE();
1073 }
1074
hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void * const hw,uint8_t index)1075 static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index)
1076 {
1077 PORT_CRITICAL_SECTION_ENTER();
1078 ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
1079 PORT_CRITICAL_SECTION_LEAVE();
1080 }
1081
hri_portgroup_set_PINCFG_INEN_bit(const void * const hw,uint8_t index)1082 static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index)
1083 {
1084 PORT_CRITICAL_SECTION_ENTER();
1085 ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN;
1086 PORT_CRITICAL_SECTION_LEAVE();
1087 }
1088
hri_portgroup_get_PINCFG_INEN_bit(const void * const hw,uint8_t index)1089 static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index)
1090 {
1091 uint8_t tmp;
1092 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1093 tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
1094 return (bool)tmp;
1095 }
1096
hri_portgroup_write_PINCFG_INEN_bit(const void * const hw,uint8_t index,bool value)1097 static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value)
1098 {
1099 uint8_t tmp;
1100 PORT_CRITICAL_SECTION_ENTER();
1101 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1102 tmp &= ~PORT_PINCFG_INEN;
1103 tmp |= value << PORT_PINCFG_INEN_Pos;
1104 ((PortGroup *)hw)->PINCFG[index].reg = tmp;
1105 PORT_CRITICAL_SECTION_LEAVE();
1106 }
1107
hri_portgroup_clear_PINCFG_INEN_bit(const void * const hw,uint8_t index)1108 static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index)
1109 {
1110 PORT_CRITICAL_SECTION_ENTER();
1111 ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN;
1112 PORT_CRITICAL_SECTION_LEAVE();
1113 }
1114
hri_portgroup_toggle_PINCFG_INEN_bit(const void * const hw,uint8_t index)1115 static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index)
1116 {
1117 PORT_CRITICAL_SECTION_ENTER();
1118 ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN;
1119 PORT_CRITICAL_SECTION_LEAVE();
1120 }
1121
hri_portgroup_set_PINCFG_PULLEN_bit(const void * const hw,uint8_t index)1122 static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
1123 {
1124 PORT_CRITICAL_SECTION_ENTER();
1125 ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN;
1126 PORT_CRITICAL_SECTION_LEAVE();
1127 }
1128
hri_portgroup_get_PINCFG_PULLEN_bit(const void * const hw,uint8_t index)1129 static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
1130 {
1131 uint8_t tmp;
1132 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1133 tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
1134 return (bool)tmp;
1135 }
1136
hri_portgroup_write_PINCFG_PULLEN_bit(const void * const hw,uint8_t index,bool value)1137 static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value)
1138 {
1139 uint8_t tmp;
1140 PORT_CRITICAL_SECTION_ENTER();
1141 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1142 tmp &= ~PORT_PINCFG_PULLEN;
1143 tmp |= value << PORT_PINCFG_PULLEN_Pos;
1144 ((PortGroup *)hw)->PINCFG[index].reg = tmp;
1145 PORT_CRITICAL_SECTION_LEAVE();
1146 }
1147
hri_portgroup_clear_PINCFG_PULLEN_bit(const void * const hw,uint8_t index)1148 static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
1149 {
1150 PORT_CRITICAL_SECTION_ENTER();
1151 ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
1152 PORT_CRITICAL_SECTION_LEAVE();
1153 }
1154
hri_portgroup_toggle_PINCFG_PULLEN_bit(const void * const hw,uint8_t index)1155 static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index)
1156 {
1157 PORT_CRITICAL_SECTION_ENTER();
1158 ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
1159 PORT_CRITICAL_SECTION_LEAVE();
1160 }
1161
hri_portgroup_set_PINCFG_DRVSTR_bit(const void * const hw,uint8_t index)1162 static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
1163 {
1164 PORT_CRITICAL_SECTION_ENTER();
1165 ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
1166 PORT_CRITICAL_SECTION_LEAVE();
1167 }
1168
hri_portgroup_get_PINCFG_DRVSTR_bit(const void * const hw,uint8_t index)1169 static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
1170 {
1171 uint8_t tmp;
1172 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1173 tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
1174 return (bool)tmp;
1175 }
1176
hri_portgroup_write_PINCFG_DRVSTR_bit(const void * const hw,uint8_t index,bool value)1177 static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value)
1178 {
1179 uint8_t tmp;
1180 PORT_CRITICAL_SECTION_ENTER();
1181 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1182 tmp &= ~PORT_PINCFG_DRVSTR;
1183 tmp |= value << PORT_PINCFG_DRVSTR_Pos;
1184 ((PortGroup *)hw)->PINCFG[index].reg = tmp;
1185 PORT_CRITICAL_SECTION_LEAVE();
1186 }
1187
hri_portgroup_clear_PINCFG_DRVSTR_bit(const void * const hw,uint8_t index)1188 static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
1189 {
1190 PORT_CRITICAL_SECTION_ENTER();
1191 ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
1192 PORT_CRITICAL_SECTION_LEAVE();
1193 }
1194
hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void * const hw,uint8_t index)1195 static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index)
1196 {
1197 PORT_CRITICAL_SECTION_ENTER();
1198 ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
1199 PORT_CRITICAL_SECTION_LEAVE();
1200 }
1201
hri_portgroup_set_PINCFG_reg(const void * const hw,uint8_t index,hri_port_pincfg_reg_t mask)1202 static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
1203 {
1204 PORT_CRITICAL_SECTION_ENTER();
1205 ((PortGroup *)hw)->PINCFG[index].reg |= mask;
1206 PORT_CRITICAL_SECTION_LEAVE();
1207 }
1208
hri_portgroup_get_PINCFG_reg(const void * const hw,uint8_t index,hri_port_pincfg_reg_t mask)1209 static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index,
1210 hri_port_pincfg_reg_t mask)
1211 {
1212 uint8_t tmp;
1213 tmp = ((PortGroup *)hw)->PINCFG[index].reg;
1214 tmp &= mask;
1215 return tmp;
1216 }
1217
hri_portgroup_write_PINCFG_reg(const void * const hw,uint8_t index,hri_port_pincfg_reg_t data)1218 static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data)
1219 {
1220 PORT_CRITICAL_SECTION_ENTER();
1221 ((PortGroup *)hw)->PINCFG[index].reg = data;
1222 PORT_CRITICAL_SECTION_LEAVE();
1223 }
1224
hri_portgroup_clear_PINCFG_reg(const void * const hw,uint8_t index,hri_port_pincfg_reg_t mask)1225 static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
1226 {
1227 PORT_CRITICAL_SECTION_ENTER();
1228 ((PortGroup *)hw)->PINCFG[index].reg &= ~mask;
1229 PORT_CRITICAL_SECTION_LEAVE();
1230 }
1231
hri_portgroup_toggle_PINCFG_reg(const void * const hw,uint8_t index,hri_port_pincfg_reg_t mask)1232 static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask)
1233 {
1234 PORT_CRITICAL_SECTION_ENTER();
1235 ((PortGroup *)hw)->PINCFG[index].reg ^= mask;
1236 PORT_CRITICAL_SECTION_LEAVE();
1237 }
1238
hri_portgroup_read_PINCFG_reg(const void * const hw,uint8_t index)1239 static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index)
1240 {
1241 return ((PortGroup *)hw)->PINCFG[index].reg;
1242 }
1243
hri_portgroup_get_IN_IN_bf(const void * const hw,hri_port_in_reg_t mask)1244 static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask)
1245 {
1246 return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
1247 }
1248
hri_portgroup_read_IN_IN_bf(const void * const hw)1249 static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw)
1250 {
1251 return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
1252 }
1253
hri_portgroup_get_IN_reg(const void * const hw,hri_port_in_reg_t mask)1254 static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask)
1255 {
1256 uint32_t tmp;
1257 tmp = ((PortGroup *)hw)->IN.reg;
1258 tmp &= mask;
1259 return tmp;
1260 }
1261
hri_portgroup_read_IN_reg(const void * const hw)1262 static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw)
1263 {
1264 return ((PortGroup *)hw)->IN.reg;
1265 }
1266
hri_port_set_DIR_DIR_bf(const void * const hw,uint8_t submodule_index,hri_port_dir_reg_t mask)1267 static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1268 {
1269 ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask);
1270 }
1271
hri_port_get_DIR_DIR_bf(const void * const hw,uint8_t submodule_index,hri_port_dir_reg_t mask)1272 static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index,
1273 hri_port_dir_reg_t mask)
1274 {
1275 uint32_t tmp;
1276 tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
1277 tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos;
1278 return tmp;
1279 }
1280
hri_port_read_DIR_DIR_bf(const void * const hw,uint8_t submodule_index)1281 static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index)
1282 {
1283 uint32_t tmp;
1284 tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
1285 tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos;
1286 return tmp;
1287 }
1288
hri_port_write_DIR_DIR_bf(const void * const hw,uint8_t submodule_index,hri_port_dir_reg_t data)1289 static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
1290 {
1291 ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data);
1292 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data);
1293 }
1294
hri_port_clear_DIR_DIR_bf(const void * const hw,uint8_t submodule_index,hri_port_dir_reg_t mask)1295 static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1296 {
1297 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask);
1298 }
1299
hri_port_toggle_DIR_DIR_bf(const void * const hw,uint8_t submodule_index,hri_port_dir_reg_t mask)1300 static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1301 {
1302 ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask);
1303 }
1304
hri_port_set_DIR_reg(const void * const hw,uint8_t submodule_index,hri_port_dir_reg_t mask)1305 static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1306 {
1307 ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
1308 }
1309
hri_port_get_DIR_reg(const void * const hw,uint8_t submodule_index,hri_port_dir_reg_t mask)1310 static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index,
1311 hri_port_dir_reg_t mask)
1312 {
1313 uint32_t tmp;
1314 tmp = ((Port *)hw)->Group[submodule_index].DIR.reg;
1315 tmp &= mask;
1316 return tmp;
1317 }
1318
hri_port_read_DIR_reg(const void * const hw,uint8_t submodule_index)1319 static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index)
1320 {
1321 return ((Port *)hw)->Group[submodule_index].DIR.reg;
1322 }
1323
hri_port_write_DIR_reg(const void * const hw,uint8_t submodule_index,hri_port_dir_reg_t data)1324 static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data)
1325 {
1326 ((Port *)hw)->Group[submodule_index].DIRSET.reg = data;
1327 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data;
1328 }
1329
hri_port_clear_DIR_reg(const void * const hw,uint8_t submodule_index,hri_port_dir_reg_t mask)1330 static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1331 {
1332 ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
1333 }
1334
hri_port_toggle_DIR_reg(const void * const hw,uint8_t submodule_index,hri_port_dir_reg_t mask)1335 static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
1336 {
1337 ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask;
1338 }
1339
hri_port_set_OUT_OUT_bf(const void * const hw,uint8_t submodule_index,hri_port_out_reg_t mask)1340 static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1341 {
1342 ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask);
1343 }
1344
hri_port_get_OUT_OUT_bf(const void * const hw,uint8_t submodule_index,hri_port_out_reg_t mask)1345 static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index,
1346 hri_port_out_reg_t mask)
1347 {
1348 uint32_t tmp;
1349 tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
1350 tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos;
1351 return tmp;
1352 }
1353
hri_port_read_OUT_OUT_bf(const void * const hw,uint8_t submodule_index)1354 static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index)
1355 {
1356 uint32_t tmp;
1357 tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
1358 tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos;
1359 return tmp;
1360 }
1361
hri_port_write_OUT_OUT_bf(const void * const hw,uint8_t submodule_index,hri_port_out_reg_t data)1362 static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
1363 {
1364 ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data);
1365 ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data);
1366 }
1367
hri_port_clear_OUT_OUT_bf(const void * const hw,uint8_t submodule_index,hri_port_out_reg_t mask)1368 static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1369 {
1370 ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask);
1371 }
1372
hri_port_toggle_OUT_OUT_bf(const void * const hw,uint8_t submodule_index,hri_port_out_reg_t mask)1373 static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1374 {
1375 ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask);
1376 }
1377
hri_port_set_OUT_reg(const void * const hw,uint8_t submodule_index,hri_port_out_reg_t mask)1378 static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1379 {
1380 ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask;
1381 }
1382
hri_port_get_OUT_reg(const void * const hw,uint8_t submodule_index,hri_port_out_reg_t mask)1383 static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index,
1384 hri_port_out_reg_t mask)
1385 {
1386 uint32_t tmp;
1387 tmp = ((Port *)hw)->Group[submodule_index].OUT.reg;
1388 tmp &= mask;
1389 return tmp;
1390 }
1391
hri_port_read_OUT_reg(const void * const hw,uint8_t submodule_index)1392 static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index)
1393 {
1394 return ((Port *)hw)->Group[submodule_index].OUT.reg;
1395 }
1396
hri_port_write_OUT_reg(const void * const hw,uint8_t submodule_index,hri_port_out_reg_t data)1397 static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data)
1398 {
1399 ((Port *)hw)->Group[submodule_index].OUTSET.reg = data;
1400 ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data;
1401 }
1402
hri_port_clear_OUT_reg(const void * const hw,uint8_t submodule_index,hri_port_out_reg_t mask)1403 static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1404 {
1405 ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
1406 }
1407
hri_port_toggle_OUT_reg(const void * const hw,uint8_t submodule_index,hri_port_out_reg_t mask)1408 static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask)
1409 {
1410 ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask;
1411 }
1412
hri_port_write_WRCONFIG_reg(const void * const hw,uint8_t submodule_index,hri_port_wrconfig_reg_t data)1413 static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
1414 hri_port_wrconfig_reg_t data)
1415 {
1416 PORT_CRITICAL_SECTION_ENTER();
1417 ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
1418 PORT_CRITICAL_SECTION_LEAVE();
1419 }
1420
hri_port_set_CTRL_SAMPLING_bf(const void * const hw,uint8_t submodule_index,hri_port_ctrl_reg_t mask)1421 static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
1422 hri_port_ctrl_reg_t mask)
1423 {
1424 PORT_CRITICAL_SECTION_ENTER();
1425 ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask);
1426 PORT_CRITICAL_SECTION_LEAVE();
1427 }
1428
hri_port_get_CTRL_SAMPLING_bf(const void * const hw,uint8_t submodule_index,hri_port_ctrl_reg_t mask)1429 static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
1430 hri_port_ctrl_reg_t mask)
1431 {
1432 uint32_t tmp;
1433 tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
1434 tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos;
1435 return tmp;
1436 }
1437
hri_port_write_CTRL_SAMPLING_bf(const void * const hw,uint8_t submodule_index,hri_port_ctrl_reg_t data)1438 static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
1439 hri_port_ctrl_reg_t data)
1440 {
1441 uint32_t tmp;
1442 PORT_CRITICAL_SECTION_ENTER();
1443 tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
1444 tmp &= ~PORT_CTRL_SAMPLING_Msk;
1445 tmp |= PORT_CTRL_SAMPLING(data);
1446 ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp;
1447 PORT_CRITICAL_SECTION_LEAVE();
1448 }
1449
hri_port_clear_CTRL_SAMPLING_bf(const void * const hw,uint8_t submodule_index,hri_port_ctrl_reg_t mask)1450 static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
1451 hri_port_ctrl_reg_t mask)
1452 {
1453 PORT_CRITICAL_SECTION_ENTER();
1454 ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask);
1455 PORT_CRITICAL_SECTION_LEAVE();
1456 }
1457
hri_port_toggle_CTRL_SAMPLING_bf(const void * const hw,uint8_t submodule_index,hri_port_ctrl_reg_t mask)1458 static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index,
1459 hri_port_ctrl_reg_t mask)
1460 {
1461 PORT_CRITICAL_SECTION_ENTER();
1462 ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask);
1463 PORT_CRITICAL_SECTION_LEAVE();
1464 }
1465
hri_port_read_CTRL_SAMPLING_bf(const void * const hw,uint8_t submodule_index)1466 static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index)
1467 {
1468 uint32_t tmp;
1469 tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
1470 tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos;
1471 return tmp;
1472 }
1473
hri_port_set_CTRL_reg(const void * const hw,uint8_t submodule_index,hri_port_ctrl_reg_t mask)1474 static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
1475 {
1476 PORT_CRITICAL_SECTION_ENTER();
1477 ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask;
1478 PORT_CRITICAL_SECTION_LEAVE();
1479 }
1480
hri_port_get_CTRL_reg(const void * const hw,uint8_t submodule_index,hri_port_ctrl_reg_t mask)1481 static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index,
1482 hri_port_ctrl_reg_t mask)
1483 {
1484 uint32_t tmp;
1485 tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg;
1486 tmp &= mask;
1487 return tmp;
1488 }
1489
hri_port_write_CTRL_reg(const void * const hw,uint8_t submodule_index,hri_port_ctrl_reg_t data)1490 static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data)
1491 {
1492 PORT_CRITICAL_SECTION_ENTER();
1493 ((Port *)hw)->Group[submodule_index].CTRL.reg = data;
1494 PORT_CRITICAL_SECTION_LEAVE();
1495 }
1496
hri_port_clear_CTRL_reg(const void * const hw,uint8_t submodule_index,hri_port_ctrl_reg_t mask)1497 static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
1498 {
1499 PORT_CRITICAL_SECTION_ENTER();
1500 ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask;
1501 PORT_CRITICAL_SECTION_LEAVE();
1502 }
1503
hri_port_toggle_CTRL_reg(const void * const hw,uint8_t submodule_index,hri_port_ctrl_reg_t mask)1504 static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask)
1505 {
1506 PORT_CRITICAL_SECTION_ENTER();
1507 ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask;
1508 PORT_CRITICAL_SECTION_LEAVE();
1509 }
1510
hri_port_read_CTRL_reg(const void * const hw,uint8_t submodule_index)1511 static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index)
1512 {
1513 return ((Port *)hw)->Group[submodule_index].CTRL.reg;
1514 }
1515
hri_port_set_EVCTRL_PORTEI0_bit(const void * const hw,uint8_t submodule_index)1516 static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
1517 {
1518 PORT_CRITICAL_SECTION_ENTER();
1519 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
1520 PORT_CRITICAL_SECTION_LEAVE();
1521 }
1522
hri_port_get_EVCTRL_PORTEI0_bit(const void * const hw,uint8_t submodule_index)1523 static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
1524 {
1525 uint32_t tmp;
1526 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1527 tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos;
1528 return (bool)tmp;
1529 }
1530
hri_port_write_EVCTRL_PORTEI0_bit(const void * const hw,uint8_t submodule_index,bool value)1531 static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value)
1532 {
1533 uint32_t tmp;
1534 PORT_CRITICAL_SECTION_ENTER();
1535 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1536 tmp &= ~PORT_EVCTRL_PORTEI0;
1537 tmp |= value << PORT_EVCTRL_PORTEI0_Pos;
1538 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1539 PORT_CRITICAL_SECTION_LEAVE();
1540 }
1541
hri_port_clear_EVCTRL_PORTEI0_bit(const void * const hw,uint8_t submodule_index)1542 static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
1543 {
1544 PORT_CRITICAL_SECTION_ENTER();
1545 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
1546 PORT_CRITICAL_SECTION_LEAVE();
1547 }
1548
hri_port_toggle_EVCTRL_PORTEI0_bit(const void * const hw,uint8_t submodule_index)1549 static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index)
1550 {
1551 PORT_CRITICAL_SECTION_ENTER();
1552 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0;
1553 PORT_CRITICAL_SECTION_LEAVE();
1554 }
1555
hri_port_set_EVCTRL_PORTEI1_bit(const void * const hw,uint8_t submodule_index)1556 static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
1557 {
1558 PORT_CRITICAL_SECTION_ENTER();
1559 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
1560 PORT_CRITICAL_SECTION_LEAVE();
1561 }
1562
hri_port_get_EVCTRL_PORTEI1_bit(const void * const hw,uint8_t submodule_index)1563 static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
1564 {
1565 uint32_t tmp;
1566 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1567 tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos;
1568 return (bool)tmp;
1569 }
1570
hri_port_write_EVCTRL_PORTEI1_bit(const void * const hw,uint8_t submodule_index,bool value)1571 static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value)
1572 {
1573 uint32_t tmp;
1574 PORT_CRITICAL_SECTION_ENTER();
1575 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1576 tmp &= ~PORT_EVCTRL_PORTEI1;
1577 tmp |= value << PORT_EVCTRL_PORTEI1_Pos;
1578 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1579 PORT_CRITICAL_SECTION_LEAVE();
1580 }
1581
hri_port_clear_EVCTRL_PORTEI1_bit(const void * const hw,uint8_t submodule_index)1582 static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
1583 {
1584 PORT_CRITICAL_SECTION_ENTER();
1585 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
1586 PORT_CRITICAL_SECTION_LEAVE();
1587 }
1588
hri_port_toggle_EVCTRL_PORTEI1_bit(const void * const hw,uint8_t submodule_index)1589 static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index)
1590 {
1591 PORT_CRITICAL_SECTION_ENTER();
1592 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1;
1593 PORT_CRITICAL_SECTION_LEAVE();
1594 }
1595
hri_port_set_EVCTRL_PORTEI2_bit(const void * const hw,uint8_t submodule_index)1596 static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
1597 {
1598 PORT_CRITICAL_SECTION_ENTER();
1599 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
1600 PORT_CRITICAL_SECTION_LEAVE();
1601 }
1602
hri_port_get_EVCTRL_PORTEI2_bit(const void * const hw,uint8_t submodule_index)1603 static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
1604 {
1605 uint32_t tmp;
1606 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1607 tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos;
1608 return (bool)tmp;
1609 }
1610
hri_port_write_EVCTRL_PORTEI2_bit(const void * const hw,uint8_t submodule_index,bool value)1611 static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value)
1612 {
1613 uint32_t tmp;
1614 PORT_CRITICAL_SECTION_ENTER();
1615 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1616 tmp &= ~PORT_EVCTRL_PORTEI2;
1617 tmp |= value << PORT_EVCTRL_PORTEI2_Pos;
1618 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1619 PORT_CRITICAL_SECTION_LEAVE();
1620 }
1621
hri_port_clear_EVCTRL_PORTEI2_bit(const void * const hw,uint8_t submodule_index)1622 static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
1623 {
1624 PORT_CRITICAL_SECTION_ENTER();
1625 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
1626 PORT_CRITICAL_SECTION_LEAVE();
1627 }
1628
hri_port_toggle_EVCTRL_PORTEI2_bit(const void * const hw,uint8_t submodule_index)1629 static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index)
1630 {
1631 PORT_CRITICAL_SECTION_ENTER();
1632 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2;
1633 PORT_CRITICAL_SECTION_LEAVE();
1634 }
1635
hri_port_set_EVCTRL_PORTEI3_bit(const void * const hw,uint8_t submodule_index)1636 static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
1637 {
1638 PORT_CRITICAL_SECTION_ENTER();
1639 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
1640 PORT_CRITICAL_SECTION_LEAVE();
1641 }
1642
hri_port_get_EVCTRL_PORTEI3_bit(const void * const hw,uint8_t submodule_index)1643 static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
1644 {
1645 uint32_t tmp;
1646 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1647 tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos;
1648 return (bool)tmp;
1649 }
1650
hri_port_write_EVCTRL_PORTEI3_bit(const void * const hw,uint8_t submodule_index,bool value)1651 static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value)
1652 {
1653 uint32_t tmp;
1654 PORT_CRITICAL_SECTION_ENTER();
1655 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1656 tmp &= ~PORT_EVCTRL_PORTEI3;
1657 tmp |= value << PORT_EVCTRL_PORTEI3_Pos;
1658 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1659 PORT_CRITICAL_SECTION_LEAVE();
1660 }
1661
hri_port_clear_EVCTRL_PORTEI3_bit(const void * const hw,uint8_t submodule_index)1662 static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
1663 {
1664 PORT_CRITICAL_SECTION_ENTER();
1665 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
1666 PORT_CRITICAL_SECTION_LEAVE();
1667 }
1668
hri_port_toggle_EVCTRL_PORTEI3_bit(const void * const hw,uint8_t submodule_index)1669 static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index)
1670 {
1671 PORT_CRITICAL_SECTION_ENTER();
1672 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3;
1673 PORT_CRITICAL_SECTION_LEAVE();
1674 }
1675
hri_port_set_EVCTRL_PID0_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1676 static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
1677 hri_port_evctrl_reg_t mask)
1678 {
1679 PORT_CRITICAL_SECTION_ENTER();
1680 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask);
1681 PORT_CRITICAL_SECTION_LEAVE();
1682 }
1683
hri_port_get_EVCTRL_PID0_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1684 static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
1685 hri_port_evctrl_reg_t mask)
1686 {
1687 uint32_t tmp;
1688 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1689 tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos;
1690 return tmp;
1691 }
1692
hri_port_write_EVCTRL_PID0_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t data)1693 static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
1694 hri_port_evctrl_reg_t data)
1695 {
1696 uint32_t tmp;
1697 PORT_CRITICAL_SECTION_ENTER();
1698 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1699 tmp &= ~PORT_EVCTRL_PID0_Msk;
1700 tmp |= PORT_EVCTRL_PID0(data);
1701 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1702 PORT_CRITICAL_SECTION_LEAVE();
1703 }
1704
hri_port_clear_EVCTRL_PID0_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1705 static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
1706 hri_port_evctrl_reg_t mask)
1707 {
1708 PORT_CRITICAL_SECTION_ENTER();
1709 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask);
1710 PORT_CRITICAL_SECTION_LEAVE();
1711 }
1712
hri_port_toggle_EVCTRL_PID0_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1713 static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index,
1714 hri_port_evctrl_reg_t mask)
1715 {
1716 PORT_CRITICAL_SECTION_ENTER();
1717 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask);
1718 PORT_CRITICAL_SECTION_LEAVE();
1719 }
1720
hri_port_read_EVCTRL_PID0_bf(const void * const hw,uint8_t submodule_index)1721 static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index)
1722 {
1723 uint32_t tmp;
1724 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1725 tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos;
1726 return tmp;
1727 }
1728
hri_port_set_EVCTRL_EVACT0_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1729 static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
1730 hri_port_evctrl_reg_t mask)
1731 {
1732 PORT_CRITICAL_SECTION_ENTER();
1733 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask);
1734 PORT_CRITICAL_SECTION_LEAVE();
1735 }
1736
hri_port_get_EVCTRL_EVACT0_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1737 static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
1738 hri_port_evctrl_reg_t mask)
1739 {
1740 uint32_t tmp;
1741 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1742 tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos;
1743 return tmp;
1744 }
1745
hri_port_write_EVCTRL_EVACT0_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t data)1746 static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
1747 hri_port_evctrl_reg_t data)
1748 {
1749 uint32_t tmp;
1750 PORT_CRITICAL_SECTION_ENTER();
1751 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1752 tmp &= ~PORT_EVCTRL_EVACT0_Msk;
1753 tmp |= PORT_EVCTRL_EVACT0(data);
1754 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1755 PORT_CRITICAL_SECTION_LEAVE();
1756 }
1757
hri_port_clear_EVCTRL_EVACT0_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1758 static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
1759 hri_port_evctrl_reg_t mask)
1760 {
1761 PORT_CRITICAL_SECTION_ENTER();
1762 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask);
1763 PORT_CRITICAL_SECTION_LEAVE();
1764 }
1765
hri_port_toggle_EVCTRL_EVACT0_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1766 static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index,
1767 hri_port_evctrl_reg_t mask)
1768 {
1769 PORT_CRITICAL_SECTION_ENTER();
1770 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask);
1771 PORT_CRITICAL_SECTION_LEAVE();
1772 }
1773
hri_port_read_EVCTRL_EVACT0_bf(const void * const hw,uint8_t submodule_index)1774 static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index)
1775 {
1776 uint32_t tmp;
1777 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1778 tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos;
1779 return tmp;
1780 }
1781
hri_port_set_EVCTRL_PID1_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1782 static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
1783 hri_port_evctrl_reg_t mask)
1784 {
1785 PORT_CRITICAL_SECTION_ENTER();
1786 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask);
1787 PORT_CRITICAL_SECTION_LEAVE();
1788 }
1789
hri_port_get_EVCTRL_PID1_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1790 static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
1791 hri_port_evctrl_reg_t mask)
1792 {
1793 uint32_t tmp;
1794 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1795 tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos;
1796 return tmp;
1797 }
1798
hri_port_write_EVCTRL_PID1_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t data)1799 static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
1800 hri_port_evctrl_reg_t data)
1801 {
1802 uint32_t tmp;
1803 PORT_CRITICAL_SECTION_ENTER();
1804 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1805 tmp &= ~PORT_EVCTRL_PID1_Msk;
1806 tmp |= PORT_EVCTRL_PID1(data);
1807 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1808 PORT_CRITICAL_SECTION_LEAVE();
1809 }
1810
hri_port_clear_EVCTRL_PID1_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1811 static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
1812 hri_port_evctrl_reg_t mask)
1813 {
1814 PORT_CRITICAL_SECTION_ENTER();
1815 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask);
1816 PORT_CRITICAL_SECTION_LEAVE();
1817 }
1818
hri_port_toggle_EVCTRL_PID1_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1819 static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index,
1820 hri_port_evctrl_reg_t mask)
1821 {
1822 PORT_CRITICAL_SECTION_ENTER();
1823 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask);
1824 PORT_CRITICAL_SECTION_LEAVE();
1825 }
1826
hri_port_read_EVCTRL_PID1_bf(const void * const hw,uint8_t submodule_index)1827 static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index)
1828 {
1829 uint32_t tmp;
1830 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1831 tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos;
1832 return tmp;
1833 }
1834
hri_port_set_EVCTRL_EVACT1_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1835 static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
1836 hri_port_evctrl_reg_t mask)
1837 {
1838 PORT_CRITICAL_SECTION_ENTER();
1839 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask);
1840 PORT_CRITICAL_SECTION_LEAVE();
1841 }
1842
hri_port_get_EVCTRL_EVACT1_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1843 static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
1844 hri_port_evctrl_reg_t mask)
1845 {
1846 uint32_t tmp;
1847 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1848 tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos;
1849 return tmp;
1850 }
1851
hri_port_write_EVCTRL_EVACT1_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t data)1852 static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
1853 hri_port_evctrl_reg_t data)
1854 {
1855 uint32_t tmp;
1856 PORT_CRITICAL_SECTION_ENTER();
1857 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1858 tmp &= ~PORT_EVCTRL_EVACT1_Msk;
1859 tmp |= PORT_EVCTRL_EVACT1(data);
1860 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1861 PORT_CRITICAL_SECTION_LEAVE();
1862 }
1863
hri_port_clear_EVCTRL_EVACT1_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1864 static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
1865 hri_port_evctrl_reg_t mask)
1866 {
1867 PORT_CRITICAL_SECTION_ENTER();
1868 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask);
1869 PORT_CRITICAL_SECTION_LEAVE();
1870 }
1871
hri_port_toggle_EVCTRL_EVACT1_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1872 static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index,
1873 hri_port_evctrl_reg_t mask)
1874 {
1875 PORT_CRITICAL_SECTION_ENTER();
1876 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask);
1877 PORT_CRITICAL_SECTION_LEAVE();
1878 }
1879
hri_port_read_EVCTRL_EVACT1_bf(const void * const hw,uint8_t submodule_index)1880 static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index)
1881 {
1882 uint32_t tmp;
1883 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1884 tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos;
1885 return tmp;
1886 }
1887
hri_port_set_EVCTRL_PID2_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1888 static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
1889 hri_port_evctrl_reg_t mask)
1890 {
1891 PORT_CRITICAL_SECTION_ENTER();
1892 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask);
1893 PORT_CRITICAL_SECTION_LEAVE();
1894 }
1895
hri_port_get_EVCTRL_PID2_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1896 static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
1897 hri_port_evctrl_reg_t mask)
1898 {
1899 uint32_t tmp;
1900 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1901 tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos;
1902 return tmp;
1903 }
1904
hri_port_write_EVCTRL_PID2_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t data)1905 static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
1906 hri_port_evctrl_reg_t data)
1907 {
1908 uint32_t tmp;
1909 PORT_CRITICAL_SECTION_ENTER();
1910 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1911 tmp &= ~PORT_EVCTRL_PID2_Msk;
1912 tmp |= PORT_EVCTRL_PID2(data);
1913 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1914 PORT_CRITICAL_SECTION_LEAVE();
1915 }
1916
hri_port_clear_EVCTRL_PID2_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1917 static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
1918 hri_port_evctrl_reg_t mask)
1919 {
1920 PORT_CRITICAL_SECTION_ENTER();
1921 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask);
1922 PORT_CRITICAL_SECTION_LEAVE();
1923 }
1924
hri_port_toggle_EVCTRL_PID2_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1925 static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index,
1926 hri_port_evctrl_reg_t mask)
1927 {
1928 PORT_CRITICAL_SECTION_ENTER();
1929 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask);
1930 PORT_CRITICAL_SECTION_LEAVE();
1931 }
1932
hri_port_read_EVCTRL_PID2_bf(const void * const hw,uint8_t submodule_index)1933 static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index)
1934 {
1935 uint32_t tmp;
1936 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1937 tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos;
1938 return tmp;
1939 }
1940
hri_port_set_EVCTRL_EVACT2_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1941 static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
1942 hri_port_evctrl_reg_t mask)
1943 {
1944 PORT_CRITICAL_SECTION_ENTER();
1945 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask);
1946 PORT_CRITICAL_SECTION_LEAVE();
1947 }
1948
hri_port_get_EVCTRL_EVACT2_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1949 static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
1950 hri_port_evctrl_reg_t mask)
1951 {
1952 uint32_t tmp;
1953 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1954 tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos;
1955 return tmp;
1956 }
1957
hri_port_write_EVCTRL_EVACT2_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t data)1958 static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
1959 hri_port_evctrl_reg_t data)
1960 {
1961 uint32_t tmp;
1962 PORT_CRITICAL_SECTION_ENTER();
1963 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1964 tmp &= ~PORT_EVCTRL_EVACT2_Msk;
1965 tmp |= PORT_EVCTRL_EVACT2(data);
1966 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
1967 PORT_CRITICAL_SECTION_LEAVE();
1968 }
1969
hri_port_clear_EVCTRL_EVACT2_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1970 static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
1971 hri_port_evctrl_reg_t mask)
1972 {
1973 PORT_CRITICAL_SECTION_ENTER();
1974 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask);
1975 PORT_CRITICAL_SECTION_LEAVE();
1976 }
1977
hri_port_toggle_EVCTRL_EVACT2_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1978 static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index,
1979 hri_port_evctrl_reg_t mask)
1980 {
1981 PORT_CRITICAL_SECTION_ENTER();
1982 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask);
1983 PORT_CRITICAL_SECTION_LEAVE();
1984 }
1985
hri_port_read_EVCTRL_EVACT2_bf(const void * const hw,uint8_t submodule_index)1986 static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index)
1987 {
1988 uint32_t tmp;
1989 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
1990 tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos;
1991 return tmp;
1992 }
1993
hri_port_set_EVCTRL_PID3_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)1994 static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
1995 hri_port_evctrl_reg_t mask)
1996 {
1997 PORT_CRITICAL_SECTION_ENTER();
1998 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask);
1999 PORT_CRITICAL_SECTION_LEAVE();
2000 }
2001
hri_port_get_EVCTRL_PID3_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)2002 static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
2003 hri_port_evctrl_reg_t mask)
2004 {
2005 uint32_t tmp;
2006 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2007 tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos;
2008 return tmp;
2009 }
2010
hri_port_write_EVCTRL_PID3_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t data)2011 static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
2012 hri_port_evctrl_reg_t data)
2013 {
2014 uint32_t tmp;
2015 PORT_CRITICAL_SECTION_ENTER();
2016 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2017 tmp &= ~PORT_EVCTRL_PID3_Msk;
2018 tmp |= PORT_EVCTRL_PID3(data);
2019 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
2020 PORT_CRITICAL_SECTION_LEAVE();
2021 }
2022
hri_port_clear_EVCTRL_PID3_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)2023 static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
2024 hri_port_evctrl_reg_t mask)
2025 {
2026 PORT_CRITICAL_SECTION_ENTER();
2027 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask);
2028 PORT_CRITICAL_SECTION_LEAVE();
2029 }
2030
hri_port_toggle_EVCTRL_PID3_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)2031 static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index,
2032 hri_port_evctrl_reg_t mask)
2033 {
2034 PORT_CRITICAL_SECTION_ENTER();
2035 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask);
2036 PORT_CRITICAL_SECTION_LEAVE();
2037 }
2038
hri_port_read_EVCTRL_PID3_bf(const void * const hw,uint8_t submodule_index)2039 static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index)
2040 {
2041 uint32_t tmp;
2042 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2043 tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos;
2044 return tmp;
2045 }
2046
hri_port_set_EVCTRL_EVACT3_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)2047 static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
2048 hri_port_evctrl_reg_t mask)
2049 {
2050 PORT_CRITICAL_SECTION_ENTER();
2051 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask);
2052 PORT_CRITICAL_SECTION_LEAVE();
2053 }
2054
hri_port_get_EVCTRL_EVACT3_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)2055 static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
2056 hri_port_evctrl_reg_t mask)
2057 {
2058 uint32_t tmp;
2059 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2060 tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos;
2061 return tmp;
2062 }
2063
hri_port_write_EVCTRL_EVACT3_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t data)2064 static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
2065 hri_port_evctrl_reg_t data)
2066 {
2067 uint32_t tmp;
2068 PORT_CRITICAL_SECTION_ENTER();
2069 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2070 tmp &= ~PORT_EVCTRL_EVACT3_Msk;
2071 tmp |= PORT_EVCTRL_EVACT3(data);
2072 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp;
2073 PORT_CRITICAL_SECTION_LEAVE();
2074 }
2075
hri_port_clear_EVCTRL_EVACT3_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)2076 static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
2077 hri_port_evctrl_reg_t mask)
2078 {
2079 PORT_CRITICAL_SECTION_ENTER();
2080 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask);
2081 PORT_CRITICAL_SECTION_LEAVE();
2082 }
2083
hri_port_toggle_EVCTRL_EVACT3_bf(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)2084 static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index,
2085 hri_port_evctrl_reg_t mask)
2086 {
2087 PORT_CRITICAL_SECTION_ENTER();
2088 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask);
2089 PORT_CRITICAL_SECTION_LEAVE();
2090 }
2091
hri_port_read_EVCTRL_EVACT3_bf(const void * const hw,uint8_t submodule_index)2092 static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index)
2093 {
2094 uint32_t tmp;
2095 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2096 tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos;
2097 return tmp;
2098 }
2099
hri_port_set_EVCTRL_reg(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)2100 static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
2101 {
2102 PORT_CRITICAL_SECTION_ENTER();
2103 ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask;
2104 PORT_CRITICAL_SECTION_LEAVE();
2105 }
2106
hri_port_get_EVCTRL_reg(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)2107 static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index,
2108 hri_port_evctrl_reg_t mask)
2109 {
2110 uint32_t tmp;
2111 tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2112 tmp &= mask;
2113 return tmp;
2114 }
2115
hri_port_write_EVCTRL_reg(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t data)2116 static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data)
2117 {
2118 PORT_CRITICAL_SECTION_ENTER();
2119 ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data;
2120 PORT_CRITICAL_SECTION_LEAVE();
2121 }
2122
hri_port_clear_EVCTRL_reg(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)2123 static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
2124 {
2125 PORT_CRITICAL_SECTION_ENTER();
2126 ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask;
2127 PORT_CRITICAL_SECTION_LEAVE();
2128 }
2129
hri_port_toggle_EVCTRL_reg(const void * const hw,uint8_t submodule_index,hri_port_evctrl_reg_t mask)2130 static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask)
2131 {
2132 PORT_CRITICAL_SECTION_ENTER();
2133 ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask;
2134 PORT_CRITICAL_SECTION_LEAVE();
2135 }
2136
hri_port_read_EVCTRL_reg(const void * const hw,uint8_t submodule_index)2137 static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index)
2138 {
2139 return ((Port *)hw)->Group[submodule_index].EVCTRL.reg;
2140 }
2141
hri_port_set_PMUX_PMUXE_bf(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2142 static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2143 hri_port_pmux_reg_t mask)
2144 {
2145 PORT_CRITICAL_SECTION_ENTER();
2146 ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask);
2147 PORT_CRITICAL_SECTION_LEAVE();
2148 }
2149
hri_port_get_PMUX_PMUXE_bf(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2150 static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
2151 uint8_t index, hri_port_pmux_reg_t mask)
2152 {
2153 uint8_t tmp;
2154 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2155 tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos;
2156 return tmp;
2157 }
2158
hri_port_write_PMUX_PMUXE_bf(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t data)2159 static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2160 hri_port_pmux_reg_t data)
2161 {
2162 uint8_t tmp;
2163 PORT_CRITICAL_SECTION_ENTER();
2164 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2165 tmp &= ~PORT_PMUX_PMUXE_Msk;
2166 tmp |= PORT_PMUX_PMUXE(data);
2167 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
2168 PORT_CRITICAL_SECTION_LEAVE();
2169 }
2170
hri_port_clear_PMUX_PMUXE_bf(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2171 static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2172 hri_port_pmux_reg_t mask)
2173 {
2174 PORT_CRITICAL_SECTION_ENTER();
2175 ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask);
2176 PORT_CRITICAL_SECTION_LEAVE();
2177 }
2178
hri_port_toggle_PMUX_PMUXE_bf(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2179 static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2180 hri_port_pmux_reg_t mask)
2181 {
2182 PORT_CRITICAL_SECTION_ENTER();
2183 ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask);
2184 PORT_CRITICAL_SECTION_LEAVE();
2185 }
2186
hri_port_read_PMUX_PMUXE_bf(const void * const hw,uint8_t submodule_index,uint8_t index)2187 static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index,
2188 uint8_t index)
2189 {
2190 uint8_t tmp;
2191 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2192 tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
2193 return tmp;
2194 }
2195
hri_port_set_PMUX_PMUXO_bf(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2196 static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2197 hri_port_pmux_reg_t mask)
2198 {
2199 PORT_CRITICAL_SECTION_ENTER();
2200 ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask);
2201 PORT_CRITICAL_SECTION_LEAVE();
2202 }
2203
hri_port_get_PMUX_PMUXO_bf(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2204 static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
2205 uint8_t index, hri_port_pmux_reg_t mask)
2206 {
2207 uint8_t tmp;
2208 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2209 tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos;
2210 return tmp;
2211 }
2212
hri_port_write_PMUX_PMUXO_bf(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t data)2213 static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2214 hri_port_pmux_reg_t data)
2215 {
2216 uint8_t tmp;
2217 PORT_CRITICAL_SECTION_ENTER();
2218 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2219 tmp &= ~PORT_PMUX_PMUXO_Msk;
2220 tmp |= PORT_PMUX_PMUXO(data);
2221 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
2222 PORT_CRITICAL_SECTION_LEAVE();
2223 }
2224
hri_port_clear_PMUX_PMUXO_bf(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2225 static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2226 hri_port_pmux_reg_t mask)
2227 {
2228 PORT_CRITICAL_SECTION_ENTER();
2229 ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask);
2230 PORT_CRITICAL_SECTION_LEAVE();
2231 }
2232
hri_port_toggle_PMUX_PMUXO_bf(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2233 static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
2234 hri_port_pmux_reg_t mask)
2235 {
2236 PORT_CRITICAL_SECTION_ENTER();
2237 ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask);
2238 PORT_CRITICAL_SECTION_LEAVE();
2239 }
2240
hri_port_read_PMUX_PMUXO_bf(const void * const hw,uint8_t submodule_index,uint8_t index)2241 static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index,
2242 uint8_t index)
2243 {
2244 uint8_t tmp;
2245 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2246 tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
2247 return tmp;
2248 }
2249
hri_port_set_PMUX_reg(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2250 static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2251 hri_port_pmux_reg_t mask)
2252 {
2253 PORT_CRITICAL_SECTION_ENTER();
2254 ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask;
2255 PORT_CRITICAL_SECTION_LEAVE();
2256 }
2257
hri_port_get_PMUX_reg(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2258 static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2259 hri_port_pmux_reg_t mask)
2260 {
2261 uint8_t tmp;
2262 tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2263 tmp &= mask;
2264 return tmp;
2265 }
2266
hri_port_write_PMUX_reg(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t data)2267 static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2268 hri_port_pmux_reg_t data)
2269 {
2270 PORT_CRITICAL_SECTION_ENTER();
2271 ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data;
2272 PORT_CRITICAL_SECTION_LEAVE();
2273 }
2274
hri_port_clear_PMUX_reg(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2275 static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2276 hri_port_pmux_reg_t mask)
2277 {
2278 PORT_CRITICAL_SECTION_ENTER();
2279 ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask;
2280 PORT_CRITICAL_SECTION_LEAVE();
2281 }
2282
hri_port_toggle_PMUX_reg(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pmux_reg_t mask)2283 static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2284 hri_port_pmux_reg_t mask)
2285 {
2286 PORT_CRITICAL_SECTION_ENTER();
2287 ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask;
2288 PORT_CRITICAL_SECTION_LEAVE();
2289 }
2290
hri_port_read_PMUX_reg(const void * const hw,uint8_t submodule_index,uint8_t index)2291 static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index)
2292 {
2293 return ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
2294 }
2295
hri_port_set_PINCFG_PMUXEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2296 static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2297 {
2298 PORT_CRITICAL_SECTION_ENTER();
2299 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN;
2300 PORT_CRITICAL_SECTION_LEAVE();
2301 }
2302
hri_port_get_PINCFG_PMUXEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2303 static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2304 {
2305 uint8_t tmp;
2306 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2307 tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos;
2308 return (bool)tmp;
2309 }
2310
hri_port_write_PINCFG_PMUXEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index,bool value)2311 static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
2312 bool value)
2313 {
2314 uint8_t tmp;
2315 PORT_CRITICAL_SECTION_ENTER();
2316 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2317 tmp &= ~PORT_PINCFG_PMUXEN;
2318 tmp |= value << PORT_PINCFG_PMUXEN_Pos;
2319 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
2320 PORT_CRITICAL_SECTION_LEAVE();
2321 }
2322
hri_port_clear_PINCFG_PMUXEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2323 static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2324 {
2325 PORT_CRITICAL_SECTION_ENTER();
2326 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN;
2327 PORT_CRITICAL_SECTION_LEAVE();
2328 }
2329
hri_port_toggle_PINCFG_PMUXEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2330 static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2331 {
2332 PORT_CRITICAL_SECTION_ENTER();
2333 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN;
2334 PORT_CRITICAL_SECTION_LEAVE();
2335 }
2336
hri_port_set_PINCFG_INEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2337 static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2338 {
2339 PORT_CRITICAL_SECTION_ENTER();
2340 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN;
2341 PORT_CRITICAL_SECTION_LEAVE();
2342 }
2343
hri_port_get_PINCFG_INEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2344 static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2345 {
2346 uint8_t tmp;
2347 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2348 tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos;
2349 return (bool)tmp;
2350 }
2351
hri_port_write_PINCFG_INEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index,bool value)2352 static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
2353 bool value)
2354 {
2355 uint8_t tmp;
2356 PORT_CRITICAL_SECTION_ENTER();
2357 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2358 tmp &= ~PORT_PINCFG_INEN;
2359 tmp |= value << PORT_PINCFG_INEN_Pos;
2360 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
2361 PORT_CRITICAL_SECTION_LEAVE();
2362 }
2363
hri_port_clear_PINCFG_INEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2364 static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2365 {
2366 PORT_CRITICAL_SECTION_ENTER();
2367 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN;
2368 PORT_CRITICAL_SECTION_LEAVE();
2369 }
2370
hri_port_toggle_PINCFG_INEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2371 static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2372 {
2373 PORT_CRITICAL_SECTION_ENTER();
2374 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN;
2375 PORT_CRITICAL_SECTION_LEAVE();
2376 }
2377
hri_port_set_PINCFG_PULLEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2378 static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2379 {
2380 PORT_CRITICAL_SECTION_ENTER();
2381 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN;
2382 PORT_CRITICAL_SECTION_LEAVE();
2383 }
2384
hri_port_get_PINCFG_PULLEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2385 static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2386 {
2387 uint8_t tmp;
2388 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2389 tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos;
2390 return (bool)tmp;
2391 }
2392
hri_port_write_PINCFG_PULLEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index,bool value)2393 static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
2394 bool value)
2395 {
2396 uint8_t tmp;
2397 PORT_CRITICAL_SECTION_ENTER();
2398 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2399 tmp &= ~PORT_PINCFG_PULLEN;
2400 tmp |= value << PORT_PINCFG_PULLEN_Pos;
2401 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
2402 PORT_CRITICAL_SECTION_LEAVE();
2403 }
2404
hri_port_clear_PINCFG_PULLEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2405 static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2406 {
2407 PORT_CRITICAL_SECTION_ENTER();
2408 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
2409 PORT_CRITICAL_SECTION_LEAVE();
2410 }
2411
hri_port_toggle_PINCFG_PULLEN_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2412 static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2413 {
2414 PORT_CRITICAL_SECTION_ENTER();
2415 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN;
2416 PORT_CRITICAL_SECTION_LEAVE();
2417 }
2418
hri_port_set_PINCFG_DRVSTR_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2419 static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2420 {
2421 PORT_CRITICAL_SECTION_ENTER();
2422 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR;
2423 PORT_CRITICAL_SECTION_LEAVE();
2424 }
2425
hri_port_get_PINCFG_DRVSTR_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2426 static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2427 {
2428 uint8_t tmp;
2429 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2430 tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos;
2431 return (bool)tmp;
2432 }
2433
hri_port_write_PINCFG_DRVSTR_bit(const void * const hw,uint8_t submodule_index,uint8_t index,bool value)2434 static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
2435 bool value)
2436 {
2437 uint8_t tmp;
2438 PORT_CRITICAL_SECTION_ENTER();
2439 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2440 tmp &= ~PORT_PINCFG_DRVSTR;
2441 tmp |= value << PORT_PINCFG_DRVSTR_Pos;
2442 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
2443 PORT_CRITICAL_SECTION_LEAVE();
2444 }
2445
hri_port_clear_PINCFG_DRVSTR_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2446 static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2447 {
2448 PORT_CRITICAL_SECTION_ENTER();
2449 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR;
2450 PORT_CRITICAL_SECTION_LEAVE();
2451 }
2452
hri_port_toggle_PINCFG_DRVSTR_bit(const void * const hw,uint8_t submodule_index,uint8_t index)2453 static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index)
2454 {
2455 PORT_CRITICAL_SECTION_ENTER();
2456 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR;
2457 PORT_CRITICAL_SECTION_LEAVE();
2458 }
2459
hri_port_set_PINCFG_reg(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pincfg_reg_t mask)2460 static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2461 hri_port_pincfg_reg_t mask)
2462 {
2463 PORT_CRITICAL_SECTION_ENTER();
2464 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask;
2465 PORT_CRITICAL_SECTION_LEAVE();
2466 }
2467
hri_port_get_PINCFG_reg(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pincfg_reg_t mask)2468 static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index,
2469 uint8_t index, hri_port_pincfg_reg_t mask)
2470 {
2471 uint8_t tmp;
2472 tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2473 tmp &= mask;
2474 return tmp;
2475 }
2476
hri_port_write_PINCFG_reg(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pincfg_reg_t data)2477 static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2478 hri_port_pincfg_reg_t data)
2479 {
2480 PORT_CRITICAL_SECTION_ENTER();
2481 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data;
2482 PORT_CRITICAL_SECTION_LEAVE();
2483 }
2484
hri_port_clear_PINCFG_reg(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pincfg_reg_t mask)2485 static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2486 hri_port_pincfg_reg_t mask)
2487 {
2488 PORT_CRITICAL_SECTION_ENTER();
2489 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask;
2490 PORT_CRITICAL_SECTION_LEAVE();
2491 }
2492
hri_port_toggle_PINCFG_reg(const void * const hw,uint8_t submodule_index,uint8_t index,hri_port_pincfg_reg_t mask)2493 static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index,
2494 hri_port_pincfg_reg_t mask)
2495 {
2496 PORT_CRITICAL_SECTION_ENTER();
2497 ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask;
2498 PORT_CRITICAL_SECTION_LEAVE();
2499 }
2500
hri_port_read_PINCFG_reg(const void * const hw,uint8_t submodule_index,uint8_t index)2501 static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index,
2502 uint8_t index)
2503 {
2504 return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
2505 }
2506
hri_port_get_IN_IN_bf(const void * const hw,uint8_t submodule_index,hri_port_in_reg_t mask)2507 static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index,
2508 hri_port_in_reg_t mask)
2509 {
2510 return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos;
2511 }
2512
hri_port_read_IN_IN_bf(const void * const hw,uint8_t submodule_index)2513 static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index)
2514 {
2515 return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos;
2516 }
2517
hri_port_get_IN_reg(const void * const hw,uint8_t submodule_index,hri_port_in_reg_t mask)2518 static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index,
2519 hri_port_in_reg_t mask)
2520 {
2521 uint32_t tmp;
2522 tmp = ((Port *)hw)->Group[submodule_index].IN.reg;
2523 tmp &= mask;
2524 return tmp;
2525 }
2526
hri_port_read_IN_reg(const void * const hw,uint8_t submodule_index)2527 static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index)
2528 {
2529 return ((Port *)hw)->Group[submodule_index].IN.reg;
2530 }
2531
2532 #ifdef __cplusplus
2533 }
2534 #endif
2535
2536 #endif /* _HRI_PORT_L21_H_INCLUDED */
2537 #endif /* _SAML21_PORT_COMPONENT_ */
2538
