1 /**
2  * \file
3  *
4  * \brief SAM EIC
5  *
6  * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7  *
8  * \asf_license_start
9  *
10  * \page License
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions are met:
14  *
15  * 1. Redistributions of source code must retain the above copyright notice,
16  *    this list of conditions and the following disclaimer.
17  *
18  * 2. Redistributions in binary form must reproduce the above copyright notice,
19  *    this list of conditions and the following disclaimer in the documentation
20  *    and/or other materials provided with the distribution.
21  *
22  * 3. The name of Atmel may not be used to endorse or promote products derived
23  *    from this software without specific prior written permission.
24  *
25  * 4. This software may only be redistributed and used in connection with an
26  *    Atmel microcontroller product.
27  *
28  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGE.
39  *
40  * \asf_license_stop
41  */
42 
43 #ifdef _SAML21_EIC_COMPONENT_
44 #ifndef _HRI_EIC_L21_H_INCLUDED_
45 #define _HRI_EIC_L21_H_INCLUDED_
46 
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50 
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53 
54 #if defined(ENABLE_EIC_CRITICAL_SECTIONS)
55 #define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define EIC_CRITICAL_SECTION_ENTER()
59 #define EIC_CRITICAL_SECTION_LEAVE()
60 #endif
61 
62 typedef uint16_t hri_eic_nmiflag_reg_t;
63 typedef uint32_t hri_eic_asynch_reg_t;
64 typedef uint32_t hri_eic_config_reg_t;
65 typedef uint32_t hri_eic_evctrl_reg_t;
66 typedef uint32_t hri_eic_intenset_reg_t;
67 typedef uint32_t hri_eic_intflag_reg_t;
68 typedef uint32_t hri_eic_syncbusy_reg_t;
69 typedef uint8_t  hri_eic_ctrla_reg_t;
70 typedef uint8_t  hri_eic_nmictrl_reg_t;
71 
hri_eic_wait_for_sync(const void * const hw,hri_eic_syncbusy_reg_t reg)72 static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg)
73 {
74 	while (((Eic *)hw)->SYNCBUSY.reg & reg) {
75 	};
76 }
77 
hri_eic_is_syncing(const void * const hw,hri_eic_syncbusy_reg_t reg)78 static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg)
79 {
80 	return ((Eic *)hw)->SYNCBUSY.reg & reg;
81 }
82 
hri_eic_set_INTEN_EXTINT_bf(const void * const hw,hri_eic_intenset_reg_t mask)83 static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
84 {
85 	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask);
86 }
87 
hri_eic_get_INTEN_EXTINT_bf(const void * const hw,hri_eic_intenset_reg_t mask)88 static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
89 {
90 	uint32_t tmp;
91 	tmp = ((Eic *)hw)->INTENSET.reg;
92 	tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos;
93 	return tmp;
94 }
95 
hri_eic_read_INTEN_EXTINT_bf(const void * const hw)96 static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw)
97 {
98 	uint32_t tmp;
99 	tmp = ((Eic *)hw)->INTENSET.reg;
100 	tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos;
101 	return tmp;
102 }
103 
hri_eic_write_INTEN_EXTINT_bf(const void * const hw,hri_eic_intenset_reg_t data)104 static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data)
105 {
106 	((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data);
107 	((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data);
108 }
109 
hri_eic_clear_INTEN_EXTINT_bf(const void * const hw,hri_eic_intenset_reg_t mask)110 static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask)
111 {
112 	((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask);
113 }
114 
hri_eic_set_INTEN_reg(const void * const hw,hri_eic_intenset_reg_t mask)115 static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
116 {
117 	((Eic *)hw)->INTENSET.reg = mask;
118 }
119 
hri_eic_get_INTEN_reg(const void * const hw,hri_eic_intenset_reg_t mask)120 static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
121 {
122 	uint32_t tmp;
123 	tmp = ((Eic *)hw)->INTENSET.reg;
124 	tmp &= mask;
125 	return tmp;
126 }
127 
hri_eic_read_INTEN_reg(const void * const hw)128 static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw)
129 {
130 	return ((Eic *)hw)->INTENSET.reg;
131 }
132 
hri_eic_write_INTEN_reg(const void * const hw,hri_eic_intenset_reg_t data)133 static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data)
134 {
135 	((Eic *)hw)->INTENSET.reg = data;
136 	((Eic *)hw)->INTENCLR.reg = ~data;
137 }
138 
hri_eic_clear_INTEN_reg(const void * const hw,hri_eic_intenset_reg_t mask)139 static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask)
140 {
141 	((Eic *)hw)->INTENCLR.reg = mask;
142 }
143 
hri_eic_get_NMIFLAG_NMI_bit(const void * const hw)144 static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw)
145 {
146 	return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos;
147 }
148 
hri_eic_clear_NMIFLAG_NMI_bit(const void * const hw)149 static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw)
150 {
151 	((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI;
152 }
153 
hri_eic_get_NMIFLAG_reg(const void * const hw,hri_eic_nmiflag_reg_t mask)154 static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
155 {
156 	uint16_t tmp;
157 	tmp = ((Eic *)hw)->NMIFLAG.reg;
158 	tmp &= mask;
159 	return tmp;
160 }
161 
hri_eic_read_NMIFLAG_reg(const void * const hw)162 static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw)
163 {
164 	return ((Eic *)hw)->NMIFLAG.reg;
165 }
166 
hri_eic_clear_NMIFLAG_reg(const void * const hw,hri_eic_nmiflag_reg_t mask)167 static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask)
168 {
169 	((Eic *)hw)->NMIFLAG.reg = mask;
170 }
171 
hri_eic_get_INTFLAG_reg(const void * const hw,hri_eic_intflag_reg_t mask)172 static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
173 {
174 	uint32_t tmp;
175 	tmp = ((Eic *)hw)->INTFLAG.reg;
176 	tmp &= mask;
177 	return tmp;
178 }
179 
hri_eic_read_INTFLAG_reg(const void * const hw)180 static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw)
181 {
182 	return ((Eic *)hw)->INTFLAG.reg;
183 }
184 
hri_eic_clear_INTFLAG_reg(const void * const hw,hri_eic_intflag_reg_t mask)185 static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask)
186 {
187 	((Eic *)hw)->INTFLAG.reg = mask;
188 }
189 
hri_eic_set_CTRLA_SWRST_bit(const void * const hw)190 static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw)
191 {
192 	EIC_CRITICAL_SECTION_ENTER();
193 	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
194 	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST;
195 	EIC_CRITICAL_SECTION_LEAVE();
196 }
197 
hri_eic_get_CTRLA_SWRST_bit(const void * const hw)198 static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw)
199 {
200 	uint8_t tmp;
201 	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST);
202 	tmp = ((Eic *)hw)->CTRLA.reg;
203 	tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos;
204 	return (bool)tmp;
205 }
206 
hri_eic_set_CTRLA_ENABLE_bit(const void * const hw)207 static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw)
208 {
209 	EIC_CRITICAL_SECTION_ENTER();
210 	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
211 	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE;
212 	EIC_CRITICAL_SECTION_LEAVE();
213 }
214 
hri_eic_get_CTRLA_ENABLE_bit(const void * const hw)215 static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw)
216 {
217 	uint8_t tmp;
218 	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
219 	tmp = ((Eic *)hw)->CTRLA.reg;
220 	tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos;
221 	return (bool)tmp;
222 }
223 
hri_eic_write_CTRLA_ENABLE_bit(const void * const hw,bool value)224 static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
225 {
226 	uint8_t tmp;
227 	EIC_CRITICAL_SECTION_ENTER();
228 	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
229 	tmp = ((Eic *)hw)->CTRLA.reg;
230 	tmp &= ~EIC_CTRLA_ENABLE;
231 	tmp |= value << EIC_CTRLA_ENABLE_Pos;
232 	((Eic *)hw)->CTRLA.reg = tmp;
233 	EIC_CRITICAL_SECTION_LEAVE();
234 }
235 
hri_eic_clear_CTRLA_ENABLE_bit(const void * const hw)236 static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw)
237 {
238 	EIC_CRITICAL_SECTION_ENTER();
239 	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
240 	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
241 	EIC_CRITICAL_SECTION_LEAVE();
242 }
243 
hri_eic_toggle_CTRLA_ENABLE_bit(const void * const hw)244 static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw)
245 {
246 	EIC_CRITICAL_SECTION_ENTER();
247 	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE);
248 	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE;
249 	EIC_CRITICAL_SECTION_LEAVE();
250 }
251 
hri_eic_set_CTRLA_CKSEL_bit(const void * const hw)252 static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw)
253 {
254 	EIC_CRITICAL_SECTION_ENTER();
255 	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
256 	((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL;
257 	EIC_CRITICAL_SECTION_LEAVE();
258 }
259 
hri_eic_get_CTRLA_CKSEL_bit(const void * const hw)260 static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw)
261 {
262 	uint8_t tmp;
263 	tmp = ((Eic *)hw)->CTRLA.reg;
264 	tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos;
265 	return (bool)tmp;
266 }
267 
hri_eic_write_CTRLA_CKSEL_bit(const void * const hw,bool value)268 static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value)
269 {
270 	uint8_t tmp;
271 	EIC_CRITICAL_SECTION_ENTER();
272 	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
273 	tmp = ((Eic *)hw)->CTRLA.reg;
274 	tmp &= ~EIC_CTRLA_CKSEL;
275 	tmp |= value << EIC_CTRLA_CKSEL_Pos;
276 	((Eic *)hw)->CTRLA.reg = tmp;
277 	EIC_CRITICAL_SECTION_LEAVE();
278 }
279 
hri_eic_clear_CTRLA_CKSEL_bit(const void * const hw)280 static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw)
281 {
282 	EIC_CRITICAL_SECTION_ENTER();
283 	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
284 	((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL;
285 	EIC_CRITICAL_SECTION_LEAVE();
286 }
287 
hri_eic_toggle_CTRLA_CKSEL_bit(const void * const hw)288 static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw)
289 {
290 	EIC_CRITICAL_SECTION_ENTER();
291 	hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK);
292 	((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL;
293 	EIC_CRITICAL_SECTION_LEAVE();
294 }
295 
hri_eic_set_CTRLA_reg(const void * const hw,hri_eic_ctrla_reg_t mask)296 static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
297 {
298 	EIC_CRITICAL_SECTION_ENTER();
299 	((Eic *)hw)->CTRLA.reg |= mask;
300 	EIC_CRITICAL_SECTION_LEAVE();
301 }
302 
hri_eic_get_CTRLA_reg(const void * const hw,hri_eic_ctrla_reg_t mask)303 static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
304 {
305 	uint8_t tmp;
306 	tmp = ((Eic *)hw)->CTRLA.reg;
307 	tmp &= mask;
308 	return tmp;
309 }
310 
hri_eic_write_CTRLA_reg(const void * const hw,hri_eic_ctrla_reg_t data)311 static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data)
312 {
313 	EIC_CRITICAL_SECTION_ENTER();
314 	((Eic *)hw)->CTRLA.reg = data;
315 	EIC_CRITICAL_SECTION_LEAVE();
316 }
317 
hri_eic_clear_CTRLA_reg(const void * const hw,hri_eic_ctrla_reg_t mask)318 static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
319 {
320 	EIC_CRITICAL_SECTION_ENTER();
321 	((Eic *)hw)->CTRLA.reg &= ~mask;
322 	EIC_CRITICAL_SECTION_LEAVE();
323 }
324 
hri_eic_toggle_CTRLA_reg(const void * const hw,hri_eic_ctrla_reg_t mask)325 static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask)
326 {
327 	EIC_CRITICAL_SECTION_ENTER();
328 	((Eic *)hw)->CTRLA.reg ^= mask;
329 	EIC_CRITICAL_SECTION_LEAVE();
330 }
331 
hri_eic_read_CTRLA_reg(const void * const hw)332 static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw)
333 {
334 	return ((Eic *)hw)->CTRLA.reg;
335 }
336 
hri_eic_set_NMICTRL_NMIFILTEN_bit(const void * const hw)337 static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw)
338 {
339 	EIC_CRITICAL_SECTION_ENTER();
340 	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN;
341 	EIC_CRITICAL_SECTION_LEAVE();
342 }
343 
hri_eic_get_NMICTRL_NMIFILTEN_bit(const void * const hw)344 static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw)
345 {
346 	uint8_t tmp;
347 	tmp = ((Eic *)hw)->NMICTRL.reg;
348 	tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos;
349 	return (bool)tmp;
350 }
351 
hri_eic_write_NMICTRL_NMIFILTEN_bit(const void * const hw,bool value)352 static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value)
353 {
354 	uint8_t tmp;
355 	EIC_CRITICAL_SECTION_ENTER();
356 	tmp = ((Eic *)hw)->NMICTRL.reg;
357 	tmp &= ~EIC_NMICTRL_NMIFILTEN;
358 	tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos;
359 	((Eic *)hw)->NMICTRL.reg = tmp;
360 	EIC_CRITICAL_SECTION_LEAVE();
361 }
362 
hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void * const hw)363 static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw)
364 {
365 	EIC_CRITICAL_SECTION_ENTER();
366 	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN;
367 	EIC_CRITICAL_SECTION_LEAVE();
368 }
369 
hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void * const hw)370 static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw)
371 {
372 	EIC_CRITICAL_SECTION_ENTER();
373 	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN;
374 	EIC_CRITICAL_SECTION_LEAVE();
375 }
376 
hri_eic_set_NMICTRL_NMIASYNCH_bit(const void * const hw)377 static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw)
378 {
379 	EIC_CRITICAL_SECTION_ENTER();
380 	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH;
381 	EIC_CRITICAL_SECTION_LEAVE();
382 }
383 
hri_eic_get_NMICTRL_NMIASYNCH_bit(const void * const hw)384 static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw)
385 {
386 	uint8_t tmp;
387 	tmp = ((Eic *)hw)->NMICTRL.reg;
388 	tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos;
389 	return (bool)tmp;
390 }
391 
hri_eic_write_NMICTRL_NMIASYNCH_bit(const void * const hw,bool value)392 static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value)
393 {
394 	uint8_t tmp;
395 	EIC_CRITICAL_SECTION_ENTER();
396 	tmp = ((Eic *)hw)->NMICTRL.reg;
397 	tmp &= ~EIC_NMICTRL_NMIASYNCH;
398 	tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos;
399 	((Eic *)hw)->NMICTRL.reg = tmp;
400 	EIC_CRITICAL_SECTION_LEAVE();
401 }
402 
hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void * const hw)403 static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw)
404 {
405 	EIC_CRITICAL_SECTION_ENTER();
406 	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH;
407 	EIC_CRITICAL_SECTION_LEAVE();
408 }
409 
hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void * const hw)410 static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw)
411 {
412 	EIC_CRITICAL_SECTION_ENTER();
413 	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH;
414 	EIC_CRITICAL_SECTION_LEAVE();
415 }
416 
hri_eic_set_NMICTRL_NMISENSE_bf(const void * const hw,hri_eic_nmictrl_reg_t mask)417 static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
418 {
419 	EIC_CRITICAL_SECTION_ENTER();
420 	((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask);
421 	EIC_CRITICAL_SECTION_LEAVE();
422 }
423 
hri_eic_get_NMICTRL_NMISENSE_bf(const void * const hw,hri_eic_nmictrl_reg_t mask)424 static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
425 {
426 	uint8_t tmp;
427 	tmp = ((Eic *)hw)->NMICTRL.reg;
428 	tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos;
429 	return tmp;
430 }
431 
hri_eic_write_NMICTRL_NMISENSE_bf(const void * const hw,hri_eic_nmictrl_reg_t data)432 static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data)
433 {
434 	uint8_t tmp;
435 	EIC_CRITICAL_SECTION_ENTER();
436 	tmp = ((Eic *)hw)->NMICTRL.reg;
437 	tmp &= ~EIC_NMICTRL_NMISENSE_Msk;
438 	tmp |= EIC_NMICTRL_NMISENSE(data);
439 	((Eic *)hw)->NMICTRL.reg = tmp;
440 	EIC_CRITICAL_SECTION_LEAVE();
441 }
442 
hri_eic_clear_NMICTRL_NMISENSE_bf(const void * const hw,hri_eic_nmictrl_reg_t mask)443 static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
444 {
445 	EIC_CRITICAL_SECTION_ENTER();
446 	((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask);
447 	EIC_CRITICAL_SECTION_LEAVE();
448 }
449 
hri_eic_toggle_NMICTRL_NMISENSE_bf(const void * const hw,hri_eic_nmictrl_reg_t mask)450 static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask)
451 {
452 	EIC_CRITICAL_SECTION_ENTER();
453 	((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask);
454 	EIC_CRITICAL_SECTION_LEAVE();
455 }
456 
hri_eic_read_NMICTRL_NMISENSE_bf(const void * const hw)457 static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw)
458 {
459 	uint8_t tmp;
460 	tmp = ((Eic *)hw)->NMICTRL.reg;
461 	tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos;
462 	return tmp;
463 }
464 
hri_eic_set_NMICTRL_reg(const void * const hw,hri_eic_nmictrl_reg_t mask)465 static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
466 {
467 	EIC_CRITICAL_SECTION_ENTER();
468 	((Eic *)hw)->NMICTRL.reg |= mask;
469 	EIC_CRITICAL_SECTION_LEAVE();
470 }
471 
hri_eic_get_NMICTRL_reg(const void * const hw,hri_eic_nmictrl_reg_t mask)472 static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
473 {
474 	uint8_t tmp;
475 	tmp = ((Eic *)hw)->NMICTRL.reg;
476 	tmp &= mask;
477 	return tmp;
478 }
479 
hri_eic_write_NMICTRL_reg(const void * const hw,hri_eic_nmictrl_reg_t data)480 static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data)
481 {
482 	EIC_CRITICAL_SECTION_ENTER();
483 	((Eic *)hw)->NMICTRL.reg = data;
484 	EIC_CRITICAL_SECTION_LEAVE();
485 }
486 
hri_eic_clear_NMICTRL_reg(const void * const hw,hri_eic_nmictrl_reg_t mask)487 static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
488 {
489 	EIC_CRITICAL_SECTION_ENTER();
490 	((Eic *)hw)->NMICTRL.reg &= ~mask;
491 	EIC_CRITICAL_SECTION_LEAVE();
492 }
493 
hri_eic_toggle_NMICTRL_reg(const void * const hw,hri_eic_nmictrl_reg_t mask)494 static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask)
495 {
496 	EIC_CRITICAL_SECTION_ENTER();
497 	((Eic *)hw)->NMICTRL.reg ^= mask;
498 	EIC_CRITICAL_SECTION_LEAVE();
499 }
500 
hri_eic_read_NMICTRL_reg(const void * const hw)501 static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw)
502 {
503 	return ((Eic *)hw)->NMICTRL.reg;
504 }
505 
hri_eic_set_EVCTRL_EXTINTEO_bf(const void * const hw,hri_eic_evctrl_reg_t mask)506 static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
507 {
508 	EIC_CRITICAL_SECTION_ENTER();
509 	((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask);
510 	EIC_CRITICAL_SECTION_LEAVE();
511 }
512 
hri_eic_get_EVCTRL_EXTINTEO_bf(const void * const hw,hri_eic_evctrl_reg_t mask)513 static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
514 {
515 	uint32_t tmp;
516 	tmp = ((Eic *)hw)->EVCTRL.reg;
517 	tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos;
518 	return tmp;
519 }
520 
hri_eic_write_EVCTRL_EXTINTEO_bf(const void * const hw,hri_eic_evctrl_reg_t data)521 static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data)
522 {
523 	uint32_t tmp;
524 	EIC_CRITICAL_SECTION_ENTER();
525 	tmp = ((Eic *)hw)->EVCTRL.reg;
526 	tmp &= ~EIC_EVCTRL_EXTINTEO_Msk;
527 	tmp |= EIC_EVCTRL_EXTINTEO(data);
528 	((Eic *)hw)->EVCTRL.reg = tmp;
529 	EIC_CRITICAL_SECTION_LEAVE();
530 }
531 
hri_eic_clear_EVCTRL_EXTINTEO_bf(const void * const hw,hri_eic_evctrl_reg_t mask)532 static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
533 {
534 	EIC_CRITICAL_SECTION_ENTER();
535 	((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask);
536 	EIC_CRITICAL_SECTION_LEAVE();
537 }
538 
hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void * const hw,hri_eic_evctrl_reg_t mask)539 static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask)
540 {
541 	EIC_CRITICAL_SECTION_ENTER();
542 	((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask);
543 	EIC_CRITICAL_SECTION_LEAVE();
544 }
545 
hri_eic_read_EVCTRL_EXTINTEO_bf(const void * const hw)546 static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw)
547 {
548 	uint32_t tmp;
549 	tmp = ((Eic *)hw)->EVCTRL.reg;
550 	tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos;
551 	return tmp;
552 }
553 
hri_eic_set_EVCTRL_reg(const void * const hw,hri_eic_evctrl_reg_t mask)554 static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
555 {
556 	EIC_CRITICAL_SECTION_ENTER();
557 	((Eic *)hw)->EVCTRL.reg |= mask;
558 	EIC_CRITICAL_SECTION_LEAVE();
559 }
560 
hri_eic_get_EVCTRL_reg(const void * const hw,hri_eic_evctrl_reg_t mask)561 static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
562 {
563 	uint32_t tmp;
564 	tmp = ((Eic *)hw)->EVCTRL.reg;
565 	tmp &= mask;
566 	return tmp;
567 }
568 
hri_eic_write_EVCTRL_reg(const void * const hw,hri_eic_evctrl_reg_t data)569 static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data)
570 {
571 	EIC_CRITICAL_SECTION_ENTER();
572 	((Eic *)hw)->EVCTRL.reg = data;
573 	EIC_CRITICAL_SECTION_LEAVE();
574 }
575 
hri_eic_clear_EVCTRL_reg(const void * const hw,hri_eic_evctrl_reg_t mask)576 static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
577 {
578 	EIC_CRITICAL_SECTION_ENTER();
579 	((Eic *)hw)->EVCTRL.reg &= ~mask;
580 	EIC_CRITICAL_SECTION_LEAVE();
581 }
582 
hri_eic_toggle_EVCTRL_reg(const void * const hw,hri_eic_evctrl_reg_t mask)583 static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask)
584 {
585 	EIC_CRITICAL_SECTION_ENTER();
586 	((Eic *)hw)->EVCTRL.reg ^= mask;
587 	EIC_CRITICAL_SECTION_LEAVE();
588 }
589 
hri_eic_read_EVCTRL_reg(const void * const hw)590 static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw)
591 {
592 	return ((Eic *)hw)->EVCTRL.reg;
593 }
594 
hri_eic_set_ASYNCH_ASYNCH_bf(const void * const hw,hri_eic_asynch_reg_t mask)595 static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
596 {
597 	EIC_CRITICAL_SECTION_ENTER();
598 	((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask);
599 	EIC_CRITICAL_SECTION_LEAVE();
600 }
601 
hri_eic_get_ASYNCH_ASYNCH_bf(const void * const hw,hri_eic_asynch_reg_t mask)602 static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
603 {
604 	uint32_t tmp;
605 	tmp = ((Eic *)hw)->ASYNCH.reg;
606 	tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos;
607 	return tmp;
608 }
609 
hri_eic_write_ASYNCH_ASYNCH_bf(const void * const hw,hri_eic_asynch_reg_t data)610 static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data)
611 {
612 	uint32_t tmp;
613 	EIC_CRITICAL_SECTION_ENTER();
614 	tmp = ((Eic *)hw)->ASYNCH.reg;
615 	tmp &= ~EIC_ASYNCH_ASYNCH_Msk;
616 	tmp |= EIC_ASYNCH_ASYNCH(data);
617 	((Eic *)hw)->ASYNCH.reg = tmp;
618 	EIC_CRITICAL_SECTION_LEAVE();
619 }
620 
hri_eic_clear_ASYNCH_ASYNCH_bf(const void * const hw,hri_eic_asynch_reg_t mask)621 static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
622 {
623 	EIC_CRITICAL_SECTION_ENTER();
624 	((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask);
625 	EIC_CRITICAL_SECTION_LEAVE();
626 }
627 
hri_eic_toggle_ASYNCH_ASYNCH_bf(const void * const hw,hri_eic_asynch_reg_t mask)628 static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask)
629 {
630 	EIC_CRITICAL_SECTION_ENTER();
631 	((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask);
632 	EIC_CRITICAL_SECTION_LEAVE();
633 }
634 
hri_eic_read_ASYNCH_ASYNCH_bf(const void * const hw)635 static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw)
636 {
637 	uint32_t tmp;
638 	tmp = ((Eic *)hw)->ASYNCH.reg;
639 	tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos;
640 	return tmp;
641 }
642 
hri_eic_set_ASYNCH_reg(const void * const hw,hri_eic_asynch_reg_t mask)643 static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
644 {
645 	EIC_CRITICAL_SECTION_ENTER();
646 	((Eic *)hw)->ASYNCH.reg |= mask;
647 	EIC_CRITICAL_SECTION_LEAVE();
648 }
649 
hri_eic_get_ASYNCH_reg(const void * const hw,hri_eic_asynch_reg_t mask)650 static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
651 {
652 	uint32_t tmp;
653 	tmp = ((Eic *)hw)->ASYNCH.reg;
654 	tmp &= mask;
655 	return tmp;
656 }
657 
hri_eic_write_ASYNCH_reg(const void * const hw,hri_eic_asynch_reg_t data)658 static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data)
659 {
660 	EIC_CRITICAL_SECTION_ENTER();
661 	((Eic *)hw)->ASYNCH.reg = data;
662 	EIC_CRITICAL_SECTION_LEAVE();
663 }
664 
hri_eic_clear_ASYNCH_reg(const void * const hw,hri_eic_asynch_reg_t mask)665 static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
666 {
667 	EIC_CRITICAL_SECTION_ENTER();
668 	((Eic *)hw)->ASYNCH.reg &= ~mask;
669 	EIC_CRITICAL_SECTION_LEAVE();
670 }
671 
hri_eic_toggle_ASYNCH_reg(const void * const hw,hri_eic_asynch_reg_t mask)672 static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask)
673 {
674 	EIC_CRITICAL_SECTION_ENTER();
675 	((Eic *)hw)->ASYNCH.reg ^= mask;
676 	EIC_CRITICAL_SECTION_LEAVE();
677 }
678 
hri_eic_read_ASYNCH_reg(const void * const hw)679 static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw)
680 {
681 	return ((Eic *)hw)->ASYNCH.reg;
682 }
683 
hri_eic_set_CONFIG_FILTEN0_bit(const void * const hw,uint8_t index)684 static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
685 {
686 	EIC_CRITICAL_SECTION_ENTER();
687 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0;
688 	EIC_CRITICAL_SECTION_LEAVE();
689 }
690 
hri_eic_get_CONFIG_FILTEN0_bit(const void * const hw,uint8_t index)691 static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
692 {
693 	uint32_t tmp;
694 	tmp = ((Eic *)hw)->CONFIG[index].reg;
695 	tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos;
696 	return (bool)tmp;
697 }
698 
hri_eic_write_CONFIG_FILTEN0_bit(const void * const hw,uint8_t index,bool value)699 static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value)
700 {
701 	uint32_t tmp;
702 	EIC_CRITICAL_SECTION_ENTER();
703 	tmp = ((Eic *)hw)->CONFIG[index].reg;
704 	tmp &= ~EIC_CONFIG_FILTEN0;
705 	tmp |= value << EIC_CONFIG_FILTEN0_Pos;
706 	((Eic *)hw)->CONFIG[index].reg = tmp;
707 	EIC_CRITICAL_SECTION_LEAVE();
708 }
709 
hri_eic_clear_CONFIG_FILTEN0_bit(const void * const hw,uint8_t index)710 static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
711 {
712 	EIC_CRITICAL_SECTION_ENTER();
713 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0;
714 	EIC_CRITICAL_SECTION_LEAVE();
715 }
716 
hri_eic_toggle_CONFIG_FILTEN0_bit(const void * const hw,uint8_t index)717 static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index)
718 {
719 	EIC_CRITICAL_SECTION_ENTER();
720 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0;
721 	EIC_CRITICAL_SECTION_LEAVE();
722 }
723 
hri_eic_set_CONFIG_FILTEN1_bit(const void * const hw,uint8_t index)724 static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
725 {
726 	EIC_CRITICAL_SECTION_ENTER();
727 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1;
728 	EIC_CRITICAL_SECTION_LEAVE();
729 }
730 
hri_eic_get_CONFIG_FILTEN1_bit(const void * const hw,uint8_t index)731 static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
732 {
733 	uint32_t tmp;
734 	tmp = ((Eic *)hw)->CONFIG[index].reg;
735 	tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos;
736 	return (bool)tmp;
737 }
738 
hri_eic_write_CONFIG_FILTEN1_bit(const void * const hw,uint8_t index,bool value)739 static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value)
740 {
741 	uint32_t tmp;
742 	EIC_CRITICAL_SECTION_ENTER();
743 	tmp = ((Eic *)hw)->CONFIG[index].reg;
744 	tmp &= ~EIC_CONFIG_FILTEN1;
745 	tmp |= value << EIC_CONFIG_FILTEN1_Pos;
746 	((Eic *)hw)->CONFIG[index].reg = tmp;
747 	EIC_CRITICAL_SECTION_LEAVE();
748 }
749 
hri_eic_clear_CONFIG_FILTEN1_bit(const void * const hw,uint8_t index)750 static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
751 {
752 	EIC_CRITICAL_SECTION_ENTER();
753 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1;
754 	EIC_CRITICAL_SECTION_LEAVE();
755 }
756 
hri_eic_toggle_CONFIG_FILTEN1_bit(const void * const hw,uint8_t index)757 static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index)
758 {
759 	EIC_CRITICAL_SECTION_ENTER();
760 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1;
761 	EIC_CRITICAL_SECTION_LEAVE();
762 }
763 
hri_eic_set_CONFIG_FILTEN2_bit(const void * const hw,uint8_t index)764 static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
765 {
766 	EIC_CRITICAL_SECTION_ENTER();
767 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2;
768 	EIC_CRITICAL_SECTION_LEAVE();
769 }
770 
hri_eic_get_CONFIG_FILTEN2_bit(const void * const hw,uint8_t index)771 static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
772 {
773 	uint32_t tmp;
774 	tmp = ((Eic *)hw)->CONFIG[index].reg;
775 	tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos;
776 	return (bool)tmp;
777 }
778 
hri_eic_write_CONFIG_FILTEN2_bit(const void * const hw,uint8_t index,bool value)779 static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value)
780 {
781 	uint32_t tmp;
782 	EIC_CRITICAL_SECTION_ENTER();
783 	tmp = ((Eic *)hw)->CONFIG[index].reg;
784 	tmp &= ~EIC_CONFIG_FILTEN2;
785 	tmp |= value << EIC_CONFIG_FILTEN2_Pos;
786 	((Eic *)hw)->CONFIG[index].reg = tmp;
787 	EIC_CRITICAL_SECTION_LEAVE();
788 }
789 
hri_eic_clear_CONFIG_FILTEN2_bit(const void * const hw,uint8_t index)790 static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
791 {
792 	EIC_CRITICAL_SECTION_ENTER();
793 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2;
794 	EIC_CRITICAL_SECTION_LEAVE();
795 }
796 
hri_eic_toggle_CONFIG_FILTEN2_bit(const void * const hw,uint8_t index)797 static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index)
798 {
799 	EIC_CRITICAL_SECTION_ENTER();
800 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2;
801 	EIC_CRITICAL_SECTION_LEAVE();
802 }
803 
hri_eic_set_CONFIG_FILTEN3_bit(const void * const hw,uint8_t index)804 static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
805 {
806 	EIC_CRITICAL_SECTION_ENTER();
807 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3;
808 	EIC_CRITICAL_SECTION_LEAVE();
809 }
810 
hri_eic_get_CONFIG_FILTEN3_bit(const void * const hw,uint8_t index)811 static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
812 {
813 	uint32_t tmp;
814 	tmp = ((Eic *)hw)->CONFIG[index].reg;
815 	tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos;
816 	return (bool)tmp;
817 }
818 
hri_eic_write_CONFIG_FILTEN3_bit(const void * const hw,uint8_t index,bool value)819 static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value)
820 {
821 	uint32_t tmp;
822 	EIC_CRITICAL_SECTION_ENTER();
823 	tmp = ((Eic *)hw)->CONFIG[index].reg;
824 	tmp &= ~EIC_CONFIG_FILTEN3;
825 	tmp |= value << EIC_CONFIG_FILTEN3_Pos;
826 	((Eic *)hw)->CONFIG[index].reg = tmp;
827 	EIC_CRITICAL_SECTION_LEAVE();
828 }
829 
hri_eic_clear_CONFIG_FILTEN3_bit(const void * const hw,uint8_t index)830 static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
831 {
832 	EIC_CRITICAL_SECTION_ENTER();
833 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3;
834 	EIC_CRITICAL_SECTION_LEAVE();
835 }
836 
hri_eic_toggle_CONFIG_FILTEN3_bit(const void * const hw,uint8_t index)837 static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index)
838 {
839 	EIC_CRITICAL_SECTION_ENTER();
840 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3;
841 	EIC_CRITICAL_SECTION_LEAVE();
842 }
843 
hri_eic_set_CONFIG_FILTEN4_bit(const void * const hw,uint8_t index)844 static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
845 {
846 	EIC_CRITICAL_SECTION_ENTER();
847 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4;
848 	EIC_CRITICAL_SECTION_LEAVE();
849 }
850 
hri_eic_get_CONFIG_FILTEN4_bit(const void * const hw,uint8_t index)851 static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
852 {
853 	uint32_t tmp;
854 	tmp = ((Eic *)hw)->CONFIG[index].reg;
855 	tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos;
856 	return (bool)tmp;
857 }
858 
hri_eic_write_CONFIG_FILTEN4_bit(const void * const hw,uint8_t index,bool value)859 static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value)
860 {
861 	uint32_t tmp;
862 	EIC_CRITICAL_SECTION_ENTER();
863 	tmp = ((Eic *)hw)->CONFIG[index].reg;
864 	tmp &= ~EIC_CONFIG_FILTEN4;
865 	tmp |= value << EIC_CONFIG_FILTEN4_Pos;
866 	((Eic *)hw)->CONFIG[index].reg = tmp;
867 	EIC_CRITICAL_SECTION_LEAVE();
868 }
869 
hri_eic_clear_CONFIG_FILTEN4_bit(const void * const hw,uint8_t index)870 static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
871 {
872 	EIC_CRITICAL_SECTION_ENTER();
873 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4;
874 	EIC_CRITICAL_SECTION_LEAVE();
875 }
876 
hri_eic_toggle_CONFIG_FILTEN4_bit(const void * const hw,uint8_t index)877 static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index)
878 {
879 	EIC_CRITICAL_SECTION_ENTER();
880 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4;
881 	EIC_CRITICAL_SECTION_LEAVE();
882 }
883 
hri_eic_set_CONFIG_FILTEN5_bit(const void * const hw,uint8_t index)884 static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
885 {
886 	EIC_CRITICAL_SECTION_ENTER();
887 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5;
888 	EIC_CRITICAL_SECTION_LEAVE();
889 }
890 
hri_eic_get_CONFIG_FILTEN5_bit(const void * const hw,uint8_t index)891 static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
892 {
893 	uint32_t tmp;
894 	tmp = ((Eic *)hw)->CONFIG[index].reg;
895 	tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos;
896 	return (bool)tmp;
897 }
898 
hri_eic_write_CONFIG_FILTEN5_bit(const void * const hw,uint8_t index,bool value)899 static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value)
900 {
901 	uint32_t tmp;
902 	EIC_CRITICAL_SECTION_ENTER();
903 	tmp = ((Eic *)hw)->CONFIG[index].reg;
904 	tmp &= ~EIC_CONFIG_FILTEN5;
905 	tmp |= value << EIC_CONFIG_FILTEN5_Pos;
906 	((Eic *)hw)->CONFIG[index].reg = tmp;
907 	EIC_CRITICAL_SECTION_LEAVE();
908 }
909 
hri_eic_clear_CONFIG_FILTEN5_bit(const void * const hw,uint8_t index)910 static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
911 {
912 	EIC_CRITICAL_SECTION_ENTER();
913 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5;
914 	EIC_CRITICAL_SECTION_LEAVE();
915 }
916 
hri_eic_toggle_CONFIG_FILTEN5_bit(const void * const hw,uint8_t index)917 static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index)
918 {
919 	EIC_CRITICAL_SECTION_ENTER();
920 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5;
921 	EIC_CRITICAL_SECTION_LEAVE();
922 }
923 
hri_eic_set_CONFIG_FILTEN6_bit(const void * const hw,uint8_t index)924 static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
925 {
926 	EIC_CRITICAL_SECTION_ENTER();
927 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6;
928 	EIC_CRITICAL_SECTION_LEAVE();
929 }
930 
hri_eic_get_CONFIG_FILTEN6_bit(const void * const hw,uint8_t index)931 static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
932 {
933 	uint32_t tmp;
934 	tmp = ((Eic *)hw)->CONFIG[index].reg;
935 	tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos;
936 	return (bool)tmp;
937 }
938 
hri_eic_write_CONFIG_FILTEN6_bit(const void * const hw,uint8_t index,bool value)939 static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value)
940 {
941 	uint32_t tmp;
942 	EIC_CRITICAL_SECTION_ENTER();
943 	tmp = ((Eic *)hw)->CONFIG[index].reg;
944 	tmp &= ~EIC_CONFIG_FILTEN6;
945 	tmp |= value << EIC_CONFIG_FILTEN6_Pos;
946 	((Eic *)hw)->CONFIG[index].reg = tmp;
947 	EIC_CRITICAL_SECTION_LEAVE();
948 }
949 
hri_eic_clear_CONFIG_FILTEN6_bit(const void * const hw,uint8_t index)950 static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
951 {
952 	EIC_CRITICAL_SECTION_ENTER();
953 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6;
954 	EIC_CRITICAL_SECTION_LEAVE();
955 }
956 
hri_eic_toggle_CONFIG_FILTEN6_bit(const void * const hw,uint8_t index)957 static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index)
958 {
959 	EIC_CRITICAL_SECTION_ENTER();
960 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6;
961 	EIC_CRITICAL_SECTION_LEAVE();
962 }
963 
hri_eic_set_CONFIG_FILTEN7_bit(const void * const hw,uint8_t index)964 static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
965 {
966 	EIC_CRITICAL_SECTION_ENTER();
967 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7;
968 	EIC_CRITICAL_SECTION_LEAVE();
969 }
970 
hri_eic_get_CONFIG_FILTEN7_bit(const void * const hw,uint8_t index)971 static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
972 {
973 	uint32_t tmp;
974 	tmp = ((Eic *)hw)->CONFIG[index].reg;
975 	tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos;
976 	return (bool)tmp;
977 }
978 
hri_eic_write_CONFIG_FILTEN7_bit(const void * const hw,uint8_t index,bool value)979 static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value)
980 {
981 	uint32_t tmp;
982 	EIC_CRITICAL_SECTION_ENTER();
983 	tmp = ((Eic *)hw)->CONFIG[index].reg;
984 	tmp &= ~EIC_CONFIG_FILTEN7;
985 	tmp |= value << EIC_CONFIG_FILTEN7_Pos;
986 	((Eic *)hw)->CONFIG[index].reg = tmp;
987 	EIC_CRITICAL_SECTION_LEAVE();
988 }
989 
hri_eic_clear_CONFIG_FILTEN7_bit(const void * const hw,uint8_t index)990 static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
991 {
992 	EIC_CRITICAL_SECTION_ENTER();
993 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7;
994 	EIC_CRITICAL_SECTION_LEAVE();
995 }
996 
hri_eic_toggle_CONFIG_FILTEN7_bit(const void * const hw,uint8_t index)997 static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index)
998 {
999 	EIC_CRITICAL_SECTION_ENTER();
1000 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7;
1001 	EIC_CRITICAL_SECTION_LEAVE();
1002 }
1003 
hri_eic_set_CONFIG_SENSE0_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1004 static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1005 {
1006 	EIC_CRITICAL_SECTION_ENTER();
1007 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask);
1008 	EIC_CRITICAL_SECTION_LEAVE();
1009 }
1010 
hri_eic_get_CONFIG_SENSE0_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1011 static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index,
1012                                                                 hri_eic_config_reg_t mask)
1013 {
1014 	uint32_t tmp;
1015 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1016 	tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos;
1017 	return tmp;
1018 }
1019 
hri_eic_write_CONFIG_SENSE0_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t data)1020 static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
1021 {
1022 	uint32_t tmp;
1023 	EIC_CRITICAL_SECTION_ENTER();
1024 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1025 	tmp &= ~EIC_CONFIG_SENSE0_Msk;
1026 	tmp |= EIC_CONFIG_SENSE0(data);
1027 	((Eic *)hw)->CONFIG[index].reg = tmp;
1028 	EIC_CRITICAL_SECTION_LEAVE();
1029 }
1030 
hri_eic_clear_CONFIG_SENSE0_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1031 static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1032 {
1033 	EIC_CRITICAL_SECTION_ENTER();
1034 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask);
1035 	EIC_CRITICAL_SECTION_LEAVE();
1036 }
1037 
hri_eic_toggle_CONFIG_SENSE0_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1038 static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1039 {
1040 	EIC_CRITICAL_SECTION_ENTER();
1041 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask);
1042 	EIC_CRITICAL_SECTION_LEAVE();
1043 }
1044 
hri_eic_read_CONFIG_SENSE0_bf(const void * const hw,uint8_t index)1045 static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index)
1046 {
1047 	uint32_t tmp;
1048 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1049 	tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos;
1050 	return tmp;
1051 }
1052 
hri_eic_set_CONFIG_SENSE1_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1053 static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1054 {
1055 	EIC_CRITICAL_SECTION_ENTER();
1056 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask);
1057 	EIC_CRITICAL_SECTION_LEAVE();
1058 }
1059 
hri_eic_get_CONFIG_SENSE1_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1060 static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index,
1061                                                                 hri_eic_config_reg_t mask)
1062 {
1063 	uint32_t tmp;
1064 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1065 	tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos;
1066 	return tmp;
1067 }
1068 
hri_eic_write_CONFIG_SENSE1_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t data)1069 static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
1070 {
1071 	uint32_t tmp;
1072 	EIC_CRITICAL_SECTION_ENTER();
1073 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1074 	tmp &= ~EIC_CONFIG_SENSE1_Msk;
1075 	tmp |= EIC_CONFIG_SENSE1(data);
1076 	((Eic *)hw)->CONFIG[index].reg = tmp;
1077 	EIC_CRITICAL_SECTION_LEAVE();
1078 }
1079 
hri_eic_clear_CONFIG_SENSE1_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1080 static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1081 {
1082 	EIC_CRITICAL_SECTION_ENTER();
1083 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask);
1084 	EIC_CRITICAL_SECTION_LEAVE();
1085 }
1086 
hri_eic_toggle_CONFIG_SENSE1_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1087 static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1088 {
1089 	EIC_CRITICAL_SECTION_ENTER();
1090 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask);
1091 	EIC_CRITICAL_SECTION_LEAVE();
1092 }
1093 
hri_eic_read_CONFIG_SENSE1_bf(const void * const hw,uint8_t index)1094 static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index)
1095 {
1096 	uint32_t tmp;
1097 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1098 	tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos;
1099 	return tmp;
1100 }
1101 
hri_eic_set_CONFIG_SENSE2_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1102 static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1103 {
1104 	EIC_CRITICAL_SECTION_ENTER();
1105 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask);
1106 	EIC_CRITICAL_SECTION_LEAVE();
1107 }
1108 
hri_eic_get_CONFIG_SENSE2_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1109 static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index,
1110                                                                 hri_eic_config_reg_t mask)
1111 {
1112 	uint32_t tmp;
1113 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1114 	tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos;
1115 	return tmp;
1116 }
1117 
hri_eic_write_CONFIG_SENSE2_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t data)1118 static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
1119 {
1120 	uint32_t tmp;
1121 	EIC_CRITICAL_SECTION_ENTER();
1122 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1123 	tmp &= ~EIC_CONFIG_SENSE2_Msk;
1124 	tmp |= EIC_CONFIG_SENSE2(data);
1125 	((Eic *)hw)->CONFIG[index].reg = tmp;
1126 	EIC_CRITICAL_SECTION_LEAVE();
1127 }
1128 
hri_eic_clear_CONFIG_SENSE2_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1129 static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1130 {
1131 	EIC_CRITICAL_SECTION_ENTER();
1132 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask);
1133 	EIC_CRITICAL_SECTION_LEAVE();
1134 }
1135 
hri_eic_toggle_CONFIG_SENSE2_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1136 static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1137 {
1138 	EIC_CRITICAL_SECTION_ENTER();
1139 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask);
1140 	EIC_CRITICAL_SECTION_LEAVE();
1141 }
1142 
hri_eic_read_CONFIG_SENSE2_bf(const void * const hw,uint8_t index)1143 static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index)
1144 {
1145 	uint32_t tmp;
1146 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1147 	tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos;
1148 	return tmp;
1149 }
1150 
hri_eic_set_CONFIG_SENSE3_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1151 static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1152 {
1153 	EIC_CRITICAL_SECTION_ENTER();
1154 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask);
1155 	EIC_CRITICAL_SECTION_LEAVE();
1156 }
1157 
hri_eic_get_CONFIG_SENSE3_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1158 static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index,
1159                                                                 hri_eic_config_reg_t mask)
1160 {
1161 	uint32_t tmp;
1162 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1163 	tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos;
1164 	return tmp;
1165 }
1166 
hri_eic_write_CONFIG_SENSE3_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t data)1167 static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
1168 {
1169 	uint32_t tmp;
1170 	EIC_CRITICAL_SECTION_ENTER();
1171 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1172 	tmp &= ~EIC_CONFIG_SENSE3_Msk;
1173 	tmp |= EIC_CONFIG_SENSE3(data);
1174 	((Eic *)hw)->CONFIG[index].reg = tmp;
1175 	EIC_CRITICAL_SECTION_LEAVE();
1176 }
1177 
hri_eic_clear_CONFIG_SENSE3_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1178 static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1179 {
1180 	EIC_CRITICAL_SECTION_ENTER();
1181 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask);
1182 	EIC_CRITICAL_SECTION_LEAVE();
1183 }
1184 
hri_eic_toggle_CONFIG_SENSE3_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1185 static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1186 {
1187 	EIC_CRITICAL_SECTION_ENTER();
1188 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask);
1189 	EIC_CRITICAL_SECTION_LEAVE();
1190 }
1191 
hri_eic_read_CONFIG_SENSE3_bf(const void * const hw,uint8_t index)1192 static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index)
1193 {
1194 	uint32_t tmp;
1195 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1196 	tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos;
1197 	return tmp;
1198 }
1199 
hri_eic_set_CONFIG_SENSE4_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1200 static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1201 {
1202 	EIC_CRITICAL_SECTION_ENTER();
1203 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask);
1204 	EIC_CRITICAL_SECTION_LEAVE();
1205 }
1206 
hri_eic_get_CONFIG_SENSE4_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1207 static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index,
1208                                                                 hri_eic_config_reg_t mask)
1209 {
1210 	uint32_t tmp;
1211 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1212 	tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos;
1213 	return tmp;
1214 }
1215 
hri_eic_write_CONFIG_SENSE4_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t data)1216 static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
1217 {
1218 	uint32_t tmp;
1219 	EIC_CRITICAL_SECTION_ENTER();
1220 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1221 	tmp &= ~EIC_CONFIG_SENSE4_Msk;
1222 	tmp |= EIC_CONFIG_SENSE4(data);
1223 	((Eic *)hw)->CONFIG[index].reg = tmp;
1224 	EIC_CRITICAL_SECTION_LEAVE();
1225 }
1226 
hri_eic_clear_CONFIG_SENSE4_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1227 static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1228 {
1229 	EIC_CRITICAL_SECTION_ENTER();
1230 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask);
1231 	EIC_CRITICAL_SECTION_LEAVE();
1232 }
1233 
hri_eic_toggle_CONFIG_SENSE4_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1234 static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1235 {
1236 	EIC_CRITICAL_SECTION_ENTER();
1237 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask);
1238 	EIC_CRITICAL_SECTION_LEAVE();
1239 }
1240 
hri_eic_read_CONFIG_SENSE4_bf(const void * const hw,uint8_t index)1241 static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index)
1242 {
1243 	uint32_t tmp;
1244 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1245 	tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos;
1246 	return tmp;
1247 }
1248 
hri_eic_set_CONFIG_SENSE5_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1249 static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1250 {
1251 	EIC_CRITICAL_SECTION_ENTER();
1252 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask);
1253 	EIC_CRITICAL_SECTION_LEAVE();
1254 }
1255 
hri_eic_get_CONFIG_SENSE5_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1256 static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index,
1257                                                                 hri_eic_config_reg_t mask)
1258 {
1259 	uint32_t tmp;
1260 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1261 	tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos;
1262 	return tmp;
1263 }
1264 
hri_eic_write_CONFIG_SENSE5_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t data)1265 static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
1266 {
1267 	uint32_t tmp;
1268 	EIC_CRITICAL_SECTION_ENTER();
1269 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1270 	tmp &= ~EIC_CONFIG_SENSE5_Msk;
1271 	tmp |= EIC_CONFIG_SENSE5(data);
1272 	((Eic *)hw)->CONFIG[index].reg = tmp;
1273 	EIC_CRITICAL_SECTION_LEAVE();
1274 }
1275 
hri_eic_clear_CONFIG_SENSE5_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1276 static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1277 {
1278 	EIC_CRITICAL_SECTION_ENTER();
1279 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask);
1280 	EIC_CRITICAL_SECTION_LEAVE();
1281 }
1282 
hri_eic_toggle_CONFIG_SENSE5_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1283 static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1284 {
1285 	EIC_CRITICAL_SECTION_ENTER();
1286 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask);
1287 	EIC_CRITICAL_SECTION_LEAVE();
1288 }
1289 
hri_eic_read_CONFIG_SENSE5_bf(const void * const hw,uint8_t index)1290 static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index)
1291 {
1292 	uint32_t tmp;
1293 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1294 	tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos;
1295 	return tmp;
1296 }
1297 
hri_eic_set_CONFIG_SENSE6_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1298 static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1299 {
1300 	EIC_CRITICAL_SECTION_ENTER();
1301 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask);
1302 	EIC_CRITICAL_SECTION_LEAVE();
1303 }
1304 
hri_eic_get_CONFIG_SENSE6_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1305 static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index,
1306                                                                 hri_eic_config_reg_t mask)
1307 {
1308 	uint32_t tmp;
1309 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1310 	tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos;
1311 	return tmp;
1312 }
1313 
hri_eic_write_CONFIG_SENSE6_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t data)1314 static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
1315 {
1316 	uint32_t tmp;
1317 	EIC_CRITICAL_SECTION_ENTER();
1318 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1319 	tmp &= ~EIC_CONFIG_SENSE6_Msk;
1320 	tmp |= EIC_CONFIG_SENSE6(data);
1321 	((Eic *)hw)->CONFIG[index].reg = tmp;
1322 	EIC_CRITICAL_SECTION_LEAVE();
1323 }
1324 
hri_eic_clear_CONFIG_SENSE6_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1325 static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1326 {
1327 	EIC_CRITICAL_SECTION_ENTER();
1328 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask);
1329 	EIC_CRITICAL_SECTION_LEAVE();
1330 }
1331 
hri_eic_toggle_CONFIG_SENSE6_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1332 static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1333 {
1334 	EIC_CRITICAL_SECTION_ENTER();
1335 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask);
1336 	EIC_CRITICAL_SECTION_LEAVE();
1337 }
1338 
hri_eic_read_CONFIG_SENSE6_bf(const void * const hw,uint8_t index)1339 static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index)
1340 {
1341 	uint32_t tmp;
1342 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1343 	tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos;
1344 	return tmp;
1345 }
1346 
hri_eic_set_CONFIG_SENSE7_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1347 static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1348 {
1349 	EIC_CRITICAL_SECTION_ENTER();
1350 	((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask);
1351 	EIC_CRITICAL_SECTION_LEAVE();
1352 }
1353 
hri_eic_get_CONFIG_SENSE7_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1354 static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index,
1355                                                                 hri_eic_config_reg_t mask)
1356 {
1357 	uint32_t tmp;
1358 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1359 	tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos;
1360 	return tmp;
1361 }
1362 
hri_eic_write_CONFIG_SENSE7_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t data)1363 static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
1364 {
1365 	uint32_t tmp;
1366 	EIC_CRITICAL_SECTION_ENTER();
1367 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1368 	tmp &= ~EIC_CONFIG_SENSE7_Msk;
1369 	tmp |= EIC_CONFIG_SENSE7(data);
1370 	((Eic *)hw)->CONFIG[index].reg = tmp;
1371 	EIC_CRITICAL_SECTION_LEAVE();
1372 }
1373 
hri_eic_clear_CONFIG_SENSE7_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1374 static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1375 {
1376 	EIC_CRITICAL_SECTION_ENTER();
1377 	((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask);
1378 	EIC_CRITICAL_SECTION_LEAVE();
1379 }
1380 
hri_eic_toggle_CONFIG_SENSE7_bf(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1381 static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1382 {
1383 	EIC_CRITICAL_SECTION_ENTER();
1384 	((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask);
1385 	EIC_CRITICAL_SECTION_LEAVE();
1386 }
1387 
hri_eic_read_CONFIG_SENSE7_bf(const void * const hw,uint8_t index)1388 static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index)
1389 {
1390 	uint32_t tmp;
1391 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1392 	tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos;
1393 	return tmp;
1394 }
1395 
hri_eic_set_CONFIG_reg(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1396 static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1397 {
1398 	EIC_CRITICAL_SECTION_ENTER();
1399 	((Eic *)hw)->CONFIG[index].reg |= mask;
1400 	EIC_CRITICAL_SECTION_LEAVE();
1401 }
1402 
hri_eic_get_CONFIG_reg(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1403 static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index,
1404                                                           hri_eic_config_reg_t mask)
1405 {
1406 	uint32_t tmp;
1407 	tmp = ((Eic *)hw)->CONFIG[index].reg;
1408 	tmp &= mask;
1409 	return tmp;
1410 }
1411 
hri_eic_write_CONFIG_reg(const void * const hw,uint8_t index,hri_eic_config_reg_t data)1412 static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data)
1413 {
1414 	EIC_CRITICAL_SECTION_ENTER();
1415 	((Eic *)hw)->CONFIG[index].reg = data;
1416 	EIC_CRITICAL_SECTION_LEAVE();
1417 }
1418 
hri_eic_clear_CONFIG_reg(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1419 static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1420 {
1421 	EIC_CRITICAL_SECTION_ENTER();
1422 	((Eic *)hw)->CONFIG[index].reg &= ~mask;
1423 	EIC_CRITICAL_SECTION_LEAVE();
1424 }
1425 
hri_eic_toggle_CONFIG_reg(const void * const hw,uint8_t index,hri_eic_config_reg_t mask)1426 static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask)
1427 {
1428 	EIC_CRITICAL_SECTION_ENTER();
1429 	((Eic *)hw)->CONFIG[index].reg ^= mask;
1430 	EIC_CRITICAL_SECTION_LEAVE();
1431 }
1432 
hri_eic_read_CONFIG_reg(const void * const hw,uint8_t index)1433 static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index)
1434 {
1435 	return ((Eic *)hw)->CONFIG[index].reg;
1436 }
1437 
hri_eic_get_SYNCBUSY_SWRST_bit(const void * const hw)1438 static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw)
1439 {
1440 	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos;
1441 }
1442 
hri_eic_get_SYNCBUSY_ENABLE_bit(const void * const hw)1443 static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw)
1444 {
1445 	return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos;
1446 }
1447 
hri_eic_get_SYNCBUSY_reg(const void * const hw,hri_eic_syncbusy_reg_t mask)1448 static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask)
1449 {
1450 	uint32_t tmp;
1451 	tmp = ((Eic *)hw)->SYNCBUSY.reg;
1452 	tmp &= mask;
1453 	return tmp;
1454 }
1455 
hri_eic_read_SYNCBUSY_reg(const void * const hw)1456 static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw)
1457 {
1458 	return ((Eic *)hw)->SYNCBUSY.reg;
1459 }
1460 
1461 #ifdef __cplusplus
1462 }
1463 #endif
1464 
1465 #endif /* _HRI_EIC_L21_H_INCLUDED */
1466 #endif /* _SAML21_EIC_COMPONENT_ */
1467