1 /** 2 * \file 3 * 4 * \brief Component description for USB 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_USB_COMPONENT_ 30 #define _SAML21_USB_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR USB */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_USB Universal Serial Bus */ 36 /*@{*/ 37 38 #define USB_U2222 39 #define REV_USB 0x111 40 41 /* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ 48 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 49 uint8_t MODE:1; /*!< bit: 7 Operating Mode */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } USB_CTRLA_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */ 56 #define USB_CTRLA_RESETVALUE _U(0x00) /**< \brief (USB_CTRLA reset_value) Control A */ 57 58 #define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */ 59 #define USB_CTRLA_SWRST (_U(0x1) << USB_CTRLA_SWRST_Pos) 60 #define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */ 61 #define USB_CTRLA_ENABLE (_U(0x1) << USB_CTRLA_ENABLE_Pos) 62 #define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */ 63 #define USB_CTRLA_RUNSTDBY (_U(0x1) << USB_CTRLA_RUNSTDBY_Pos) 64 #define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */ 65 #define USB_CTRLA_MODE (_U(0x1) << USB_CTRLA_MODE_Pos) 66 #define USB_CTRLA_MODE_DEVICE_Val _U(0x0) /**< \brief (USB_CTRLA) Device Mode */ 67 #define USB_CTRLA_MODE_HOST_Val _U(0x1) /**< \brief (USB_CTRLA) Host Mode */ 68 #define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos) 69 #define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos) 70 #define USB_CTRLA_MASK _U(0x87) /**< \brief (USB_CTRLA) MASK Register */ 71 72 /* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */ 73 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 74 typedef union { 75 struct { 76 uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 77 uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ 78 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 79 } bit; /*!< Structure used for bit access */ 80 uint8_t reg; /*!< Type used for register access */ 81 } USB_SYNCBUSY_Type; 82 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 83 84 #define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */ 85 #define USB_SYNCBUSY_RESETVALUE _U(0x00) /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */ 86 87 #define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */ 88 #define USB_SYNCBUSY_SWRST (_U(0x1) << USB_SYNCBUSY_SWRST_Pos) 89 #define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */ 90 #define USB_SYNCBUSY_ENABLE (_U(0x1) << USB_SYNCBUSY_ENABLE_Pos) 91 #define USB_SYNCBUSY_MASK _U(0x03) /**< \brief (USB_SYNCBUSY) MASK Register */ 92 93 /* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */ 94 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 95 typedef union { 96 struct { 97 uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ 98 uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ 99 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 100 } bit; /*!< Structure used for bit access */ 101 uint8_t reg; /*!< Type used for register access */ 102 } USB_QOSCTRL_Type; 103 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 #define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */ 106 #define USB_QOSCTRL_RESETVALUE _U(0x0F) /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */ 107 108 #define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */ 109 #define USB_QOSCTRL_CQOS_Msk (_U(0x3) << USB_QOSCTRL_CQOS_Pos) 110 #define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos)) 111 #define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */ 112 #define USB_QOSCTRL_DQOS_Msk (_U(0x3) << USB_QOSCTRL_DQOS_Pos) 113 #define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos)) 114 #define USB_QOSCTRL_MASK _U(0x0F) /**< \brief (USB_QOSCTRL) MASK Register */ 115 116 /* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */ 117 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 118 typedef union { 119 struct { 120 uint16_t DETACH:1; /*!< bit: 0 Detach */ 121 uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ 122 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ 123 uint16_t NREPLY:1; /*!< bit: 4 No Reply */ 124 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ 125 uint16_t TSTK:1; /*!< bit: 6 Test mode K */ 126 uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ 127 uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ 128 uint16_t GNAK:1; /*!< bit: 9 Global NAK */ 129 uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ 130 uint16_t :4; /*!< bit: 12..15 Reserved */ 131 } bit; /*!< Structure used for bit access */ 132 uint16_t reg; /*!< Type used for register access */ 133 } USB_DEVICE_CTRLB_Type; 134 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 135 136 #define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */ 137 #define USB_DEVICE_CTRLB_RESETVALUE _U(0x0001) /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */ 138 139 #define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */ 140 #define USB_DEVICE_CTRLB_DETACH (_U(0x1) << USB_DEVICE_CTRLB_DETACH_Pos) 141 #define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */ 142 #define USB_DEVICE_CTRLB_UPRSM (_U(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos) 143 #define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */ 144 #define USB_DEVICE_CTRLB_SPDCONF_Msk (_U(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos) 145 #define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos)) 146 #define USB_DEVICE_CTRLB_SPDCONF_FS_Val _U(0x0) /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */ 147 #define USB_DEVICE_CTRLB_SPDCONF_LS_Val _U(0x1) /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */ 148 #define USB_DEVICE_CTRLB_SPDCONF_HS_Val _U(0x2) /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */ 149 #define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val _U(0x3) /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */ 150 #define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) 151 #define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) 152 #define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) 153 #define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) 154 #define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */ 155 #define USB_DEVICE_CTRLB_NREPLY (_U(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos) 156 #define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */ 157 #define USB_DEVICE_CTRLB_TSTJ (_U(0x1) << USB_DEVICE_CTRLB_TSTJ_Pos) 158 #define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */ 159 #define USB_DEVICE_CTRLB_TSTK (_U(0x1) << USB_DEVICE_CTRLB_TSTK_Pos) 160 #define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */ 161 #define USB_DEVICE_CTRLB_TSTPCKT (_U(0x1) << USB_DEVICE_CTRLB_TSTPCKT_Pos) 162 #define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */ 163 #define USB_DEVICE_CTRLB_OPMODE2 (_U(0x1) << USB_DEVICE_CTRLB_OPMODE2_Pos) 164 #define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */ 165 #define USB_DEVICE_CTRLB_GNAK (_U(0x1) << USB_DEVICE_CTRLB_GNAK_Pos) 166 #define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */ 167 #define USB_DEVICE_CTRLB_LPMHDSK_Msk (_U(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos) 168 #define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos)) 169 #define USB_DEVICE_CTRLB_LPMHDSK_NO_Val _U(0x0) /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */ 170 #define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val _U(0x1) /**< \brief (USB_DEVICE_CTRLB) ACK */ 171 #define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val _U(0x2) /**< \brief (USB_DEVICE_CTRLB) NYET */ 172 #define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val _U(0x3) /**< \brief (USB_DEVICE_CTRLB) STALL */ 173 #define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) 174 #define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) 175 #define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) 176 #define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) 177 #define USB_DEVICE_CTRLB_MASK _U(0x0FFF) /**< \brief (USB_DEVICE_CTRLB) MASK Register */ 178 179 /* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */ 180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 181 typedef union { 182 struct { 183 uint16_t :1; /*!< bit: 0 Reserved */ 184 uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ 185 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ 186 uint16_t AUTORESUME:1; /*!< bit: 4 Auto Resume Enable */ 187 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ 188 uint16_t TSTK:1; /*!< bit: 6 Test mode K */ 189 uint16_t :1; /*!< bit: 7 Reserved */ 190 uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ 191 uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ 192 uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ 193 uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ 194 uint16_t :4; /*!< bit: 12..15 Reserved */ 195 } bit; /*!< Structure used for bit access */ 196 uint16_t reg; /*!< Type used for register access */ 197 } USB_HOST_CTRLB_Type; 198 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 199 200 #define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */ 201 #define USB_HOST_CTRLB_RESETVALUE _U(0x0000) /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */ 202 203 #define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */ 204 #define USB_HOST_CTRLB_RESUME (_U(0x1) << USB_HOST_CTRLB_RESUME_Pos) 205 #define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */ 206 #define USB_HOST_CTRLB_SPDCONF_Msk (_U(0x3) << USB_HOST_CTRLB_SPDCONF_Pos) 207 #define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos)) 208 #define USB_HOST_CTRLB_SPDCONF_NORMAL_Val _U(0x0) /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */ 209 #define USB_HOST_CTRLB_SPDCONF_FS_Val _U(0x3) /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */ 210 #define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos) 211 #define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos) 212 #define USB_HOST_CTRLB_AUTORESUME_Pos 4 /**< \brief (USB_HOST_CTRLB) Auto Resume Enable */ 213 #define USB_HOST_CTRLB_AUTORESUME (_U(0x1) << USB_HOST_CTRLB_AUTORESUME_Pos) 214 #define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */ 215 #define USB_HOST_CTRLB_TSTJ (_U(0x1) << USB_HOST_CTRLB_TSTJ_Pos) 216 #define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */ 217 #define USB_HOST_CTRLB_TSTK (_U(0x1) << USB_HOST_CTRLB_TSTK_Pos) 218 #define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */ 219 #define USB_HOST_CTRLB_SOFE (_U(0x1) << USB_HOST_CTRLB_SOFE_Pos) 220 #define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */ 221 #define USB_HOST_CTRLB_BUSRESET (_U(0x1) << USB_HOST_CTRLB_BUSRESET_Pos) 222 #define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */ 223 #define USB_HOST_CTRLB_VBUSOK (_U(0x1) << USB_HOST_CTRLB_VBUSOK_Pos) 224 #define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */ 225 #define USB_HOST_CTRLB_L1RESUME (_U(0x1) << USB_HOST_CTRLB_L1RESUME_Pos) 226 #define USB_HOST_CTRLB_MASK _U(0x0F7E) /**< \brief (USB_HOST_CTRLB) MASK Register */ 227 228 /* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */ 229 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 230 typedef union { 231 struct { 232 uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ 233 uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ 234 } bit; /*!< Structure used for bit access */ 235 uint8_t reg; /*!< Type used for register access */ 236 } USB_DEVICE_DADD_Type; 237 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 238 239 #define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */ 240 #define USB_DEVICE_DADD_RESETVALUE _U(0x00) /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */ 241 242 #define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */ 243 #define USB_DEVICE_DADD_DADD_Msk (_U(0x7F) << USB_DEVICE_DADD_DADD_Pos) 244 #define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos)) 245 #define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */ 246 #define USB_DEVICE_DADD_ADDEN (_U(0x1) << USB_DEVICE_DADD_ADDEN_Pos) 247 #define USB_DEVICE_DADD_MASK _U(0xFF) /**< \brief (USB_DEVICE_DADD) MASK Register */ 248 249 /* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */ 250 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 251 typedef union { 252 struct { 253 uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ 254 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 255 uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ 256 } bit; /*!< Structure used for bit access */ 257 uint8_t reg; /*!< Type used for register access */ 258 } USB_HOST_HSOFC_Type; 259 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 260 261 #define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */ 262 #define USB_HOST_HSOFC_RESETVALUE _U(0x00) /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */ 263 264 #define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */ 265 #define USB_HOST_HSOFC_FLENC_Msk (_U(0xF) << USB_HOST_HSOFC_FLENC_Pos) 266 #define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos)) 267 #define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */ 268 #define USB_HOST_HSOFC_FLENCE (_U(0x1) << USB_HOST_HSOFC_FLENCE_Pos) 269 #define USB_HOST_HSOFC_MASK _U(0x8F) /**< \brief (USB_HOST_HSOFC) MASK Register */ 270 271 /* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */ 272 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 273 typedef union { 274 struct { 275 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 276 uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ 277 uint8_t :2; /*!< bit: 4.. 5 Reserved */ 278 uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ 279 } bit; /*!< Structure used for bit access */ 280 uint8_t reg; /*!< Type used for register access */ 281 } USB_DEVICE_STATUS_Type; 282 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 283 284 #define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */ 285 #define USB_DEVICE_STATUS_RESETVALUE _U(0x40) /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */ 286 287 #define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */ 288 #define USB_DEVICE_STATUS_SPEED_Msk (_U(0x3) << USB_DEVICE_STATUS_SPEED_Pos) 289 #define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos)) 290 #define USB_DEVICE_STATUS_SPEED_FS_Val _U(0x0) /**< \brief (USB_DEVICE_STATUS) Full-speed mode */ 291 #define USB_DEVICE_STATUS_SPEED_HS_Val _U(0x1) /**< \brief (USB_DEVICE_STATUS) High-speed mode */ 292 #define USB_DEVICE_STATUS_SPEED_LS_Val _U(0x2) /**< \brief (USB_DEVICE_STATUS) Low-speed mode */ 293 #define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos) 294 #define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos) 295 #define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos) 296 #define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */ 297 #define USB_DEVICE_STATUS_LINESTATE_Msk (_U(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos) 298 #define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos)) 299 #define USB_DEVICE_STATUS_LINESTATE_0_Val _U(0x0) /**< \brief (USB_DEVICE_STATUS) SE0/RESET */ 300 #define USB_DEVICE_STATUS_LINESTATE_1_Val _U(0x1) /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */ 301 #define USB_DEVICE_STATUS_LINESTATE_2_Val _U(0x2) /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */ 302 #define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos) 303 #define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos) 304 #define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos) 305 #define USB_DEVICE_STATUS_MASK _U(0xCC) /**< \brief (USB_DEVICE_STATUS) MASK Register */ 306 307 /* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */ 308 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 309 typedef union { 310 struct { 311 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 312 uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ 313 uint8_t :2; /*!< bit: 4.. 5 Reserved */ 314 uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ 315 } bit; /*!< Structure used for bit access */ 316 uint8_t reg; /*!< Type used for register access */ 317 } USB_HOST_STATUS_Type; 318 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 319 320 #define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */ 321 #define USB_HOST_STATUS_RESETVALUE _U(0x00) /**< \brief (USB_HOST_STATUS reset_value) HOST Status */ 322 323 #define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */ 324 #define USB_HOST_STATUS_SPEED_Msk (_U(0x3) << USB_HOST_STATUS_SPEED_Pos) 325 #define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos)) 326 #define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */ 327 #define USB_HOST_STATUS_LINESTATE_Msk (_U(0x3) << USB_HOST_STATUS_LINESTATE_Pos) 328 #define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos)) 329 #define USB_HOST_STATUS_MASK _U(0xCC) /**< \brief (USB_HOST_STATUS) MASK Register */ 330 331 /* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */ 332 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 333 typedef union { 334 struct { 335 uint8_t FSMSTATE:7; /*!< bit: 0.. 6 Fine State Machine Status */ 336 uint8_t :1; /*!< bit: 7 Reserved */ 337 } bit; /*!< Structure used for bit access */ 338 uint8_t reg; /*!< Type used for register access */ 339 } USB_FSMSTATUS_Type; 340 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 341 342 #define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */ 343 #define USB_FSMSTATUS_RESETVALUE _U(0x01) /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */ 344 345 #define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */ 346 #define USB_FSMSTATUS_FSMSTATE_Msk (_U(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos) 347 #define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos)) 348 #define USB_FSMSTATUS_FSMSTATE_OFF_Val _U(0x1) /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */ 349 #define USB_FSMSTATUS_FSMSTATE_ON_Val _U(0x2) /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */ 350 #define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val _U(0x4) /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */ 351 #define USB_FSMSTATUS_FSMSTATE_SLEEP_Val _U(0x8) /**< \brief (USB_FSMSTATUS) SLEEP (L1) */ 352 #define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _U(0x10) /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */ 353 #define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _U(0x20) /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */ 354 #define USB_FSMSTATUS_FSMSTATE_RESET_Val _U(0x40) /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */ 355 #define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos) 356 #define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos) 357 #define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos) 358 #define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos) 359 #define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) 360 #define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) 361 #define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos) 362 #define USB_FSMSTATUS_MASK _U(0x7F) /**< \brief (USB_FSMSTATUS) MASK Register */ 363 364 /* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */ 365 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 366 typedef union { 367 struct { 368 uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ 369 uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ 370 uint16_t :1; /*!< bit: 14 Reserved */ 371 uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ 372 } bit; /*!< Structure used for bit access */ 373 uint16_t reg; /*!< Type used for register access */ 374 } USB_DEVICE_FNUM_Type; 375 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 376 377 #define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */ 378 #define USB_DEVICE_FNUM_RESETVALUE _U(0x0000) /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */ 379 380 #define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */ 381 #define USB_DEVICE_FNUM_MFNUM_Msk (_U(0x7) << USB_DEVICE_FNUM_MFNUM_Pos) 382 #define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos)) 383 #define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */ 384 #define USB_DEVICE_FNUM_FNUM_Msk (_U(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos) 385 #define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos)) 386 #define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */ 387 #define USB_DEVICE_FNUM_FNCERR (_U(0x1) << USB_DEVICE_FNUM_FNCERR_Pos) 388 #define USB_DEVICE_FNUM_MASK _U(0xBFFF) /**< \brief (USB_DEVICE_FNUM) MASK Register */ 389 390 /* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */ 391 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 392 typedef union { 393 struct { 394 uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ 395 uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ 396 uint16_t :2; /*!< bit: 14..15 Reserved */ 397 } bit; /*!< Structure used for bit access */ 398 uint16_t reg; /*!< Type used for register access */ 399 } USB_HOST_FNUM_Type; 400 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 401 402 #define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */ 403 #define USB_HOST_FNUM_RESETVALUE _U(0x0000) /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */ 404 405 #define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */ 406 #define USB_HOST_FNUM_MFNUM_Msk (_U(0x7) << USB_HOST_FNUM_MFNUM_Pos) 407 #define USB_HOST_FNUM_MFNUM(value) (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos)) 408 #define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */ 409 #define USB_HOST_FNUM_FNUM_Msk (_U(0x7FF) << USB_HOST_FNUM_FNUM_Pos) 410 #define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos)) 411 #define USB_HOST_FNUM_MASK _U(0x3FFF) /**< \brief (USB_HOST_FNUM) MASK Register */ 412 413 /* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */ 414 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 415 typedef union { 416 struct { 417 uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ 418 } bit; /*!< Structure used for bit access */ 419 uint8_t reg; /*!< Type used for register access */ 420 } USB_HOST_FLENHIGH_Type; 421 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 422 423 #define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */ 424 #define USB_HOST_FLENHIGH_RESETVALUE _U(0x00) /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */ 425 426 #define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */ 427 #define USB_HOST_FLENHIGH_FLENHIGH_Msk (_U(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos) 428 #define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos)) 429 #define USB_HOST_FLENHIGH_MASK _U(0xFF) /**< \brief (USB_HOST_FLENHIGH) MASK Register */ 430 431 /* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */ 432 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 433 typedef union { 434 struct { 435 uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ 436 uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ 437 uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ 438 uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ 439 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ 440 uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ 441 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ 442 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ 443 uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ 444 uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ 445 uint16_t :6; /*!< bit: 10..15 Reserved */ 446 } bit; /*!< Structure used for bit access */ 447 uint16_t reg; /*!< Type used for register access */ 448 } USB_DEVICE_INTENCLR_Type; 449 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 450 451 #define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */ 452 #define USB_DEVICE_INTENCLR_RESETVALUE _U(0x0000) /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */ 453 454 #define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */ 455 #define USB_DEVICE_INTENCLR_SUSPEND (_U(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos) 456 #define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */ 457 #define USB_DEVICE_INTENCLR_MSOF (_U(0x1) << USB_DEVICE_INTENCLR_MSOF_Pos) 458 #define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */ 459 #define USB_DEVICE_INTENCLR_SOF (_U(0x1) << USB_DEVICE_INTENCLR_SOF_Pos) 460 #define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */ 461 #define USB_DEVICE_INTENCLR_EORST (_U(0x1) << USB_DEVICE_INTENCLR_EORST_Pos) 462 #define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */ 463 #define USB_DEVICE_INTENCLR_WAKEUP (_U(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos) 464 #define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */ 465 #define USB_DEVICE_INTENCLR_EORSM (_U(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos) 466 #define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */ 467 #define USB_DEVICE_INTENCLR_UPRSM (_U(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos) 468 #define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */ 469 #define USB_DEVICE_INTENCLR_RAMACER (_U(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos) 470 #define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */ 471 #define USB_DEVICE_INTENCLR_LPMNYET (_U(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos) 472 #define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */ 473 #define USB_DEVICE_INTENCLR_LPMSUSP (_U(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos) 474 #define USB_DEVICE_INTENCLR_MASK _U(0x03FF) /**< \brief (USB_DEVICE_INTENCLR) MASK Register */ 475 476 /* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */ 477 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 478 typedef union { 479 struct { 480 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 481 uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ 482 uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ 483 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ 484 uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ 485 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ 486 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ 487 uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ 488 uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ 489 uint16_t :6; /*!< bit: 10..15 Reserved */ 490 } bit; /*!< Structure used for bit access */ 491 uint16_t reg; /*!< Type used for register access */ 492 } USB_HOST_INTENCLR_Type; 493 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 494 495 #define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */ 496 #define USB_HOST_INTENCLR_RESETVALUE _U(0x0000) /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */ 497 498 #define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */ 499 #define USB_HOST_INTENCLR_HSOF (_U(0x1) << USB_HOST_INTENCLR_HSOF_Pos) 500 #define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */ 501 #define USB_HOST_INTENCLR_RST (_U(0x1) << USB_HOST_INTENCLR_RST_Pos) 502 #define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */ 503 #define USB_HOST_INTENCLR_WAKEUP (_U(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos) 504 #define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */ 505 #define USB_HOST_INTENCLR_DNRSM (_U(0x1) << USB_HOST_INTENCLR_DNRSM_Pos) 506 #define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */ 507 #define USB_HOST_INTENCLR_UPRSM (_U(0x1) << USB_HOST_INTENCLR_UPRSM_Pos) 508 #define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */ 509 #define USB_HOST_INTENCLR_RAMACER (_U(0x1) << USB_HOST_INTENCLR_RAMACER_Pos) 510 #define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */ 511 #define USB_HOST_INTENCLR_DCONN (_U(0x1) << USB_HOST_INTENCLR_DCONN_Pos) 512 #define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */ 513 #define USB_HOST_INTENCLR_DDISC (_U(0x1) << USB_HOST_INTENCLR_DDISC_Pos) 514 #define USB_HOST_INTENCLR_MASK _U(0x03FC) /**< \brief (USB_HOST_INTENCLR) MASK Register */ 515 516 /* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */ 517 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 518 typedef union { 519 struct { 520 uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ 521 uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ 522 uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ 523 uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ 524 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ 525 uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ 526 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ 527 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ 528 uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ 529 uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ 530 uint16_t :6; /*!< bit: 10..15 Reserved */ 531 } bit; /*!< Structure used for bit access */ 532 uint16_t reg; /*!< Type used for register access */ 533 } USB_DEVICE_INTENSET_Type; 534 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 535 536 #define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */ 537 #define USB_DEVICE_INTENSET_RESETVALUE _U(0x0000) /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */ 538 539 #define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */ 540 #define USB_DEVICE_INTENSET_SUSPEND (_U(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos) 541 #define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */ 542 #define USB_DEVICE_INTENSET_MSOF (_U(0x1) << USB_DEVICE_INTENSET_MSOF_Pos) 543 #define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */ 544 #define USB_DEVICE_INTENSET_SOF (_U(0x1) << USB_DEVICE_INTENSET_SOF_Pos) 545 #define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */ 546 #define USB_DEVICE_INTENSET_EORST (_U(0x1) << USB_DEVICE_INTENSET_EORST_Pos) 547 #define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */ 548 #define USB_DEVICE_INTENSET_WAKEUP (_U(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos) 549 #define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */ 550 #define USB_DEVICE_INTENSET_EORSM (_U(0x1) << USB_DEVICE_INTENSET_EORSM_Pos) 551 #define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */ 552 #define USB_DEVICE_INTENSET_UPRSM (_U(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos) 553 #define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */ 554 #define USB_DEVICE_INTENSET_RAMACER (_U(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos) 555 #define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */ 556 #define USB_DEVICE_INTENSET_LPMNYET (_U(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos) 557 #define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */ 558 #define USB_DEVICE_INTENSET_LPMSUSP (_U(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos) 559 #define USB_DEVICE_INTENSET_MASK _U(0x03FF) /**< \brief (USB_DEVICE_INTENSET) MASK Register */ 560 561 /* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */ 562 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 563 typedef union { 564 struct { 565 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 566 uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ 567 uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ 568 uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ 569 uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ 570 uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ 571 uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ 572 uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ 573 uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ 574 uint16_t :6; /*!< bit: 10..15 Reserved */ 575 } bit; /*!< Structure used for bit access */ 576 uint16_t reg; /*!< Type used for register access */ 577 } USB_HOST_INTENSET_Type; 578 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 579 580 #define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */ 581 #define USB_HOST_INTENSET_RESETVALUE _U(0x0000) /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */ 582 583 #define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */ 584 #define USB_HOST_INTENSET_HSOF (_U(0x1) << USB_HOST_INTENSET_HSOF_Pos) 585 #define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */ 586 #define USB_HOST_INTENSET_RST (_U(0x1) << USB_HOST_INTENSET_RST_Pos) 587 #define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */ 588 #define USB_HOST_INTENSET_WAKEUP (_U(0x1) << USB_HOST_INTENSET_WAKEUP_Pos) 589 #define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */ 590 #define USB_HOST_INTENSET_DNRSM (_U(0x1) << USB_HOST_INTENSET_DNRSM_Pos) 591 #define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */ 592 #define USB_HOST_INTENSET_UPRSM (_U(0x1) << USB_HOST_INTENSET_UPRSM_Pos) 593 #define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */ 594 #define USB_HOST_INTENSET_RAMACER (_U(0x1) << USB_HOST_INTENSET_RAMACER_Pos) 595 #define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */ 596 #define USB_HOST_INTENSET_DCONN (_U(0x1) << USB_HOST_INTENSET_DCONN_Pos) 597 #define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */ 598 #define USB_HOST_INTENSET_DDISC (_U(0x1) << USB_HOST_INTENSET_DDISC_Pos) 599 #define USB_HOST_INTENSET_MASK _U(0x03FC) /**< \brief (USB_HOST_INTENSET) MASK Register */ 600 601 /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */ 602 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 603 typedef union { // __I to avoid read-modify-write on write-to-clear register 604 struct { 605 __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ 606 __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ 607 __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ 608 __I uint16_t EORST:1; /*!< bit: 3 End of Reset */ 609 __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ 610 __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ 611 __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ 612 __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ 613 __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ 614 __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ 615 __I uint16_t :6; /*!< bit: 10..15 Reserved */ 616 } bit; /*!< Structure used for bit access */ 617 uint16_t reg; /*!< Type used for register access */ 618 } USB_DEVICE_INTFLAG_Type; 619 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 620 621 #define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */ 622 #define USB_DEVICE_INTFLAG_RESETVALUE _U(0x0000) /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */ 623 624 #define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */ 625 #define USB_DEVICE_INTFLAG_SUSPEND (_U(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos) 626 #define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */ 627 #define USB_DEVICE_INTFLAG_MSOF (_U(0x1) << USB_DEVICE_INTFLAG_MSOF_Pos) 628 #define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */ 629 #define USB_DEVICE_INTFLAG_SOF (_U(0x1) << USB_DEVICE_INTFLAG_SOF_Pos) 630 #define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */ 631 #define USB_DEVICE_INTFLAG_EORST (_U(0x1) << USB_DEVICE_INTFLAG_EORST_Pos) 632 #define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */ 633 #define USB_DEVICE_INTFLAG_WAKEUP (_U(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos) 634 #define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */ 635 #define USB_DEVICE_INTFLAG_EORSM (_U(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos) 636 #define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */ 637 #define USB_DEVICE_INTFLAG_UPRSM (_U(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos) 638 #define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */ 639 #define USB_DEVICE_INTFLAG_RAMACER (_U(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos) 640 #define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */ 641 #define USB_DEVICE_INTFLAG_LPMNYET (_U(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos) 642 #define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */ 643 #define USB_DEVICE_INTFLAG_LPMSUSP (_U(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos) 644 #define USB_DEVICE_INTFLAG_MASK _U(0x03FF) /**< \brief (USB_DEVICE_INTFLAG) MASK Register */ 645 646 /* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */ 647 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 648 typedef union { // __I to avoid read-modify-write on write-to-clear register 649 struct { 650 __I uint16_t :2; /*!< bit: 0.. 1 Reserved */ 651 __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ 652 __I uint16_t RST:1; /*!< bit: 3 Bus Reset */ 653 __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ 654 __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */ 655 __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ 656 __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ 657 __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */ 658 __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ 659 __I uint16_t :6; /*!< bit: 10..15 Reserved */ 660 } bit; /*!< Structure used for bit access */ 661 uint16_t reg; /*!< Type used for register access */ 662 } USB_HOST_INTFLAG_Type; 663 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 664 665 #define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */ 666 #define USB_HOST_INTFLAG_RESETVALUE _U(0x0000) /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */ 667 668 #define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */ 669 #define USB_HOST_INTFLAG_HSOF (_U(0x1) << USB_HOST_INTFLAG_HSOF_Pos) 670 #define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */ 671 #define USB_HOST_INTFLAG_RST (_U(0x1) << USB_HOST_INTFLAG_RST_Pos) 672 #define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */ 673 #define USB_HOST_INTFLAG_WAKEUP (_U(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos) 674 #define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */ 675 #define USB_HOST_INTFLAG_DNRSM (_U(0x1) << USB_HOST_INTFLAG_DNRSM_Pos) 676 #define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */ 677 #define USB_HOST_INTFLAG_UPRSM (_U(0x1) << USB_HOST_INTFLAG_UPRSM_Pos) 678 #define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */ 679 #define USB_HOST_INTFLAG_RAMACER (_U(0x1) << USB_HOST_INTFLAG_RAMACER_Pos) 680 #define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */ 681 #define USB_HOST_INTFLAG_DCONN (_U(0x1) << USB_HOST_INTFLAG_DCONN_Pos) 682 #define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */ 683 #define USB_HOST_INTFLAG_DDISC (_U(0x1) << USB_HOST_INTFLAG_DDISC_Pos) 684 #define USB_HOST_INTFLAG_MASK _U(0x03FC) /**< \brief (USB_HOST_INTFLAG) MASK Register */ 685 686 /* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */ 687 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 688 typedef union { 689 struct { 690 uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ 691 uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ 692 uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ 693 uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ 694 uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ 695 uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ 696 uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ 697 uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ 698 uint16_t :8; /*!< bit: 8..15 Reserved */ 699 } bit; /*!< Structure used for bit access */ 700 struct { 701 uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ 702 uint16_t :8; /*!< bit: 8..15 Reserved */ 703 } vec; /*!< Structure used for vec access */ 704 uint16_t reg; /*!< Type used for register access */ 705 } USB_DEVICE_EPINTSMRY_Type; 706 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 707 708 #define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */ 709 #define USB_DEVICE_EPINTSMRY_RESETVALUE _U(0x0000) /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */ 710 711 #define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */ 712 #define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos) 713 #define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */ 714 #define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos) 715 #define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */ 716 #define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos) 717 #define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */ 718 #define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos) 719 #define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */ 720 #define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos) 721 #define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */ 722 #define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos) 723 #define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */ 724 #define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos) 725 #define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */ 726 #define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos) 727 #define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */ 728 #define USB_DEVICE_EPINTSMRY_EPINT_Msk (_U(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos) 729 #define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos)) 730 #define USB_DEVICE_EPINTSMRY_MASK _U(0x00FF) /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */ 731 732 /* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */ 733 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 734 typedef union { 735 struct { 736 uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ 737 uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ 738 uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ 739 uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ 740 uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ 741 uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ 742 uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ 743 uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ 744 uint16_t :8; /*!< bit: 8..15 Reserved */ 745 } bit; /*!< Structure used for bit access */ 746 struct { 747 uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ 748 uint16_t :8; /*!< bit: 8..15 Reserved */ 749 } vec; /*!< Structure used for vec access */ 750 uint16_t reg; /*!< Type used for register access */ 751 } USB_HOST_PINTSMRY_Type; 752 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 753 754 #define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */ 755 #define USB_HOST_PINTSMRY_RESETVALUE _U(0x0000) /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */ 756 757 #define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */ 758 #define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos) 759 #define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */ 760 #define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos) 761 #define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */ 762 #define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos) 763 #define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */ 764 #define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos) 765 #define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */ 766 #define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos) 767 #define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */ 768 #define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos) 769 #define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */ 770 #define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos) 771 #define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */ 772 #define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos) 773 #define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */ 774 #define USB_HOST_PINTSMRY_EPINT_Msk (_U(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos) 775 #define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos)) 776 #define USB_HOST_PINTSMRY_MASK _U(0x00FF) /**< \brief (USB_HOST_PINTSMRY) MASK Register */ 777 778 /* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */ 779 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 780 typedef union { 781 struct { 782 uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ 783 } bit; /*!< Structure used for bit access */ 784 uint32_t reg; /*!< Type used for register access */ 785 } USB_DESCADD_Type; 786 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 787 788 #define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */ 789 #define USB_DESCADD_RESETVALUE _U(0x00000000) /**< \brief (USB_DESCADD reset_value) Descriptor Address */ 790 791 #define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */ 792 #define USB_DESCADD_DESCADD_Msk (_U(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos) 793 #define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos)) 794 #define USB_DESCADD_MASK _U(0xFFFFFFFF) /**< \brief (USB_DESCADD) MASK Register */ 795 796 /* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */ 797 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 798 typedef union { 799 struct { 800 uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ 801 uint16_t :1; /*!< bit: 5 Reserved */ 802 uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ 803 uint16_t :1; /*!< bit: 11 Reserved */ 804 uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ 805 uint16_t :1; /*!< bit: 15 Reserved */ 806 } bit; /*!< Structure used for bit access */ 807 uint16_t reg; /*!< Type used for register access */ 808 } USB_PADCAL_Type; 809 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 810 811 #define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */ 812 #define USB_PADCAL_RESETVALUE _U(0x0000) /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */ 813 814 #define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */ 815 #define USB_PADCAL_TRANSP_Msk (_U(0x1F) << USB_PADCAL_TRANSP_Pos) 816 #define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos)) 817 #define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */ 818 #define USB_PADCAL_TRANSN_Msk (_U(0x1F) << USB_PADCAL_TRANSN_Pos) 819 #define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos)) 820 #define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */ 821 #define USB_PADCAL_TRIM_Msk (_U(0x7) << USB_PADCAL_TRIM_Pos) 822 #define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos)) 823 #define USB_PADCAL_MASK _U(0x77DF) /**< \brief (USB_PADCAL) MASK Register */ 824 825 /* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */ 826 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 827 typedef union { 828 struct { 829 uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ 830 uint8_t :1; /*!< bit: 3 Reserved */ 831 uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ 832 uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ 833 } bit; /*!< Structure used for bit access */ 834 uint8_t reg; /*!< Type used for register access */ 835 } USB_DEVICE_EPCFG_Type; 836 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 837 838 #define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */ 839 #define USB_DEVICE_EPCFG_RESETVALUE _U(0x00) /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */ 840 841 #define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */ 842 #define USB_DEVICE_EPCFG_EPTYPE0_Msk (_U(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos) 843 #define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos)) 844 #define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */ 845 #define USB_DEVICE_EPCFG_EPTYPE1_Msk (_U(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos) 846 #define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos)) 847 #define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */ 848 #define USB_DEVICE_EPCFG_NYETDIS (_U(0x1) << USB_DEVICE_EPCFG_NYETDIS_Pos) 849 #define USB_DEVICE_EPCFG_MASK _U(0xF7) /**< \brief (USB_DEVICE_EPCFG) MASK Register */ 850 851 /* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */ 852 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 853 typedef union { 854 struct { 855 uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ 856 uint8_t BK:1; /*!< bit: 2 Pipe Bank */ 857 uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ 858 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 859 } bit; /*!< Structure used for bit access */ 860 uint8_t reg; /*!< Type used for register access */ 861 } USB_HOST_PCFG_Type; 862 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 863 864 #define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */ 865 #define USB_HOST_PCFG_RESETVALUE _U(0x00) /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */ 866 867 #define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */ 868 #define USB_HOST_PCFG_PTOKEN_Msk (_U(0x3) << USB_HOST_PCFG_PTOKEN_Pos) 869 #define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos)) 870 #define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */ 871 #define USB_HOST_PCFG_BK (_U(0x1) << USB_HOST_PCFG_BK_Pos) 872 #define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */ 873 #define USB_HOST_PCFG_PTYPE_Msk (_U(0x7) << USB_HOST_PCFG_PTYPE_Pos) 874 #define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos)) 875 #define USB_HOST_PCFG_MASK _U(0x3F) /**< \brief (USB_HOST_PCFG) MASK Register */ 876 877 /* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */ 878 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 879 typedef union { 880 struct { 881 uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ 882 } bit; /*!< Structure used for bit access */ 883 uint8_t reg; /*!< Type used for register access */ 884 } USB_HOST_BINTERVAL_Type; 885 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 886 887 #define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */ 888 #define USB_HOST_BINTERVAL_RESETVALUE _U(0x00) /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */ 889 890 #define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */ 891 #define USB_HOST_BINTERVAL_BITINTERVAL_Msk (_U(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos) 892 #define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)) 893 #define USB_HOST_BINTERVAL_MASK _U(0xFF) /**< \brief (USB_HOST_BINTERVAL) MASK Register */ 894 895 /* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ 896 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 897 typedef union { 898 struct { 899 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ 900 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ 901 uint8_t CURBK:1; /*!< bit: 2 Current Bank Clear */ 902 uint8_t :1; /*!< bit: 3 Reserved */ 903 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ 904 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ 905 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ 906 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ 907 } bit; /*!< Structure used for bit access */ 908 struct { 909 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 910 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ 911 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 912 } vec; /*!< Structure used for vec access */ 913 uint8_t reg; /*!< Type used for register access */ 914 } USB_DEVICE_EPSTATUSCLR_Type; 915 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 916 917 #define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */ 918 #define USB_DEVICE_EPSTATUSCLR_RESETVALUE _U(0x00) /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */ 919 920 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */ 921 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT (_U(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos) 922 #define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */ 923 #define USB_DEVICE_EPSTATUSCLR_DTGLIN (_U(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos) 924 #define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Current Bank Clear */ 925 #define USB_DEVICE_EPSTATUSCLR_CURBK (_U(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos) 926 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */ 927 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos) 928 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */ 929 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos) 930 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */ 931 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (_U(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos) 932 #define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)) 933 #define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */ 934 #define USB_DEVICE_EPSTATUSCLR_BK0RDY (_U(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos) 935 #define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */ 936 #define USB_DEVICE_EPSTATUSCLR_BK1RDY (_U(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos) 937 #define USB_DEVICE_EPSTATUSCLR_MASK _U(0xF7) /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */ 938 939 /* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */ 940 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 941 typedef union { 942 struct { 943 uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ 944 uint8_t :1; /*!< bit: 1 Reserved */ 945 uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ 946 uint8_t :1; /*!< bit: 3 Reserved */ 947 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ 948 uint8_t :1; /*!< bit: 5 Reserved */ 949 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ 950 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ 951 } bit; /*!< Structure used for bit access */ 952 uint8_t reg; /*!< Type used for register access */ 953 } USB_HOST_PSTATUSCLR_Type; 954 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 955 956 #define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */ 957 #define USB_HOST_PSTATUSCLR_RESETVALUE _U(0x00) /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */ 958 959 #define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */ 960 #define USB_HOST_PSTATUSCLR_DTGL (_U(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos) 961 #define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */ 962 #define USB_HOST_PSTATUSCLR_CURBK (_U(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos) 963 #define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */ 964 #define USB_HOST_PSTATUSCLR_PFREEZE (_U(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos) 965 #define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */ 966 #define USB_HOST_PSTATUSCLR_BK0RDY (_U(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos) 967 #define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */ 968 #define USB_HOST_PSTATUSCLR_BK1RDY (_U(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos) 969 #define USB_HOST_PSTATUSCLR_MASK _U(0xD5) /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */ 970 971 /* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */ 972 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 973 typedef union { 974 struct { 975 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ 976 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ 977 uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ 978 uint8_t :1; /*!< bit: 3 Reserved */ 979 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ 980 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ 981 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ 982 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ 983 } bit; /*!< Structure used for bit access */ 984 struct { 985 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 986 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ 987 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 988 } vec; /*!< Structure used for vec access */ 989 uint8_t reg; /*!< Type used for register access */ 990 } USB_DEVICE_EPSTATUSSET_Type; 991 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 992 993 #define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */ 994 #define USB_DEVICE_EPSTATUSSET_RESETVALUE _U(0x00) /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */ 995 996 #define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */ 997 #define USB_DEVICE_EPSTATUSSET_DTGLOUT (_U(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos) 998 #define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */ 999 #define USB_DEVICE_EPSTATUSSET_DTGLIN (_U(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos) 1000 #define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */ 1001 #define USB_DEVICE_EPSTATUSSET_CURBK (_U(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos) 1002 #define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */ 1003 #define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos) 1004 #define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */ 1005 #define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos) 1006 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */ 1007 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (_U(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos) 1008 #define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)) 1009 #define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */ 1010 #define USB_DEVICE_EPSTATUSSET_BK0RDY (_U(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos) 1011 #define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */ 1012 #define USB_DEVICE_EPSTATUSSET_BK1RDY (_U(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos) 1013 #define USB_DEVICE_EPSTATUSSET_MASK _U(0xF7) /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */ 1014 1015 /* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */ 1016 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1017 typedef union { 1018 struct { 1019 uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ 1020 uint8_t :1; /*!< bit: 1 Reserved */ 1021 uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ 1022 uint8_t :1; /*!< bit: 3 Reserved */ 1023 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ 1024 uint8_t :1; /*!< bit: 5 Reserved */ 1025 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ 1026 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ 1027 } bit; /*!< Structure used for bit access */ 1028 uint8_t reg; /*!< Type used for register access */ 1029 } USB_HOST_PSTATUSSET_Type; 1030 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1031 1032 #define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */ 1033 #define USB_HOST_PSTATUSSET_RESETVALUE _U(0x00) /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */ 1034 1035 #define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */ 1036 #define USB_HOST_PSTATUSSET_DTGL (_U(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos) 1037 #define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */ 1038 #define USB_HOST_PSTATUSSET_CURBK (_U(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos) 1039 #define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */ 1040 #define USB_HOST_PSTATUSSET_PFREEZE (_U(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos) 1041 #define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */ 1042 #define USB_HOST_PSTATUSSET_BK0RDY (_U(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos) 1043 #define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */ 1044 #define USB_HOST_PSTATUSSET_BK1RDY (_U(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos) 1045 #define USB_HOST_PSTATUSSET_MASK _U(0xD5) /**< \brief (USB_HOST_PSTATUSSET) MASK Register */ 1046 1047 /* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */ 1048 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1049 typedef union { 1050 struct { 1051 uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ 1052 uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ 1053 uint8_t CURBK:1; /*!< bit: 2 Current Bank */ 1054 uint8_t :1; /*!< bit: 3 Reserved */ 1055 uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ 1056 uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ 1057 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ 1058 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ 1059 } bit; /*!< Structure used for bit access */ 1060 struct { 1061 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 1062 uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ 1063 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 1064 } vec; /*!< Structure used for vec access */ 1065 uint8_t reg; /*!< Type used for register access */ 1066 } USB_DEVICE_EPSTATUS_Type; 1067 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1068 1069 #define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */ 1070 #define USB_DEVICE_EPSTATUS_RESETVALUE _U(0x00) /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */ 1071 1072 #define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */ 1073 #define USB_DEVICE_EPSTATUS_DTGLOUT (_U(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos) 1074 #define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */ 1075 #define USB_DEVICE_EPSTATUS_DTGLIN (_U(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos) 1076 #define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */ 1077 #define USB_DEVICE_EPSTATUS_CURBK (_U(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos) 1078 #define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */ 1079 #define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos) 1080 #define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */ 1081 #define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos) 1082 #define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */ 1083 #define USB_DEVICE_EPSTATUS_STALLRQ_Msk (_U(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos) 1084 #define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)) 1085 #define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */ 1086 #define USB_DEVICE_EPSTATUS_BK0RDY (_U(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos) 1087 #define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */ 1088 #define USB_DEVICE_EPSTATUS_BK1RDY (_U(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos) 1089 #define USB_DEVICE_EPSTATUS_MASK _U(0xF7) /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */ 1090 1091 /* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */ 1092 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1093 typedef union { 1094 struct { 1095 uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ 1096 uint8_t :1; /*!< bit: 1 Reserved */ 1097 uint8_t CURBK:1; /*!< bit: 2 Current Bank */ 1098 uint8_t :1; /*!< bit: 3 Reserved */ 1099 uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ 1100 uint8_t :1; /*!< bit: 5 Reserved */ 1101 uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ 1102 uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ 1103 } bit; /*!< Structure used for bit access */ 1104 uint8_t reg; /*!< Type used for register access */ 1105 } USB_HOST_PSTATUS_Type; 1106 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1107 1108 #define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */ 1109 #define USB_HOST_PSTATUS_RESETVALUE _U(0x00) /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */ 1110 1111 #define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */ 1112 #define USB_HOST_PSTATUS_DTGL (_U(0x1) << USB_HOST_PSTATUS_DTGL_Pos) 1113 #define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */ 1114 #define USB_HOST_PSTATUS_CURBK (_U(0x1) << USB_HOST_PSTATUS_CURBK_Pos) 1115 #define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */ 1116 #define USB_HOST_PSTATUS_PFREEZE (_U(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos) 1117 #define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */ 1118 #define USB_HOST_PSTATUS_BK0RDY (_U(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos) 1119 #define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */ 1120 #define USB_HOST_PSTATUS_BK1RDY (_U(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos) 1121 #define USB_HOST_PSTATUS_MASK _U(0xD5) /**< \brief (USB_HOST_PSTATUS) MASK Register */ 1122 1123 /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */ 1124 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1125 typedef union { // __I to avoid read-modify-write on write-to-clear register 1126 struct { 1127 __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ 1128 __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ 1129 __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ 1130 __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ 1131 __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ 1132 __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ 1133 __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ 1134 __I uint8_t :1; /*!< bit: 7 Reserved */ 1135 } bit; /*!< Structure used for bit access */ 1136 struct { 1137 __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ 1138 __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ 1139 __I uint8_t :1; /*!< bit: 4 Reserved */ 1140 __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ 1141 __I uint8_t :1; /*!< bit: 7 Reserved */ 1142 } vec; /*!< Structure used for vec access */ 1143 uint8_t reg; /*!< Type used for register access */ 1144 } USB_DEVICE_EPINTFLAG_Type; 1145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1146 1147 #define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */ 1148 #define USB_DEVICE_EPINTFLAG_RESETVALUE _U(0x00) /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */ 1149 1150 #define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */ 1151 #define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos) 1152 #define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */ 1153 #define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos) 1154 #define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */ 1155 #define USB_DEVICE_EPINTFLAG_TRCPT_Msk (_U(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos) 1156 #define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)) 1157 #define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */ 1158 #define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos) 1159 #define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */ 1160 #define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos) 1161 #define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */ 1162 #define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (_U(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos) 1163 #define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)) 1164 #define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */ 1165 #define USB_DEVICE_EPINTFLAG_RXSTP (_U(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos) 1166 #define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */ 1167 #define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos) 1168 #define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */ 1169 #define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos) 1170 #define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */ 1171 #define USB_DEVICE_EPINTFLAG_STALL_Msk (_U(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos) 1172 #define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos)) 1173 #define USB_DEVICE_EPINTFLAG_MASK _U(0x7F) /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */ 1174 1175 /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */ 1176 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1177 typedef union { // __I to avoid read-modify-write on write-to-clear register 1178 struct { 1179 __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ 1180 __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ 1181 __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ 1182 __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ 1183 __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ 1184 __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ 1185 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 1186 } bit; /*!< Structure used for bit access */ 1187 struct { 1188 __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ 1189 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 1190 } vec; /*!< Structure used for vec access */ 1191 uint8_t reg; /*!< Type used for register access */ 1192 } USB_HOST_PINTFLAG_Type; 1193 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1194 1195 #define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */ 1196 #define USB_HOST_PINTFLAG_RESETVALUE _U(0x00) /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */ 1197 1198 #define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */ 1199 #define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos) 1200 #define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */ 1201 #define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos) 1202 #define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */ 1203 #define USB_HOST_PINTFLAG_TRCPT_Msk (_U(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos) 1204 #define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos)) 1205 #define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */ 1206 #define USB_HOST_PINTFLAG_TRFAIL (_U(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos) 1207 #define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */ 1208 #define USB_HOST_PINTFLAG_PERR (_U(0x1) << USB_HOST_PINTFLAG_PERR_Pos) 1209 #define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */ 1210 #define USB_HOST_PINTFLAG_TXSTP (_U(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos) 1211 #define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */ 1212 #define USB_HOST_PINTFLAG_STALL (_U(0x1) << USB_HOST_PINTFLAG_STALL_Pos) 1213 #define USB_HOST_PINTFLAG_MASK _U(0x3F) /**< \brief (USB_HOST_PINTFLAG) MASK Register */ 1214 1215 /* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ 1216 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1217 typedef union { 1218 struct { 1219 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ 1220 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ 1221 uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ 1222 uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ 1223 uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ 1224 uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ 1225 uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ 1226 uint8_t :1; /*!< bit: 7 Reserved */ 1227 } bit; /*!< Structure used for bit access */ 1228 struct { 1229 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ 1230 uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ 1231 uint8_t :1; /*!< bit: 4 Reserved */ 1232 uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ 1233 uint8_t :1; /*!< bit: 7 Reserved */ 1234 } vec; /*!< Structure used for vec access */ 1235 uint8_t reg; /*!< Type used for register access */ 1236 } USB_DEVICE_EPINTENCLR_Type; 1237 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1238 1239 #define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ 1240 #define USB_DEVICE_EPINTENCLR_RESETVALUE _U(0x00) /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ 1241 1242 #define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */ 1243 #define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos) 1244 #define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */ 1245 #define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos) 1246 #define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */ 1247 #define USB_DEVICE_EPINTENCLR_TRCPT_Msk (_U(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos) 1248 #define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)) 1249 #define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */ 1250 #define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos) 1251 #define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */ 1252 #define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos) 1253 #define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */ 1254 #define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (_U(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos) 1255 #define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)) 1256 #define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */ 1257 #define USB_DEVICE_EPINTENCLR_RXSTP (_U(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos) 1258 #define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */ 1259 #define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos) 1260 #define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */ 1261 #define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos) 1262 #define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */ 1263 #define USB_DEVICE_EPINTENCLR_STALL_Msk (_U(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos) 1264 #define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos)) 1265 #define USB_DEVICE_EPINTENCLR_MASK _U(0x7F) /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */ 1266 1267 /* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */ 1268 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1269 typedef union { 1270 struct { 1271 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ 1272 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ 1273 uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ 1274 uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ 1275 uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ 1276 uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */ 1277 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 1278 } bit; /*!< Structure used for bit access */ 1279 struct { 1280 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ 1281 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 1282 } vec; /*!< Structure used for vec access */ 1283 uint8_t reg; /*!< Type used for register access */ 1284 } USB_HOST_PINTENCLR_Type; 1285 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1286 1287 #define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */ 1288 #define USB_HOST_PINTENCLR_RESETVALUE _U(0x00) /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */ 1289 1290 #define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */ 1291 #define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos) 1292 #define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */ 1293 #define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos) 1294 #define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */ 1295 #define USB_HOST_PINTENCLR_TRCPT_Msk (_U(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos) 1296 #define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos)) 1297 #define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */ 1298 #define USB_HOST_PINTENCLR_TRFAIL (_U(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos) 1299 #define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */ 1300 #define USB_HOST_PINTENCLR_PERR (_U(0x1) << USB_HOST_PINTENCLR_PERR_Pos) 1301 #define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */ 1302 #define USB_HOST_PINTENCLR_TXSTP (_U(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos) 1303 #define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */ 1304 #define USB_HOST_PINTENCLR_STALL (_U(0x1) << USB_HOST_PINTENCLR_STALL_Pos) 1305 #define USB_HOST_PINTENCLR_MASK _U(0x3F) /**< \brief (USB_HOST_PINTENCLR) MASK Register */ 1306 1307 /* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ 1308 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1309 typedef union { 1310 struct { 1311 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ 1312 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ 1313 uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ 1314 uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ 1315 uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ 1316 uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ 1317 uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ 1318 uint8_t :1; /*!< bit: 7 Reserved */ 1319 } bit; /*!< Structure used for bit access */ 1320 struct { 1321 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ 1322 uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ 1323 uint8_t :1; /*!< bit: 4 Reserved */ 1324 uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ 1325 uint8_t :1; /*!< bit: 7 Reserved */ 1326 } vec; /*!< Structure used for vec access */ 1327 uint8_t reg; /*!< Type used for register access */ 1328 } USB_DEVICE_EPINTENSET_Type; 1329 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1330 1331 #define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */ 1332 #define USB_DEVICE_EPINTENSET_RESETVALUE _U(0x00) /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */ 1333 1334 #define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */ 1335 #define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos) 1336 #define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */ 1337 #define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos) 1338 #define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */ 1339 #define USB_DEVICE_EPINTENSET_TRCPT_Msk (_U(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos) 1340 #define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos)) 1341 #define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */ 1342 #define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos) 1343 #define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */ 1344 #define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos) 1345 #define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */ 1346 #define USB_DEVICE_EPINTENSET_TRFAIL_Msk (_U(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos) 1347 #define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)) 1348 #define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */ 1349 #define USB_DEVICE_EPINTENSET_RXSTP (_U(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos) 1350 #define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */ 1351 #define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos) 1352 #define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */ 1353 #define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos) 1354 #define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */ 1355 #define USB_DEVICE_EPINTENSET_STALL_Msk (_U(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos) 1356 #define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos)) 1357 #define USB_DEVICE_EPINTENSET_MASK _U(0x7F) /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */ 1358 1359 /* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */ 1360 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1361 typedef union { 1362 struct { 1363 uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ 1364 uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ 1365 uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ 1366 uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ 1367 uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ 1368 uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ 1369 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 1370 } bit; /*!< Structure used for bit access */ 1371 struct { 1372 uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ 1373 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 1374 } vec; /*!< Structure used for vec access */ 1375 uint8_t reg; /*!< Type used for register access */ 1376 } USB_HOST_PINTENSET_Type; 1377 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1378 1379 #define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */ 1380 #define USB_HOST_PINTENSET_RESETVALUE _U(0x00) /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */ 1381 1382 #define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */ 1383 #define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos) 1384 #define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */ 1385 #define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos) 1386 #define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */ 1387 #define USB_HOST_PINTENSET_TRCPT_Msk (_U(0x3) << USB_HOST_PINTENSET_TRCPT_Pos) 1388 #define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos)) 1389 #define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */ 1390 #define USB_HOST_PINTENSET_TRFAIL (_U(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos) 1391 #define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */ 1392 #define USB_HOST_PINTENSET_PERR (_U(0x1) << USB_HOST_PINTENSET_PERR_Pos) 1393 #define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */ 1394 #define USB_HOST_PINTENSET_TXSTP (_U(0x1) << USB_HOST_PINTENSET_TXSTP_Pos) 1395 #define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */ 1396 #define USB_HOST_PINTENSET_STALL (_U(0x1) << USB_HOST_PINTENSET_STALL_Pos) 1397 #define USB_HOST_PINTENSET_MASK _U(0x3F) /**< \brief (USB_HOST_PINTENSET) MASK Register */ 1398 1399 /* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ 1400 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1401 typedef union { 1402 struct { 1403 uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ 1404 } bit; /*!< Structure used for bit access */ 1405 uint32_t reg; /*!< Type used for register access */ 1406 } USB_DEVICE_ADDR_Type; 1407 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1408 1409 #define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ 1410 1411 #define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */ 1412 #define USB_DEVICE_ADDR_ADDR_Msk (_U(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos) 1413 #define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos)) 1414 #define USB_DEVICE_ADDR_MASK _U(0xFFFFFFFF) /**< \brief (USB_DEVICE_ADDR) MASK Register */ 1415 1416 /* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ 1417 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1418 typedef union { 1419 struct { 1420 uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ 1421 } bit; /*!< Structure used for bit access */ 1422 uint32_t reg; /*!< Type used for register access */ 1423 } USB_HOST_ADDR_Type; 1424 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1425 1426 #define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ 1427 1428 #define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */ 1429 #define USB_HOST_ADDR_ADDR_Msk (_U(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos) 1430 #define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos)) 1431 #define USB_HOST_ADDR_MASK _U(0xFFFFFFFF) /**< \brief (USB_HOST_ADDR) MASK Register */ 1432 1433 /* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ 1434 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1435 typedef union { 1436 struct { 1437 uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ 1438 uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ 1439 uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ 1440 uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ 1441 } bit; /*!< Structure used for bit access */ 1442 uint32_t reg; /*!< Type used for register access */ 1443 } USB_DEVICE_PCKSIZE_Type; 1444 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1445 1446 #define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ 1447 1448 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */ 1449 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (_U(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos) 1450 #define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)) 1451 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */ 1452 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) 1453 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)) 1454 #define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */ 1455 #define USB_DEVICE_PCKSIZE_SIZE_Msk (_U(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos) 1456 #define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos)) 1457 #define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */ 1458 #define USB_DEVICE_PCKSIZE_AUTO_ZLP (_U(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos) 1459 #define USB_DEVICE_PCKSIZE_MASK _U(0xFFFFFFFF) /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */ 1460 1461 /* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */ 1462 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1463 typedef union { 1464 struct { 1465 uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ 1466 uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ 1467 uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ 1468 uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ 1469 } bit; /*!< Structure used for bit access */ 1470 uint32_t reg; /*!< Type used for register access */ 1471 } USB_HOST_PCKSIZE_Type; 1472 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1473 1474 #define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */ 1475 1476 #define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */ 1477 #define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (_U(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos) 1478 #define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)) 1479 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */ 1480 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos) 1481 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)) 1482 #define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */ 1483 #define USB_HOST_PCKSIZE_SIZE_Msk (_U(0x7) << USB_HOST_PCKSIZE_SIZE_Pos) 1484 #define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos)) 1485 #define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */ 1486 #define USB_HOST_PCKSIZE_AUTO_ZLP (_U(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos) 1487 #define USB_HOST_PCKSIZE_MASK _U(0xFFFFFFFF) /**< \brief (USB_HOST_PCKSIZE) MASK Register */ 1488 1489 /* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ 1490 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1491 typedef union { 1492 struct { 1493 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ 1494 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ 1495 uint16_t :1; /*!< bit: 15 Reserved */ 1496 } bit; /*!< Structure used for bit access */ 1497 uint16_t reg; /*!< Type used for register access */ 1498 } USB_DEVICE_EXTREG_Type; 1499 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1500 1501 #define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */ 1502 1503 #define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */ 1504 #define USB_DEVICE_EXTREG_SUBPID_Msk (_U(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos) 1505 #define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos)) 1506 #define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */ 1507 #define USB_DEVICE_EXTREG_VARIABLE_Msk (_U(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos) 1508 #define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos)) 1509 #define USB_DEVICE_EXTREG_MASK _U(0x7FFF) /**< \brief (USB_DEVICE_EXTREG) MASK Register */ 1510 1511 /* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */ 1512 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1513 typedef union { 1514 struct { 1515 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ 1516 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ 1517 uint16_t :1; /*!< bit: 15 Reserved */ 1518 } bit; /*!< Structure used for bit access */ 1519 uint16_t reg; /*!< Type used for register access */ 1520 } USB_HOST_EXTREG_Type; 1521 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1522 1523 #define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */ 1524 1525 #define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */ 1526 #define USB_HOST_EXTREG_SUBPID_Msk (_U(0xF) << USB_HOST_EXTREG_SUBPID_Pos) 1527 #define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos)) 1528 #define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */ 1529 #define USB_HOST_EXTREG_VARIABLE_Msk (_U(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos) 1530 #define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos)) 1531 #define USB_HOST_EXTREG_MASK _U(0x7FFF) /**< \brief (USB_HOST_EXTREG) MASK Register */ 1532 1533 /* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ 1534 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1535 typedef union { 1536 struct { 1537 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ 1538 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ 1539 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 1540 } bit; /*!< Structure used for bit access */ 1541 uint8_t reg; /*!< Type used for register access */ 1542 } USB_DEVICE_STATUS_BK_Type; 1543 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1544 1545 #define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ 1546 1547 #define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */ 1548 #define USB_DEVICE_STATUS_BK_CRCERR (_U(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos) 1549 #define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */ 1550 #define USB_DEVICE_STATUS_BK_ERRORFLOW (_U(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos) 1551 #define USB_DEVICE_STATUS_BK_MASK _U(0x03) /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */ 1552 1553 /* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */ 1554 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1555 typedef union { 1556 struct { 1557 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ 1558 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ 1559 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 1560 } bit; /*!< Structure used for bit access */ 1561 uint8_t reg; /*!< Type used for register access */ 1562 } USB_HOST_STATUS_BK_Type; 1563 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1564 1565 #define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */ 1566 1567 #define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */ 1568 #define USB_HOST_STATUS_BK_CRCERR (_U(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos) 1569 #define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */ 1570 #define USB_HOST_STATUS_BK_ERRORFLOW (_U(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos) 1571 #define USB_HOST_STATUS_BK_MASK _U(0x03) /**< \brief (USB_HOST_STATUS_BK) MASK Register */ 1572 1573 /* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ 1574 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1575 typedef union { 1576 struct { 1577 uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ 1578 uint16_t :1; /*!< bit: 7 Reserved */ 1579 uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ 1580 uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ 1581 } bit; /*!< Structure used for bit access */ 1582 uint16_t reg; /*!< Type used for register access */ 1583 } USB_HOST_CTRL_PIPE_Type; 1584 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1585 1586 #define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */ 1587 #define USB_HOST_CTRL_PIPE_RESETVALUE _U(0x0000) /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */ 1588 1589 #define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */ 1590 #define USB_HOST_CTRL_PIPE_PDADDR_Msk (_U(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos) 1591 #define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos)) 1592 #define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */ 1593 #define USB_HOST_CTRL_PIPE_PEPNUM_Msk (_U(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos) 1594 #define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)) 1595 #define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */ 1596 #define USB_HOST_CTRL_PIPE_PERMAX_Msk (_U(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos) 1597 #define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos)) 1598 #define USB_HOST_CTRL_PIPE_MASK _U(0xFF7F) /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */ 1599 1600 /* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ 1601 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1602 typedef union { 1603 struct { 1604 uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ 1605 uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ 1606 uint16_t PIDER:1; /*!< bit: 2 PID Error */ 1607 uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ 1608 uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ 1609 uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ 1610 uint16_t :8; /*!< bit: 8..15 Reserved */ 1611 } bit; /*!< Structure used for bit access */ 1612 uint16_t reg; /*!< Type used for register access */ 1613 } USB_HOST_STATUS_PIPE_Type; 1614 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1615 1616 #define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */ 1617 1618 #define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */ 1619 #define USB_HOST_STATUS_PIPE_DTGLER (_U(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos) 1620 #define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */ 1621 #define USB_HOST_STATUS_PIPE_DAPIDER (_U(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos) 1622 #define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */ 1623 #define USB_HOST_STATUS_PIPE_PIDER (_U(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos) 1624 #define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */ 1625 #define USB_HOST_STATUS_PIPE_TOUTER (_U(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos) 1626 #define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */ 1627 #define USB_HOST_STATUS_PIPE_CRC16ER (_U(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos) 1628 #define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */ 1629 #define USB_HOST_STATUS_PIPE_ERCNT_Msk (_U(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos) 1630 #define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos)) 1631 #define USB_HOST_STATUS_PIPE_MASK _U(0x00FF) /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */ 1632 1633 /** \brief UsbDeviceDescBank SRAM registers */ 1634 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1635 typedef struct { 1636 __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ 1637 __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ 1638 __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ 1639 __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ 1640 RoReg8 Reserved1[0x5]; 1641 } UsbDeviceDescBank; 1642 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1643 1644 /** \brief UsbHostDescBank SRAM registers */ 1645 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1646 typedef struct { 1647 __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ 1648 __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ 1649 __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ 1650 __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ 1651 RoReg8 Reserved1[0x1]; 1652 __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ 1653 __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ 1654 } UsbHostDescBank; 1655 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1656 1657 /** \brief UsbDeviceEndpoint hardware registers */ 1658 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1659 typedef struct { 1660 __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ 1661 RoReg8 Reserved1[0x3]; 1662 __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ 1663 __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ 1664 __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ 1665 __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ 1666 __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ 1667 __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ 1668 RoReg8 Reserved2[0x16]; 1669 } UsbDeviceEndpoint; 1670 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1671 1672 /** \brief UsbHostPipe hardware registers */ 1673 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1674 typedef struct { 1675 __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ 1676 RoReg8 Reserved1[0x2]; 1677 __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ 1678 __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ 1679 __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ 1680 __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ 1681 __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ 1682 __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ 1683 __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ 1684 RoReg8 Reserved2[0x16]; 1685 } UsbHostPipe; 1686 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1687 1688 /** \brief USB_DEVICE APB hardware registers */ 1689 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1690 typedef struct { /* USB is Device */ 1691 __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ 1692 RoReg8 Reserved1[0x1]; 1693 __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ 1694 __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ 1695 RoReg8 Reserved2[0x4]; 1696 __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ 1697 __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ 1698 RoReg8 Reserved3[0x1]; 1699 __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ 1700 __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ 1701 RoReg8 Reserved4[0x2]; 1702 __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ 1703 RoReg8 Reserved5[0x2]; 1704 __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ 1705 RoReg8 Reserved6[0x2]; 1706 __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ 1707 RoReg8 Reserved7[0x2]; 1708 __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ 1709 RoReg8 Reserved8[0x2]; 1710 __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ 1711 RoReg8 Reserved9[0x2]; 1712 __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ 1713 __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ 1714 RoReg8 Reserved10[0xD6]; 1715 UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ 1716 } UsbDevice; 1717 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1718 1719 /** \brief USB_HOST hardware registers */ 1720 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1721 typedef struct { /* USB is Host */ 1722 __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ 1723 RoReg8 Reserved1[0x1]; 1724 __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ 1725 __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ 1726 RoReg8 Reserved2[0x4]; 1727 __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ 1728 __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ 1729 RoReg8 Reserved3[0x1]; 1730 __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ 1731 __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ 1732 RoReg8 Reserved4[0x2]; 1733 __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ 1734 __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ 1735 RoReg8 Reserved5[0x1]; 1736 __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ 1737 RoReg8 Reserved6[0x2]; 1738 __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ 1739 RoReg8 Reserved7[0x2]; 1740 __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ 1741 RoReg8 Reserved8[0x2]; 1742 __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ 1743 RoReg8 Reserved9[0x2]; 1744 __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ 1745 __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ 1746 RoReg8 Reserved10[0xD6]; 1747 UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ 1748 } UsbHost; 1749 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1750 1751 /** \brief USB_DEVICE Descriptor SRAM registers */ 1752 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1753 typedef struct { /* USB is Device */ 1754 UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ 1755 } UsbDeviceDescriptor; 1756 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1757 1758 /** \brief USB_HOST Descriptor SRAM registers */ 1759 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1760 typedef struct { /* USB is Host */ 1761 UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ 1762 } UsbHostDescriptor; 1763 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1764 1765 #ifdef __GNUC__ 1766 #define SECTION_USB_DESCRIPTOR __attribute__ ((section(".hsram"))) 1767 #elif defined(__ICCARM__) 1768 #define SECTION_USB_DESCRIPTOR @".hsram" 1769 #endif 1770 1771 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1772 typedef union { 1773 UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ 1774 UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ 1775 } Usb; 1776 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1777 1778 /*@}*/ 1779 1780 #endif /* _SAML21_USB_COMPONENT_ */ 1781
