Searched refs:TIM_DCR_DBL_Pos (Results 1 – 8 of 8) sorted by relevance
5809 #define TIM_DCR_DBL_Pos (8U) macro5810 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */5812 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */5813 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */5814 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */5815 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */5816 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
6171 #define TIM_DCR_DBL_Pos (8U) macro6172 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */6174 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */6175 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */6176 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */6177 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */6178 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
6067 #define TIM_DCR_DBL_Pos (8U) macro6068 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */6070 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */6071 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */6072 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */6073 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */6074 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
6330 #define TIM_DCR_DBL_Pos (8U) macro6331 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */6333 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */6334 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */6335 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */6336 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */6337 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
6891 #define TIM_DCR_DBL_Pos (8U) macro6892 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */6894 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */6895 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */6896 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */6897 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */6898 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
7193 #define TIM_DCR_DBL_Pos (8U) macro7194 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */7196 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */7197 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */7198 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */7199 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */7200 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
14612 #define TIM_DCR_DBL_Pos (8U) macro14613 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */14615 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */14616 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */14617 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */14618 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */14619 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
