Searched refs:SERCOM_SPI_INTFLAG_DRE (Results 1 – 4 of 4) sorted by relevance
80 while( ( SERCOM_SPI_INTFLAG_DRE & hri_sercomspi_read_INTFLAG_reg( SERCOM4 ) ) == 0 ) in SpiInOut()84 hri_sercomspi_clear_INTFLAG_reg( SERCOM4, SERCOM_SPI_INTFLAG_DRE ); in SpiInOut()
2165 …RCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); in _spi_async_disable()2587 while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { in _spi_wait_bus_idle()2590 hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); in _spi_wait_bus_idle()2637 if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { in _spi_tx_check_and_send()2845 return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); in _spi_s_sync_is_tx_ready()
846 #define SERCOM_SPI_INTFLAG_DRE (_U(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos) macro
297 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; in hri_sercomspi_get_INTFLAG_DRE_bit()302 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; in hri_sercomspi_clear_INTFLAG_DRE_bit()347 return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; in hri_sercomspi_get_interrupt_DRE_bit()352 ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; in hri_sercomspi_clear_interrupt_DRE_bit()
