1 /** 2 * \file 3 * 4 * \brief Component description for OSCCTRL 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_OSCCTRL_COMPONENT_ 30 #define _SAML21_OSCCTRL_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR OSCCTRL */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_OSCCTRL Oscillators Control */ 36 /*@{*/ 37 38 #define OSCCTRL_U2119 39 #define REV_OSCCTRL 0x110 40 41 /* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ 46 uint32_t :3; /*!< bit: 1.. 3 Reserved */ 47 uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready Interrupt Enable */ 48 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 49 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ 50 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ 51 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ 52 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ 53 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ 54 uint32_t :3; /*!< bit: 13..15 Reserved */ 55 uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise Interrupt Enable */ 56 uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall Interrupt Enable */ 57 uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Time Out Interrupt Enable */ 58 uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready Interrupt Enable */ 59 uint32_t :12; /*!< bit: 20..31 Reserved */ 60 } bit; /*!< Structure used for bit access */ 61 uint32_t reg; /*!< Type used for register access */ 62 } OSCCTRL_INTENCLR_Type; 63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 65 #define OSCCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */ 66 #define OSCCTRL_INTENCLR_RESETVALUE _U(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 67 68 #define OSCCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC Ready Interrupt Enable */ 69 #define OSCCTRL_INTENCLR_XOSCRDY (_U(0x1) << OSCCTRL_INTENCLR_XOSCRDY_Pos) 70 #define OSCCTRL_INTENCLR_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTENCLR) OSC16M Ready Interrupt Enable */ 71 #define OSCCTRL_INTENCLR_OSC16MRDY (_U(0x1) << OSCCTRL_INTENCLR_OSC16MRDY_Pos) 72 #define OSCCTRL_INTENCLR_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */ 73 #define OSCCTRL_INTENCLR_DFLLRDY (_U(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos) 74 #define OSCCTRL_INTENCLR_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */ 75 #define OSCCTRL_INTENCLR_DFLLOOB (_U(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos) 76 #define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */ 77 #define OSCCTRL_INTENCLR_DFLLLCKF (_U(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos) 78 #define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */ 79 #define OSCCTRL_INTENCLR_DFLLLCKC (_U(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos) 80 #define OSCCTRL_INTENCLR_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */ 81 #define OSCCTRL_INTENCLR_DFLLRCS (_U(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos) 82 #define OSCCTRL_INTENCLR_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */ 83 #define OSCCTRL_INTENCLR_DPLLLCKR (_U(0x1) << OSCCTRL_INTENCLR_DPLLLCKR_Pos) 84 #define OSCCTRL_INTENCLR_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */ 85 #define OSCCTRL_INTENCLR_DPLLLCKF (_U(0x1) << OSCCTRL_INTENCLR_DPLLLCKF_Pos) 86 #define OSCCTRL_INTENCLR_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTENCLR) DPLL Time Out Interrupt Enable */ 87 #define OSCCTRL_INTENCLR_DPLLLTO (_U(0x1) << OSCCTRL_INTENCLR_DPLLLTO_Pos) 88 #define OSCCTRL_INTENCLR_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTENCLR) DPLL Ratio Ready Interrupt Enable */ 89 #define OSCCTRL_INTENCLR_DPLLLDRTO (_U(0x1) << OSCCTRL_INTENCLR_DPLLLDRTO_Pos) 90 #define OSCCTRL_INTENCLR_MASK _U(0x000F1F11) /**< \brief (OSCCTRL_INTENCLR) MASK Register */ 91 92 /* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 93 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 94 typedef union { 95 struct { 96 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ 97 uint32_t :3; /*!< bit: 1.. 3 Reserved */ 98 uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready Interrupt Enable */ 99 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 100 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ 101 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ 102 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ 103 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ 104 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ 105 uint32_t :3; /*!< bit: 13..15 Reserved */ 106 uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise Interrupt Enable */ 107 uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall Interrupt Enable */ 108 uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Time Out Interrupt Enable */ 109 uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready Interrupt Enable */ 110 uint32_t :12; /*!< bit: 20..31 Reserved */ 111 } bit; /*!< Structure used for bit access */ 112 uint32_t reg; /*!< Type used for register access */ 113 } OSCCTRL_INTENSET_Type; 114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 115 116 #define OSCCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */ 117 #define OSCCTRL_INTENSET_RESETVALUE _U(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */ 118 119 #define OSCCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC Ready Interrupt Enable */ 120 #define OSCCTRL_INTENSET_XOSCRDY (_U(0x1) << OSCCTRL_INTENSET_XOSCRDY_Pos) 121 #define OSCCTRL_INTENSET_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTENSET) OSC16M Ready Interrupt Enable */ 122 #define OSCCTRL_INTENSET_OSC16MRDY (_U(0x1) << OSCCTRL_INTENSET_OSC16MRDY_Pos) 123 #define OSCCTRL_INTENSET_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */ 124 #define OSCCTRL_INTENSET_DFLLRDY (_U(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos) 125 #define OSCCTRL_INTENSET_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */ 126 #define OSCCTRL_INTENSET_DFLLOOB (_U(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos) 127 #define OSCCTRL_INTENSET_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */ 128 #define OSCCTRL_INTENSET_DFLLLCKF (_U(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos) 129 #define OSCCTRL_INTENSET_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */ 130 #define OSCCTRL_INTENSET_DFLLLCKC (_U(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos) 131 #define OSCCTRL_INTENSET_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */ 132 #define OSCCTRL_INTENSET_DFLLRCS (_U(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos) 133 #define OSCCTRL_INTENSET_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */ 134 #define OSCCTRL_INTENSET_DPLLLCKR (_U(0x1) << OSCCTRL_INTENSET_DPLLLCKR_Pos) 135 #define OSCCTRL_INTENSET_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */ 136 #define OSCCTRL_INTENSET_DPLLLCKF (_U(0x1) << OSCCTRL_INTENSET_DPLLLCKF_Pos) 137 #define OSCCTRL_INTENSET_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTENSET) DPLL Time Out Interrupt Enable */ 138 #define OSCCTRL_INTENSET_DPLLLTO (_U(0x1) << OSCCTRL_INTENSET_DPLLLTO_Pos) 139 #define OSCCTRL_INTENSET_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTENSET) DPLL Ratio Ready Interrupt Enable */ 140 #define OSCCTRL_INTENSET_DPLLLDRTO (_U(0x1) << OSCCTRL_INTENSET_DPLLLDRTO_Pos) 141 #define OSCCTRL_INTENSET_MASK _U(0x000F1F11) /**< \brief (OSCCTRL_INTENSET) MASK Register */ 142 143 /* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 144 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 145 typedef union { // __I to avoid read-modify-write on write-to-clear register 146 struct { 147 __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ 148 __I uint32_t :3; /*!< bit: 1.. 3 Reserved */ 149 __I uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready */ 150 __I uint32_t :3; /*!< bit: 5.. 7 Reserved */ 151 __I uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ 152 __I uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ 153 __I uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ 154 __I uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ 155 __I uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ 156 __I uint32_t :3; /*!< bit: 13..15 Reserved */ 157 __I uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise */ 158 __I uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall */ 159 __I uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Timeout */ 160 __I uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready */ 161 __I uint32_t :12; /*!< bit: 20..31 Reserved */ 162 } bit; /*!< Structure used for bit access */ 163 uint32_t reg; /*!< Type used for register access */ 164 } OSCCTRL_INTFLAG_Type; 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 #define OSCCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 168 #define OSCCTRL_INTFLAG_RESETVALUE _U(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 169 170 #define OSCCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC Ready */ 171 #define OSCCTRL_INTFLAG_XOSCRDY (_U(0x1) << OSCCTRL_INTFLAG_XOSCRDY_Pos) 172 #define OSCCTRL_INTFLAG_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTFLAG) OSC16M Ready */ 173 #define OSCCTRL_INTFLAG_OSC16MRDY (_U(0x1) << OSCCTRL_INTFLAG_OSC16MRDY_Pos) 174 #define OSCCTRL_INTFLAG_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */ 175 #define OSCCTRL_INTFLAG_DFLLRDY (_U(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos) 176 #define OSCCTRL_INTFLAG_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */ 177 #define OSCCTRL_INTFLAG_DFLLOOB (_U(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos) 178 #define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */ 179 #define OSCCTRL_INTFLAG_DFLLLCKF (_U(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos) 180 #define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */ 181 #define OSCCTRL_INTFLAG_DFLLLCKC (_U(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos) 182 #define OSCCTRL_INTFLAG_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */ 183 #define OSCCTRL_INTFLAG_DFLLRCS (_U(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos) 184 #define OSCCTRL_INTFLAG_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Rise */ 185 #define OSCCTRL_INTFLAG_DPLLLCKR (_U(0x1) << OSCCTRL_INTFLAG_DPLLLCKR_Pos) 186 #define OSCCTRL_INTFLAG_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Fall */ 187 #define OSCCTRL_INTFLAG_DPLLLCKF (_U(0x1) << OSCCTRL_INTFLAG_DPLLLCKF_Pos) 188 #define OSCCTRL_INTFLAG_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTFLAG) DPLL Timeout */ 189 #define OSCCTRL_INTFLAG_DPLLLTO (_U(0x1) << OSCCTRL_INTFLAG_DPLLLTO_Pos) 190 #define OSCCTRL_INTFLAG_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTFLAG) DPLL Ratio Ready */ 191 #define OSCCTRL_INTFLAG_DPLLLDRTO (_U(0x1) << OSCCTRL_INTFLAG_DPLLLDRTO_Pos) 192 #define OSCCTRL_INTFLAG_MASK _U(0x000F1F11) /**< \brief (OSCCTRL_INTFLAG) MASK Register */ 193 194 /* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ 195 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 196 typedef union { 197 struct { 198 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ 199 uint32_t :3; /*!< bit: 1.. 3 Reserved */ 200 uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready */ 201 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 202 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ 203 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ 204 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ 205 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ 206 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ 207 uint32_t :3; /*!< bit: 13..15 Reserved */ 208 uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise */ 209 uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall */ 210 uint32_t DPLLTO:1; /*!< bit: 18 DPLL Timeout */ 211 uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready */ 212 uint32_t :12; /*!< bit: 20..31 Reserved */ 213 } bit; /*!< Structure used for bit access */ 214 uint32_t reg; /*!< Type used for register access */ 215 } OSCCTRL_STATUS_Type; 216 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 217 218 #define OSCCTRL_STATUS_OFFSET 0x0C /**< \brief (OSCCTRL_STATUS offset) Power and Clocks Status */ 219 #define OSCCTRL_STATUS_RESETVALUE _U(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Power and Clocks Status */ 220 221 #define OSCCTRL_STATUS_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC Ready */ 222 #define OSCCTRL_STATUS_XOSCRDY (_U(0x1) << OSCCTRL_STATUS_XOSCRDY_Pos) 223 #define OSCCTRL_STATUS_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_STATUS) OSC16M Ready */ 224 #define OSCCTRL_STATUS_OSC16MRDY (_U(0x1) << OSCCTRL_STATUS_OSC16MRDY_Pos) 225 #define OSCCTRL_STATUS_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_STATUS) DFLL Ready */ 226 #define OSCCTRL_STATUS_DFLLRDY (_U(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos) 227 #define OSCCTRL_STATUS_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */ 228 #define OSCCTRL_STATUS_DFLLOOB (_U(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos) 229 #define OSCCTRL_STATUS_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */ 230 #define OSCCTRL_STATUS_DFLLLCKF (_U(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos) 231 #define OSCCTRL_STATUS_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */ 232 #define OSCCTRL_STATUS_DFLLLCKC (_U(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos) 233 #define OSCCTRL_STATUS_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */ 234 #define OSCCTRL_STATUS_DFLLRCS (_U(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos) 235 #define OSCCTRL_STATUS_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_STATUS) DPLL Lock Rise */ 236 #define OSCCTRL_STATUS_DPLLLCKR (_U(0x1) << OSCCTRL_STATUS_DPLLLCKR_Pos) 237 #define OSCCTRL_STATUS_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_STATUS) DPLL Lock Fall */ 238 #define OSCCTRL_STATUS_DPLLLCKF (_U(0x1) << OSCCTRL_STATUS_DPLLLCKF_Pos) 239 #define OSCCTRL_STATUS_DPLLTO_Pos 18 /**< \brief (OSCCTRL_STATUS) DPLL Timeout */ 240 #define OSCCTRL_STATUS_DPLLTO (_U(0x1) << OSCCTRL_STATUS_DPLLTO_Pos) 241 #define OSCCTRL_STATUS_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_STATUS) DPLL Ratio Ready */ 242 #define OSCCTRL_STATUS_DPLLLDRTO (_U(0x1) << OSCCTRL_STATUS_DPLLLDRTO_Pos) 243 #define OSCCTRL_STATUS_MASK _U(0x000F1F11) /**< \brief (OSCCTRL_STATUS) MASK Register */ 244 245 /* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ 246 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 247 typedef union { 248 struct { 249 uint16_t :1; /*!< bit: 0 Reserved */ 250 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 251 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ 252 uint16_t :3; /*!< bit: 3.. 5 Reserved */ 253 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 254 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 255 uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ 256 uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ 257 uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ 258 } bit; /*!< Structure used for bit access */ 259 uint16_t reg; /*!< Type used for register access */ 260 } OSCCTRL_XOSCCTRL_Type; 261 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 262 263 #define OSCCTRL_XOSCCTRL_OFFSET 0x10 /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator (XOSC) Control */ 264 #define OSCCTRL_XOSCCTRL_RESETVALUE _U(0x0080) /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */ 265 266 #define OSCCTRL_XOSCCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */ 267 #define OSCCTRL_XOSCCTRL_ENABLE (_U(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos) 268 #define OSCCTRL_XOSCCTRL_XTALEN_Pos 2 /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */ 269 #define OSCCTRL_XOSCCTRL_XTALEN (_U(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos) 270 #define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */ 271 #define OSCCTRL_XOSCCTRL_RUNSTDBY (_U(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) 272 #define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */ 273 #define OSCCTRL_XOSCCTRL_ONDEMAND (_U(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) 274 #define OSCCTRL_XOSCCTRL_GAIN_Pos 8 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Gain */ 275 #define OSCCTRL_XOSCCTRL_GAIN_Msk (_U(0x7) << OSCCTRL_XOSCCTRL_GAIN_Pos) 276 #define OSCCTRL_XOSCCTRL_GAIN(value) (OSCCTRL_XOSCCTRL_GAIN_Msk & ((value) << OSCCTRL_XOSCCTRL_GAIN_Pos)) 277 #define OSCCTRL_XOSCCTRL_AMPGC_Pos 11 /**< \brief (OSCCTRL_XOSCCTRL) Automatic Amplitude Gain Control */ 278 #define OSCCTRL_XOSCCTRL_AMPGC (_U(0x1) << OSCCTRL_XOSCCTRL_AMPGC_Pos) 279 #define OSCCTRL_XOSCCTRL_STARTUP_Pos 12 /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */ 280 #define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos) 281 #define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos)) 282 #define OSCCTRL_XOSCCTRL_MASK _U(0xFFC6) /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */ 283 284 /* -------- OSCCTRL_OSC16MCTRL : (OSCCTRL Offset: 0x14) (R/W 8) 16MHz Internal Oscillator (OSC16M) Control -------- */ 285 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 286 typedef union { 287 struct { 288 uint8_t :1; /*!< bit: 0 Reserved */ 289 uint8_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 290 uint8_t FSEL:2; /*!< bit: 2.. 3 Oscillator Frequency Select */ 291 uint8_t :2; /*!< bit: 4.. 5 Reserved */ 292 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 293 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 294 } bit; /*!< Structure used for bit access */ 295 uint8_t reg; /*!< Type used for register access */ 296 } OSCCTRL_OSC16MCTRL_Type; 297 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 298 299 #define OSCCTRL_OSC16MCTRL_OFFSET 0x14 /**< \brief (OSCCTRL_OSC16MCTRL offset) 16MHz Internal Oscillator (OSC16M) Control */ 300 #define OSCCTRL_OSC16MCTRL_RESETVALUE _U(0x82) /**< \brief (OSCCTRL_OSC16MCTRL reset_value) 16MHz Internal Oscillator (OSC16M) Control */ 301 302 #define OSCCTRL_OSC16MCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_OSC16MCTRL) Oscillator Enable */ 303 #define OSCCTRL_OSC16MCTRL_ENABLE (_U(0x1) << OSCCTRL_OSC16MCTRL_ENABLE_Pos) 304 #define OSCCTRL_OSC16MCTRL_FSEL_Pos 2 /**< \brief (OSCCTRL_OSC16MCTRL) Oscillator Frequency Select */ 305 #define OSCCTRL_OSC16MCTRL_FSEL_Msk (_U(0x3) << OSCCTRL_OSC16MCTRL_FSEL_Pos) 306 #define OSCCTRL_OSC16MCTRL_FSEL(value) (OSCCTRL_OSC16MCTRL_FSEL_Msk & ((value) << OSCCTRL_OSC16MCTRL_FSEL_Pos)) 307 #define OSCCTRL_OSC16MCTRL_FSEL_4_Val _U(0x0) /**< \brief (OSCCTRL_OSC16MCTRL) 4MHz */ 308 #define OSCCTRL_OSC16MCTRL_FSEL_8_Val _U(0x1) /**< \brief (OSCCTRL_OSC16MCTRL) 8MHz */ 309 #define OSCCTRL_OSC16MCTRL_FSEL_12_Val _U(0x2) /**< \brief (OSCCTRL_OSC16MCTRL) 12MHz */ 310 #define OSCCTRL_OSC16MCTRL_FSEL_16_Val _U(0x3) /**< \brief (OSCCTRL_OSC16MCTRL) 16MHz */ 311 #define OSCCTRL_OSC16MCTRL_FSEL_4 (OSCCTRL_OSC16MCTRL_FSEL_4_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) 312 #define OSCCTRL_OSC16MCTRL_FSEL_8 (OSCCTRL_OSC16MCTRL_FSEL_8_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) 313 #define OSCCTRL_OSC16MCTRL_FSEL_12 (OSCCTRL_OSC16MCTRL_FSEL_12_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) 314 #define OSCCTRL_OSC16MCTRL_FSEL_16 (OSCCTRL_OSC16MCTRL_FSEL_16_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) 315 #define OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_OSC16MCTRL) Run in Standby */ 316 #define OSCCTRL_OSC16MCTRL_RUNSTDBY (_U(0x1) << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos) 317 #define OSCCTRL_OSC16MCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_OSC16MCTRL) On Demand Control */ 318 #define OSCCTRL_OSC16MCTRL_ONDEMAND (_U(0x1) << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos) 319 #define OSCCTRL_OSC16MCTRL_MASK _U(0xCE) /**< \brief (OSCCTRL_OSC16MCTRL) MASK Register */ 320 321 /* -------- OSCCTRL_DFLLCTRL : (OSCCTRL Offset: 0x18) (R/W 16) DFLL48M Control -------- */ 322 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 323 typedef union { 324 struct { 325 uint16_t :1; /*!< bit: 0 Reserved */ 326 uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ 327 uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ 328 uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ 329 uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ 330 uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ 331 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 332 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 333 uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ 334 uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ 335 uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ 336 uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ 337 uint16_t :4; /*!< bit: 12..15 Reserved */ 338 } bit; /*!< Structure used for bit access */ 339 uint16_t reg; /*!< Type used for register access */ 340 } OSCCTRL_DFLLCTRL_Type; 341 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 342 343 #define OSCCTRL_DFLLCTRL_OFFSET 0x18 /**< \brief (OSCCTRL_DFLLCTRL offset) DFLL48M Control */ 344 #define OSCCTRL_DFLLCTRL_RESETVALUE _U(0x0080) /**< \brief (OSCCTRL_DFLLCTRL reset_value) DFLL48M Control */ 345 346 #define OSCCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRL) DFLL Enable */ 347 #define OSCCTRL_DFLLCTRL_ENABLE (_U(0x1) << OSCCTRL_DFLLCTRL_ENABLE_Pos) 348 #define OSCCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (OSCCTRL_DFLLCTRL) Operating Mode Selection */ 349 #define OSCCTRL_DFLLCTRL_MODE (_U(0x1) << OSCCTRL_DFLLCTRL_MODE_Pos) 350 #define OSCCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (OSCCTRL_DFLLCTRL) Stable DFLL Frequency */ 351 #define OSCCTRL_DFLLCTRL_STABLE (_U(0x1) << OSCCTRL_DFLLCTRL_STABLE_Pos) 352 #define OSCCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (OSCCTRL_DFLLCTRL) Lose Lock After Wake */ 353 #define OSCCTRL_DFLLCTRL_LLAW (_U(0x1) << OSCCTRL_DFLLCTRL_LLAW_Pos) 354 #define OSCCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (OSCCTRL_DFLLCTRL) USB Clock Recovery Mode */ 355 #define OSCCTRL_DFLLCTRL_USBCRM (_U(0x1) << OSCCTRL_DFLLCTRL_USBCRM_Pos) 356 #define OSCCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DFLLCTRL) Run in Standby */ 357 #define OSCCTRL_DFLLCTRL_RUNSTDBY (_U(0x1) << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos) 358 #define OSCCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DFLLCTRL) On Demand Control */ 359 #define OSCCTRL_DFLLCTRL_ONDEMAND (_U(0x1) << OSCCTRL_DFLLCTRL_ONDEMAND_Pos) 360 #define OSCCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (OSCCTRL_DFLLCTRL) Chill Cycle Disable */ 361 #define OSCCTRL_DFLLCTRL_CCDIS (_U(0x1) << OSCCTRL_DFLLCTRL_CCDIS_Pos) 362 #define OSCCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (OSCCTRL_DFLLCTRL) Quick Lock Disable */ 363 #define OSCCTRL_DFLLCTRL_QLDIS (_U(0x1) << OSCCTRL_DFLLCTRL_QLDIS_Pos) 364 #define OSCCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (OSCCTRL_DFLLCTRL) Bypass Coarse Lock */ 365 #define OSCCTRL_DFLLCTRL_BPLCKC (_U(0x1) << OSCCTRL_DFLLCTRL_BPLCKC_Pos) 366 #define OSCCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (OSCCTRL_DFLLCTRL) Wait Lock */ 367 #define OSCCTRL_DFLLCTRL_WAITLOCK (_U(0x1) << OSCCTRL_DFLLCTRL_WAITLOCK_Pos) 368 #define OSCCTRL_DFLLCTRL_MASK _U(0x0FFE) /**< \brief (OSCCTRL_DFLLCTRL) MASK Register */ 369 370 /* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x1C) (R/W 32) DFLL48M Value -------- */ 371 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 372 typedef union { 373 struct { 374 uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ 375 uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ 376 uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ 377 } bit; /*!< Structure used for bit access */ 378 uint32_t reg; /*!< Type used for register access */ 379 } OSCCTRL_DFLLVAL_Type; 380 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 381 382 #define OSCCTRL_DFLLVAL_OFFSET 0x1C /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */ 383 #define OSCCTRL_DFLLVAL_RESETVALUE _U(0x00000000) /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */ 384 385 #define OSCCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (OSCCTRL_DFLLVAL) Fine Value */ 386 #define OSCCTRL_DFLLVAL_FINE_Msk (_U(0x3FF) << OSCCTRL_DFLLVAL_FINE_Pos) 387 #define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos)) 388 #define OSCCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */ 389 #define OSCCTRL_DFLLVAL_COARSE_Msk (_U(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos) 390 #define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos)) 391 #define OSCCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */ 392 #define OSCCTRL_DFLLVAL_DIFF_Msk (_U(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos) 393 #define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos)) 394 #define OSCCTRL_DFLLVAL_MASK _U(0xFFFFFFFF) /**< \brief (OSCCTRL_DFLLVAL) MASK Register */ 395 396 /* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x20) (R/W 32) DFLL48M Multiplier -------- */ 397 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 398 typedef union { 399 struct { 400 uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ 401 uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ 402 uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ 403 } bit; /*!< Structure used for bit access */ 404 uint32_t reg; /*!< Type used for register access */ 405 } OSCCTRL_DFLLMUL_Type; 406 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 407 408 #define OSCCTRL_DFLLMUL_OFFSET 0x20 /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */ 409 #define OSCCTRL_DFLLMUL_RESETVALUE _U(0x00000000) /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */ 410 411 #define OSCCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */ 412 #define OSCCTRL_DFLLMUL_MUL_Msk (_U(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos) 413 #define OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos)) 414 #define OSCCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */ 415 #define OSCCTRL_DFLLMUL_FSTEP_Msk (_U(0x3FF) << OSCCTRL_DFLLMUL_FSTEP_Pos) 416 #define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos)) 417 #define OSCCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */ 418 #define OSCCTRL_DFLLMUL_CSTEP_Msk (_U(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos) 419 #define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos)) 420 #define OSCCTRL_DFLLMUL_MASK _U(0xFFFFFFFF) /**< \brief (OSCCTRL_DFLLMUL) MASK Register */ 421 422 /* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x24) (R/W 8) DFLL48M Synchronization -------- */ 423 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 424 typedef union { 425 struct { 426 uint8_t :7; /*!< bit: 0.. 6 Reserved */ 427 uint8_t READREQ:1; /*!< bit: 7 Read Request */ 428 } bit; /*!< Structure used for bit access */ 429 uint8_t reg; /*!< Type used for register access */ 430 } OSCCTRL_DFLLSYNC_Type; 431 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 432 433 #define OSCCTRL_DFLLSYNC_OFFSET 0x24 /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */ 434 #define OSCCTRL_DFLLSYNC_RESETVALUE _U(0x00) /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */ 435 436 #define OSCCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (OSCCTRL_DFLLSYNC) Read Request */ 437 #define OSCCTRL_DFLLSYNC_READREQ (_U(0x1) << OSCCTRL_DFLLSYNC_READREQ_Pos) 438 #define OSCCTRL_DFLLSYNC_MASK _U(0x80) /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */ 439 440 /* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x28) (R/W 8) DPLL Control -------- */ 441 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 442 typedef union { 443 struct { 444 uint8_t :1; /*!< bit: 0 Reserved */ 445 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 446 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 447 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 448 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand */ 449 } bit; /*!< Structure used for bit access */ 450 uint8_t reg; /*!< Type used for register access */ 451 } OSCCTRL_DPLLCTRLA_Type; 452 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 453 454 #define OSCCTRL_DPLLCTRLA_OFFSET 0x28 /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control */ 455 #define OSCCTRL_DPLLCTRLA_RESETVALUE _U(0x80) /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control */ 456 457 #define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLCTRLA) Enable */ 458 #define OSCCTRL_DPLLCTRLA_ENABLE (_U(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos) 459 #define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */ 460 #define OSCCTRL_DPLLCTRLA_RUNSTDBY (_U(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) 461 #define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DPLLCTRLA) On Demand */ 462 #define OSCCTRL_DPLLCTRLA_ONDEMAND (_U(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) 463 #define OSCCTRL_DPLLCTRLA_MASK _U(0xC2) /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */ 464 465 /* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x2C) (R/W 32) DPLL Ratio Control -------- */ 466 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 467 typedef union { 468 struct { 469 uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ 470 uint32_t :4; /*!< bit: 12..15 Reserved */ 471 uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ 472 uint32_t :12; /*!< bit: 20..31 Reserved */ 473 } bit; /*!< Structure used for bit access */ 474 uint32_t reg; /*!< Type used for register access */ 475 } OSCCTRL_DPLLRATIO_Type; 476 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 477 478 #define OSCCTRL_DPLLRATIO_OFFSET 0x2C /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */ 479 #define OSCCTRL_DPLLRATIO_RESETVALUE _U(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */ 480 481 #define OSCCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */ 482 #define OSCCTRL_DPLLRATIO_LDR_Msk (_U(0xFFF) << OSCCTRL_DPLLRATIO_LDR_Pos) 483 #define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos)) 484 #define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */ 485 #define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U(0xF) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos) 486 #define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)) 487 #define OSCCTRL_DPLLRATIO_MASK _U(0x000F0FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */ 488 489 /* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x30) (R/W 32) Digital Core Configuration -------- */ 490 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 491 typedef union { 492 struct { 493 uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ 494 uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ 495 uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ 496 uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ 497 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 498 uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ 499 uint32_t :1; /*!< bit: 11 Reserved */ 500 uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ 501 uint32_t :3; /*!< bit: 13..15 Reserved */ 502 uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ 503 uint32_t :5; /*!< bit: 27..31 Reserved */ 504 } bit; /*!< Structure used for bit access */ 505 uint32_t reg; /*!< Type used for register access */ 506 } OSCCTRL_DPLLCTRLB_Type; 507 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 508 509 #define OSCCTRL_DPLLCTRLB_OFFSET 0x30 /**< \brief (OSCCTRL_DPLLCTRLB offset) Digital Core Configuration */ 510 #define OSCCTRL_DPLLCTRLB_RESETVALUE _U(0x00000000) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) Digital Core Configuration */ 511 512 #define OSCCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */ 513 #define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U(0x3) << OSCCTRL_DPLLCTRLB_FILTER_Pos) 514 #define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos)) 515 #define OSCCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (OSCCTRL_DPLLCTRLB) Low-Power Enable */ 516 #define OSCCTRL_DPLLCTRLB_LPEN (_U(0x1) << OSCCTRL_DPLLCTRLB_LPEN_Pos) 517 #define OSCCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */ 518 #define OSCCTRL_DPLLCTRLB_WUF (_U(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos) 519 #define OSCCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */ 520 #define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U(0x3) << OSCCTRL_DPLLCTRLB_REFCLK_Pos) 521 #define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)) 522 #define OSCCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */ 523 #define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos) 524 #define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos)) 525 #define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */ 526 #define OSCCTRL_DPLLCTRLB_LBYPASS (_U(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) 527 #define OSCCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */ 528 #define OSCCTRL_DPLLCTRLB_DIV_Msk (_U(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos) 529 #define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos)) 530 #define OSCCTRL_DPLLCTRLB_MASK _U(0x07FF173F) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */ 531 532 /* -------- OSCCTRL_DPLLPRESC : (OSCCTRL Offset: 0x34) (R/W 8) DPLL Prescaler -------- */ 533 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 534 typedef union { 535 struct { 536 uint8_t PRESC:2; /*!< bit: 0.. 1 Output Clock Prescaler */ 537 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 538 } bit; /*!< Structure used for bit access */ 539 uint8_t reg; /*!< Type used for register access */ 540 } OSCCTRL_DPLLPRESC_Type; 541 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 542 543 #define OSCCTRL_DPLLPRESC_OFFSET 0x34 /**< \brief (OSCCTRL_DPLLPRESC offset) DPLL Prescaler */ 544 #define OSCCTRL_DPLLPRESC_RESETVALUE _U(0x00) /**< \brief (OSCCTRL_DPLLPRESC reset_value) DPLL Prescaler */ 545 546 #define OSCCTRL_DPLLPRESC_PRESC_Pos 0 /**< \brief (OSCCTRL_DPLLPRESC) Output Clock Prescaler */ 547 #define OSCCTRL_DPLLPRESC_PRESC_Msk (_U(0x3) << OSCCTRL_DPLLPRESC_PRESC_Pos) 548 #define OSCCTRL_DPLLPRESC_PRESC(value) (OSCCTRL_DPLLPRESC_PRESC_Msk & ((value) << OSCCTRL_DPLLPRESC_PRESC_Pos)) 549 #define OSCCTRL_DPLLPRESC_PRESC_DIV1_Val _U(0x0) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 1 */ 550 #define OSCCTRL_DPLLPRESC_PRESC_DIV2_Val _U(0x1) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 2 */ 551 #define OSCCTRL_DPLLPRESC_PRESC_DIV4_Val _U(0x2) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 4 */ 552 #define OSCCTRL_DPLLPRESC_PRESC_DIV1 (OSCCTRL_DPLLPRESC_PRESC_DIV1_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) 553 #define OSCCTRL_DPLLPRESC_PRESC_DIV2 (OSCCTRL_DPLLPRESC_PRESC_DIV2_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) 554 #define OSCCTRL_DPLLPRESC_PRESC_DIV4 (OSCCTRL_DPLLPRESC_PRESC_DIV4_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) 555 #define OSCCTRL_DPLLPRESC_MASK _U(0x03) /**< \brief (OSCCTRL_DPLLPRESC) MASK Register */ 556 557 /* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x38) (R/ 8) DPLL Synchronization Busy -------- */ 558 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 559 typedef union { 560 struct { 561 uint8_t :1; /*!< bit: 0 Reserved */ 562 uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */ 563 uint8_t DPLLRATIO:1; /*!< bit: 2 DPLL Ratio Synchronization Status */ 564 uint8_t DPLLPRESC:1; /*!< bit: 3 DPLL Prescaler Synchronization Status */ 565 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 566 } bit; /*!< Structure used for bit access */ 567 uint8_t reg; /*!< Type used for register access */ 568 } OSCCTRL_DPLLSYNCBUSY_Type; 569 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 570 571 #define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x38 /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */ 572 #define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U(0x00) /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */ 573 574 #define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */ 575 #define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos) 576 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Ratio Synchronization Status */ 577 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos) 578 #define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos 3 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Prescaler Synchronization Status */ 579 #define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC (_U(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos) 580 #define OSCCTRL_DPLLSYNCBUSY_MASK _U(0x0E) /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */ 581 582 /* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x3C) (R/ 8) DPLL Status -------- */ 583 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 584 typedef union { 585 struct { 586 uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ 587 uint8_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */ 588 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 589 } bit; /*!< Structure used for bit access */ 590 uint8_t reg; /*!< Type used for register access */ 591 } OSCCTRL_DPLLSTATUS_Type; 592 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 593 594 #define OSCCTRL_DPLLSTATUS_OFFSET 0x3C /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */ 595 #define OSCCTRL_DPLLSTATUS_RESETVALUE _U(0x00) /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */ 596 597 #define OSCCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */ 598 #define OSCCTRL_DPLLSTATUS_LOCK (_U(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos) 599 #define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */ 600 #define OSCCTRL_DPLLSTATUS_CLKRDY (_U(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos) 601 #define OSCCTRL_DPLLSTATUS_MASK _U(0x03) /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */ 602 603 /** \brief OSCCTRL hardware registers */ 604 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 605 typedef struct { 606 __IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 607 __IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ 608 __IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 609 __I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ 610 __IO OSCCTRL_XOSCCTRL_Type XOSCCTRL; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ 611 RoReg8 Reserved1[0x2]; 612 __IO OSCCTRL_OSC16MCTRL_Type OSC16MCTRL; /**< \brief Offset: 0x14 (R/W 8) 16MHz Internal Oscillator (OSC16M) Control */ 613 RoReg8 Reserved2[0x3]; 614 __IO OSCCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x18 (R/W 16) DFLL48M Control */ 615 RoReg8 Reserved3[0x2]; 616 __IO OSCCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x1C (R/W 32) DFLL48M Value */ 617 __IO OSCCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x20 (R/W 32) DFLL48M Multiplier */ 618 __IO OSCCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x24 (R/W 8) DFLL48M Synchronization */ 619 RoReg8 Reserved4[0x3]; 620 __IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x28 (R/W 8) DPLL Control */ 621 RoReg8 Reserved5[0x3]; 622 __IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x2C (R/W 32) DPLL Ratio Control */ 623 __IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x30 (R/W 32) Digital Core Configuration */ 624 __IO OSCCTRL_DPLLPRESC_Type DPLLPRESC; /**< \brief Offset: 0x34 (R/W 8) DPLL Prescaler */ 625 RoReg8 Reserved6[0x3]; 626 __I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x38 (R/ 8) DPLL Synchronization Busy */ 627 RoReg8 Reserved7[0x3]; 628 __I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x3C (R/ 8) DPLL Status */ 629 } Oscctrl; 630 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 631 632 /*@}*/ 633 634 #endif /* _SAML21_OSCCTRL_COMPONENT_ */ 635
