Home
last modified time | relevance | path

Searched refs:RCC_PLLCFGR_PLLR (Results 1 – 4 of 4) sorted by relevance

/loramac-node-3.6.0-3.5.0/src/boards/NucleoL476/cmsis/
Dsystem_stm32l4xx.c325 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; in SystemCoreClockUpdate()
Dstm32l476xx.h10802 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk macro
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_rcc.c1407 pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; in HAL_RCC_GetSysClockFreq()
1592 …RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos)… in HAL_RCC_GetOscConfig()
1837 pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; in RCC_GetSysClockFreqFromPLLSource()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_rcc.h935 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for…
3815 …DIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, in LL_RCC_PLL_ConfigDomain_SYS()
4105 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); in LL_RCC_PLL_GetR()