RCC_CFGR_PPRE1_DIV8 (reference) in projects: loramac-node-3.6.0-3.5.0

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Searched refs:RCC_CFGR_PPRE1_DIV8 (Results 1 – 14 of 14) sorted by relevance

/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
D	stm32l1xx_ll_rcc.h	`269 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /`
D	stm32l1xx_hal_rcc.h	`496 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /`
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
D	stm32l0xx_ll_rcc.h	`309 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /`
D	stm32l0xx_hal_rcc.h	`506 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /`
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
D	stm32l4xx_ll_rcc.h	`332 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /`
D	stm32l4xx_hal_rcc.h	`492 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /`
/loramac-node-3.6.0-3.5.0/src/boards/SKiM881AXL/cmsis/
D	stm32l081xx.h	`3556 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by… macro`
/loramac-node-3.6.0-3.5.0/src/boards/B-L072Z-LRWAN1/cmsis/
D	stm32l072xx.h	`3828 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by… macro`
/loramac-node-3.6.0-3.5.0/src/boards/SKiM980A/cmsis/
D	stm32l151xba.h	`3848 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by… macro`
/loramac-node-3.6.0-3.5.0/src/boards/NucleoL073/cmsis/
D	stm32l073xx.h	`3970 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by… macro`
/loramac-node-3.6.0-3.5.0/src/boards/SKiM880B/cmsis/
D	stm32l151xba.h	`3848 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by… macro`
/loramac-node-3.6.0-3.5.0/src/boards/NAMote72/cmsis/
D	stm32l152xc.h	`4241 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by… macro`
/loramac-node-3.6.0-3.5.0/src/boards/NucleoL152/cmsis/
D	stm32l152xe.h	`4311 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by… macro`
/loramac-node-3.6.0-3.5.0/src/boards/NucleoL476/cmsis/
D	stm32l476xx.h	`10698 #define RCC_CFGR_PPRE1_DIV8 (0x00000600UL) /*!< HCLK divided by… macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
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babblesim_ext_2G4_libPhyComv1-3.7.0
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babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
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