1 /** 2 * \file 3 * 4 * \brief Component description for PORT 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_PORT_COMPONENT_ 30 #define _SAML21_PORT_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR PORT */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_PORT Port Module */ 36 /*@{*/ 37 38 #define PORT_U2210 39 #define REV_PORT 0x201 40 41 /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */ 46 } bit; /*!< Structure used for bit access */ 47 uint32_t reg; /*!< Type used for register access */ 48 } PORT_DIR_Type; 49 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 50 51 #define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */ 52 #define PORT_DIR_RESETVALUE _U(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */ 53 54 #define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */ 55 #define PORT_DIR_DIR_Msk (_U(0xFFFFFFFF) << PORT_DIR_DIR_Pos) 56 #define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)) 57 #define PORT_DIR_MASK _U(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */ 58 59 /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */ 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 61 typedef union { 62 struct { 63 uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */ 64 } bit; /*!< Structure used for bit access */ 65 uint32_t reg; /*!< Type used for register access */ 66 } PORT_DIRCLR_Type; 67 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 68 69 #define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */ 70 #define PORT_DIRCLR_RESETVALUE _U(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */ 71 72 #define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */ 73 #define PORT_DIRCLR_DIRCLR_Msk (_U(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos) 74 #define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)) 75 #define PORT_DIRCLR_MASK _U(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */ 76 77 /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */ 78 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 79 typedef union { 80 struct { 81 uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */ 82 } bit; /*!< Structure used for bit access */ 83 uint32_t reg; /*!< Type used for register access */ 84 } PORT_DIRSET_Type; 85 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 86 87 #define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */ 88 #define PORT_DIRSET_RESETVALUE _U(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */ 89 90 #define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */ 91 #define PORT_DIRSET_DIRSET_Msk (_U(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos) 92 #define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)) 93 #define PORT_DIRSET_MASK _U(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */ 94 95 /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */ 96 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 97 typedef union { 98 struct { 99 uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */ 100 } bit; /*!< Structure used for bit access */ 101 uint32_t reg; /*!< Type used for register access */ 102 } PORT_DIRTGL_Type; 103 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 #define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */ 106 #define PORT_DIRTGL_RESETVALUE _U(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */ 107 108 #define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */ 109 #define PORT_DIRTGL_DIRTGL_Msk (_U(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos) 110 #define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)) 111 #define PORT_DIRTGL_MASK _U(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */ 112 113 /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */ 114 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 115 typedef union { 116 struct { 117 uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */ 118 } bit; /*!< Structure used for bit access */ 119 uint32_t reg; /*!< Type used for register access */ 120 } PORT_OUT_Type; 121 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 122 123 #define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */ 124 #define PORT_OUT_RESETVALUE _U(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */ 125 126 #define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */ 127 #define PORT_OUT_OUT_Msk (_U(0xFFFFFFFF) << PORT_OUT_OUT_Pos) 128 #define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)) 129 #define PORT_OUT_MASK _U(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */ 130 131 /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */ 132 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 133 typedef union { 134 struct { 135 uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */ 136 } bit; /*!< Structure used for bit access */ 137 uint32_t reg; /*!< Type used for register access */ 138 } PORT_OUTCLR_Type; 139 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 140 141 #define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */ 142 #define PORT_OUTCLR_RESETVALUE _U(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */ 143 144 #define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */ 145 #define PORT_OUTCLR_OUTCLR_Msk (_U(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos) 146 #define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)) 147 #define PORT_OUTCLR_MASK _U(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */ 148 149 /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */ 150 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 151 typedef union { 152 struct { 153 uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */ 154 } bit; /*!< Structure used for bit access */ 155 uint32_t reg; /*!< Type used for register access */ 156 } PORT_OUTSET_Type; 157 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 158 159 #define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */ 160 #define PORT_OUTSET_RESETVALUE _U(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */ 161 162 #define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */ 163 #define PORT_OUTSET_OUTSET_Msk (_U(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos) 164 #define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)) 165 #define PORT_OUTSET_MASK _U(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */ 166 167 /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */ 168 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 169 typedef union { 170 struct { 171 uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */ 172 } bit; /*!< Structure used for bit access */ 173 uint32_t reg; /*!< Type used for register access */ 174 } PORT_OUTTGL_Type; 175 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 176 177 #define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */ 178 #define PORT_OUTTGL_RESETVALUE _U(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */ 179 180 #define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */ 181 #define PORT_OUTTGL_OUTTGL_Msk (_U(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos) 182 #define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)) 183 #define PORT_OUTTGL_MASK _U(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */ 184 185 /* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */ 186 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 187 typedef union { 188 struct { 189 uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */ 190 } bit; /*!< Structure used for bit access */ 191 uint32_t reg; /*!< Type used for register access */ 192 } PORT_IN_Type; 193 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 194 195 #define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */ 196 #define PORT_IN_RESETVALUE _U(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */ 197 198 #define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */ 199 #define PORT_IN_IN_Msk (_U(0xFFFFFFFF) << PORT_IN_IN_Pos) 200 #define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)) 201 #define PORT_IN_MASK _U(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */ 202 203 /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */ 204 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 205 typedef union { 206 struct { 207 uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ 208 } bit; /*!< Structure used for bit access */ 209 uint32_t reg; /*!< Type used for register access */ 210 } PORT_CTRL_Type; 211 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 212 213 #define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */ 214 #define PORT_CTRL_RESETVALUE _U(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */ 215 216 #define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */ 217 #define PORT_CTRL_SAMPLING_Msk (_U(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos) 218 #define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)) 219 #define PORT_CTRL_MASK _U(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */ 220 221 /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */ 222 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 223 typedef union { 224 struct { 225 uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ 226 uint32_t PMUXEN:1; /*!< bit: 16 Select Peripheral Multiplexer */ 227 uint32_t INEN:1; /*!< bit: 17 Input Enable */ 228 uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ 229 uint32_t :3; /*!< bit: 19..21 Reserved */ 230 uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ 231 uint32_t :1; /*!< bit: 23 Reserved */ 232 uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing Template */ 233 uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX Registers */ 234 uint32_t :1; /*!< bit: 29 Reserved */ 235 uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG Registers */ 236 uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ 237 } bit; /*!< Structure used for bit access */ 238 uint32_t reg; /*!< Type used for register access */ 239 } PORT_WRCONFIG_Type; 240 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 241 242 #define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */ 243 #define PORT_WRCONFIG_RESETVALUE _U(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */ 244 245 #define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */ 246 #define PORT_WRCONFIG_PINMASK_Msk (_U(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos) 247 #define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)) 248 #define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Select Peripheral Multiplexer */ 249 #define PORT_WRCONFIG_PMUXEN (_U(0x1) << PORT_WRCONFIG_PMUXEN_Pos) 250 #define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */ 251 #define PORT_WRCONFIG_INEN (_U(0x1) << PORT_WRCONFIG_INEN_Pos) 252 #define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */ 253 #define PORT_WRCONFIG_PULLEN (_U(0x1) << PORT_WRCONFIG_PULLEN_Pos) 254 #define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */ 255 #define PORT_WRCONFIG_DRVSTR (_U(0x1) << PORT_WRCONFIG_DRVSTR_Pos) 256 #define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing Template */ 257 #define PORT_WRCONFIG_PMUX_Msk (_U(0xF) << PORT_WRCONFIG_PMUX_Pos) 258 #define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)) 259 #define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX Registers */ 260 #define PORT_WRCONFIG_WRPMUX (_U(0x1) << PORT_WRCONFIG_WRPMUX_Pos) 261 #define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG Registers */ 262 #define PORT_WRCONFIG_WRPINCFG (_U(0x1) << PORT_WRCONFIG_WRPINCFG_Pos) 263 #define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */ 264 #define PORT_WRCONFIG_HWSEL (_U(0x1) << PORT_WRCONFIG_HWSEL_Pos) 265 #define PORT_WRCONFIG_MASK _U(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */ 266 267 /* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */ 268 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 269 typedef union { 270 struct { 271 uint32_t PID0:5; /*!< bit: 0.. 4 Port Event Pin Identifier 0 */ 272 uint32_t EVACT0:2; /*!< bit: 5.. 6 Port Event Action 0 */ 273 uint32_t PORTEI0:1; /*!< bit: 7 Port Event Enable Input 0 */ 274 uint32_t PID1:5; /*!< bit: 8..12 Port Event Pin Identifier 1 */ 275 uint32_t EVACT1:2; /*!< bit: 13..14 Port Event Action 1 */ 276 uint32_t PORTEI1:1; /*!< bit: 15 Port Event Enable Input 1 */ 277 uint32_t PID2:5; /*!< bit: 16..20 Port Event Pin Identifier 2 */ 278 uint32_t EVACT2:2; /*!< bit: 21..22 Port Event Action 2 */ 279 uint32_t PORTEI2:1; /*!< bit: 23 Port Event Enable Input 2 */ 280 uint32_t PID3:5; /*!< bit: 24..28 Port Event Pin Identifier 3 */ 281 uint32_t EVACT3:2; /*!< bit: 29..30 Port Event Action 3 */ 282 uint32_t PORTEI3:1; /*!< bit: 31 Port Event Enable Input 3 */ 283 } bit; /*!< Structure used for bit access */ 284 uint32_t reg; /*!< Type used for register access */ 285 } PORT_EVCTRL_Type; 286 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 287 288 #define PORT_EVCTRL_OFFSET 0x2C /**< \brief (PORT_EVCTRL offset) Event Input Control */ 289 #define PORT_EVCTRL_RESETVALUE _U(0x00000000) /**< \brief (PORT_EVCTRL reset_value) Event Input Control */ 290 291 #define PORT_EVCTRL_PID0_Pos 0 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 0 */ 292 #define PORT_EVCTRL_PID0_Msk (_U(0x1F) << PORT_EVCTRL_PID0_Pos) 293 #define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos)) 294 #define PORT_EVCTRL_EVACT0_Pos 5 /**< \brief (PORT_EVCTRL) Port Event Action 0 */ 295 #define PORT_EVCTRL_EVACT0_Msk (_U(0x3) << PORT_EVCTRL_EVACT0_Pos) 296 #define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos)) 297 #define PORT_EVCTRL_PORTEI0_Pos 7 /**< \brief (PORT_EVCTRL) Port Event Enable Input 0 */ 298 #define PORT_EVCTRL_PORTEI0 (_U(0x1) << PORT_EVCTRL_PORTEI0_Pos) 299 #define PORT_EVCTRL_PID1_Pos 8 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 1 */ 300 #define PORT_EVCTRL_PID1_Msk (_U(0x1F) << PORT_EVCTRL_PID1_Pos) 301 #define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos)) 302 #define PORT_EVCTRL_EVACT1_Pos 13 /**< \brief (PORT_EVCTRL) Port Event Action 1 */ 303 #define PORT_EVCTRL_EVACT1_Msk (_U(0x3) << PORT_EVCTRL_EVACT1_Pos) 304 #define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos)) 305 #define PORT_EVCTRL_PORTEI1_Pos 15 /**< \brief (PORT_EVCTRL) Port Event Enable Input 1 */ 306 #define PORT_EVCTRL_PORTEI1 (_U(0x1) << PORT_EVCTRL_PORTEI1_Pos) 307 #define PORT_EVCTRL_PID2_Pos 16 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 2 */ 308 #define PORT_EVCTRL_PID2_Msk (_U(0x1F) << PORT_EVCTRL_PID2_Pos) 309 #define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos)) 310 #define PORT_EVCTRL_EVACT2_Pos 21 /**< \brief (PORT_EVCTRL) Port Event Action 2 */ 311 #define PORT_EVCTRL_EVACT2_Msk (_U(0x3) << PORT_EVCTRL_EVACT2_Pos) 312 #define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos)) 313 #define PORT_EVCTRL_PORTEI2_Pos 23 /**< \brief (PORT_EVCTRL) Port Event Enable Input 2 */ 314 #define PORT_EVCTRL_PORTEI2 (_U(0x1) << PORT_EVCTRL_PORTEI2_Pos) 315 #define PORT_EVCTRL_PID3_Pos 24 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 3 */ 316 #define PORT_EVCTRL_PID3_Msk (_U(0x1F) << PORT_EVCTRL_PID3_Pos) 317 #define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos)) 318 #define PORT_EVCTRL_EVACT3_Pos 29 /**< \brief (PORT_EVCTRL) Port Event Action 3 */ 319 #define PORT_EVCTRL_EVACT3_Msk (_U(0x3) << PORT_EVCTRL_EVACT3_Pos) 320 #define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos)) 321 #define PORT_EVCTRL_PORTEI3_Pos 31 /**< \brief (PORT_EVCTRL) Port Event Enable Input 3 */ 322 #define PORT_EVCTRL_PORTEI3 (_U(0x1) << PORT_EVCTRL_PORTEI3_Pos) 323 #define PORT_EVCTRL_MASK _U(0xFFFFFFFF) /**< \brief (PORT_EVCTRL) MASK Register */ 324 325 /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */ 326 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 327 typedef union { 328 struct { 329 uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */ 330 uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */ 331 } bit; /*!< Structure used for bit access */ 332 uint8_t reg; /*!< Type used for register access */ 333 } PORT_PMUX_Type; 334 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 335 336 #define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */ 337 #define PORT_PMUX_RESETVALUE _U(0x00) /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */ 338 339 #define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */ 340 #define PORT_PMUX_PMUXE_Msk (_U(0xF) << PORT_PMUX_PMUXE_Pos) 341 #define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)) 342 #define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */ 343 #define PORT_PMUX_PMUXO_Msk (_U(0xF) << PORT_PMUX_PMUXO_Pos) 344 #define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)) 345 #define PORT_PMUX_MASK _U(0xFF) /**< \brief (PORT_PMUX) MASK Register */ 346 347 /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */ 348 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 349 typedef union { 350 struct { 351 uint8_t PMUXEN:1; /*!< bit: 0 Select Peripheral Multiplexer */ 352 uint8_t INEN:1; /*!< bit: 1 Input Enable */ 353 uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ 354 uint8_t :3; /*!< bit: 3.. 5 Reserved */ 355 uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ 356 uint8_t :1; /*!< bit: 7 Reserved */ 357 } bit; /*!< Structure used for bit access */ 358 uint8_t reg; /*!< Type used for register access */ 359 } PORT_PINCFG_Type; 360 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 361 362 #define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */ 363 #define PORT_PINCFG_RESETVALUE _U(0x00) /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */ 364 365 #define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Select Peripheral Multiplexer */ 366 #define PORT_PINCFG_PMUXEN (_U(0x1) << PORT_PINCFG_PMUXEN_Pos) 367 #define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */ 368 #define PORT_PINCFG_INEN (_U(0x1) << PORT_PINCFG_INEN_Pos) 369 #define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */ 370 #define PORT_PINCFG_PULLEN (_U(0x1) << PORT_PINCFG_PULLEN_Pos) 371 #define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */ 372 #define PORT_PINCFG_DRVSTR (_U(0x1) << PORT_PINCFG_DRVSTR_Pos) 373 #define PORT_PINCFG_MASK _U(0x47) /**< \brief (PORT_PINCFG) MASK Register */ 374 375 /** \brief PortGroup hardware registers */ 376 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 377 typedef struct { 378 __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ 379 __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ 380 __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ 381 __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ 382 __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ 383 __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ 384 __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ 385 __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ 386 __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ 387 __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ 388 __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ 389 __IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control */ 390 __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ 391 __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ 392 RoReg8 Reserved1[0x20]; 393 } PortGroup; 394 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 395 396 /** \brief PORT hardware registers */ 397 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 398 typedef struct { 399 PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ 400 } Port; 401 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 402 403 /*@}*/ 404 405 #endif /* _SAML21_PORT_COMPONENT_ */ 406
