Home
last modified time | relevance | path

Searched refs:MPU (Results 1 – 20 of 20) sorted by relevance

/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_ll_cortex.h509 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); in LL_MPU_Enable()
526 WRITE_REG(MPU->CTRL, 0U); in LL_MPU_Disable()
536 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); in LL_MPU_IsEnabled()
556 WRITE_REG(MPU->RNR, Region); in LL_MPU_EnableRegion()
558 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); in LL_MPU_EnableRegion()
602 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegion()
604 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); in LL_MPU_ConfigRegion()
606 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); in LL_MPU_ConfigRegion()
627 WRITE_REG(MPU->RNR, Region); in LL_MPU_DisableRegion()
629 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); in LL_MPU_DisableRegion()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_ll_cortex.h509 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); in LL_MPU_Enable()
526 WRITE_REG(MPU->CTRL, 0U); in LL_MPU_Disable()
536 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); in LL_MPU_IsEnabled()
556 WRITE_REG(MPU->RNR, Region); in LL_MPU_EnableRegion()
558 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); in LL_MPU_EnableRegion()
602 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegion()
604 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); in LL_MPU_ConfigRegion()
606 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); in LL_MPU_ConfigRegion()
627 WRITE_REG(MPU->RNR, Region); in LL_MPU_DisableRegion()
629 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); in LL_MPU_DisableRegion()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_ll_cortex.h460 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); in LL_MPU_Enable()
477 WRITE_REG(MPU->CTRL, 0U); in LL_MPU_Disable()
487 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); in LL_MPU_IsEnabled()
507 WRITE_REG(MPU->RNR, Region); in LL_MPU_EnableRegion()
509 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); in LL_MPU_EnableRegion()
553 WRITE_REG(MPU->RNR, Region); in LL_MPU_ConfigRegion()
555 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); in LL_MPU_ConfigRegion()
557 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); in LL_MPU_ConfigRegion()
578 WRITE_REG(MPU->RNR, Region); in LL_MPU_DisableRegion()
580 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); in LL_MPU_DisableRegion()
Dstm32l0xx_hal_cortex.h273 MPU->CTRL = 0; in HAL_MPU_Disable()
291 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; in HAL_MPU_Enable()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_cortex.c310 MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); in HAL_MPU_Enable()
327 MPU->CTRL = 0; in HAL_MPU_Disable()
343 MPU->RNR = MPU_Init->Number; in HAL_MPU_ConfigRegion()
357 MPU->RBAR = MPU_Init->BaseAddress; in HAL_MPU_ConfigRegion()
358 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | in HAL_MPU_ConfigRegion()
370 MPU->RBAR = 0x00; in HAL_MPU_ConfigRegion()
371 MPU->RASR = 0x00; in HAL_MPU_ConfigRegion()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_cortex.c449 MPU->CTRL = 0U; in HAL_MPU_Disable()
466 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; in HAL_MPU_Enable()
489 MPU->RNR = MPU_Init->Number; in HAL_MPU_ConfigRegion()
503 MPU->RBAR = MPU_Init->BaseAddress; in HAL_MPU_ConfigRegion()
504 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | in HAL_MPU_ConfigRegion()
516 MPU->RBAR = 0x00; in HAL_MPU_ConfigRegion()
517 MPU->RASR = 0x00; in HAL_MPU_ConfigRegion()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_hal_cortex.c343 MPU->RNR = MPU_Init->Number; in HAL_MPU_ConfigRegion()
357 MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0U; in HAL_MPU_ConfigRegion()
360 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | in HAL_MPU_ConfigRegion()
371 MPU->RBAR = 0x00U; in HAL_MPU_ConfigRegion()
372 MPU->RASR = 0x00U; in HAL_MPU_ConfigRegion()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/saml21/cmsis/
Dcore_cm0plus.h616 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit … macro
Dcore_sc000.h636 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit … macro
Dcore_cm3.h1274 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit … macro
Dcore_sc300.h1254 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit … macro
Dcore_cm4.h1420 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit … macro
Dcore_cm7.h1607 …#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit … macro
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/cmsis/
Dcore_cm0plus.h705 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
Dcore_sc000.h717 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
Dcore_cm3.h1384 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
Dcore_sc300.h1366 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
Dcore_cm4.h1553 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
Dcore_cm7.h1761 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ macro
/loramac-node-3.6.0-3.5.0/src/boards/NucleoL476/cmsis/arm-std/
Dstartup_stm32l476xx.s78 DCD MemManage_Handler ; MPU Fault Handler