1 /** 2 * \file 3 * 4 * \brief Component description for EIC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_EIC_COMPONENT_ 30 #define _SAML21_EIC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR EIC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_EIC External Interrupt Controller */ 36 /*@{*/ 37 38 #define EIC_U2254 39 #define REV_EIC 0x202 40 41 /* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 48 uint8_t CKSEL:1; /*!< bit: 4 Clock Selection */ 49 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } EIC_CTRLA_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define EIC_CTRLA_OFFSET 0x00 /**< \brief (EIC_CTRLA offset) Control */ 56 #define EIC_CTRLA_RESETVALUE _U(0x00) /**< \brief (EIC_CTRLA reset_value) Control */ 57 58 #define EIC_CTRLA_SWRST_Pos 0 /**< \brief (EIC_CTRLA) Software Reset */ 59 #define EIC_CTRLA_SWRST (_U(0x1) << EIC_CTRLA_SWRST_Pos) 60 #define EIC_CTRLA_ENABLE_Pos 1 /**< \brief (EIC_CTRLA) Enable */ 61 #define EIC_CTRLA_ENABLE (_U(0x1) << EIC_CTRLA_ENABLE_Pos) 62 #define EIC_CTRLA_CKSEL_Pos 4 /**< \brief (EIC_CTRLA) Clock Selection */ 63 #define EIC_CTRLA_CKSEL (_U(0x1) << EIC_CTRLA_CKSEL_Pos) 64 #define EIC_CTRLA_MASK _U(0x13) /**< \brief (EIC_CTRLA) MASK Register */ 65 66 /* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) NMI Control -------- */ 67 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 68 typedef union { 69 struct { 70 uint8_t NMISENSE:3; /*!< bit: 0.. 2 NMI Input Sense Configuration */ 71 uint8_t NMIFILTEN:1; /*!< bit: 3 NMI Filter Enable */ 72 uint8_t NMIASYNCH:1; /*!< bit: 4 NMI Asynchronous edge Detection Enable */ 73 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 74 } bit; /*!< Structure used for bit access */ 75 uint8_t reg; /*!< Type used for register access */ 76 } EIC_NMICTRL_Type; 77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 79 #define EIC_NMICTRL_OFFSET 0x01 /**< \brief (EIC_NMICTRL offset) NMI Control */ 80 #define EIC_NMICTRL_RESETVALUE _U(0x00) /**< \brief (EIC_NMICTRL reset_value) NMI Control */ 81 82 #define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) NMI Input Sense Configuration */ 83 #define EIC_NMICTRL_NMISENSE_Msk (_U(0x7) << EIC_NMICTRL_NMISENSE_Pos) 84 #define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos)) 85 #define EIC_NMICTRL_NMISENSE_NONE_Val _U(0x0) /**< \brief (EIC_NMICTRL) No detection */ 86 #define EIC_NMICTRL_NMISENSE_RISE_Val _U(0x1) /**< \brief (EIC_NMICTRL) Rising edge detection */ 87 #define EIC_NMICTRL_NMISENSE_FALL_Val _U(0x2) /**< \brief (EIC_NMICTRL) Falling edge detection */ 88 #define EIC_NMICTRL_NMISENSE_BOTH_Val _U(0x3) /**< \brief (EIC_NMICTRL) Both edges detection */ 89 #define EIC_NMICTRL_NMISENSE_HIGH_Val _U(0x4) /**< \brief (EIC_NMICTRL) High level detection */ 90 #define EIC_NMICTRL_NMISENSE_LOW_Val _U(0x5) /**< \brief (EIC_NMICTRL) Low level detection */ 91 #define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos) 92 #define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos) 93 #define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos) 94 #define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos) 95 #define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos) 96 #define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos) 97 #define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) NMI Filter Enable */ 98 #define EIC_NMICTRL_NMIFILTEN (_U(0x1) << EIC_NMICTRL_NMIFILTEN_Pos) 99 #define EIC_NMICTRL_NMIASYNCH_Pos 4 /**< \brief (EIC_NMICTRL) NMI Asynchronous edge Detection Enable */ 100 #define EIC_NMICTRL_NMIASYNCH (_U(0x1) << EIC_NMICTRL_NMIASYNCH_Pos) 101 #define EIC_NMICTRL_MASK _U(0x1F) /**< \brief (EIC_NMICTRL) MASK Register */ 102 103 /* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) NMI Interrupt Flag -------- */ 104 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 105 typedef union { 106 struct { 107 uint16_t NMI:1; /*!< bit: 0 NMI Interrupt Flag */ 108 uint16_t :15; /*!< bit: 1..15 Reserved */ 109 } bit; /*!< Structure used for bit access */ 110 uint16_t reg; /*!< Type used for register access */ 111 } EIC_NMIFLAG_Type; 112 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 113 114 #define EIC_NMIFLAG_OFFSET 0x02 /**< \brief (EIC_NMIFLAG offset) NMI Interrupt Flag */ 115 #define EIC_NMIFLAG_RESETVALUE _U(0x0000) /**< \brief (EIC_NMIFLAG reset_value) NMI Interrupt Flag */ 116 117 #define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) NMI Interrupt Flag */ 118 #define EIC_NMIFLAG_NMI (_U(0x1) << EIC_NMIFLAG_NMI_Pos) 119 #define EIC_NMIFLAG_MASK _U(0x0001) /**< \brief (EIC_NMIFLAG) MASK Register */ 120 121 /* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/ 32) Syncbusy register -------- */ 122 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 123 typedef union { 124 struct { 125 uint32_t SWRST:1; /*!< bit: 0 Software reset synchronisation */ 126 uint32_t ENABLE:1; /*!< bit: 1 Enable synchronisation */ 127 uint32_t :30; /*!< bit: 2..31 Reserved */ 128 } bit; /*!< Structure used for bit access */ 129 uint32_t reg; /*!< Type used for register access */ 130 } EIC_SYNCBUSY_Type; 131 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 132 133 #define EIC_SYNCBUSY_OFFSET 0x04 /**< \brief (EIC_SYNCBUSY offset) Syncbusy register */ 134 #define EIC_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (EIC_SYNCBUSY reset_value) Syncbusy register */ 135 136 #define EIC_SYNCBUSY_SWRST_Pos 0 /**< \brief (EIC_SYNCBUSY) Software reset synchronisation */ 137 #define EIC_SYNCBUSY_SWRST (_U(0x1) << EIC_SYNCBUSY_SWRST_Pos) 138 #define EIC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (EIC_SYNCBUSY) Enable synchronisation */ 139 #define EIC_SYNCBUSY_ENABLE (_U(0x1) << EIC_SYNCBUSY_ENABLE_Pos) 140 #define EIC_SYNCBUSY_MASK _U(0x00000003) /**< \brief (EIC_SYNCBUSY) MASK Register */ 141 142 /* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */ 143 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 144 typedef union { 145 struct { 146 uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt Event Output Enable */ 147 uint32_t :16; /*!< bit: 16..31 Reserved */ 148 } bit; /*!< Structure used for bit access */ 149 uint32_t reg; /*!< Type used for register access */ 150 } EIC_EVCTRL_Type; 151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 152 153 #define EIC_EVCTRL_OFFSET 0x08 /**< \brief (EIC_EVCTRL offset) Event Control */ 154 #define EIC_EVCTRL_RESETVALUE _U(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */ 155 156 #define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */ 157 #define EIC_EVCTRL_EXTINTEO_Msk (_U(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos) 158 #define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)) 159 #define EIC_EVCTRL_MASK _U(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */ 160 161 /* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */ 162 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 163 typedef union { 164 struct { 165 uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Disable */ 166 uint32_t :16; /*!< bit: 16..31 Reserved */ 167 } bit; /*!< Structure used for bit access */ 168 uint32_t reg; /*!< Type used for register access */ 169 } EIC_INTENCLR_Type; 170 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 171 172 #define EIC_INTENCLR_OFFSET 0x0C /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */ 173 #define EIC_INTENCLR_RESETVALUE _U(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */ 174 175 #define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt Disable */ 176 #define EIC_INTENCLR_EXTINT_Msk (_U(0xFFFF) << EIC_INTENCLR_EXTINT_Pos) 177 #define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)) 178 #define EIC_INTENCLR_MASK _U(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */ 179 180 /* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */ 181 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 182 typedef union { 183 struct { 184 uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Disable */ 185 uint32_t :16; /*!< bit: 16..31 Reserved */ 186 } bit; /*!< Structure used for bit access */ 187 uint32_t reg; /*!< Type used for register access */ 188 } EIC_INTENSET_Type; 189 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 190 191 #define EIC_INTENSET_OFFSET 0x10 /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */ 192 #define EIC_INTENSET_RESETVALUE _U(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */ 193 194 #define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt Disable */ 195 #define EIC_INTENSET_EXTINT_Msk (_U(0xFFFF) << EIC_INTENSET_EXTINT_Pos) 196 #define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)) 197 #define EIC_INTENSET_MASK _U(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */ 198 199 /* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */ 200 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 201 typedef union { // __I to avoid read-modify-write on write-to-clear register 202 struct { 203 __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Flag */ 204 __I uint32_t :16; /*!< bit: 16..31 Reserved */ 205 } bit; /*!< Structure used for bit access */ 206 uint32_t reg; /*!< Type used for register access */ 207 } EIC_INTFLAG_Type; 208 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 209 210 #define EIC_INTFLAG_OFFSET 0x14 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */ 211 #define EIC_INTFLAG_RESETVALUE _U(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 212 213 #define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt Flag */ 214 #define EIC_INTFLAG_EXTINT_Msk (_U(0xFFFF) << EIC_INTFLAG_EXTINT_Pos) 215 #define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)) 216 #define EIC_INTFLAG_MASK _U(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */ 217 218 /* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) EIC Asynchronous edge Detection Enable -------- */ 219 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 220 typedef union { 221 struct { 222 uint32_t ASYNCH:16; /*!< bit: 0..15 EIC Asynchronous edge Detection Enable */ 223 uint32_t :16; /*!< bit: 16..31 Reserved */ 224 } bit; /*!< Structure used for bit access */ 225 uint32_t reg; /*!< Type used for register access */ 226 } EIC_ASYNCH_Type; 227 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 228 229 #define EIC_ASYNCH_OFFSET 0x18 /**< \brief (EIC_ASYNCH offset) EIC Asynchronous edge Detection Enable */ 230 #define EIC_ASYNCH_RESETVALUE _U(0x00000000) /**< \brief (EIC_ASYNCH reset_value) EIC Asynchronous edge Detection Enable */ 231 232 #define EIC_ASYNCH_ASYNCH_Pos 0 /**< \brief (EIC_ASYNCH) EIC Asynchronous edge Detection Enable */ 233 #define EIC_ASYNCH_ASYNCH_Msk (_U(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos) 234 #define EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos)) 235 #define EIC_ASYNCH_MASK _U(0x0000FFFF) /**< \brief (EIC_ASYNCH) MASK Register */ 236 237 /* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) Configuration n -------- */ 238 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 239 typedef union { 240 struct { 241 uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense Configuration 0 */ 242 uint32_t FILTEN0:1; /*!< bit: 3 Filter Enable 0 */ 243 uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense Configuration 1 */ 244 uint32_t FILTEN1:1; /*!< bit: 7 Filter Enable 1 */ 245 uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense Configuration 2 */ 246 uint32_t FILTEN2:1; /*!< bit: 11 Filter Enable 2 */ 247 uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense Configuration 3 */ 248 uint32_t FILTEN3:1; /*!< bit: 15 Filter Enable 3 */ 249 uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense Configuration 4 */ 250 uint32_t FILTEN4:1; /*!< bit: 19 Filter Enable 4 */ 251 uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense Configuration 5 */ 252 uint32_t FILTEN5:1; /*!< bit: 23 Filter Enable 5 */ 253 uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense Configuration 6 */ 254 uint32_t FILTEN6:1; /*!< bit: 27 Filter Enable 6 */ 255 uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense Configuration 7 */ 256 uint32_t FILTEN7:1; /*!< bit: 31 Filter Enable 7 */ 257 } bit; /*!< Structure used for bit access */ 258 uint32_t reg; /*!< Type used for register access */ 259 } EIC_CONFIG_Type; 260 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 261 262 #define EIC_CONFIG_OFFSET 0x1C /**< \brief (EIC_CONFIG offset) Configuration n */ 263 #define EIC_CONFIG_RESETVALUE _U(0x00000000) /**< \brief (EIC_CONFIG reset_value) Configuration n */ 264 265 #define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */ 266 #define EIC_CONFIG_SENSE0_Msk (_U(0x7) << EIC_CONFIG_SENSE0_Pos) 267 #define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)) 268 #define EIC_CONFIG_SENSE0_NONE_Val _U(0x0) /**< \brief (EIC_CONFIG) No detection */ 269 #define EIC_CONFIG_SENSE0_RISE_Val _U(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 270 #define EIC_CONFIG_SENSE0_FALL_Val _U(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 271 #define EIC_CONFIG_SENSE0_BOTH_Val _U(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 272 #define EIC_CONFIG_SENSE0_HIGH_Val _U(0x4) /**< \brief (EIC_CONFIG) High level detection */ 273 #define EIC_CONFIG_SENSE0_LOW_Val _U(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 274 #define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos) 275 #define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos) 276 #define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos) 277 #define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos) 278 #define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos) 279 #define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos) 280 #define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter Enable 0 */ 281 #define EIC_CONFIG_FILTEN0 (_U(0x1) << EIC_CONFIG_FILTEN0_Pos) 282 #define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */ 283 #define EIC_CONFIG_SENSE1_Msk (_U(0x7) << EIC_CONFIG_SENSE1_Pos) 284 #define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)) 285 #define EIC_CONFIG_SENSE1_NONE_Val _U(0x0) /**< \brief (EIC_CONFIG) No detection */ 286 #define EIC_CONFIG_SENSE1_RISE_Val _U(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 287 #define EIC_CONFIG_SENSE1_FALL_Val _U(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 288 #define EIC_CONFIG_SENSE1_BOTH_Val _U(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 289 #define EIC_CONFIG_SENSE1_HIGH_Val _U(0x4) /**< \brief (EIC_CONFIG) High level detection */ 290 #define EIC_CONFIG_SENSE1_LOW_Val _U(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 291 #define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos) 292 #define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos) 293 #define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos) 294 #define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos) 295 #define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos) 296 #define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos) 297 #define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter Enable 1 */ 298 #define EIC_CONFIG_FILTEN1 (_U(0x1) << EIC_CONFIG_FILTEN1_Pos) 299 #define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */ 300 #define EIC_CONFIG_SENSE2_Msk (_U(0x7) << EIC_CONFIG_SENSE2_Pos) 301 #define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)) 302 #define EIC_CONFIG_SENSE2_NONE_Val _U(0x0) /**< \brief (EIC_CONFIG) No detection */ 303 #define EIC_CONFIG_SENSE2_RISE_Val _U(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 304 #define EIC_CONFIG_SENSE2_FALL_Val _U(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 305 #define EIC_CONFIG_SENSE2_BOTH_Val _U(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 306 #define EIC_CONFIG_SENSE2_HIGH_Val _U(0x4) /**< \brief (EIC_CONFIG) High level detection */ 307 #define EIC_CONFIG_SENSE2_LOW_Val _U(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 308 #define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos) 309 #define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos) 310 #define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos) 311 #define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos) 312 #define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos) 313 #define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos) 314 #define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter Enable 2 */ 315 #define EIC_CONFIG_FILTEN2 (_U(0x1) << EIC_CONFIG_FILTEN2_Pos) 316 #define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */ 317 #define EIC_CONFIG_SENSE3_Msk (_U(0x7) << EIC_CONFIG_SENSE3_Pos) 318 #define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)) 319 #define EIC_CONFIG_SENSE3_NONE_Val _U(0x0) /**< \brief (EIC_CONFIG) No detection */ 320 #define EIC_CONFIG_SENSE3_RISE_Val _U(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 321 #define EIC_CONFIG_SENSE3_FALL_Val _U(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 322 #define EIC_CONFIG_SENSE3_BOTH_Val _U(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 323 #define EIC_CONFIG_SENSE3_HIGH_Val _U(0x4) /**< \brief (EIC_CONFIG) High level detection */ 324 #define EIC_CONFIG_SENSE3_LOW_Val _U(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 325 #define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos) 326 #define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos) 327 #define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos) 328 #define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos) 329 #define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos) 330 #define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos) 331 #define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter Enable 3 */ 332 #define EIC_CONFIG_FILTEN3 (_U(0x1) << EIC_CONFIG_FILTEN3_Pos) 333 #define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */ 334 #define EIC_CONFIG_SENSE4_Msk (_U(0x7) << EIC_CONFIG_SENSE4_Pos) 335 #define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos)) 336 #define EIC_CONFIG_SENSE4_NONE_Val _U(0x0) /**< \brief (EIC_CONFIG) No detection */ 337 #define EIC_CONFIG_SENSE4_RISE_Val _U(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 338 #define EIC_CONFIG_SENSE4_FALL_Val _U(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 339 #define EIC_CONFIG_SENSE4_BOTH_Val _U(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 340 #define EIC_CONFIG_SENSE4_HIGH_Val _U(0x4) /**< \brief (EIC_CONFIG) High level detection */ 341 #define EIC_CONFIG_SENSE4_LOW_Val _U(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 342 #define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos) 343 #define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos) 344 #define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos) 345 #define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos) 346 #define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos) 347 #define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos) 348 #define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter Enable 4 */ 349 #define EIC_CONFIG_FILTEN4 (_U(0x1) << EIC_CONFIG_FILTEN4_Pos) 350 #define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */ 351 #define EIC_CONFIG_SENSE5_Msk (_U(0x7) << EIC_CONFIG_SENSE5_Pos) 352 #define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos)) 353 #define EIC_CONFIG_SENSE5_NONE_Val _U(0x0) /**< \brief (EIC_CONFIG) No detection */ 354 #define EIC_CONFIG_SENSE5_RISE_Val _U(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 355 #define EIC_CONFIG_SENSE5_FALL_Val _U(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 356 #define EIC_CONFIG_SENSE5_BOTH_Val _U(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 357 #define EIC_CONFIG_SENSE5_HIGH_Val _U(0x4) /**< \brief (EIC_CONFIG) High level detection */ 358 #define EIC_CONFIG_SENSE5_LOW_Val _U(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 359 #define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos) 360 #define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos) 361 #define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos) 362 #define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos) 363 #define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos) 364 #define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos) 365 #define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter Enable 5 */ 366 #define EIC_CONFIG_FILTEN5 (_U(0x1) << EIC_CONFIG_FILTEN5_Pos) 367 #define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */ 368 #define EIC_CONFIG_SENSE6_Msk (_U(0x7) << EIC_CONFIG_SENSE6_Pos) 369 #define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos)) 370 #define EIC_CONFIG_SENSE6_NONE_Val _U(0x0) /**< \brief (EIC_CONFIG) No detection */ 371 #define EIC_CONFIG_SENSE6_RISE_Val _U(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 372 #define EIC_CONFIG_SENSE6_FALL_Val _U(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 373 #define EIC_CONFIG_SENSE6_BOTH_Val _U(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 374 #define EIC_CONFIG_SENSE6_HIGH_Val _U(0x4) /**< \brief (EIC_CONFIG) High level detection */ 375 #define EIC_CONFIG_SENSE6_LOW_Val _U(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 376 #define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos) 377 #define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos) 378 #define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos) 379 #define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos) 380 #define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos) 381 #define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos) 382 #define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter Enable 6 */ 383 #define EIC_CONFIG_FILTEN6 (_U(0x1) << EIC_CONFIG_FILTEN6_Pos) 384 #define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */ 385 #define EIC_CONFIG_SENSE7_Msk (_U(0x7) << EIC_CONFIG_SENSE7_Pos) 386 #define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos)) 387 #define EIC_CONFIG_SENSE7_NONE_Val _U(0x0) /**< \brief (EIC_CONFIG) No detection */ 388 #define EIC_CONFIG_SENSE7_RISE_Val _U(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 389 #define EIC_CONFIG_SENSE7_FALL_Val _U(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 390 #define EIC_CONFIG_SENSE7_BOTH_Val _U(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 391 #define EIC_CONFIG_SENSE7_HIGH_Val _U(0x4) /**< \brief (EIC_CONFIG) High level detection */ 392 #define EIC_CONFIG_SENSE7_LOW_Val _U(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 393 #define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos) 394 #define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos) 395 #define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos) 396 #define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos) 397 #define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos) 398 #define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos) 399 #define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter Enable 7 */ 400 #define EIC_CONFIG_FILTEN7 (_U(0x1) << EIC_CONFIG_FILTEN7_Pos) 401 #define EIC_CONFIG_MASK _U(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */ 402 403 /** \brief EIC hardware registers */ 404 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 405 typedef struct { 406 __IO EIC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ 407 __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x01 (R/W 8) NMI Control */ 408 __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x02 (R/W 16) NMI Interrupt Flag */ 409 __I EIC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Syncbusy register */ 410 __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x08 (R/W 32) Event Control */ 411 __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */ 412 __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */ 413 __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */ 414 __IO EIC_ASYNCH_Type ASYNCH; /**< \brief Offset: 0x18 (R/W 32) EIC Asynchronous edge Detection Enable */ 415 __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x1C (R/W 32) Configuration n */ 416 } Eic; 417 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 418 419 /*@}*/ 420 421 #endif /* _SAML21_EIC_COMPONENT_ */ 422
