1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef STM32L4xx_HAL_DMA_H 38 #define STM32L4xx_HAL_DMA_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup DMA 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup DMA_Exported_Types DMA Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief DMA Configuration Structure definition 62 */ 63 typedef struct 64 { 65 uint32_t Request; /*!< Specifies the request selected for the specified channel. 66 This parameter can be a value of @ref DMA_request */ 67 68 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 69 from memory to memory or from peripheral to memory. 70 This parameter can be a value of @ref DMA_Data_transfer_direction */ 71 72 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 73 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 74 75 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 76 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 77 78 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 79 This parameter can be a value of @ref DMA_Peripheral_data_size */ 80 81 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 82 This parameter can be a value of @ref DMA_Memory_data_size */ 83 84 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 85 This parameter can be a value of @ref DMA_mode 86 @note The circular buffer mode cannot be used if the memory-to-memory 87 data transfer is configured on the selected Channel */ 88 89 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 90 This parameter can be a value of @ref DMA_Priority_level */ 91 } DMA_InitTypeDef; 92 93 /** 94 * @brief HAL DMA State structures definition 95 */ 96 typedef enum 97 { 98 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 99 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 100 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 101 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 102 }HAL_DMA_StateTypeDef; 103 104 /** 105 * @brief HAL DMA Error Code structure definition 106 */ 107 typedef enum 108 { 109 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 110 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 111 }HAL_DMA_LevelCompleteTypeDef; 112 113 114 /** 115 * @brief HAL DMA Callback ID structure definition 116 */ 117 typedef enum 118 { 119 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 120 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 121 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 122 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 123 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 124 }HAL_DMA_CallbackIDTypeDef; 125 126 /** 127 * @brief DMA handle Structure definition 128 */ 129 typedef struct __DMA_HandleTypeDef 130 { 131 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 132 133 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 134 135 HAL_LockTypeDef Lock; /*!< DMA locking object */ 136 137 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 138 139 void *Parent; /*!< Parent object state */ 140 141 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 142 143 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 144 145 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 146 147 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 148 149 __IO uint32_t ErrorCode; /*!< DMA Error code */ 150 151 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 152 153 uint32_t ChannelIndex; /*!< DMA Channel Index */ 154 155 #if defined(DMAMUX1) 156 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 157 158 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 159 160 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 161 162 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 163 164 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 165 166 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 167 168 #endif /* DMAMUX1 */ 169 170 }DMA_HandleTypeDef; 171 172 /** 173 * @} 174 */ 175 176 /* Exported constants --------------------------------------------------------*/ 177 178 /** @defgroup DMA_Exported_Constants DMA Exported Constants 179 * @{ 180 */ 181 182 /** @defgroup DMA_Error_Code DMA Error Code 183 * @{ 184 */ 185 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 186 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 187 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 188 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 189 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 190 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 191 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 192 193 /** 194 * @} 195 */ 196 197 /** @defgroup DMA_request DMA request 198 * @{ 199 */ 200 #if !defined (DMAMUX1) 201 202 #define DMA_REQUEST_0 0U 203 #define DMA_REQUEST_1 1U 204 #define DMA_REQUEST_2 2U 205 #define DMA_REQUEST_3 3U 206 #define DMA_REQUEST_4 4U 207 #define DMA_REQUEST_5 5U 208 #define DMA_REQUEST_6 6U 209 #define DMA_REQUEST_7 7U 210 211 #endif 212 213 #if defined(DMAMUX1) 214 215 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 216 217 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ 218 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ 219 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ 220 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ 221 222 #define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */ 223 224 #define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */ 225 #define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */ 226 227 #define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */ 228 #define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */ 229 230 #define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */ 231 #define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */ 232 #define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */ 233 #define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */ 234 #define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */ 235 #define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */ 236 237 #define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */ 238 #define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */ 239 #define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */ 240 #define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */ 241 #define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */ 242 #define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */ 243 #define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */ 244 #define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */ 245 246 #define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */ 247 #define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */ 248 #define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */ 249 #define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */ 250 #define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */ 251 #define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */ 252 253 #define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */ 254 #define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */ 255 #define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */ 256 #define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */ 257 258 #define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */ 259 #define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */ 260 261 #define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */ 262 #define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */ 263 #define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */ 264 #define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */ 265 266 #define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */ 267 #define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */ 268 269 #define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */ 270 #define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */ 271 #define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */ 272 #define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */ 273 #define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */ 274 #define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */ 275 #define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */ 276 277 #define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */ 278 #define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */ 279 #define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */ 280 #define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */ 281 #define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */ 282 #define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */ 283 #define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */ 284 285 #define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */ 286 #define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */ 287 #define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */ 288 #define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */ 289 #define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */ 290 291 #define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */ 292 #define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */ 293 #define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */ 294 #define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */ 295 #define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */ 296 #define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */ 297 298 #define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */ 299 #define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */ 300 #define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */ 301 #define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */ 302 #define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */ 303 304 #define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */ 305 #define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */ 306 #define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */ 307 #define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */ 308 #define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */ 309 #define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */ 310 311 #define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */ 312 #define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */ 313 #define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */ 314 #define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */ 315 316 #define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */ 317 #define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */ 318 #define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */ 319 #define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */ 320 321 #define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */ 322 #define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */ 323 #define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */ 324 #define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */ 325 326 #define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */ 327 328 #define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */ 329 #define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */ 330 331 #define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */ 332 333 #endif /* DMAMUX1 */ 334 335 /** 336 * @} 337 */ 338 339 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 340 * @{ 341 */ 342 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 343 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 344 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 345 /** 346 * @} 347 */ 348 349 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 350 * @{ 351 */ 352 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 353 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 354 /** 355 * @} 356 */ 357 358 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 359 * @{ 360 */ 361 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 362 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 363 /** 364 * @} 365 */ 366 367 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 368 * @{ 369 */ 370 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 371 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 372 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 373 /** 374 * @} 375 */ 376 377 /** @defgroup DMA_Memory_data_size DMA Memory data size 378 * @{ 379 */ 380 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 381 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 382 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 383 /** 384 * @} 385 */ 386 387 /** @defgroup DMA_mode DMA mode 388 * @{ 389 */ 390 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 391 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 392 /** 393 * @} 394 */ 395 396 /** @defgroup DMA_Priority_level DMA Priority level 397 * @{ 398 */ 399 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 400 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 401 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 402 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 403 /** 404 * @} 405 */ 406 407 408 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 409 * @{ 410 */ 411 #define DMA_IT_TC DMA_CCR_TCIE 412 #define DMA_IT_HT DMA_CCR_HTIE 413 #define DMA_IT_TE DMA_CCR_TEIE 414 /** 415 * @} 416 */ 417 418 /** @defgroup DMA_flag_definitions DMA flag definitions 419 * @{ 420 */ 421 #define DMA_FLAG_GL1 DMA_ISR_GIF1 422 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 423 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 424 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 425 #define DMA_FLAG_GL2 DMA_ISR_GIF2 426 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 427 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 428 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 429 #define DMA_FLAG_GL3 DMA_ISR_GIF3 430 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 431 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 432 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 433 #define DMA_FLAG_GL4 DMA_ISR_GIF4 434 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 435 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 436 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 437 #define DMA_FLAG_GL5 DMA_ISR_GIF5 438 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 439 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 440 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 441 #define DMA_FLAG_GL6 DMA_ISR_GIF6 442 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 443 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 444 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 445 #define DMA_FLAG_GL7 DMA_ISR_GIF7 446 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 447 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 448 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 449 /** 450 * @} 451 */ 452 453 /** 454 * @} 455 */ 456 457 /* Exported macros -----------------------------------------------------------*/ 458 /** @defgroup DMA_Exported_Macros DMA Exported Macros 459 * @{ 460 */ 461 462 /** @brief Reset DMA handle state. 463 * @param __HANDLE__: DMA handle 464 * @retval None 465 */ 466 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 467 468 /** 469 * @brief Enable the specified DMA Channel. 470 * @param __HANDLE__: DMA handle 471 * @retval None 472 */ 473 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 474 475 /** 476 * @brief Disable the specified DMA Channel. 477 * @param __HANDLE__: DMA handle 478 * @retval None 479 */ 480 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 481 482 483 /* Interrupt & Flag management */ 484 485 /** 486 * @brief Return the current DMA Channel transfer complete flag. 487 * @param __HANDLE__: DMA handle 488 * @retval The specified transfer complete flag index. 489 */ 490 491 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 492 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ 504 DMA_FLAG_TC7) 505 506 /** 507 * @brief Return the current DMA Channel half transfer complete flag. 508 * @param __HANDLE__: DMA handle 509 * @retval The specified half transfer complete flag index. 510 */ 511 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 512 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ 524 DMA_FLAG_HT7) 525 526 /** 527 * @brief Return the current DMA Channel transfer error flag. 528 * @param __HANDLE__: DMA handle 529 * @retval The specified transfer error flag index. 530 */ 531 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 532 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ 544 DMA_FLAG_TE7) 545 546 /** 547 * @brief Return the current DMA Channel Global interrupt flag. 548 * @param __HANDLE__: DMA handle 549 * @retval The specified transfer error flag index. 550 */ 551 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 552 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 553 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 554 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 555 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 556 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 557 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 558 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 559 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 560 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 561 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 562 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 563 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ 564 DMA_ISR_GIF7) 565 566 /** 567 * @brief Get the DMA Channel pending flags. 568 * @param __HANDLE__: DMA handle 569 * @param __FLAG__: Get the specified flag. 570 * This parameter can be any combination of the following values: 571 * @arg DMA_FLAG_TCx: Transfer complete flag 572 * @arg DMA_FLAG_HTx: Half transfer complete flag 573 * @arg DMA_FLAG_TEx: Transfer error flag 574 * @arg DMA_FLAG_GLx: Global interrupt flag 575 * Where x can be from 1 to 7 to select the DMA Channel x flag. 576 * @retval The state of FLAG (SET or RESET). 577 */ 578 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 579 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 580 581 /** 582 * @brief Clear the DMA Channel pending flags. 583 * @param __HANDLE__: DMA handle 584 * @param __FLAG__: specifies the flag to clear. 585 * This parameter can be any combination of the following values: 586 * @arg DMA_FLAG_TCx: Transfer complete flag 587 * @arg DMA_FLAG_HTx: Half transfer complete flag 588 * @arg DMA_FLAG_TEx: Transfer error flag 589 * @arg DMA_FLAG_GLx: Global interrupt flag 590 * Where x can be from 1 to 7 to select the DMA Channel x flag. 591 * @retval None 592 */ 593 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 594 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 595 596 /** 597 * @brief Enable the specified DMA Channel interrupts. 598 * @param __HANDLE__: DMA handle 599 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 600 * This parameter can be any combination of the following values: 601 * @arg DMA_IT_TC: Transfer complete interrupt mask 602 * @arg DMA_IT_HT: Half transfer complete interrupt mask 603 * @arg DMA_IT_TE: Transfer error interrupt mask 604 * @retval None 605 */ 606 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 607 608 /** 609 * @brief Disable the specified DMA Channel interrupts. 610 * @param __HANDLE__: DMA handle 611 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 612 * This parameter can be any combination of the following values: 613 * @arg DMA_IT_TC: Transfer complete interrupt mask 614 * @arg DMA_IT_HT: Half transfer complete interrupt mask 615 * @arg DMA_IT_TE: Transfer error interrupt mask 616 * @retval None 617 */ 618 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 619 620 /** 621 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 622 * @param __HANDLE__: DMA handle 623 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 624 * This parameter can be one of the following values: 625 * @arg DMA_IT_TC: Transfer complete interrupt mask 626 * @arg DMA_IT_HT: Half transfer complete interrupt mask 627 * @arg DMA_IT_TE: Transfer error interrupt mask 628 * @retval The state of DMA_IT (SET or RESET). 629 */ 630 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 631 632 /** 633 * @brief Return the number of remaining data units in the current DMA Channel transfer. 634 * @param __HANDLE__: DMA handle 635 * @retval The number of remaining data units in the current DMA Channel transfer. 636 */ 637 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 638 639 /** 640 * @} 641 */ 642 643 #if defined(DMAMUX1) 644 /* Include DMA HAL Extension module */ 645 #include "stm32l4xx_hal_dma_ex.h" 646 #endif /* DMAMUX1 */ 647 648 /* Exported functions --------------------------------------------------------*/ 649 650 /** @addtogroup DMA_Exported_Functions 651 * @{ 652 */ 653 654 /** @addtogroup DMA_Exported_Functions_Group1 655 * @{ 656 */ 657 /* Initialization and de-initialization functions *****************************/ 658 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 659 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 660 /** 661 * @} 662 */ 663 664 /** @addtogroup DMA_Exported_Functions_Group2 665 * @{ 666 */ 667 /* IO operation functions *****************************************************/ 668 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 669 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 670 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 671 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 672 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 673 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 674 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 675 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 676 677 /** 678 * @} 679 */ 680 681 /** @addtogroup DMA_Exported_Functions_Group3 682 * @{ 683 */ 684 /* Peripheral State and Error functions ***************************************/ 685 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 686 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 687 /** 688 * @} 689 */ 690 691 /** 692 * @} 693 */ 694 695 /* Private macros ------------------------------------------------------------*/ 696 /** @defgroup DMA_Private_Macros DMA Private Macros 697 * @{ 698 */ 699 700 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 701 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 702 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 703 704 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 705 706 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 707 ((STATE) == DMA_PINC_DISABLE)) 708 709 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 710 ((STATE) == DMA_MINC_DISABLE)) 711 712 #if !defined (DMAMUX1) 713 714 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 715 ((REQUEST) == DMA_REQUEST_1) || \ 716 ((REQUEST) == DMA_REQUEST_2) || \ 717 ((REQUEST) == DMA_REQUEST_3) || \ 718 ((REQUEST) == DMA_REQUEST_4) || \ 719 ((REQUEST) == DMA_REQUEST_5) || \ 720 ((REQUEST) == DMA_REQUEST_6) || \ 721 ((REQUEST) == DMA_REQUEST_7)) 722 #endif 723 724 #if defined(DMAMUX1) 725 726 #define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN) 727 728 #endif /* DMAMUX1 */ 729 730 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 731 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 732 ((SIZE) == DMA_PDATAALIGN_WORD)) 733 734 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 735 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 736 ((SIZE) == DMA_MDATAALIGN_WORD )) 737 738 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 739 ((MODE) == DMA_CIRCULAR)) 740 741 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 742 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 743 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 744 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 745 746 /** 747 * @} 748 */ 749 750 /* Private functions ---------------------------------------------------------*/ 751 752 /** 753 * @} 754 */ 755 756 /** 757 * @} 758 */ 759 760 #ifdef __cplusplus 761 } 762 #endif 763 764 #endif /* STM32L4xx_HAL_DMA_H */ 765 766 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 767
