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Searched refs:CCER (Results 1 – 21 of 21) sorted by relevance

/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_ll_tim.c450 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_ENCODER_Init()
456 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_ENCODER_Init()
483 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_ENCODER_Init()
521 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); in OC1Config()
524 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC1Config()
554 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC1Config()
580 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); in OC2Config()
583 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC2Config()
613 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC2Config()
639 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); in OC3Config()
[all …]
Dstm32l1xx_hal_tim.c2219 tmpccer = htim->Instance->CCER; in HAL_TIM_Encoder_Init()
2246 htim->Instance->CCER = tmpccer; in HAL_TIM_Encoder_Init()
4500 TIMx->CCER &= ~TIM_CCER_CC1E; in TIM_OC1_SetConfig()
4503 tmpccer = TIMx->CCER; in TIM_OC1_SetConfig()
4531 TIMx->CCER = tmpccer; in TIM_OC1_SetConfig()
4547 TIMx->CCER &= ~TIM_CCER_CC2E; in TIM_OC2_SetConfig()
4550 tmpccer = TIMx->CCER; in TIM_OC2_SetConfig()
4579 TIMx->CCER = tmpccer; in TIM_OC2_SetConfig()
4595 TIMx->CCER &= ~TIM_CCER_CC3E; in TIM_OC3_SetConfig()
4598 tmpccer = TIMx->CCER; in TIM_OC3_SetConfig()
[all …]
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Src/
Dstm32l0xx_ll_tim.c427 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_ENCODER_Init()
433 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_ENCODER_Init()
460 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_ENCODER_Init()
499 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); in OC1Config()
502 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC1Config()
532 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC1Config()
558 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); in OC2Config()
561 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC2Config()
591 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC2Config()
617 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); in OC3Config()
[all …]
Dstm32l0xx_hal_tim.c2212 tmpccer = htim->Instance->CCER; in HAL_TIM_Encoder_Init()
2239 htim->Instance->CCER = tmpccer; in HAL_TIM_Encoder_Init()
4430 TIMx->CCER &= ~TIM_CCER_CC1E; in TIM_OC1_SetConfig()
4433 tmpccer = TIMx->CCER; in TIM_OC1_SetConfig()
4461 TIMx->CCER = tmpccer; in TIM_OC1_SetConfig()
4477 TIMx->CCER &= ~TIM_CCER_CC2E; in TIM_OC2_SetConfig()
4480 tmpccer = TIMx->CCER; in TIM_OC2_SetConfig()
4509 TIMx->CCER = tmpccer; in TIM_OC2_SetConfig()
4525 TIMx->CCER &= ~TIM_CCER_CC3E; in TIM_OC3_SetConfig()
4528 tmpccer = TIMx->CCER; in TIM_OC3_SetConfig()
[all …]
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_ll_tim.c547 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_ENCODER_Init()
553 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_ENCODER_Init()
580 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_ENCODER_Init()
634 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_HALLSENSOR_Init()
643 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_HALLSENSOR_Init()
684 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_HALLSENSOR_Init()
813 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); in OC1Config()
816 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC1Config()
864 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC1Config()
892 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); in OC2Config()
[all …]
Dstm32l4xx_hal_tim.c2603 tmpccer = htim->Instance->CCER; in HAL_TIM_Encoder_Init()
2630 htim->Instance->CCER = tmpccer; in HAL_TIM_Encoder_Init()
5653 TIMx->CCER &= ~TIM_CCER_CC1E; in TIM_OC1_SetConfig()
5656 tmpccer = TIMx->CCER; in TIM_OC1_SetConfig()
5712 TIMx->CCER = tmpccer; in TIM_OC1_SetConfig()
5728 TIMx->CCER &= ~TIM_CCER_CC2E; in TIM_OC2_SetConfig()
5731 tmpccer = TIMx->CCER; in TIM_OC2_SetConfig()
5788 TIMx->CCER = tmpccer; in TIM_OC2_SetConfig()
5804 TIMx->CCER &= ~TIM_CCER_CC3E; in TIM_OC3_SetConfig()
5807 tmpccer = TIMx->CCER; in TIM_OC3_SetConfig()
[all …]
Dstm32l4xx_hal_tim_ex.c676 tmpccer = htim->Instance->CCER; in HAL_TIMEx_OCN_Stop_IT()
1069 tmpccer = htim->Instance->CCER; in HAL_TIMEx_PWMN_Stop_IT()
2295 TIMx->CCER &= ~tmp; in TIM_CCxNChannelCmd()
2298 TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ in TIM_CCxNChannelCmd()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_hal_tim.h1010 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1011 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
1012 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
1013 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
1021 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TI…
1022 …((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TI…
1023 …((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TI…
1024 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
1057 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
Dstm32l1xx_ll_tim.h1262 SET_BIT(TIMx->CCER, Channels); in LL_TIM_CC_EnableChannel()
1281 CLEAR_BIT(TIMx->CCER, Channels); in LL_TIM_CC_DisableChannel()
1300 return (READ_BIT(TIMx->CCER, Channels) == (Channels)); in LL_TIM_CC_IsEnabledChannel()
1335 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_OC_ConfigOutput()
1419 …MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iC… in LL_TIM_OC_SetPolarity()
1441 …return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChann… in LL_TIM_OC_GetPolarity()
1828 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config()
2032 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity()
2060 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_hal_tim.h1019 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
1051 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1052 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1053 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1054 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
1057 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TI…
1058 …((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TI…
1059 …((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TI…
1060 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
Dstm32l0xx_ll_tim.h1287 SET_BIT(TIMx->CCER, Channels); in LL_TIM_CC_EnableChannel()
1306 CLEAR_BIT(TIMx->CCER, Channels); in LL_TIM_CC_DisableChannel()
1325 return (READ_BIT(TIMx->CCER, Channels) == (Channels)); in LL_TIM_CC_IsEnabledChannel()
1360 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_OC_ConfigOutput()
1444 …MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iC… in LL_TIM_OC_SetPolarity()
1466 …return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChann… in LL_TIM_OC_GetPolarity()
1829 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config()
2033 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity()
2061 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_tim.h1126 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1128 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1143 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1145 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1870 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1871 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1872 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1873 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
1876 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TI…
1877 …((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TI…
[all …]
Dstm32l4xx_ll_tim.h1962 SET_BIT(TIMx->CCER, Channels); in LL_TIM_CC_EnableChannel()
1991 CLEAR_BIT(TIMx->CCER, Channels); in LL_TIM_CC_DisableChannel()
2020 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); in LL_TIM_CC_IsEnabledChannel()
2068 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_OC_ConfigOutput()
2184 …MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iC… in LL_TIM_OC_SetPolarity()
2216 …return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChann… in LL_TIM_OC_GetPolarity()
2797 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_Config()
3001 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), in LL_TIM_IC_SetPolarity()
3029 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> in LL_TIM_IC_GetPolarity()
/loramac-node-3.6.0-3.5.0/src/boards/SKiM881AXL/cmsis/
Dstm32l081xx.h494 …__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ member
/loramac-node-3.6.0-3.5.0/src/boards/B-L072Z-LRWAN1/cmsis/
Dstm32l072xx.h521 …__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ member
/loramac-node-3.6.0-3.5.0/src/boards/SKiM980A/cmsis/
Dstm32l151xba.h493 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ member
/loramac-node-3.6.0-3.5.0/src/boards/NucleoL073/cmsis/
Dstm32l073xx.h535 …__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ member
/loramac-node-3.6.0-3.5.0/src/boards/SKiM880B/cmsis/
Dstm32l151xba.h493 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ member
/loramac-node-3.6.0-3.5.0/src/boards/NAMote72/cmsis/
Dstm32l152xc.h561 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ member
/loramac-node-3.6.0-3.5.0/src/boards/NucleoL152/cmsis/
Dstm32l152xe.h576 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ member
/loramac-node-3.6.0-3.5.0/src/boards/NucleoL476/cmsis/
Dstm32l476xx.h920 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ member