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Searched refs:APB2ENR (Results 1 – 16 of 16) sorted by relevance

/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_hal_rcc.h873 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
875 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
880 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
882 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
887 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
889 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
894 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
896 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
901 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
903 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
[all …]
Dstm32l1xx_ll_bus.h914 SET_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_EnableClock()
916 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_EnableClock()
945 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); in LL_APB2_GRP1_IsEnabledClock()
973 CLEAR_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_DisableClock()
Dstm32l1xx_hal_rcc_ex.h356 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
358 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
361 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
736 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
737 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_rcc.h1444 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
1446 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
1452 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
1454 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
1461 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
1463 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
1470 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
1472 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
1478 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
1480 … tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
[all …]
Dstm32l4xx_ll_bus.h1691 SET_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_EnableClock()
1693 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_EnableClock()
1736 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); in LL_APB2_GRP1_IsEnabledClock()
1776 CLEAR_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_DisableClock()
/loramac-node-3.6.0-3.5.0/src/boards/mcu/stm32/STM32L0xx_HAL_Driver/Inc/
Dstm32l0xx_hal_rcc_ex.h869 #define __HAL_RCC_TIM21_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
871 #define __HAL_RCC_TIM22_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
873 #define __HAL_RCC_ADC1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
874 #define __HAL_RCC_SPI1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
875 #define __HAL_RCC_USART1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
877 #define __HAL_RCC_TIM21_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
879 #define __HAL_RCC_TIM22_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
881 #define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
882 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
883 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
[all …]
Dstm32l0xx_ll_bus.h805 SET_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_EnableClock()
807 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_EnableClock()
836 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); in LL_APB2_GRP1_IsEnabledClock()
864 CLEAR_BIT(RCC->APB2ENR, Periphs); in LL_APB2_GRP1_DisableClock()
Dstm32l0xx_hal_rcc.h795 #define __HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
796 #define __HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
798 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
799 #define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
867 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != R…
868 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != R…
869 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == R…
870 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) == R…
/loramac-node-3.6.0-3.5.0/src/boards/SKiM881AXL/cmsis/
Dstm32l081xx.h422 …__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Ad… member
/loramac-node-3.6.0-3.5.0/src/boards/B-L072Z-LRWAN1/cmsis/
Dstm32l072xx.h439 …__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Ad… member
/loramac-node-3.6.0-3.5.0/src/boards/SKiM980A/cmsis/
Dstm32l151xba.h396 …__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Ad… member
/loramac-node-3.6.0-3.5.0/src/boards/NucleoL073/cmsis/
Dstm32l073xx.h453 …__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Ad… member
/loramac-node-3.6.0-3.5.0/src/boards/SKiM880B/cmsis/
Dstm32l151xba.h396 …__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Ad… member
/loramac-node-3.6.0-3.5.0/src/boards/NAMote72/cmsis/
Dstm32l152xc.h440 …__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Ad… member
/loramac-node-3.6.0-3.5.0/src/boards/NucleoL152/cmsis/
Dstm32l152xe.h449 …__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Ad… member
/loramac-node-3.6.0-3.5.0/src/boards/NucleoL476/cmsis/
Dstm32l476xx.h728 …__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, … member