| /loramac-node-3.4.0/src/boards/mcu/saml21/hri/ |
| D | hri_nvic_l21.h | 85 uint32_t tmp; in hri_nvic_get_NVICISER_SETENA_bf() local
86 tmp = ((Nvic *)hw)->NVICISER.reg; in hri_nvic_get_NVICISER_SETENA_bf()
87 tmp = (tmp & NVIC_NVICISER_SETENA(mask)) >> 0; in hri_nvic_get_NVICISER_SETENA_bf()
88 return tmp; in hri_nvic_get_NVICISER_SETENA_bf()
93 uint32_t tmp; in hri_nvic_write_NVICISER_SETENA_bf() local
95 tmp = ((Nvic *)hw)->NVICISER.reg; in hri_nvic_write_NVICISER_SETENA_bf()
96 tmp &= ~NVIC_NVICISER_SETENA_Msk; in hri_nvic_write_NVICISER_SETENA_bf()
97 tmp |= NVIC_NVICISER_SETENA(data); in hri_nvic_write_NVICISER_SETENA_bf()
98 ((Nvic *)hw)->NVICISER.reg = tmp; in hri_nvic_write_NVICISER_SETENA_bf()
118 uint32_t tmp; in hri_nvic_read_NVICISER_SETENA_bf() local
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| D | hri_mclk_l21.h | 106 uint8_t tmp; in hri_mclk_get_INTEN_reg() local
107 tmp = ((Mclk *)hw)->INTENSET.reg; in hri_mclk_get_INTEN_reg()
108 tmp &= mask; in hri_mclk_get_INTEN_reg()
109 return tmp; in hri_mclk_get_INTEN_reg()
150 uint8_t tmp; in hri_mclk_get_INTFLAG_reg() local
151 tmp = ((Mclk *)hw)->INTFLAG.reg; in hri_mclk_get_INTFLAG_reg()
152 tmp &= mask; in hri_mclk_get_INTFLAG_reg()
153 return tmp; in hri_mclk_get_INTFLAG_reg()
175 uint8_t tmp; in hri_mclk_get_CTRLA_reg() local
176 tmp = ((Mclk *)hw)->CTRLA.reg; in hri_mclk_get_CTRLA_reg()
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| D | hri_tal_l21.h | 116 uint8_t tmp; in hri_tal_get_INTEN_reg() local
117 tmp = ((Tal *)hw)->INTENSET.reg; in hri_tal_get_INTEN_reg()
118 tmp &= mask; in hri_tal_get_INTEN_reg()
119 return tmp; in hri_tal_get_INTEN_reg()
160 uint8_t tmp; in hri_tal_get_INTFLAG_reg() local
161 tmp = ((Tal *)hw)->INTFLAG.reg; in hri_tal_get_INTFLAG_reg()
162 tmp &= mask; in hri_tal_get_INTFLAG_reg()
163 return tmp; in hri_tal_get_INTFLAG_reg()
199 uint8_t tmp; in hri_tal_get_CTRLA_SWRST_bit() local
200 tmp = ((Tal *)hw)->CTRLA.reg; in hri_tal_get_CTRLA_SWRST_bit()
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| D | hri_dmac_l21.h | 169 uint8_t tmp; in hri_dmac_get_CHINTEN_reg() local
170 tmp = ((Dmac *)hw)->CHINTENSET.reg; in hri_dmac_get_CHINTEN_reg()
171 tmp &= mask; in hri_dmac_get_CHINTEN_reg()
172 return tmp; in hri_dmac_get_CHINTEN_reg()
253 uint8_t tmp; in hri_dmac_get_CHINTFLAG_reg() local
254 tmp = ((Dmac *)hw)->CHINTFLAG.reg; in hri_dmac_get_CHINTFLAG_reg()
255 tmp &= mask; in hri_dmac_get_CHINTFLAG_reg()
256 return tmp; in hri_dmac_get_CHINTFLAG_reg()
278 uint16_t tmp; in hri_dmac_get_CTRL_SWRST_bit() local
279 tmp = ((Dmac *)hw)->CTRL.reg; in hri_dmac_get_CTRL_SWRST_bit()
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| D | hri_tcc_l21.h | 103 uint32_t tmp; in hri_tcc_get_COUNT_DITH4_COUNT_bf() local
104 tmp = ((Tcc *)hw)->COUNT.reg; in hri_tcc_get_COUNT_DITH4_COUNT_bf()
105 tmp = (tmp & TCC_COUNT_DITH4_COUNT(mask)) >> TCC_COUNT_DITH4_COUNT_Pos; in hri_tcc_get_COUNT_DITH4_COUNT_bf()
106 return tmp; in hri_tcc_get_COUNT_DITH4_COUNT_bf()
111 uint32_t tmp; in hri_tcc_write_COUNT_DITH4_COUNT_bf() local
113 tmp = ((Tcc *)hw)->COUNT.reg; in hri_tcc_write_COUNT_DITH4_COUNT_bf()
114 tmp &= ~TCC_COUNT_DITH4_COUNT_Msk; in hri_tcc_write_COUNT_DITH4_COUNT_bf()
115 tmp |= TCC_COUNT_DITH4_COUNT(data); in hri_tcc_write_COUNT_DITH4_COUNT_bf()
116 ((Tcc *)hw)->COUNT.reg = tmp; in hri_tcc_write_COUNT_DITH4_COUNT_bf()
136 uint32_t tmp; in hri_tcc_read_COUNT_DITH4_COUNT_bf() local
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| D | hri_systemcontrol_l21.h | 81 uint32_t tmp; in hri_systemcontrol_get_CPUID_REVISION_bf() local
82 tmp = ((Systemcontrol *)hw)->CPUID.reg; in hri_systemcontrol_get_CPUID_REVISION_bf()
83 tmp = (tmp & SystemControl_CPUID_REVISION(mask)) >> 0; in hri_systemcontrol_get_CPUID_REVISION_bf()
84 return tmp; in hri_systemcontrol_get_CPUID_REVISION_bf()
89 uint32_t tmp; in hri_systemcontrol_write_CPUID_REVISION_bf() local
91 tmp = ((Systemcontrol *)hw)->CPUID.reg; in hri_systemcontrol_write_CPUID_REVISION_bf()
92 tmp &= ~SystemControl_CPUID_REVISION_Msk; in hri_systemcontrol_write_CPUID_REVISION_bf()
93 tmp |= SystemControl_CPUID_REVISION(data); in hri_systemcontrol_write_CPUID_REVISION_bf()
94 ((Systemcontrol *)hw)->CPUID.reg = tmp; in hri_systemcontrol_write_CPUID_REVISION_bf()
114 uint32_t tmp; in hri_systemcontrol_read_CPUID_REVISION_bf() local
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| D | hri_supc_l21.h | 296 uint32_t tmp; in hri_supc_get_INTEN_reg() local
297 tmp = ((Supc *)hw)->INTENSET.reg; in hri_supc_get_INTEN_reg()
298 tmp &= mask; in hri_supc_get_INTEN_reg()
299 return tmp; in hri_supc_get_INTEN_reg()
500 uint32_t tmp; in hri_supc_get_INTFLAG_reg() local
501 tmp = ((Supc *)hw)->INTFLAG.reg; in hri_supc_get_INTFLAG_reg()
502 tmp &= mask; in hri_supc_get_INTFLAG_reg()
503 return tmp; in hri_supc_get_INTFLAG_reg()
525 uint32_t tmp; in hri_supc_get_BOD33_ENABLE_bit() local
526 tmp = ((Supc *)hw)->BOD33.reg; in hri_supc_get_BOD33_ENABLE_bit()
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| D | hri_eic_l21.h | 90 uint32_t tmp; in hri_eic_get_INTEN_EXTINT_bf() local
91 tmp = ((Eic *)hw)->INTENSET.reg; in hri_eic_get_INTEN_EXTINT_bf()
92 tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; in hri_eic_get_INTEN_EXTINT_bf()
93 return tmp; in hri_eic_get_INTEN_EXTINT_bf()
98 uint32_t tmp; in hri_eic_read_INTEN_EXTINT_bf() local
99 tmp = ((Eic *)hw)->INTENSET.reg; in hri_eic_read_INTEN_EXTINT_bf()
100 tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; in hri_eic_read_INTEN_EXTINT_bf()
101 return tmp; in hri_eic_read_INTEN_EXTINT_bf()
122 uint32_t tmp; in hri_eic_get_INTEN_reg() local
123 tmp = ((Eic *)hw)->INTENSET.reg; in hri_eic_get_INTEN_reg()
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| D | hri_pm_l21.h | 101 uint8_t tmp; in hri_pm_get_INTEN_reg() local
102 tmp = ((Pm *)hw)->INTENSET.reg; in hri_pm_get_INTEN_reg()
103 tmp &= mask; in hri_pm_get_INTEN_reg()
104 return tmp; in hri_pm_get_INTEN_reg()
145 uint8_t tmp; in hri_pm_get_INTFLAG_reg() local
146 tmp = ((Pm *)hw)->INTFLAG.reg; in hri_pm_get_INTFLAG_reg()
147 tmp &= mask; in hri_pm_get_INTFLAG_reg()
148 return tmp; in hri_pm_get_INTFLAG_reg()
170 uint8_t tmp; in hri_pm_get_CTRLA_IORET_bit() local
171 tmp = ((Pm *)hw)->CTRLA.reg; in hri_pm_get_CTRLA_IORET_bit()
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| D | hri_osc32kctrl_l21.h | 126 uint32_t tmp; in hri_osc32kctrl_get_INTEN_reg() local
127 tmp = ((Osc32kctrl *)hw)->INTENSET.reg; in hri_osc32kctrl_get_INTEN_reg()
128 tmp &= mask; in hri_osc32kctrl_get_INTEN_reg()
129 return tmp; in hri_osc32kctrl_get_INTEN_reg()
191 uint32_t tmp; in hri_osc32kctrl_get_INTFLAG_reg() local
192 tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; in hri_osc32kctrl_get_INTFLAG_reg()
193 tmp &= mask; in hri_osc32kctrl_get_INTFLAG_reg()
194 return tmp; in hri_osc32kctrl_get_INTFLAG_reg()
217 uint32_t tmp; in hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf() local
218 tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; in hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf()
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| D | hri_adc_l21.h | 174 uint8_t tmp; in hri_adc_get_INTEN_reg() local
175 tmp = ((Adc *)hw)->INTENSET.reg; in hri_adc_get_INTEN_reg()
176 tmp &= mask; in hri_adc_get_INTEN_reg()
177 return tmp; in hri_adc_get_INTEN_reg()
258 uint8_t tmp; in hri_adc_get_INTFLAG_reg() local
259 tmp = ((Adc *)hw)->INTFLAG.reg; in hri_adc_get_INTFLAG_reg()
260 tmp &= mask; in hri_adc_get_INTFLAG_reg()
261 return tmp; in hri_adc_get_INTFLAG_reg()
284 uint8_t tmp; in hri_adc_get_CTRLA_SWRST_bit() local
286 tmp = ((Adc *)hw)->CTRLA.reg; in hri_adc_get_CTRLA_SWRST_bit()
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| D | hri_oscctrl_l21.h | 350 uint32_t tmp; in hri_oscctrl_get_INTEN_reg() local
351 tmp = ((Oscctrl *)hw)->INTENSET.reg; in hri_oscctrl_get_INTEN_reg()
352 tmp &= mask; in hri_oscctrl_get_INTEN_reg()
353 return tmp; in hri_oscctrl_get_INTEN_reg()
595 uint32_t tmp; in hri_oscctrl_get_INTFLAG_reg() local
596 tmp = ((Oscctrl *)hw)->INTFLAG.reg; in hri_oscctrl_get_INTFLAG_reg()
597 tmp &= mask; in hri_oscctrl_get_INTFLAG_reg()
598 return tmp; in hri_oscctrl_get_INTFLAG_reg()
620 uint16_t tmp; in hri_oscctrl_get_XOSCCTRL_ENABLE_bit() local
621 tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; in hri_oscctrl_get_XOSCCTRL_ENABLE_bit()
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| D | hri_port_l21.h | 86 uint32_t tmp; in hri_portgroup_get_DIR_DIR_bf() local
87 tmp = ((PortGroup *)hw)->DIR.reg; in hri_portgroup_get_DIR_DIR_bf()
88 tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; in hri_portgroup_get_DIR_DIR_bf()
89 return tmp; in hri_portgroup_get_DIR_DIR_bf()
94 uint32_t tmp; in hri_portgroup_read_DIR_DIR_bf() local
95 tmp = ((PortGroup *)hw)->DIR.reg; in hri_portgroup_read_DIR_DIR_bf()
96 tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; in hri_portgroup_read_DIR_DIR_bf()
97 return tmp; in hri_portgroup_read_DIR_DIR_bf()
123 uint32_t tmp; in hri_portgroup_get_DIR_reg() local
124 tmp = ((PortGroup *)hw)->DIR.reg; in hri_portgroup_get_DIR_reg()
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| D | hri_opamp_l21.h | 75 uint8_t tmp; in hri_opamp_get_CTRLA_SWRST_bit() local
76 tmp = ((Opamp *)hw)->CTRLA.reg; in hri_opamp_get_CTRLA_SWRST_bit()
77 tmp = (tmp & OPAMP_CTRLA_SWRST) >> OPAMP_CTRLA_SWRST_Pos; in hri_opamp_get_CTRLA_SWRST_bit()
78 return (bool)tmp; in hri_opamp_get_CTRLA_SWRST_bit()
90 uint8_t tmp; in hri_opamp_get_CTRLA_ENABLE_bit() local
91 tmp = ((Opamp *)hw)->CTRLA.reg; in hri_opamp_get_CTRLA_ENABLE_bit()
92 tmp = (tmp & OPAMP_CTRLA_ENABLE) >> OPAMP_CTRLA_ENABLE_Pos; in hri_opamp_get_CTRLA_ENABLE_bit()
93 return (bool)tmp; in hri_opamp_get_CTRLA_ENABLE_bit()
98 uint8_t tmp; in hri_opamp_write_CTRLA_ENABLE_bit() local
100 tmp = ((Opamp *)hw)->CTRLA.reg; in hri_opamp_write_CTRLA_ENABLE_bit()
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| D | hri_sercom_l21.h | 273 uint8_t tmp; in hri_sercomspi_get_INTEN_reg() local
274 tmp = ((Sercom *)hw)->SPI.INTENSET.reg; in hri_sercomspi_get_INTEN_reg()
275 tmp &= mask; in hri_sercomspi_get_INTEN_reg()
276 return tmp; in hri_sercomspi_get_INTEN_reg()
398 uint8_t tmp; in hri_sercomspi_get_INTFLAG_reg() local
399 tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; in hri_sercomspi_get_INTFLAG_reg()
400 tmp &= mask; in hri_sercomspi_get_INTFLAG_reg()
401 return tmp; in hri_sercomspi_get_INTFLAG_reg()
424 uint32_t tmp; in hri_sercomspi_get_CTRLA_SWRST_bit() local
426 tmp = ((Sercom *)hw)->SPI.CTRLA.reg; in hri_sercomspi_get_CTRLA_SWRST_bit()
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| D | hri_ccl_l21.h | 75 uint8_t tmp; in hri_ccl_get_CTRL_SWRST_bit() local
76 tmp = ((Ccl *)hw)->CTRL.reg; in hri_ccl_get_CTRL_SWRST_bit()
77 tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; in hri_ccl_get_CTRL_SWRST_bit()
78 return (bool)tmp; in hri_ccl_get_CTRL_SWRST_bit()
90 uint8_t tmp; in hri_ccl_get_CTRL_ENABLE_bit() local
91 tmp = ((Ccl *)hw)->CTRL.reg; in hri_ccl_get_CTRL_ENABLE_bit()
92 tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; in hri_ccl_get_CTRL_ENABLE_bit()
93 return (bool)tmp; in hri_ccl_get_CTRL_ENABLE_bit()
98 uint8_t tmp; in hri_ccl_write_CTRL_ENABLE_bit() local
100 tmp = ((Ccl *)hw)->CTRL.reg; in hri_ccl_write_CTRL_ENABLE_bit()
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| D | hri_systick_l21.h | 76 uint32_t tmp; in hri_systick_get_CSR_ENABLE_bit() local
77 tmp = ((Systick *)hw)->CSR.reg; in hri_systick_get_CSR_ENABLE_bit()
78 tmp = (tmp & SysTick_CSR_ENABLE) >> 0; in hri_systick_get_CSR_ENABLE_bit()
79 return (bool)tmp; in hri_systick_get_CSR_ENABLE_bit()
84 uint32_t tmp; in hri_systick_write_CSR_ENABLE_bit() local
86 tmp = ((Systick *)hw)->CSR.reg; in hri_systick_write_CSR_ENABLE_bit()
87 tmp &= ~SysTick_CSR_ENABLE; in hri_systick_write_CSR_ENABLE_bit()
88 tmp |= value << 0; in hri_systick_write_CSR_ENABLE_bit()
89 ((Systick *)hw)->CSR.reg = tmp; in hri_systick_write_CSR_ENABLE_bit()
116 uint32_t tmp; in hri_systick_get_CSR_TICKINT_bit() local
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| D | hri_nvmctrl_l21.h | 127 uint8_t tmp; in hri_nvmctrl_get_INTEN_reg() local
128 tmp = ((Nvmctrl *)hw)->INTENSET.reg; in hri_nvmctrl_get_INTEN_reg()
129 tmp &= mask; in hri_nvmctrl_get_INTEN_reg()
130 return tmp; in hri_nvmctrl_get_INTEN_reg()
192 uint8_t tmp; in hri_nvmctrl_get_INTFLAG_reg() local
193 tmp = ((Nvmctrl *)hw)->INTFLAG.reg; in hri_nvmctrl_get_INTFLAG_reg()
194 tmp &= mask; in hri_nvmctrl_get_INTFLAG_reg()
195 return tmp; in hri_nvmctrl_get_INTFLAG_reg()
217 uint16_t tmp; in hri_nvmctrl_get_CTRLA_CMD_bf() local
218 tmp = ((Nvmctrl *)hw)->CTRLA.reg; in hri_nvmctrl_get_CTRLA_CMD_bf()
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| D | hri_aes_l21.h | 131 uint8_t tmp; in hri_aes_get_INTEN_reg() local
132 tmp = ((Aes *)hw)->INTENSET.reg; in hri_aes_get_INTEN_reg()
133 tmp &= mask; in hri_aes_get_INTEN_reg()
134 return tmp; in hri_aes_get_INTEN_reg()
195 uint8_t tmp; in hri_aes_get_INTFLAG_reg() local
196 tmp = ((Aes *)hw)->INTFLAG.reg; in hri_aes_get_INTFLAG_reg()
197 tmp &= mask; in hri_aes_get_INTFLAG_reg()
198 return tmp; in hri_aes_get_INTFLAG_reg()
241 uint32_t tmp; in hri_aes_get_CTRLA_SWRST_bit() local
242 tmp = ((Aes *)hw)->CTRLA.reg; in hri_aes_get_CTRLA_SWRST_bit()
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| D | hri_ac_l21.h | 165 uint8_t tmp; in hri_ac_get_INTEN_reg() local
166 tmp = ((Ac *)hw)->INTENSET.reg; in hri_ac_get_INTEN_reg()
167 tmp &= mask; in hri_ac_get_INTEN_reg()
168 return tmp; in hri_ac_get_INTEN_reg()
249 uint8_t tmp; in hri_ac_get_INTFLAG_reg() local
250 tmp = ((Ac *)hw)->INTFLAG.reg; in hri_ac_get_INTFLAG_reg()
251 tmp &= mask; in hri_ac_get_INTFLAG_reg()
252 return tmp; in hri_ac_get_INTFLAG_reg()
282 uint8_t tmp; in hri_ac_get_CTRLA_SWRST_bit() local
284 tmp = ((Ac *)hw)->CTRLA.reg; in hri_ac_get_CTRLA_SWRST_bit()
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| D | hri_gclk_l21.h | 88 uint8_t tmp; in hri_gclk_get_CTRLA_SWRST_bit() local
90 tmp = ((Gclk *)hw)->CTRLA.reg; in hri_gclk_get_CTRLA_SWRST_bit()
91 tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; in hri_gclk_get_CTRLA_SWRST_bit()
92 return (bool)tmp; in hri_gclk_get_CTRLA_SWRST_bit()
104 uint8_t tmp; in hri_gclk_get_CTRLA_reg() local
105 tmp = ((Gclk *)hw)->CTRLA.reg; in hri_gclk_get_CTRLA_reg()
106 tmp &= mask; in hri_gclk_get_CTRLA_reg()
107 return tmp; in hri_gclk_get_CTRLA_reg()
145 uint32_t tmp; in hri_gclk_get_GENCTRL_GENEN_bit() local
146 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
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| D | hri_dac_l21.h | 188 uint8_t tmp; in hri_dac_get_INTEN_reg() local
189 tmp = ((Dac *)hw)->INTENSET.reg; in hri_dac_get_INTEN_reg()
190 tmp &= mask; in hri_dac_get_INTEN_reg()
191 return tmp; in hri_dac_get_INTEN_reg()
292 uint8_t tmp; in hri_dac_get_INTFLAG_reg() local
293 tmp = ((Dac *)hw)->INTFLAG.reg; in hri_dac_get_INTFLAG_reg()
294 tmp &= mask; in hri_dac_get_INTFLAG_reg()
295 return tmp; in hri_dac_get_INTFLAG_reg()
332 uint8_t tmp; in hri_dac_get_CTRLA_SWRST_bit() local
334 tmp = ((Dac *)hw)->CTRLA.reg; in hri_dac_get_CTRLA_SWRST_bit()
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| D | hri_tc_l21.h | 104 uint16_t tmp; in hri_tccount16_get_COUNT_COUNT_bf() local
105 tmp = ((Tc *)hw)->COUNT16.COUNT.reg; in hri_tccount16_get_COUNT_COUNT_bf()
106 tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; in hri_tccount16_get_COUNT_COUNT_bf()
107 return tmp; in hri_tccount16_get_COUNT_COUNT_bf()
112 uint16_t tmp; in hri_tccount16_write_COUNT_COUNT_bf() local
114 tmp = ((Tc *)hw)->COUNT16.COUNT.reg; in hri_tccount16_write_COUNT_COUNT_bf()
115 tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; in hri_tccount16_write_COUNT_COUNT_bf()
116 tmp |= TC_COUNT16_COUNT_COUNT(data); in hri_tccount16_write_COUNT_COUNT_bf()
117 ((Tc *)hw)->COUNT16.COUNT.reg = tmp; in hri_tccount16_write_COUNT_COUNT_bf()
137 uint16_t tmp; in hri_tccount16_read_COUNT_COUNT_bf() local
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| D | hri_mtb_l21.h | 94 uint32_t tmp; in hri_mtb_get_CLAIM_reg() local
95 tmp = ((Mtb *)hw)->CLAIMSET.reg; in hri_mtb_get_CLAIM_reg()
96 tmp &= mask; in hri_mtb_get_CLAIM_reg()
97 return tmp; in hri_mtb_get_CLAIM_reg()
125 uint32_t tmp; in hri_mtb_get_POSITION_reg() local
126 tmp = ((Mtb *)hw)->POSITION.reg; in hri_mtb_get_POSITION_reg()
127 tmp &= mask; in hri_mtb_get_POSITION_reg()
128 return tmp; in hri_mtb_get_POSITION_reg()
166 uint32_t tmp; in hri_mtb_get_MASTER_reg() local
167 tmp = ((Mtb *)hw)->MASTER.reg; in hri_mtb_get_MASTER_reg()
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| D | hri_rtc_l21.h | 141 uint32_t tmp; in hri_rtcalarm_get_ALARM_SECOND_bf() local
142 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; in hri_rtcalarm_get_ALARM_SECOND_bf()
143 tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; in hri_rtcalarm_get_ALARM_SECOND_bf()
144 return tmp; in hri_rtcalarm_get_ALARM_SECOND_bf()
150 uint32_t tmp; in hri_rtcalarm_write_ALARM_SECOND_bf() local
152 tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; in hri_rtcalarm_write_ALARM_SECOND_bf()
153 tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; in hri_rtcalarm_write_ALARM_SECOND_bf()
154 tmp |= RTC_MODE2_ALARM_SECOND(data); in hri_rtcalarm_write_ALARM_SECOND_bf()
155 ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; in hri_rtcalarm_write_ALARM_SECOND_bf()
177 uint32_t tmp; in hri_rtcalarm_read_ALARM_SECOND_bf() local
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