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Searched refs:reg_value (Results 1 – 23 of 23) sorted by relevance

/Zephyr-latest/drivers/pinctrl/
Dpinctrl_eos_s3.c65 uint32_t reg_value = 0; in pinctrl_eos_s3_configure_pin() local
68 reg_value |= (pin->iof & PAD_FUNC_SEL_MASK); in pinctrl_eos_s3_configure_pin()
71 WRITE_BIT(reg_value, PAD_OUTPUT_EN_BIT, pin->output_enable ? 0 : 1); in pinctrl_eos_s3_configure_pin()
74 WRITE_BIT(reg_value, PAD_INPUT_EN_BIT, pin->input_enable); in pinctrl_eos_s3_configure_pin()
75 WRITE_BIT(reg_value, PAD_SLEW_RATE_BIT, pin->slew_rate); in pinctrl_eos_s3_configure_pin()
76 WRITE_BIT(reg_value, PAD_SCHMITT_EN_BIT, pin->schmitt_enable); in pinctrl_eos_s3_configure_pin()
77 WRITE_BIT(reg_value, PAD_CTRL_SEL_BIT0, pin->control_selection & BIT(0)); in pinctrl_eos_s3_configure_pin()
78 WRITE_BIT(reg_value, PAD_CTRL_SEL_BIT1, pin->control_selection & BIT(1)); in pinctrl_eos_s3_configure_pin()
82 WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 0); in pinctrl_eos_s3_configure_pin()
83 WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 0); in pinctrl_eos_s3_configure_pin()
[all …]
/Zephyr-latest/drivers/sensor/vishay/vcnl36825t/
Dvcnl36825t.c272 uint16_t reg_value; in vcnl36825t_init_registers() local
292 reg_value = 0x01; /* must be set according to datasheet */ in vcnl36825t_init_registers()
293 reg_value |= VCNL36825T_PS_ON; in vcnl36825t_init_registers()
295 rc = vcnl36825t_write(&config->i2c, VCNL36825T_REG_PS_CONF1, reg_value); in vcnl36825t_init_registers()
301 reg_value |= VCNL36825T_PS_CAL; in vcnl36825t_init_registers()
302 reg_value |= 1 << 9; /* reserved, must be set by datasheet */ in vcnl36825t_init_registers()
304 rc = vcnl36825t_write(&config->i2c, VCNL36825T_REG_PS_CONF1, reg_value); in vcnl36825t_init_registers()
312 reg_value = 0; in vcnl36825t_init_registers()
316 reg_value |= VCNL36825T_PS_PERIOD_10MS; in vcnl36825t_init_registers()
319 reg_value |= VCNL36825T_PS_PERIOD_20MS; in vcnl36825t_init_registers()
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Dvcnl36825t_trigger.c97 uint16_t reg_value; in vcnl36825t_thread_cb() local
109 rc = vcnl36825t_read(&config->i2c, VCNL36825T_REG_INT_FLAG, &reg_value); in vcnl36825t_thread_cb()
115 if (FIELD_GET(VCNL36825T_PS_IF_AWAY_MSK, reg_value) == 1) { in vcnl36825t_thread_cb()
117 } else if (FIELD_GET(VCNL36825T_PS_IF_CLOSE_MSK, reg_value) == 1) { in vcnl36825t_thread_cb()
119 } else if (FIELD_GET(VCNL36825T_PS_SPFLAG_MSK, reg_value) == 1) { in vcnl36825t_thread_cb()
121 } else if (FIELD_GET(VCNL36825T_PS_ACFLAG_MSK, reg_value) == 1) { in vcnl36825t_thread_cb()
243 uint8_t reg_value; in vcnl36825t_trigger_init() local
260 reg_value = VCNL36825T_PS_INT_DISABLE; in vcnl36825t_trigger_init()
263 reg_value |= VCNL36825T_PS_SMART_PERS_ENABLED; in vcnl36825t_trigger_init()
268 reg_value |= VCNL36825T_PS_PERS_1; in vcnl36825t_trigger_init()
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/Zephyr-latest/drivers/mfd/
Dmfd_max31790.c36 uint8_t reg_value; in max31790_init() local
43 reg_value = 0; in max31790_init()
44 reg_value &= ~MAX37190_GLOBALCONFIGURATION_STANDBY_BIT; in max31790_init()
45 reg_value |= MAX37190_GLOBALCONFIGURATION_RESET_BIT; in max31790_init()
46 reg_value |= MAX37190_GLOBALCONFIGURATION_BUSTIMEOUT_BIT; in max31790_init()
47 reg_value &= ~MAX37190_GLOBALCONFIGURATION_OSCILLATORSELECTION_BIT; in max31790_init()
48 max31790_set_globalconfiguration_i2cwatchdog(&reg_value, 0); in max31790_init()
49 reg_value &= ~MAX37190_GLOBALCONFIGURATION_I2CWATCHDOGSTATUS_BIT; in max31790_init()
52 reg_value); in max31790_init()
60 &reg_value); in max31790_init()
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/Zephyr-latest/drivers/ethernet/phy/
Dphy_qualcomm_ar8031.c108 uint16_t reg_value = (device & MII_MMD_ACR_DEVAD_MASK) | MII_MMD_ACR_ADDR; in qc_ar8031_mmd_set_device() local
110 if (qc_ar8031_write(dev, MII_MMD_ACR, reg_value) < 0) { in qc_ar8031_mmd_set_device()
161 uint32_t reg_value; in qc_ar8031_update_link_state() local
164 if (qc_ar8031_read(dev, PHY_SPECIFIC_STATUS_REG, &reg_value) < 0) { in qc_ar8031_update_link_state()
168 link_up = (uint16_t)reg_value & SPEC_STATUS_REG_LINK_MASK; in qc_ar8031_update_link_state()
182 if (qc_ar8031_read(dev, PHY_SPECIFIC_STATUS_REG, &reg_value) < 0) { in qc_ar8031_update_link_state()
186 speed = reg_value & SPEC_STATUS_REG_SPEED_MASK; in qc_ar8031_update_link_state()
187 duplex = reg_value & SPEC_STATUS_REG_DUPLEX_MASK; in qc_ar8031_update_link_state()
361 uint32_t reg_value = 0; in qc_ar8031_init() local
374 if (qc_ar8031_read(dev, MII_PHYID1R, &reg_value) < 0) { in qc_ar8031_init()
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/Zephyr-latest/drivers/gpio/
Dgpio_adp5585.c76 uint8_t reg_value; in gpio_adp5585_config() local
105 reg_value = adp5585_pin_drive_od << bank_pin; in gpio_adp5585_config()
107 reg_value = adp5585_pin_drive_pp << bank_pin; in gpio_adp5585_config()
110 BIT(bank_pin), reg_value); in gpio_adp5585_config()
123 reg_value = adp5585_pull_up_300k << shift; in gpio_adp5585_config()
125 reg_value = adp5585_pull_dn_300k << shift; in gpio_adp5585_config()
127 reg_value = adp5585_pull_disable << shift; in gpio_adp5585_config()
131 0b11U << shift, reg_value); in gpio_adp5585_config()
147 reg_value = (uint8_t)data->output; in gpio_adp5585_config()
150 reg_value = (uint8_t)(data->output >> 8); in gpio_adp5585_config()
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Dgpio_pca_series.c901 uint32_t reg_value = 0; in gpio_pca_series_pin_configure() local
937 PCA_REG_TYPE_1B_OUTPUT_CONFIG, (uint8_t *)&reg_value); in gpio_pca_series_pin_configure()
938 reg_value = sys_le32_to_cpu(reg_value); in gpio_pca_series_pin_configure()
940 reg_value |= (BIT(pin)); /* set bit to set open-drain */ in gpio_pca_series_pin_configure()
942 reg_value &= (~BIT(pin)); /* clear bit to set push-pull */ in gpio_pca_series_pin_configure()
944 reg_value = sys_cpu_to_le32(reg_value); in gpio_pca_series_pin_configure()
946 PCA_REG_TYPE_1B_OUTPUT_CONFIG, (uint8_t *)&reg_value); in gpio_pca_series_pin_configure()
953 PCA_REG_TYPE_1B_PULL_SELECT, (uint8_t *)&reg_value); in gpio_pca_series_pin_configure()
954 reg_value = sys_le32_to_cpu(reg_value); in gpio_pca_series_pin_configure()
956 reg_value |= (BIT(pin)); in gpio_pca_series_pin_configure()
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Dgpio_stmpe1600.c183 uint16_t reg_value; in stmpe1600_port_get_raw() local
191 ret = read_reg16(dev->config, REG_GPMR_LSB, &reg_value); in stmpe1600_port_get_raw()
195 *value = reg_value; in stmpe1600_port_get_raw()
Dgpio_mfxstm32l152.c375 uint32_t reg_value; in mfxstm32l152_port_get_raw() local
384 ret = read_port_regs(dev, REG_GPIO_STATE, &reg_value); in mfxstm32l152_port_get_raw()
388 *value = reg_value; in mfxstm32l152_port_get_raw()
/Zephyr-latest/drivers/stepper/adi_tmc/
Dadi_tmc50xx_stepper_controller.c110 uint32_t reg_value; in stallguard_enable() local
113 err = tmc50xx_read(config->controller, TMC50XX_SWMODE(config->index), &reg_value); in stallguard_enable()
120 reg_value |= TMC5XXX_SW_MODE_SG_STOP_ENABLE; in stallguard_enable()
139 reg_value &= ~TMC5XXX_SW_MODE_SG_STOP_ENABLE; in stallguard_enable()
141 err = tmc50xx_write(config->controller, TMC50XX_SWMODE(config->index), reg_value); in stallguard_enable()
265 uint32_t reg_value; in tmc50xx_stepper_enable() local
268 err = tmc50xx_read(config->controller, TMC50XX_CHOPCONF(config->index), &reg_value); in tmc50xx_stepper_enable()
274 reg_value |= TMC5XXX_CHOPCONF_DRV_ENABLE_MASK; in tmc50xx_stepper_enable()
276 reg_value &= ~TMC5XXX_CHOPCONF_DRV_ENABLE_MASK; in tmc50xx_stepper_enable()
279 err = tmc50xx_write(config->controller, TMC50XX_CHOPCONF(config->index), reg_value); in tmc50xx_stepper_enable()
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/Zephyr-latest/drivers/sensor/amd_sb_tsi/
Dsb_tsi_emul.c108 int32_t reg_value; in sb_tsi_emul_set_channel() local
116 reg_value = CLAMP(millicelsius / 125, 0, 0x7ff); in sb_tsi_emul_set_channel()
118 data->reg[SB_TSI_TEMP_INT] = reg_value >> 3; in sb_tsi_emul_set_channel()
119 data->reg[SB_TSI_TEMP_DEC] = (reg_value & 0x7) << 5; in sb_tsi_emul_set_channel()
/Zephyr-latest/drivers/reset/
Dreset_ast10x0.c66 uint32_t reg_value; in aspeed_reset_status() local
74 ret = syscon_read_reg(syscon, addr, &reg_value); in aspeed_reset_status()
76 *status = !!(reg_value & BIT(id)); in aspeed_reset_status()
/Zephyr-latest/drivers/sensor/f75303/
Df75303_emul.c112 int32_t reg_value; in f75303_emul_set_channel() local
134 reg_value = CLAMP(millicelsius / 125, 0, 0x7ff); in f75303_emul_set_channel()
136 data->reg[reg_h] = reg_value >> 3; in f75303_emul_set_channel()
137 data->reg[reg_l] = (reg_value & 0x7) << 5; in f75303_emul_set_channel()
/Zephyr-latest/drivers/sensor/bosch/bmi160/
Demul_bmi160.c499 int64_t reg_value = intermediate / scale; in bmi160_emul_backend_set_offset() local
502 (reg_value >= INT8_MIN && reg_value <= INT8_MAX)); in bmi160_emul_backend_set_offset()
504 (reg_value >= -0x1ff - 1 && reg_value <= 0x1ff)); in bmi160_emul_backend_set_offset()
506 cfg->reg[BMI160_REG_OFFSET_ACC_X + i] = reg_value & 0xff; in bmi160_emul_backend_set_offset()
508 cfg->reg[BMI160_REG_OFFSET_GYR_X + i] = reg_value & 0xff; in bmi160_emul_backend_set_offset()
511 (reg_value & GENMASK(9, 8)); in bmi160_emul_backend_set_offset()
/Zephyr-latest/drivers/sensor/adi/adt7310/
Dadt7310.c158 uint8_t reg_value; in adt7310_update_reg() local
160 ret = adt7310_reg_read(dev, reg, &reg_value); in adt7310_update_reg()
165 reg_value &= ~mask; in adt7310_update_reg()
166 reg_value |= value; in adt7310_update_reg()
168 return adt7310_reg_write(dev, reg, reg_value); in adt7310_update_reg()
/Zephyr-latest/modules/nrf_wifi/bus/
Dspi_if.c85 int spim_read_reg(uint32_t reg_addr, uint8_t *reg_value) in spim_read_reg() argument
113 *reg_value = sr[1]; in spim_read_reg()
119 int spim_write_reg(uint32_t reg_addr, const uint8_t reg_value) in spim_write_reg() argument
122 uint8_t tx_buffer[] = { reg_addr, reg_value }; in spim_write_reg()
/Zephyr-latest/drivers/sensor/ti/tmp108/
Dtmp108.c204 __maybe_unused uint16_t reg_value; in tmp108_attr_set() local
250 reg_value = (uval * TMP108_TEMP_DIVISOR(dev)) / TMP108_TEMP_MULTIPLIER(dev); in tmp108_attr_set()
253 reg_value); in tmp108_attr_set()
258 reg_value = (uval * TMP108_TEMP_DIVISOR(dev)) / TMP108_TEMP_MULTIPLIER(dev); in tmp108_attr_set()
261 reg_value); in tmp108_attr_set()
/Zephyr-latest/drivers/sensor/bosch/bmi323/
Dbmi323.h174 #define IMU_BOSCH_BMI323_REG_VALUE_GET_FIELD(reg_value, reg, field) \ argument
175 ((reg_value >> IMU_BOSCH_BMI323_REG_##reg##_##field##_OFFSET) & \
/Zephyr-latest/drivers/sensor/st/iis328dq/
Diis328dq.c310 uint8_t reg_value; in iis328dq_init() local
315 if (iis328dq_device_id_get(ctx, &reg_value) < 0) { in iis328dq_init()
319 if (reg_value != IIS328DQ_ID) { in iis328dq_init()
331 if (iis328dq_boot_get(ctx, &reg_value) < 0) { in iis328dq_init()
334 if (reg_value != PROPERTY_DISABLE) { in iis328dq_init()
/Zephyr-latest/drivers/adc/
Dadc_cc13xx_cc26xx.c42 uint8_t reg_value; member
152 data->sample_time = adc_cc13xx_sample_times[0].reg_value; in adc_cc13xx_cc26xx_channel_setup()
157 data->sample_time = adc_cc13xx_sample_times[i].reg_value; in adc_cc13xx_cc26xx_channel_setup()
/Zephyr-latest/drivers/flash/
Dflash_cadence_nand_ll.c59 uint32_t reg_value = 0; in cdns_nand_device_info() local
65 reg_value = sys_read32(CNF_CTRLPARAM(base_address, VERSION)); in cdns_nand_device_info()
66 nf_ver = (struct nf_ctrl_version *)&reg_value; in cdns_nand_device_info()
74 reg_value = sys_read32(CNF_CTRLPARAM(base_address, DEV_PARAMS0)); in cdns_nand_device_info()
75 type = CNF_GET_DEV_TYPE(reg_value); in cdns_nand_device_info()
81 params->nluns = CNF_GET_NLUNS(reg_value); in cdns_nand_device_info()
85 reg_value = sys_read32(CNF_CTRLCFG(base_address, DEV_LAYOUT)); in cdns_nand_device_info()
86 params->npages_per_block = GET_PAGES_PER_BLOCK(reg_value); in cdns_nand_device_info()
89 reg_value = sys_read32(CNF_CTRLPARAM(base_address, DEV_AREA)); in cdns_nand_device_info()
90 params->page_size = GET_PAGE_SIZE(reg_value); in cdns_nand_device_info()
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/Zephyr-latest/drivers/usb_c/tcpc/
Dtcpci.c572 uint8_t reg_value = 0; in tcpci_tcpm_get_rp_value() local
575 ret = tcpci_read_reg8(bus, TCPC_REG_ROLE_CTRL, &reg_value); in tcpci_tcpm_get_rp_value()
576 *rp = TCPC_REG_ROLE_CTRL_RP(reg_value); in tcpci_tcpm_get_rp_value()
/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.c1355 uint32_t reg_value = MCP251XFD_REG_OSC_OSCRDY; in mcp251xfd_init_osc_reg() local
1361 reg_value |= MCP251XFD_REG_OSC_PLLRDY; in mcp251xfd_init_osc_reg()
1371 return mcp251xfd_reg_check_value_wtimeout(dev, MCP251XFD_REG_OSC, reg_value, reg_value, in mcp251xfd_init_osc_reg()