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Searched refs:hw (Results 1 – 25 of 63) sorted by relevance

123

/loramac-node-3.4.0/src/boards/mcu/saml21/hri/
Dhri_evsys_l21.h70 static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw) in hri_evsys_set_INTEN_OVR0_bit() argument
72 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; in hri_evsys_set_INTEN_OVR0_bit()
75 static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw) in hri_evsys_get_INTEN_OVR0_bit() argument
77 return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos; in hri_evsys_get_INTEN_OVR0_bit()
80 static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value) in hri_evsys_write_INTEN_OVR0_bit() argument
83 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; in hri_evsys_write_INTEN_OVR0_bit()
85 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; in hri_evsys_write_INTEN_OVR0_bit()
89 static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw) in hri_evsys_clear_INTEN_OVR0_bit() argument
91 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; in hri_evsys_clear_INTEN_OVR0_bit()
94 static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw) in hri_evsys_set_INTEN_OVR1_bit() argument
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Dhri_pac_l21.h77 static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) in hri_pac_set_INTEN_ERR_bit() argument
79 ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; in hri_pac_set_INTEN_ERR_bit()
82 static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) in hri_pac_get_INTEN_ERR_bit() argument
84 return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; in hri_pac_get_INTEN_ERR_bit()
87 static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) in hri_pac_write_INTEN_ERR_bit() argument
90 ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; in hri_pac_write_INTEN_ERR_bit()
92 ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; in hri_pac_write_INTEN_ERR_bit()
96 static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) in hri_pac_clear_INTEN_ERR_bit() argument
98 ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; in hri_pac_clear_INTEN_ERR_bit()
101 static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) in hri_pac_set_INTEN_reg() argument
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Dhri_adc_l21.h84 static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) in hri_adc_wait_for_sync() argument
86 while (((Adc *)hw)->SYNCBUSY.reg & reg) { in hri_adc_wait_for_sync()
90 static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) in hri_adc_is_syncing() argument
92 return ((Adc *)hw)->SYNCBUSY.reg & reg; in hri_adc_is_syncing()
95 static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) in hri_adc_set_INTEN_RESRDY_bit() argument
97 ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; in hri_adc_set_INTEN_RESRDY_bit()
100 static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) in hri_adc_get_INTEN_RESRDY_bit() argument
102 return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; in hri_adc_get_INTEN_RESRDY_bit()
105 static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) in hri_adc_write_INTEN_RESRDY_bit() argument
108 ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; in hri_adc_write_INTEN_RESRDY_bit()
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Dhri_sercom_l21.h101 static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t… in hri_sercomi2cm_wait_for_sync() argument
103 while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { in hri_sercomi2cm_wait_for_sync()
107 static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t re… in hri_sercomi2cm_is_syncing() argument
109 return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; in hri_sercomi2cm_is_syncing()
112 static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t… in hri_sercomi2cs_wait_for_sync() argument
114 while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { in hri_sercomi2cs_wait_for_sync()
118 static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t re… in hri_sercomi2cs_is_syncing() argument
120 return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; in hri_sercomi2cs_is_syncing()
123 static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t r… in hri_sercomspi_wait_for_sync() argument
125 while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { in hri_sercomspi_wait_for_sync()
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Dhri_oscctrl_l21.h78 static inline void hri_oscctrl_set_INTEN_XOSCRDY_bit(const void *const hw) in hri_oscctrl_set_INTEN_XOSCRDY_bit() argument
80 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_set_INTEN_XOSCRDY_bit()
83 static inline bool hri_oscctrl_get_INTEN_XOSCRDY_bit(const void *const hw) in hri_oscctrl_get_INTEN_XOSCRDY_bit() argument
85 return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY) >> OSCCTRL_INTENSET_XOSCRDY_Pos; in hri_oscctrl_get_INTEN_XOSCRDY_bit()
88 static inline void hri_oscctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value) in hri_oscctrl_write_INTEN_XOSCRDY_bit() argument
91 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_write_INTEN_XOSCRDY_bit()
93 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_write_INTEN_XOSCRDY_bit()
97 static inline void hri_oscctrl_clear_INTEN_XOSCRDY_bit(const void *const hw) in hri_oscctrl_clear_INTEN_XOSCRDY_bit() argument
99 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_clear_INTEN_XOSCRDY_bit()
102 static inline void hri_oscctrl_set_INTEN_OSC16MRDY_bit(const void *const hw) in hri_oscctrl_set_INTEN_OSC16MRDY_bit() argument
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Dhri_supc_l21.h73 static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) in hri_supc_set_INTEN_BOD33RDY_bit() argument
75 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_set_INTEN_BOD33RDY_bit()
78 static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) in hri_supc_get_INTEN_BOD33RDY_bit() argument
80 return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; in hri_supc_get_INTEN_BOD33RDY_bit()
83 static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) in hri_supc_write_INTEN_BOD33RDY_bit() argument
86 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_write_INTEN_BOD33RDY_bit()
88 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_write_INTEN_BOD33RDY_bit()
92 static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) in hri_supc_clear_INTEN_BOD33RDY_bit() argument
94 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_clear_INTEN_BOD33RDY_bit()
97 static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) in hri_supc_set_INTEN_BOD33DET_bit() argument
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Dhri_tcc_l21.h83 static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) in hri_tcc_wait_for_sync() argument
85 while (((Tcc *)hw)->SYNCBUSY.reg & reg) { in hri_tcc_wait_for_sync()
89 static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) in hri_tcc_is_syncing() argument
91 return ((Tcc *)hw)->SYNCBUSY.reg & reg; in hri_tcc_is_syncing()
94 static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) in hri_tcc_set_COUNT_DITH4_COUNT_bf() argument
97 ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH4_COUNT(mask); in hri_tcc_set_COUNT_DITH4_COUNT_bf()
101 static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_co… in hri_tcc_get_COUNT_DITH4_COUNT_bf() argument
104 tmp = ((Tcc *)hw)->COUNT.reg; in hri_tcc_get_COUNT_DITH4_COUNT_bf()
109 static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t dat… in hri_tcc_write_COUNT_DITH4_COUNT_bf() argument
113 tmp = ((Tcc *)hw)->COUNT.reg; in hri_tcc_write_COUNT_DITH4_COUNT_bf()
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Dhri_dmac_l21.h90 static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw) in hri_dmac_set_CHINTEN_TERR_bit() argument
92 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; in hri_dmac_set_CHINTEN_TERR_bit()
95 static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw) in hri_dmac_get_CHINTEN_TERR_bit() argument
97 return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; in hri_dmac_get_CHINTEN_TERR_bit()
100 static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value) in hri_dmac_write_CHINTEN_TERR_bit() argument
103 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; in hri_dmac_write_CHINTEN_TERR_bit()
105 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; in hri_dmac_write_CHINTEN_TERR_bit()
109 static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw) in hri_dmac_clear_CHINTEN_TERR_bit() argument
111 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; in hri_dmac_clear_CHINTEN_TERR_bit()
114 static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw) in hri_dmac_set_CHINTEN_TCMPL_bit() argument
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Dhri_dac_l21.h74 static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) in hri_dac_wait_for_sync() argument
76 while (((Dac *)hw)->SYNCBUSY.reg & reg) { in hri_dac_wait_for_sync()
80 static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) in hri_dac_is_syncing() argument
82 return ((Dac *)hw)->SYNCBUSY.reg & reg; in hri_dac_is_syncing()
85 static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) in hri_dac_set_INTEN_UNDERRUN0_bit() argument
87 ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; in hri_dac_set_INTEN_UNDERRUN0_bit()
90 static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) in hri_dac_get_INTEN_UNDERRUN0_bit() argument
92 return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; in hri_dac_get_INTEN_UNDERRUN0_bit()
95 static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) in hri_dac_write_INTEN_UNDERRUN0_bit() argument
98 ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; in hri_dac_write_INTEN_UNDERRUN0_bit()
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Dhri_mclk_l21.h75 static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) in hri_mclk_set_INTEN_CKRDY_bit() argument
77 ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; in hri_mclk_set_INTEN_CKRDY_bit()
80 static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) in hri_mclk_get_INTEN_CKRDY_bit() argument
82 return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; in hri_mclk_get_INTEN_CKRDY_bit()
85 static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) in hri_mclk_write_INTEN_CKRDY_bit() argument
88 ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; in hri_mclk_write_INTEN_CKRDY_bit()
90 ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; in hri_mclk_write_INTEN_CKRDY_bit()
94 static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) in hri_mclk_clear_INTEN_CKRDY_bit() argument
96 ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; in hri_mclk_clear_INTEN_CKRDY_bit()
99 static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) in hri_mclk_set_INTEN_reg() argument
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Dhri_tal_l21.h85 static inline void hri_tal_set_INTEN_BRK_bit(const void *const hw) in hri_tal_set_INTEN_BRK_bit() argument
87 ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_BRK; in hri_tal_set_INTEN_BRK_bit()
90 static inline bool hri_tal_get_INTEN_BRK_bit(const void *const hw) in hri_tal_get_INTEN_BRK_bit() argument
92 return (((Tal *)hw)->INTENSET.reg & TAL_INTENSET_BRK) >> TAL_INTENSET_BRK_Pos; in hri_tal_get_INTEN_BRK_bit()
95 static inline void hri_tal_write_INTEN_BRK_bit(const void *const hw, bool value) in hri_tal_write_INTEN_BRK_bit() argument
98 ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_BRK; in hri_tal_write_INTEN_BRK_bit()
100 ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_BRK; in hri_tal_write_INTEN_BRK_bit()
104 static inline void hri_tal_clear_INTEN_BRK_bit(const void *const hw) in hri_tal_clear_INTEN_BRK_bit() argument
106 ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_BRK; in hri_tal_clear_INTEN_BRK_bit()
109 static inline void hri_tal_set_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t mask) in hri_tal_set_INTEN_reg() argument
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Dhri_rtc_l21.h97 static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) in hri_rtcmode0_wait_for_sync() argument
99 while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { in hri_rtcmode0_wait_for_sync()
103 static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) in hri_rtcmode0_is_syncing() argument
105 return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; in hri_rtcmode0_is_syncing()
108 static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) in hri_rtcmode1_wait_for_sync() argument
110 while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { in hri_rtcmode1_wait_for_sync()
114 static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) in hri_rtcmode1_is_syncing() argument
116 return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; in hri_rtcmode1_is_syncing()
119 static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) in hri_rtcmode2_wait_for_sync() argument
121 while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { in hri_rtcmode2_wait_for_sync()
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Dhri_ac_l21.h75 static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) in hri_ac_wait_for_sync() argument
77 while (((Ac *)hw)->SYNCBUSY.reg & reg) { in hri_ac_wait_for_sync()
81 static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) in hri_ac_is_syncing() argument
83 return ((Ac *)hw)->SYNCBUSY.reg & reg; in hri_ac_is_syncing()
86 static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) in hri_ac_set_INTEN_COMP0_bit() argument
88 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; in hri_ac_set_INTEN_COMP0_bit()
91 static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) in hri_ac_get_INTEN_COMP0_bit() argument
93 return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; in hri_ac_get_INTEN_COMP0_bit()
96 static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) in hri_ac_write_INTEN_COMP0_bit() argument
99 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; in hri_ac_write_INTEN_COMP0_bit()
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Dhri_osc32kctrl_l21.h70 static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) in hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit() argument
72 ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit()
75 static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) in hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit() argument
77 …return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_… in hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit()
80 static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) in hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit() argument
83 ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit()
85 ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit()
89 static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) in hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit() argument
91 ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit()
94 static inline void hri_osc32kctrl_set_INTEN_OSC32KRDY_bit(const void *const hw) in hri_osc32kctrl_set_INTEN_OSC32KRDY_bit() argument
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Dhri_tc_l21.h84 static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) in hri_tc_wait_for_sync() argument
86 while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { in hri_tc_wait_for_sync()
90 static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) in hri_tc_is_syncing() argument
92 return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; in hri_tc_is_syncing()
95 static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) in hri_tccount16_set_COUNT_COUNT_bf() argument
98 ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); in hri_tccount16_set_COUNT_COUNT_bf()
102 static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, hri_tc_co… in hri_tccount16_get_COUNT_COUNT_bf() argument
105 tmp = ((Tc *)hw)->COUNT16.COUNT.reg; in hri_tccount16_get_COUNT_COUNT_bf()
110 static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t da… in hri_tccount16_write_COUNT_COUNT_bf() argument
114 tmp = ((Tc *)hw)->COUNT16.COUNT.reg; in hri_tccount16_write_COUNT_COUNT_bf()
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Dhri_usb_l21.h124 static inline void hri_usbdevice_wait_for_sync(const void *const hw, hri_usbdevice_syncbusy_reg_t r… in hri_usbdevice_wait_for_sync() argument
126 while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { in hri_usbdevice_wait_for_sync()
130 static inline bool hri_usbdevice_is_syncing(const void *const hw, hri_usbdevice_syncbusy_reg_t reg) in hri_usbdevice_is_syncing() argument
132 return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; in hri_usbdevice_is_syncing()
135 static inline void hri_usbhost_wait_for_sync(const void *const hw, hri_usbhost_syncbusy_reg_t reg) in hri_usbhost_wait_for_sync() argument
137 while (((Usb *)hw)->HOST.SYNCBUSY.reg & reg) { in hri_usbhost_wait_for_sync()
141 static inline bool hri_usbhost_is_syncing(const void *const hw, hri_usbhost_syncbusy_reg_t reg) in hri_usbhost_is_syncing() argument
143 return ((Usb *)hw)->HOST.SYNCBUSY.reg & reg; in hri_usbhost_is_syncing()
146 static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) in hri_usbpipe_set_PSTATUS_DTGL_bit() argument
148 ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; in hri_usbpipe_set_PSTATUS_DTGL_bit()
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Dhri_dsu_l21.h87 static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) in hri_dsu_write_CTRL_reg() argument
90 ((Dsu *)hw)->CTRL.reg = data; in hri_dsu_write_CTRL_reg()
94 static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) in hri_dsu_set_ADDR_AMOD_bf() argument
97 ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); in hri_dsu_set_ADDR_AMOD_bf()
101 static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t … in hri_dsu_get_ADDR_AMOD_bf() argument
104 tmp = ((Dsu *)hw)->ADDR.reg; in hri_dsu_get_ADDR_AMOD_bf()
109 static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) in hri_dsu_write_ADDR_AMOD_bf() argument
113 tmp = ((Dsu *)hw)->ADDR.reg; in hri_dsu_write_ADDR_AMOD_bf()
116 ((Dsu *)hw)->ADDR.reg = tmp; in hri_dsu_write_ADDR_AMOD_bf()
120 static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) in hri_dsu_clear_ADDR_AMOD_bf() argument
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Dhri_aes_l21.h76 static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) in hri_aes_set_INTEN_ENCCMP_bit() argument
78 ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; in hri_aes_set_INTEN_ENCCMP_bit()
81 static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) in hri_aes_get_INTEN_ENCCMP_bit() argument
83 return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; in hri_aes_get_INTEN_ENCCMP_bit()
86 static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) in hri_aes_write_INTEN_ENCCMP_bit() argument
89 ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; in hri_aes_write_INTEN_ENCCMP_bit()
91 ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; in hri_aes_write_INTEN_ENCCMP_bit()
95 static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) in hri_aes_clear_INTEN_ENCCMP_bit() argument
97 ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; in hri_aes_clear_INTEN_ENCCMP_bit()
100 static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) in hri_aes_set_INTEN_GFMCMP_bit() argument
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Dhri_nvic_l21.h75 static inline void hri_nvic_set_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t ma… in hri_nvic_set_NVICISER_SETENA_bf() argument
78 ((Nvic *)hw)->NVICISER.reg |= NVIC_NVICISER_SETENA(mask); in hri_nvic_set_NVICISER_SETENA_bf()
82 static inline hri_nvic_nviciser_reg_t hri_nvic_get_NVICISER_SETENA_bf(const void *const hw, in hri_nvic_get_NVICISER_SETENA_bf() argument
86 tmp = ((Nvic *)hw)->NVICISER.reg; in hri_nvic_get_NVICISER_SETENA_bf()
91 static inline void hri_nvic_write_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t … in hri_nvic_write_NVICISER_SETENA_bf() argument
95 tmp = ((Nvic *)hw)->NVICISER.reg; in hri_nvic_write_NVICISER_SETENA_bf()
98 ((Nvic *)hw)->NVICISER.reg = tmp; in hri_nvic_write_NVICISER_SETENA_bf()
102 static inline void hri_nvic_clear_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t … in hri_nvic_clear_NVICISER_SETENA_bf() argument
105 ((Nvic *)hw)->NVICISER.reg &= ~NVIC_NVICISER_SETENA(mask); in hri_nvic_clear_NVICISER_SETENA_bf()
109 static inline void hri_nvic_toggle_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t… in hri_nvic_toggle_NVICISER_SETENA_bf() argument
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Dhri_systemcontrol_l21.h71 static inline void hri_systemcontrol_set_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_… in hri_systemcontrol_set_CPUID_REVISION_bf() argument
74 ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_REVISION(mask); in hri_systemcontrol_set_CPUID_REVISION_bf()
78 …systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw, in hri_systemcontrol_get_CPUID_REVISION_bf() argument
82 tmp = ((Systemcontrol *)hw)->CPUID.reg; in hri_systemcontrol_get_CPUID_REVISION_bf()
87 static inline void hri_systemcontrol_write_CPUID_REVISION_bf(const void *const hw, hri_systemcontro… in hri_systemcontrol_write_CPUID_REVISION_bf() argument
91 tmp = ((Systemcontrol *)hw)->CPUID.reg; in hri_systemcontrol_write_CPUID_REVISION_bf()
94 ((Systemcontrol *)hw)->CPUID.reg = tmp; in hri_systemcontrol_write_CPUID_REVISION_bf()
98 static inline void hri_systemcontrol_clear_CPUID_REVISION_bf(const void *const hw, hri_systemcontro… in hri_systemcontrol_clear_CPUID_REVISION_bf() argument
101 ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_REVISION(mask); in hri_systemcontrol_clear_CPUID_REVISION_bf()
105 static inline void hri_systemcontrol_toggle_CPUID_REVISION_bf(const void *const hw, hri_systemcontr… in hri_systemcontrol_toggle_CPUID_REVISION_bf() argument
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Dhri_nvmctrl_l21.h71 static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw) in hri_nvmctrl_set_INTEN_READY_bit() argument
73 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_set_INTEN_READY_bit()
76 static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw) in hri_nvmctrl_get_INTEN_READY_bit() argument
78 return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; in hri_nvmctrl_get_INTEN_READY_bit()
81 static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value) in hri_nvmctrl_write_INTEN_READY_bit() argument
84 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_write_INTEN_READY_bit()
86 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_write_INTEN_READY_bit()
90 static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw) in hri_nvmctrl_clear_INTEN_READY_bit() argument
92 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_clear_INTEN_READY_bit()
95 static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw) in hri_nvmctrl_set_INTEN_ERROR_bit() argument
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Dhri_pm_l21.h70 static inline void hri_pm_set_INTEN_PLRDY_bit(const void *const hw) in hri_pm_set_INTEN_PLRDY_bit() argument
72 ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; in hri_pm_set_INTEN_PLRDY_bit()
75 static inline bool hri_pm_get_INTEN_PLRDY_bit(const void *const hw) in hri_pm_get_INTEN_PLRDY_bit() argument
77 return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_PLRDY) >> PM_INTENSET_PLRDY_Pos; in hri_pm_get_INTEN_PLRDY_bit()
80 static inline void hri_pm_write_INTEN_PLRDY_bit(const void *const hw, bool value) in hri_pm_write_INTEN_PLRDY_bit() argument
83 ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; in hri_pm_write_INTEN_PLRDY_bit()
85 ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; in hri_pm_write_INTEN_PLRDY_bit()
89 static inline void hri_pm_clear_INTEN_PLRDY_bit(const void *const hw) in hri_pm_clear_INTEN_PLRDY_bit() argument
91 ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; in hri_pm_clear_INTEN_PLRDY_bit()
94 static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) in hri_pm_set_INTEN_reg() argument
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Dhri_wdt_l21.h70 static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) in hri_wdt_wait_for_sync() argument
72 while (((Wdt *)hw)->SYNCBUSY.reg & reg) { in hri_wdt_wait_for_sync()
76 static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) in hri_wdt_is_syncing() argument
78 return ((Wdt *)hw)->SYNCBUSY.reg & reg; in hri_wdt_is_syncing()
81 static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) in hri_wdt_set_INTEN_EW_bit() argument
83 ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; in hri_wdt_set_INTEN_EW_bit()
86 static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) in hri_wdt_get_INTEN_EW_bit() argument
88 return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; in hri_wdt_get_INTEN_EW_bit()
91 static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) in hri_wdt_write_INTEN_EW_bit() argument
94 ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; in hri_wdt_write_INTEN_EW_bit()
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Dhri_eic_l21.h72 static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) in hri_eic_wait_for_sync() argument
74 while (((Eic *)hw)->SYNCBUSY.reg & reg) { in hri_eic_wait_for_sync()
78 static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) in hri_eic_is_syncing() argument
80 return ((Eic *)hw)->SYNCBUSY.reg & reg; in hri_eic_is_syncing()
83 static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) in hri_eic_set_INTEN_EXTINT_bf() argument
85 ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); in hri_eic_set_INTEN_EXTINT_bf()
88 static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_inte… in hri_eic_get_INTEN_EXTINT_bf() argument
91 tmp = ((Eic *)hw)->INTENSET.reg; in hri_eic_get_INTEN_EXTINT_bf()
96 static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) in hri_eic_read_INTEN_EXTINT_bf() argument
99 tmp = ((Eic *)hw)->INTENSET.reg; in hri_eic_read_INTEN_EXTINT_bf()
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Dhri_mtb_l21.h87 static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) in hri_mtb_set_CLAIM_reg() argument
89 ((Mtb *)hw)->CLAIMSET.reg = mask; in hri_mtb_set_CLAIM_reg()
92 static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_r… in hri_mtb_get_CLAIM_reg() argument
95 tmp = ((Mtb *)hw)->CLAIMSET.reg; in hri_mtb_get_CLAIM_reg()
100 static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw) in hri_mtb_read_CLAIM_reg() argument
102 return ((Mtb *)hw)->CLAIMSET.reg; in hri_mtb_read_CLAIM_reg()
105 static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data) in hri_mtb_write_CLAIM_reg() argument
107 ((Mtb *)hw)->CLAIMSET.reg = data; in hri_mtb_write_CLAIM_reg()
108 ((Mtb *)hw)->CLAIMCLR.reg = ~data; in hri_mtb_write_CLAIM_reg()
111 static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) in hri_mtb_clear_CLAIM_reg() argument
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