1 /**
2 * \file
3 *
4 * \brief SAM WDT
5 *
6 * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 */
42
43 #ifdef _SAML21_WDT_COMPONENT_
44 #ifndef _HRI_WDT_L21_H_INCLUDED_
45 #define _HRI_WDT_L21_H_INCLUDED_
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53
54 #if defined(ENABLE_WDT_CRITICAL_SECTIONS)
55 #define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define WDT_CRITICAL_SECTION_ENTER()
59 #define WDT_CRITICAL_SECTION_LEAVE()
60 #endif
61
62 typedef uint32_t hri_wdt_syncbusy_reg_t;
63 typedef uint8_t hri_wdt_clear_reg_t;
64 typedef uint8_t hri_wdt_config_reg_t;
65 typedef uint8_t hri_wdt_ctrla_reg_t;
66 typedef uint8_t hri_wdt_ewctrl_reg_t;
67 typedef uint8_t hri_wdt_intenset_reg_t;
68 typedef uint8_t hri_wdt_intflag_reg_t;
69
hri_wdt_wait_for_sync(const void * const hw,hri_wdt_syncbusy_reg_t reg)70 static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg)
71 {
72 while (((Wdt *)hw)->SYNCBUSY.reg & reg) {
73 };
74 }
75
hri_wdt_is_syncing(const void * const hw,hri_wdt_syncbusy_reg_t reg)76 static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg)
77 {
78 return ((Wdt *)hw)->SYNCBUSY.reg & reg;
79 }
80
hri_wdt_set_INTEN_EW_bit(const void * const hw)81 static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw)
82 {
83 ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
84 }
85
hri_wdt_get_INTEN_EW_bit(const void * const hw)86 static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw)
87 {
88 return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos;
89 }
90
hri_wdt_write_INTEN_EW_bit(const void * const hw,bool value)91 static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value)
92 {
93 if (value == 0x0) {
94 ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
95 } else {
96 ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW;
97 }
98 }
99
hri_wdt_clear_INTEN_EW_bit(const void * const hw)100 static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw)
101 {
102 ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW;
103 }
104
hri_wdt_set_INTEN_reg(const void * const hw,hri_wdt_intenset_reg_t mask)105 static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
106 {
107 ((Wdt *)hw)->INTENSET.reg = mask;
108 }
109
hri_wdt_get_INTEN_reg(const void * const hw,hri_wdt_intenset_reg_t mask)110 static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
111 {
112 uint8_t tmp;
113 tmp = ((Wdt *)hw)->INTENSET.reg;
114 tmp &= mask;
115 return tmp;
116 }
117
hri_wdt_read_INTEN_reg(const void * const hw)118 static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw)
119 {
120 return ((Wdt *)hw)->INTENSET.reg;
121 }
122
hri_wdt_write_INTEN_reg(const void * const hw,hri_wdt_intenset_reg_t data)123 static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data)
124 {
125 ((Wdt *)hw)->INTENSET.reg = data;
126 ((Wdt *)hw)->INTENCLR.reg = ~data;
127 }
128
hri_wdt_clear_INTEN_reg(const void * const hw,hri_wdt_intenset_reg_t mask)129 static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask)
130 {
131 ((Wdt *)hw)->INTENCLR.reg = mask;
132 }
133
hri_wdt_get_INTFLAG_EW_bit(const void * const hw)134 static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw)
135 {
136 return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
137 }
138
hri_wdt_clear_INTFLAG_EW_bit(const void * const hw)139 static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw)
140 {
141 ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
142 }
143
hri_wdt_get_interrupt_EW_bit(const void * const hw)144 static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw)
145 {
146 return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos;
147 }
148
hri_wdt_clear_interrupt_EW_bit(const void * const hw)149 static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw)
150 {
151 ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW;
152 }
153
hri_wdt_get_INTFLAG_reg(const void * const hw,hri_wdt_intflag_reg_t mask)154 static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
155 {
156 uint8_t tmp;
157 tmp = ((Wdt *)hw)->INTFLAG.reg;
158 tmp &= mask;
159 return tmp;
160 }
161
hri_wdt_read_INTFLAG_reg(const void * const hw)162 static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw)
163 {
164 return ((Wdt *)hw)->INTFLAG.reg;
165 }
166
hri_wdt_clear_INTFLAG_reg(const void * const hw,hri_wdt_intflag_reg_t mask)167 static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask)
168 {
169 ((Wdt *)hw)->INTFLAG.reg = mask;
170 }
171
hri_wdt_write_CLEAR_reg(const void * const hw,hri_wdt_clear_reg_t data)172 static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data)
173 {
174 WDT_CRITICAL_SECTION_ENTER();
175 ((Wdt *)hw)->CLEAR.reg = data;
176 WDT_CRITICAL_SECTION_LEAVE();
177 }
178
hri_wdt_set_CTRLA_ENABLE_bit(const void * const hw)179 static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw)
180 {
181 WDT_CRITICAL_SECTION_ENTER();
182 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
183 ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE;
184 WDT_CRITICAL_SECTION_LEAVE();
185 }
186
hri_wdt_get_CTRLA_ENABLE_bit(const void * const hw)187 static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw)
188 {
189 uint8_t tmp;
190 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
191 tmp = ((Wdt *)hw)->CTRLA.reg;
192 tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos;
193 return (bool)tmp;
194 }
195
hri_wdt_write_CTRLA_ENABLE_bit(const void * const hw,bool value)196 static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
197 {
198 uint8_t tmp;
199 WDT_CRITICAL_SECTION_ENTER();
200 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
201 tmp = ((Wdt *)hw)->CTRLA.reg;
202 tmp &= ~WDT_CTRLA_ENABLE;
203 tmp |= value << WDT_CTRLA_ENABLE_Pos;
204 ((Wdt *)hw)->CTRLA.reg = tmp;
205 WDT_CRITICAL_SECTION_LEAVE();
206 }
207
hri_wdt_clear_CTRLA_ENABLE_bit(const void * const hw)208 static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw)
209 {
210 WDT_CRITICAL_SECTION_ENTER();
211 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
212 ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE;
213 WDT_CRITICAL_SECTION_LEAVE();
214 }
215
hri_wdt_toggle_CTRLA_ENABLE_bit(const void * const hw)216 static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw)
217 {
218 WDT_CRITICAL_SECTION_ENTER();
219 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
220 ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE;
221 WDT_CRITICAL_SECTION_LEAVE();
222 }
223
hri_wdt_set_CTRLA_WEN_bit(const void * const hw)224 static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw)
225 {
226 WDT_CRITICAL_SECTION_ENTER();
227 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
228 ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN;
229 WDT_CRITICAL_SECTION_LEAVE();
230 }
231
hri_wdt_get_CTRLA_WEN_bit(const void * const hw)232 static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw)
233 {
234 uint8_t tmp;
235 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
236 tmp = ((Wdt *)hw)->CTRLA.reg;
237 tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos;
238 return (bool)tmp;
239 }
240
hri_wdt_write_CTRLA_WEN_bit(const void * const hw,bool value)241 static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value)
242 {
243 uint8_t tmp;
244 WDT_CRITICAL_SECTION_ENTER();
245 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
246 tmp = ((Wdt *)hw)->CTRLA.reg;
247 tmp &= ~WDT_CTRLA_WEN;
248 tmp |= value << WDT_CTRLA_WEN_Pos;
249 ((Wdt *)hw)->CTRLA.reg = tmp;
250 WDT_CRITICAL_SECTION_LEAVE();
251 }
252
hri_wdt_clear_CTRLA_WEN_bit(const void * const hw)253 static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw)
254 {
255 WDT_CRITICAL_SECTION_ENTER();
256 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
257 ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN;
258 WDT_CRITICAL_SECTION_LEAVE();
259 }
260
hri_wdt_toggle_CTRLA_WEN_bit(const void * const hw)261 static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw)
262 {
263 WDT_CRITICAL_SECTION_ENTER();
264 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
265 ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN;
266 WDT_CRITICAL_SECTION_LEAVE();
267 }
268
hri_wdt_set_CTRLA_ALWAYSON_bit(const void * const hw)269 static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw)
270 {
271 WDT_CRITICAL_SECTION_ENTER();
272 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
273 ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON;
274 WDT_CRITICAL_SECTION_LEAVE();
275 }
276
hri_wdt_get_CTRLA_ALWAYSON_bit(const void * const hw)277 static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw)
278 {
279 uint8_t tmp;
280 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
281 tmp = ((Wdt *)hw)->CTRLA.reg;
282 tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos;
283 return (bool)tmp;
284 }
285
hri_wdt_write_CTRLA_ALWAYSON_bit(const void * const hw,bool value)286 static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value)
287 {
288 uint8_t tmp;
289 WDT_CRITICAL_SECTION_ENTER();
290 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
291 tmp = ((Wdt *)hw)->CTRLA.reg;
292 tmp &= ~WDT_CTRLA_ALWAYSON;
293 tmp |= value << WDT_CTRLA_ALWAYSON_Pos;
294 ((Wdt *)hw)->CTRLA.reg = tmp;
295 WDT_CRITICAL_SECTION_LEAVE();
296 }
297
hri_wdt_clear_CTRLA_ALWAYSON_bit(const void * const hw)298 static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw)
299 {
300 WDT_CRITICAL_SECTION_ENTER();
301 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
302 ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON;
303 WDT_CRITICAL_SECTION_LEAVE();
304 }
305
hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void * const hw)306 static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw)
307 {
308 WDT_CRITICAL_SECTION_ENTER();
309 hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON);
310 ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON;
311 WDT_CRITICAL_SECTION_LEAVE();
312 }
313
hri_wdt_set_CTRLA_reg(const void * const hw,hri_wdt_ctrla_reg_t mask)314 static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
315 {
316 WDT_CRITICAL_SECTION_ENTER();
317 ((Wdt *)hw)->CTRLA.reg |= mask;
318 WDT_CRITICAL_SECTION_LEAVE();
319 }
320
hri_wdt_get_CTRLA_reg(const void * const hw,hri_wdt_ctrla_reg_t mask)321 static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
322 {
323 uint8_t tmp;
324 tmp = ((Wdt *)hw)->CTRLA.reg;
325 tmp &= mask;
326 return tmp;
327 }
328
hri_wdt_write_CTRLA_reg(const void * const hw,hri_wdt_ctrla_reg_t data)329 static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data)
330 {
331 WDT_CRITICAL_SECTION_ENTER();
332 ((Wdt *)hw)->CTRLA.reg = data;
333 WDT_CRITICAL_SECTION_LEAVE();
334 }
335
hri_wdt_clear_CTRLA_reg(const void * const hw,hri_wdt_ctrla_reg_t mask)336 static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
337 {
338 WDT_CRITICAL_SECTION_ENTER();
339 ((Wdt *)hw)->CTRLA.reg &= ~mask;
340 WDT_CRITICAL_SECTION_LEAVE();
341 }
342
hri_wdt_toggle_CTRLA_reg(const void * const hw,hri_wdt_ctrla_reg_t mask)343 static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask)
344 {
345 WDT_CRITICAL_SECTION_ENTER();
346 ((Wdt *)hw)->CTRLA.reg ^= mask;
347 WDT_CRITICAL_SECTION_LEAVE();
348 }
349
hri_wdt_read_CTRLA_reg(const void * const hw)350 static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw)
351 {
352 return ((Wdt *)hw)->CTRLA.reg;
353 }
354
hri_wdt_set_CONFIG_PER_bf(const void * const hw,hri_wdt_config_reg_t mask)355 static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
356 {
357 WDT_CRITICAL_SECTION_ENTER();
358 ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask);
359 WDT_CRITICAL_SECTION_LEAVE();
360 }
361
hri_wdt_get_CONFIG_PER_bf(const void * const hw,hri_wdt_config_reg_t mask)362 static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
363 {
364 uint8_t tmp;
365 tmp = ((Wdt *)hw)->CONFIG.reg;
366 tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos;
367 return tmp;
368 }
369
hri_wdt_write_CONFIG_PER_bf(const void * const hw,hri_wdt_config_reg_t data)370 static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data)
371 {
372 uint8_t tmp;
373 WDT_CRITICAL_SECTION_ENTER();
374 tmp = ((Wdt *)hw)->CONFIG.reg;
375 tmp &= ~WDT_CONFIG_PER_Msk;
376 tmp |= WDT_CONFIG_PER(data);
377 ((Wdt *)hw)->CONFIG.reg = tmp;
378 WDT_CRITICAL_SECTION_LEAVE();
379 }
380
hri_wdt_clear_CONFIG_PER_bf(const void * const hw,hri_wdt_config_reg_t mask)381 static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
382 {
383 WDT_CRITICAL_SECTION_ENTER();
384 ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask);
385 WDT_CRITICAL_SECTION_LEAVE();
386 }
387
hri_wdt_toggle_CONFIG_PER_bf(const void * const hw,hri_wdt_config_reg_t mask)388 static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask)
389 {
390 WDT_CRITICAL_SECTION_ENTER();
391 ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask);
392 WDT_CRITICAL_SECTION_LEAVE();
393 }
394
hri_wdt_read_CONFIG_PER_bf(const void * const hw)395 static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw)
396 {
397 uint8_t tmp;
398 tmp = ((Wdt *)hw)->CONFIG.reg;
399 tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos;
400 return tmp;
401 }
402
hri_wdt_set_CONFIG_WINDOW_bf(const void * const hw,hri_wdt_config_reg_t mask)403 static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
404 {
405 WDT_CRITICAL_SECTION_ENTER();
406 ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask);
407 WDT_CRITICAL_SECTION_LEAVE();
408 }
409
hri_wdt_get_CONFIG_WINDOW_bf(const void * const hw,hri_wdt_config_reg_t mask)410 static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
411 {
412 uint8_t tmp;
413 tmp = ((Wdt *)hw)->CONFIG.reg;
414 tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos;
415 return tmp;
416 }
417
hri_wdt_write_CONFIG_WINDOW_bf(const void * const hw,hri_wdt_config_reg_t data)418 static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data)
419 {
420 uint8_t tmp;
421 WDT_CRITICAL_SECTION_ENTER();
422 tmp = ((Wdt *)hw)->CONFIG.reg;
423 tmp &= ~WDT_CONFIG_WINDOW_Msk;
424 tmp |= WDT_CONFIG_WINDOW(data);
425 ((Wdt *)hw)->CONFIG.reg = tmp;
426 WDT_CRITICAL_SECTION_LEAVE();
427 }
428
hri_wdt_clear_CONFIG_WINDOW_bf(const void * const hw,hri_wdt_config_reg_t mask)429 static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
430 {
431 WDT_CRITICAL_SECTION_ENTER();
432 ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask);
433 WDT_CRITICAL_SECTION_LEAVE();
434 }
435
hri_wdt_toggle_CONFIG_WINDOW_bf(const void * const hw,hri_wdt_config_reg_t mask)436 static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask)
437 {
438 WDT_CRITICAL_SECTION_ENTER();
439 ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask);
440 WDT_CRITICAL_SECTION_LEAVE();
441 }
442
hri_wdt_read_CONFIG_WINDOW_bf(const void * const hw)443 static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw)
444 {
445 uint8_t tmp;
446 tmp = ((Wdt *)hw)->CONFIG.reg;
447 tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos;
448 return tmp;
449 }
450
hri_wdt_set_CONFIG_reg(const void * const hw,hri_wdt_config_reg_t mask)451 static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
452 {
453 WDT_CRITICAL_SECTION_ENTER();
454 ((Wdt *)hw)->CONFIG.reg |= mask;
455 WDT_CRITICAL_SECTION_LEAVE();
456 }
457
hri_wdt_get_CONFIG_reg(const void * const hw,hri_wdt_config_reg_t mask)458 static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
459 {
460 uint8_t tmp;
461 tmp = ((Wdt *)hw)->CONFIG.reg;
462 tmp &= mask;
463 return tmp;
464 }
465
hri_wdt_write_CONFIG_reg(const void * const hw,hri_wdt_config_reg_t data)466 static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data)
467 {
468 WDT_CRITICAL_SECTION_ENTER();
469 ((Wdt *)hw)->CONFIG.reg = data;
470 WDT_CRITICAL_SECTION_LEAVE();
471 }
472
hri_wdt_clear_CONFIG_reg(const void * const hw,hri_wdt_config_reg_t mask)473 static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
474 {
475 WDT_CRITICAL_SECTION_ENTER();
476 ((Wdt *)hw)->CONFIG.reg &= ~mask;
477 WDT_CRITICAL_SECTION_LEAVE();
478 }
479
hri_wdt_toggle_CONFIG_reg(const void * const hw,hri_wdt_config_reg_t mask)480 static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask)
481 {
482 WDT_CRITICAL_SECTION_ENTER();
483 ((Wdt *)hw)->CONFIG.reg ^= mask;
484 WDT_CRITICAL_SECTION_LEAVE();
485 }
486
hri_wdt_read_CONFIG_reg(const void * const hw)487 static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw)
488 {
489 return ((Wdt *)hw)->CONFIG.reg;
490 }
491
hri_wdt_set_EWCTRL_EWOFFSET_bf(const void * const hw,hri_wdt_ewctrl_reg_t mask)492 static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
493 {
494 WDT_CRITICAL_SECTION_ENTER();
495 ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask);
496 WDT_CRITICAL_SECTION_LEAVE();
497 }
498
hri_wdt_get_EWCTRL_EWOFFSET_bf(const void * const hw,hri_wdt_ewctrl_reg_t mask)499 static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
500 {
501 uint8_t tmp;
502 tmp = ((Wdt *)hw)->EWCTRL.reg;
503 tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos;
504 return tmp;
505 }
506
hri_wdt_write_EWCTRL_EWOFFSET_bf(const void * const hw,hri_wdt_ewctrl_reg_t data)507 static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data)
508 {
509 uint8_t tmp;
510 WDT_CRITICAL_SECTION_ENTER();
511 tmp = ((Wdt *)hw)->EWCTRL.reg;
512 tmp &= ~WDT_EWCTRL_EWOFFSET_Msk;
513 tmp |= WDT_EWCTRL_EWOFFSET(data);
514 ((Wdt *)hw)->EWCTRL.reg = tmp;
515 WDT_CRITICAL_SECTION_LEAVE();
516 }
517
hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void * const hw,hri_wdt_ewctrl_reg_t mask)518 static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
519 {
520 WDT_CRITICAL_SECTION_ENTER();
521 ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask);
522 WDT_CRITICAL_SECTION_LEAVE();
523 }
524
hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void * const hw,hri_wdt_ewctrl_reg_t mask)525 static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask)
526 {
527 WDT_CRITICAL_SECTION_ENTER();
528 ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask);
529 WDT_CRITICAL_SECTION_LEAVE();
530 }
531
hri_wdt_read_EWCTRL_EWOFFSET_bf(const void * const hw)532 static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw)
533 {
534 uint8_t tmp;
535 tmp = ((Wdt *)hw)->EWCTRL.reg;
536 tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos;
537 return tmp;
538 }
539
hri_wdt_set_EWCTRL_reg(const void * const hw,hri_wdt_ewctrl_reg_t mask)540 static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
541 {
542 WDT_CRITICAL_SECTION_ENTER();
543 ((Wdt *)hw)->EWCTRL.reg |= mask;
544 WDT_CRITICAL_SECTION_LEAVE();
545 }
546
hri_wdt_get_EWCTRL_reg(const void * const hw,hri_wdt_ewctrl_reg_t mask)547 static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
548 {
549 uint8_t tmp;
550 tmp = ((Wdt *)hw)->EWCTRL.reg;
551 tmp &= mask;
552 return tmp;
553 }
554
hri_wdt_write_EWCTRL_reg(const void * const hw,hri_wdt_ewctrl_reg_t data)555 static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data)
556 {
557 WDT_CRITICAL_SECTION_ENTER();
558 ((Wdt *)hw)->EWCTRL.reg = data;
559 WDT_CRITICAL_SECTION_LEAVE();
560 }
561
hri_wdt_clear_EWCTRL_reg(const void * const hw,hri_wdt_ewctrl_reg_t mask)562 static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
563 {
564 WDT_CRITICAL_SECTION_ENTER();
565 ((Wdt *)hw)->EWCTRL.reg &= ~mask;
566 WDT_CRITICAL_SECTION_LEAVE();
567 }
568
hri_wdt_toggle_EWCTRL_reg(const void * const hw,hri_wdt_ewctrl_reg_t mask)569 static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask)
570 {
571 WDT_CRITICAL_SECTION_ENTER();
572 ((Wdt *)hw)->EWCTRL.reg ^= mask;
573 WDT_CRITICAL_SECTION_LEAVE();
574 }
575
hri_wdt_read_EWCTRL_reg(const void * const hw)576 static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw)
577 {
578 return ((Wdt *)hw)->EWCTRL.reg;
579 }
580
hri_wdt_get_SYNCBUSY_ENABLE_bit(const void * const hw)581 static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw)
582 {
583 return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos;
584 }
585
hri_wdt_get_SYNCBUSY_WEN_bit(const void * const hw)586 static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw)
587 {
588 return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos;
589 }
590
hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void * const hw)591 static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw)
592 {
593 return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos;
594 }
595
hri_wdt_get_SYNCBUSY_CLEAR_bit(const void * const hw)596 static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw)
597 {
598 return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos;
599 }
600
hri_wdt_get_SYNCBUSY_reg(const void * const hw,hri_wdt_syncbusy_reg_t mask)601 static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask)
602 {
603 uint32_t tmp;
604 tmp = ((Wdt *)hw)->SYNCBUSY.reg;
605 tmp &= mask;
606 return tmp;
607 }
608
hri_wdt_read_SYNCBUSY_reg(const void * const hw)609 static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw)
610 {
611 return ((Wdt *)hw)->SYNCBUSY.reg;
612 }
613
614 #ifdef __cplusplus
615 }
616 #endif
617
618 #endif /* _HRI_WDT_L21_H_INCLUDED */
619 #endif /* _SAML21_WDT_COMPONENT_ */
620
