1 /**
2  * \file
3  *
4  * \brief SAM SystemControl
5  *
6  * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7  *
8  * \asf_license_start
9  *
10  * \page License
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions are met:
14  *
15  * 1. Redistributions of source code must retain the above copyright notice,
16  *    this list of conditions and the following disclaimer.
17  *
18  * 2. Redistributions in binary form must reproduce the above copyright notice,
19  *    this list of conditions and the following disclaimer in the documentation
20  *    and/or other materials provided with the distribution.
21  *
22  * 3. The name of Atmel may not be used to endorse or promote products derived
23  *    from this software without specific prior written permission.
24  *
25  * 4. This software may only be redistributed and used in connection with an
26  *    Atmel microcontroller product.
27  *
28  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGE.
39  *
40  * \asf_license_stop
41  */
42 
43 #ifdef _SAML21_SystemControl_COMPONENT_
44 #ifndef _HRI_SystemControl_L21_H_INCLUDED_
45 #define _HRI_SystemControl_L21_H_INCLUDED_
46 
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50 
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53 
54 #if defined(ENABLE_SystemControl_CRITICAL_SECTIONS)
55 #define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define SystemControl_CRITICAL_SECTION_ENTER()
59 #define SystemControl_CRITICAL_SECTION_LEAVE()
60 #endif
61 
62 typedef uint32_t hri_systemcontrol_aircr_reg_t;
63 typedef uint32_t hri_systemcontrol_ccr_reg_t;
64 typedef uint32_t hri_systemcontrol_cpuid_reg_t;
65 typedef uint32_t hri_systemcontrol_icsr_reg_t;
66 typedef uint32_t hri_systemcontrol_scr_reg_t;
67 typedef uint32_t hri_systemcontrol_shpr2_reg_t;
68 typedef uint32_t hri_systemcontrol_shpr3_reg_t;
69 typedef uint32_t hri_systemcontrol_vtor_reg_t;
70 
hri_systemcontrol_set_CPUID_REVISION_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)71 static inline void hri_systemcontrol_set_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
72 {
73 	SystemControl_CRITICAL_SECTION_ENTER();
74 	((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_REVISION(mask);
75 	SystemControl_CRITICAL_SECTION_LEAVE();
76 }
77 
hri_systemcontrol_get_CPUID_REVISION_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)78 static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const             hw,
79                                                                                     hri_systemcontrol_cpuid_reg_t mask)
80 {
81 	uint32_t tmp;
82 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
83 	tmp = (tmp & SystemControl_CPUID_REVISION(mask)) >> 0;
84 	return tmp;
85 }
86 
hri_systemcontrol_write_CPUID_REVISION_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t data)87 static inline void hri_systemcontrol_write_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data)
88 {
89 	uint32_t tmp;
90 	SystemControl_CRITICAL_SECTION_ENTER();
91 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
92 	tmp &= ~SystemControl_CPUID_REVISION_Msk;
93 	tmp |= SystemControl_CPUID_REVISION(data);
94 	((Systemcontrol *)hw)->CPUID.reg = tmp;
95 	SystemControl_CRITICAL_SECTION_LEAVE();
96 }
97 
hri_systemcontrol_clear_CPUID_REVISION_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)98 static inline void hri_systemcontrol_clear_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
99 {
100 	SystemControl_CRITICAL_SECTION_ENTER();
101 	((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_REVISION(mask);
102 	SystemControl_CRITICAL_SECTION_LEAVE();
103 }
104 
hri_systemcontrol_toggle_CPUID_REVISION_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)105 static inline void hri_systemcontrol_toggle_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
106 {
107 	SystemControl_CRITICAL_SECTION_ENTER();
108 	((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_REVISION(mask);
109 	SystemControl_CRITICAL_SECTION_LEAVE();
110 }
111 
hri_systemcontrol_read_CPUID_REVISION_bf(const void * const hw)112 static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw)
113 {
114 	uint32_t tmp;
115 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
116 	tmp = (tmp & SystemControl_CPUID_REVISION_Msk) >> 0;
117 	return tmp;
118 }
119 
hri_systemcontrol_set_CPUID_PARTNO_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)120 static inline void hri_systemcontrol_set_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
121 {
122 	SystemControl_CRITICAL_SECTION_ENTER();
123 	((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_PARTNO(mask);
124 	SystemControl_CRITICAL_SECTION_LEAVE();
125 }
126 
hri_systemcontrol_get_CPUID_PARTNO_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)127 static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const             hw,
128                                                                                   hri_systemcontrol_cpuid_reg_t mask)
129 {
130 	uint32_t tmp;
131 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
132 	tmp = (tmp & SystemControl_CPUID_PARTNO(mask)) >> 4;
133 	return tmp;
134 }
135 
hri_systemcontrol_write_CPUID_PARTNO_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t data)136 static inline void hri_systemcontrol_write_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data)
137 {
138 	uint32_t tmp;
139 	SystemControl_CRITICAL_SECTION_ENTER();
140 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
141 	tmp &= ~SystemControl_CPUID_PARTNO_Msk;
142 	tmp |= SystemControl_CPUID_PARTNO(data);
143 	((Systemcontrol *)hw)->CPUID.reg = tmp;
144 	SystemControl_CRITICAL_SECTION_LEAVE();
145 }
146 
hri_systemcontrol_clear_CPUID_PARTNO_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)147 static inline void hri_systemcontrol_clear_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
148 {
149 	SystemControl_CRITICAL_SECTION_ENTER();
150 	((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_PARTNO(mask);
151 	SystemControl_CRITICAL_SECTION_LEAVE();
152 }
153 
hri_systemcontrol_toggle_CPUID_PARTNO_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)154 static inline void hri_systemcontrol_toggle_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
155 {
156 	SystemControl_CRITICAL_SECTION_ENTER();
157 	((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_PARTNO(mask);
158 	SystemControl_CRITICAL_SECTION_LEAVE();
159 }
160 
hri_systemcontrol_read_CPUID_PARTNO_bf(const void * const hw)161 static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw)
162 {
163 	uint32_t tmp;
164 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
165 	tmp = (tmp & SystemControl_CPUID_PARTNO_Msk) >> 4;
166 	return tmp;
167 }
168 
hri_systemcontrol_set_CPUID_ARCHITECTURE_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)169 static inline void hri_systemcontrol_set_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
170 {
171 	SystemControl_CRITICAL_SECTION_ENTER();
172 	((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_ARCHITECTURE(mask);
173 	SystemControl_CRITICAL_SECTION_LEAVE();
174 }
175 
176 static inline hri_systemcontrol_cpuid_reg_t
hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)177 hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
178 {
179 	uint32_t tmp;
180 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
181 	tmp = (tmp & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16;
182 	return tmp;
183 }
184 
hri_systemcontrol_write_CPUID_ARCHITECTURE_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t data)185 static inline void hri_systemcontrol_write_CPUID_ARCHITECTURE_bf(const void *const             hw,
186                                                                  hri_systemcontrol_cpuid_reg_t data)
187 {
188 	uint32_t tmp;
189 	SystemControl_CRITICAL_SECTION_ENTER();
190 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
191 	tmp &= ~SystemControl_CPUID_ARCHITECTURE_Msk;
192 	tmp |= SystemControl_CPUID_ARCHITECTURE(data);
193 	((Systemcontrol *)hw)->CPUID.reg = tmp;
194 	SystemControl_CRITICAL_SECTION_LEAVE();
195 }
196 
hri_systemcontrol_clear_CPUID_ARCHITECTURE_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)197 static inline void hri_systemcontrol_clear_CPUID_ARCHITECTURE_bf(const void *const             hw,
198                                                                  hri_systemcontrol_cpuid_reg_t mask)
199 {
200 	SystemControl_CRITICAL_SECTION_ENTER();
201 	((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_ARCHITECTURE(mask);
202 	SystemControl_CRITICAL_SECTION_LEAVE();
203 }
204 
hri_systemcontrol_toggle_CPUID_ARCHITECTURE_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)205 static inline void hri_systemcontrol_toggle_CPUID_ARCHITECTURE_bf(const void *const             hw,
206                                                                   hri_systemcontrol_cpuid_reg_t mask)
207 {
208 	SystemControl_CRITICAL_SECTION_ENTER();
209 	((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_ARCHITECTURE(mask);
210 	SystemControl_CRITICAL_SECTION_LEAVE();
211 }
212 
hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void * const hw)213 static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw)
214 {
215 	uint32_t tmp;
216 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
217 	tmp = (tmp & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16;
218 	return tmp;
219 }
220 
hri_systemcontrol_set_CPUID_VARIANT_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)221 static inline void hri_systemcontrol_set_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
222 {
223 	SystemControl_CRITICAL_SECTION_ENTER();
224 	((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_VARIANT(mask);
225 	SystemControl_CRITICAL_SECTION_LEAVE();
226 }
227 
hri_systemcontrol_get_CPUID_VARIANT_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)228 static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const             hw,
229                                                                                    hri_systemcontrol_cpuid_reg_t mask)
230 {
231 	uint32_t tmp;
232 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
233 	tmp = (tmp & SystemControl_CPUID_VARIANT(mask)) >> 20;
234 	return tmp;
235 }
236 
hri_systemcontrol_write_CPUID_VARIANT_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t data)237 static inline void hri_systemcontrol_write_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data)
238 {
239 	uint32_t tmp;
240 	SystemControl_CRITICAL_SECTION_ENTER();
241 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
242 	tmp &= ~SystemControl_CPUID_VARIANT_Msk;
243 	tmp |= SystemControl_CPUID_VARIANT(data);
244 	((Systemcontrol *)hw)->CPUID.reg = tmp;
245 	SystemControl_CRITICAL_SECTION_LEAVE();
246 }
247 
hri_systemcontrol_clear_CPUID_VARIANT_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)248 static inline void hri_systemcontrol_clear_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
249 {
250 	SystemControl_CRITICAL_SECTION_ENTER();
251 	((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_VARIANT(mask);
252 	SystemControl_CRITICAL_SECTION_LEAVE();
253 }
254 
hri_systemcontrol_toggle_CPUID_VARIANT_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)255 static inline void hri_systemcontrol_toggle_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
256 {
257 	SystemControl_CRITICAL_SECTION_ENTER();
258 	((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_VARIANT(mask);
259 	SystemControl_CRITICAL_SECTION_LEAVE();
260 }
261 
hri_systemcontrol_read_CPUID_VARIANT_bf(const void * const hw)262 static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw)
263 {
264 	uint32_t tmp;
265 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
266 	tmp = (tmp & SystemControl_CPUID_VARIANT_Msk) >> 20;
267 	return tmp;
268 }
269 
hri_systemcontrol_set_CPUID_IMPLEMENTER_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)270 static inline void hri_systemcontrol_set_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
271 {
272 	SystemControl_CRITICAL_SECTION_ENTER();
273 	((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_IMPLEMENTER(mask);
274 	SystemControl_CRITICAL_SECTION_LEAVE();
275 }
276 
277 static inline hri_systemcontrol_cpuid_reg_t
hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)278 hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
279 {
280 	uint32_t tmp;
281 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
282 	tmp = (tmp & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24;
283 	return tmp;
284 }
285 
hri_systemcontrol_write_CPUID_IMPLEMENTER_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t data)286 static inline void hri_systemcontrol_write_CPUID_IMPLEMENTER_bf(const void *const             hw,
287                                                                 hri_systemcontrol_cpuid_reg_t data)
288 {
289 	uint32_t tmp;
290 	SystemControl_CRITICAL_SECTION_ENTER();
291 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
292 	tmp &= ~SystemControl_CPUID_IMPLEMENTER_Msk;
293 	tmp |= SystemControl_CPUID_IMPLEMENTER(data);
294 	((Systemcontrol *)hw)->CPUID.reg = tmp;
295 	SystemControl_CRITICAL_SECTION_LEAVE();
296 }
297 
hri_systemcontrol_clear_CPUID_IMPLEMENTER_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)298 static inline void hri_systemcontrol_clear_CPUID_IMPLEMENTER_bf(const void *const             hw,
299                                                                 hri_systemcontrol_cpuid_reg_t mask)
300 {
301 	SystemControl_CRITICAL_SECTION_ENTER();
302 	((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_IMPLEMENTER(mask);
303 	SystemControl_CRITICAL_SECTION_LEAVE();
304 }
305 
hri_systemcontrol_toggle_CPUID_IMPLEMENTER_bf(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)306 static inline void hri_systemcontrol_toggle_CPUID_IMPLEMENTER_bf(const void *const             hw,
307                                                                  hri_systemcontrol_cpuid_reg_t mask)
308 {
309 	SystemControl_CRITICAL_SECTION_ENTER();
310 	((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_IMPLEMENTER(mask);
311 	SystemControl_CRITICAL_SECTION_LEAVE();
312 }
313 
hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void * const hw)314 static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw)
315 {
316 	uint32_t tmp;
317 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
318 	tmp = (tmp & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24;
319 	return tmp;
320 }
321 
hri_systemcontrol_set_CPUID_reg(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)322 static inline void hri_systemcontrol_set_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
323 {
324 	SystemControl_CRITICAL_SECTION_ENTER();
325 	((Systemcontrol *)hw)->CPUID.reg |= mask;
326 	SystemControl_CRITICAL_SECTION_LEAVE();
327 }
328 
hri_systemcontrol_get_CPUID_reg(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)329 static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const             hw,
330                                                                             hri_systemcontrol_cpuid_reg_t mask)
331 {
332 	uint32_t tmp;
333 	tmp = ((Systemcontrol *)hw)->CPUID.reg;
334 	tmp &= mask;
335 	return tmp;
336 }
337 
hri_systemcontrol_write_CPUID_reg(const void * const hw,hri_systemcontrol_cpuid_reg_t data)338 static inline void hri_systemcontrol_write_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t data)
339 {
340 	SystemControl_CRITICAL_SECTION_ENTER();
341 	((Systemcontrol *)hw)->CPUID.reg = data;
342 	SystemControl_CRITICAL_SECTION_LEAVE();
343 }
344 
hri_systemcontrol_clear_CPUID_reg(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)345 static inline void hri_systemcontrol_clear_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
346 {
347 	SystemControl_CRITICAL_SECTION_ENTER();
348 	((Systemcontrol *)hw)->CPUID.reg &= ~mask;
349 	SystemControl_CRITICAL_SECTION_LEAVE();
350 }
351 
hri_systemcontrol_toggle_CPUID_reg(const void * const hw,hri_systemcontrol_cpuid_reg_t mask)352 static inline void hri_systemcontrol_toggle_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask)
353 {
354 	SystemControl_CRITICAL_SECTION_ENTER();
355 	((Systemcontrol *)hw)->CPUID.reg ^= mask;
356 	SystemControl_CRITICAL_SECTION_LEAVE();
357 }
358 
hri_systemcontrol_read_CPUID_reg(const void * const hw)359 static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw)
360 {
361 	return ((Systemcontrol *)hw)->CPUID.reg;
362 }
363 
hri_systemcontrol_set_ICSR_PENDSTCLR_bit(const void * const hw)364 static inline void hri_systemcontrol_set_ICSR_PENDSTCLR_bit(const void *const hw)
365 {
366 	SystemControl_CRITICAL_SECTION_ENTER();
367 	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSTCLR;
368 	SystemControl_CRITICAL_SECTION_LEAVE();
369 }
370 
hri_systemcontrol_get_ICSR_PENDSTCLR_bit(const void * const hw)371 static inline bool hri_systemcontrol_get_ICSR_PENDSTCLR_bit(const void *const hw)
372 {
373 	uint32_t tmp;
374 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
375 	tmp = (tmp & SystemControl_ICSR_PENDSTCLR) >> 25;
376 	return (bool)tmp;
377 }
378 
hri_systemcontrol_write_ICSR_PENDSTCLR_bit(const void * const hw,bool value)379 static inline void hri_systemcontrol_write_ICSR_PENDSTCLR_bit(const void *const hw, bool value)
380 {
381 	uint32_t tmp;
382 	SystemControl_CRITICAL_SECTION_ENTER();
383 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
384 	tmp &= ~SystemControl_ICSR_PENDSTCLR;
385 	tmp |= value << 25;
386 	((Systemcontrol *)hw)->ICSR.reg = tmp;
387 	SystemControl_CRITICAL_SECTION_LEAVE();
388 }
389 
hri_systemcontrol_clear_ICSR_PENDSTCLR_bit(const void * const hw)390 static inline void hri_systemcontrol_clear_ICSR_PENDSTCLR_bit(const void *const hw)
391 {
392 	SystemControl_CRITICAL_SECTION_ENTER();
393 	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSTCLR;
394 	SystemControl_CRITICAL_SECTION_LEAVE();
395 }
396 
hri_systemcontrol_toggle_ICSR_PENDSTCLR_bit(const void * const hw)397 static inline void hri_systemcontrol_toggle_ICSR_PENDSTCLR_bit(const void *const hw)
398 {
399 	SystemControl_CRITICAL_SECTION_ENTER();
400 	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSTCLR;
401 	SystemControl_CRITICAL_SECTION_LEAVE();
402 }
403 
hri_systemcontrol_set_ICSR_PENDSTSET_bit(const void * const hw)404 static inline void hri_systemcontrol_set_ICSR_PENDSTSET_bit(const void *const hw)
405 {
406 	SystemControl_CRITICAL_SECTION_ENTER();
407 	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSTSET;
408 	SystemControl_CRITICAL_SECTION_LEAVE();
409 }
410 
hri_systemcontrol_get_ICSR_PENDSTSET_bit(const void * const hw)411 static inline bool hri_systemcontrol_get_ICSR_PENDSTSET_bit(const void *const hw)
412 {
413 	uint32_t tmp;
414 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
415 	tmp = (tmp & SystemControl_ICSR_PENDSTSET) >> 26;
416 	return (bool)tmp;
417 }
418 
hri_systemcontrol_write_ICSR_PENDSTSET_bit(const void * const hw,bool value)419 static inline void hri_systemcontrol_write_ICSR_PENDSTSET_bit(const void *const hw, bool value)
420 {
421 	uint32_t tmp;
422 	SystemControl_CRITICAL_SECTION_ENTER();
423 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
424 	tmp &= ~SystemControl_ICSR_PENDSTSET;
425 	tmp |= value << 26;
426 	((Systemcontrol *)hw)->ICSR.reg = tmp;
427 	SystemControl_CRITICAL_SECTION_LEAVE();
428 }
429 
hri_systemcontrol_clear_ICSR_PENDSTSET_bit(const void * const hw)430 static inline void hri_systemcontrol_clear_ICSR_PENDSTSET_bit(const void *const hw)
431 {
432 	SystemControl_CRITICAL_SECTION_ENTER();
433 	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSTSET;
434 	SystemControl_CRITICAL_SECTION_LEAVE();
435 }
436 
hri_systemcontrol_toggle_ICSR_PENDSTSET_bit(const void * const hw)437 static inline void hri_systemcontrol_toggle_ICSR_PENDSTSET_bit(const void *const hw)
438 {
439 	SystemControl_CRITICAL_SECTION_ENTER();
440 	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSTSET;
441 	SystemControl_CRITICAL_SECTION_LEAVE();
442 }
443 
hri_systemcontrol_set_ICSR_PENDSVCLR_bit(const void * const hw)444 static inline void hri_systemcontrol_set_ICSR_PENDSVCLR_bit(const void *const hw)
445 {
446 	SystemControl_CRITICAL_SECTION_ENTER();
447 	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSVCLR;
448 	SystemControl_CRITICAL_SECTION_LEAVE();
449 }
450 
hri_systemcontrol_get_ICSR_PENDSVCLR_bit(const void * const hw)451 static inline bool hri_systemcontrol_get_ICSR_PENDSVCLR_bit(const void *const hw)
452 {
453 	uint32_t tmp;
454 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
455 	tmp = (tmp & SystemControl_ICSR_PENDSVCLR) >> 27;
456 	return (bool)tmp;
457 }
458 
hri_systemcontrol_write_ICSR_PENDSVCLR_bit(const void * const hw,bool value)459 static inline void hri_systemcontrol_write_ICSR_PENDSVCLR_bit(const void *const hw, bool value)
460 {
461 	uint32_t tmp;
462 	SystemControl_CRITICAL_SECTION_ENTER();
463 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
464 	tmp &= ~SystemControl_ICSR_PENDSVCLR;
465 	tmp |= value << 27;
466 	((Systemcontrol *)hw)->ICSR.reg = tmp;
467 	SystemControl_CRITICAL_SECTION_LEAVE();
468 }
469 
hri_systemcontrol_clear_ICSR_PENDSVCLR_bit(const void * const hw)470 static inline void hri_systemcontrol_clear_ICSR_PENDSVCLR_bit(const void *const hw)
471 {
472 	SystemControl_CRITICAL_SECTION_ENTER();
473 	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSVCLR;
474 	SystemControl_CRITICAL_SECTION_LEAVE();
475 }
476 
hri_systemcontrol_toggle_ICSR_PENDSVCLR_bit(const void * const hw)477 static inline void hri_systemcontrol_toggle_ICSR_PENDSVCLR_bit(const void *const hw)
478 {
479 	SystemControl_CRITICAL_SECTION_ENTER();
480 	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSVCLR;
481 	SystemControl_CRITICAL_SECTION_LEAVE();
482 }
483 
hri_systemcontrol_set_ICSR_PENDSVSET_bit(const void * const hw)484 static inline void hri_systemcontrol_set_ICSR_PENDSVSET_bit(const void *const hw)
485 {
486 	SystemControl_CRITICAL_SECTION_ENTER();
487 	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSVSET;
488 	SystemControl_CRITICAL_SECTION_LEAVE();
489 }
490 
hri_systemcontrol_get_ICSR_PENDSVSET_bit(const void * const hw)491 static inline bool hri_systemcontrol_get_ICSR_PENDSVSET_bit(const void *const hw)
492 {
493 	uint32_t tmp;
494 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
495 	tmp = (tmp & SystemControl_ICSR_PENDSVSET) >> 28;
496 	return (bool)tmp;
497 }
498 
hri_systemcontrol_write_ICSR_PENDSVSET_bit(const void * const hw,bool value)499 static inline void hri_systemcontrol_write_ICSR_PENDSVSET_bit(const void *const hw, bool value)
500 {
501 	uint32_t tmp;
502 	SystemControl_CRITICAL_SECTION_ENTER();
503 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
504 	tmp &= ~SystemControl_ICSR_PENDSVSET;
505 	tmp |= value << 28;
506 	((Systemcontrol *)hw)->ICSR.reg = tmp;
507 	SystemControl_CRITICAL_SECTION_LEAVE();
508 }
509 
hri_systemcontrol_clear_ICSR_PENDSVSET_bit(const void * const hw)510 static inline void hri_systemcontrol_clear_ICSR_PENDSVSET_bit(const void *const hw)
511 {
512 	SystemControl_CRITICAL_SECTION_ENTER();
513 	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSVSET;
514 	SystemControl_CRITICAL_SECTION_LEAVE();
515 }
516 
hri_systemcontrol_toggle_ICSR_PENDSVSET_bit(const void * const hw)517 static inline void hri_systemcontrol_toggle_ICSR_PENDSVSET_bit(const void *const hw)
518 {
519 	SystemControl_CRITICAL_SECTION_ENTER();
520 	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSVSET;
521 	SystemControl_CRITICAL_SECTION_LEAVE();
522 }
523 
hri_systemcontrol_set_ICSR_NMIPENDSET_bit(const void * const hw)524 static inline void hri_systemcontrol_set_ICSR_NMIPENDSET_bit(const void *const hw)
525 {
526 	SystemControl_CRITICAL_SECTION_ENTER();
527 	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_NMIPENDSET;
528 	SystemControl_CRITICAL_SECTION_LEAVE();
529 }
530 
hri_systemcontrol_get_ICSR_NMIPENDSET_bit(const void * const hw)531 static inline bool hri_systemcontrol_get_ICSR_NMIPENDSET_bit(const void *const hw)
532 {
533 	uint32_t tmp;
534 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
535 	tmp = (tmp & SystemControl_ICSR_NMIPENDSET) >> 31;
536 	return (bool)tmp;
537 }
538 
hri_systemcontrol_write_ICSR_NMIPENDSET_bit(const void * const hw,bool value)539 static inline void hri_systemcontrol_write_ICSR_NMIPENDSET_bit(const void *const hw, bool value)
540 {
541 	uint32_t tmp;
542 	SystemControl_CRITICAL_SECTION_ENTER();
543 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
544 	tmp &= ~SystemControl_ICSR_NMIPENDSET;
545 	tmp |= value << 31;
546 	((Systemcontrol *)hw)->ICSR.reg = tmp;
547 	SystemControl_CRITICAL_SECTION_LEAVE();
548 }
549 
hri_systemcontrol_clear_ICSR_NMIPENDSET_bit(const void * const hw)550 static inline void hri_systemcontrol_clear_ICSR_NMIPENDSET_bit(const void *const hw)
551 {
552 	SystemControl_CRITICAL_SECTION_ENTER();
553 	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_NMIPENDSET;
554 	SystemControl_CRITICAL_SECTION_LEAVE();
555 }
556 
hri_systemcontrol_toggle_ICSR_NMIPENDSET_bit(const void * const hw)557 static inline void hri_systemcontrol_toggle_ICSR_NMIPENDSET_bit(const void *const hw)
558 {
559 	SystemControl_CRITICAL_SECTION_ENTER();
560 	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_NMIPENDSET;
561 	SystemControl_CRITICAL_SECTION_LEAVE();
562 }
563 
hri_systemcontrol_set_ICSR_VECTPENDING_bf(const void * const hw,hri_systemcontrol_icsr_reg_t mask)564 static inline void hri_systemcontrol_set_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
565 {
566 	SystemControl_CRITICAL_SECTION_ENTER();
567 	((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_VECTPENDING(mask);
568 	SystemControl_CRITICAL_SECTION_LEAVE();
569 }
570 
hri_systemcontrol_get_ICSR_VECTPENDING_bf(const void * const hw,hri_systemcontrol_icsr_reg_t mask)571 static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_VECTPENDING_bf(const void *const            hw,
572                                                                                      hri_systemcontrol_icsr_reg_t mask)
573 {
574 	uint32_t tmp;
575 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
576 	tmp = (tmp & SystemControl_ICSR_VECTPENDING(mask)) >> 12;
577 	return tmp;
578 }
579 
hri_systemcontrol_write_ICSR_VECTPENDING_bf(const void * const hw,hri_systemcontrol_icsr_reg_t data)580 static inline void hri_systemcontrol_write_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t data)
581 {
582 	uint32_t tmp;
583 	SystemControl_CRITICAL_SECTION_ENTER();
584 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
585 	tmp &= ~SystemControl_ICSR_VECTPENDING_Msk;
586 	tmp |= SystemControl_ICSR_VECTPENDING(data);
587 	((Systemcontrol *)hw)->ICSR.reg = tmp;
588 	SystemControl_CRITICAL_SECTION_LEAVE();
589 }
590 
hri_systemcontrol_clear_ICSR_VECTPENDING_bf(const void * const hw,hri_systemcontrol_icsr_reg_t mask)591 static inline void hri_systemcontrol_clear_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
592 {
593 	SystemControl_CRITICAL_SECTION_ENTER();
594 	((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_VECTPENDING(mask);
595 	SystemControl_CRITICAL_SECTION_LEAVE();
596 }
597 
hri_systemcontrol_toggle_ICSR_VECTPENDING_bf(const void * const hw,hri_systemcontrol_icsr_reg_t mask)598 static inline void hri_systemcontrol_toggle_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
599 {
600 	SystemControl_CRITICAL_SECTION_ENTER();
601 	((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_VECTPENDING(mask);
602 	SystemControl_CRITICAL_SECTION_LEAVE();
603 }
604 
hri_systemcontrol_read_ICSR_VECTPENDING_bf(const void * const hw)605 static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_VECTPENDING_bf(const void *const hw)
606 {
607 	uint32_t tmp;
608 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
609 	tmp = (tmp & SystemControl_ICSR_VECTPENDING_Msk) >> 12;
610 	return tmp;
611 }
612 
hri_systemcontrol_set_ICSR_reg(const void * const hw,hri_systemcontrol_icsr_reg_t mask)613 static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
614 {
615 	SystemControl_CRITICAL_SECTION_ENTER();
616 	((Systemcontrol *)hw)->ICSR.reg |= mask;
617 	SystemControl_CRITICAL_SECTION_LEAVE();
618 }
619 
hri_systemcontrol_get_ICSR_reg(const void * const hw,hri_systemcontrol_icsr_reg_t mask)620 static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const            hw,
621                                                                           hri_systemcontrol_icsr_reg_t mask)
622 {
623 	uint32_t tmp;
624 	tmp = ((Systemcontrol *)hw)->ICSR.reg;
625 	tmp &= mask;
626 	return tmp;
627 }
628 
hri_systemcontrol_write_ICSR_reg(const void * const hw,hri_systemcontrol_icsr_reg_t data)629 static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data)
630 {
631 	SystemControl_CRITICAL_SECTION_ENTER();
632 	((Systemcontrol *)hw)->ICSR.reg = data;
633 	SystemControl_CRITICAL_SECTION_LEAVE();
634 }
635 
hri_systemcontrol_clear_ICSR_reg(const void * const hw,hri_systemcontrol_icsr_reg_t mask)636 static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
637 {
638 	SystemControl_CRITICAL_SECTION_ENTER();
639 	((Systemcontrol *)hw)->ICSR.reg &= ~mask;
640 	SystemControl_CRITICAL_SECTION_LEAVE();
641 }
642 
hri_systemcontrol_toggle_ICSR_reg(const void * const hw,hri_systemcontrol_icsr_reg_t mask)643 static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask)
644 {
645 	SystemControl_CRITICAL_SECTION_ENTER();
646 	((Systemcontrol *)hw)->ICSR.reg ^= mask;
647 	SystemControl_CRITICAL_SECTION_LEAVE();
648 }
649 
hri_systemcontrol_read_ICSR_reg(const void * const hw)650 static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw)
651 {
652 	return ((Systemcontrol *)hw)->ICSR.reg;
653 }
654 
hri_systemcontrol_set_VTOR_TBLOFF_bf(const void * const hw,hri_systemcontrol_vtor_reg_t mask)655 static inline void hri_systemcontrol_set_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
656 {
657 	SystemControl_CRITICAL_SECTION_ENTER();
658 	((Systemcontrol *)hw)->VTOR.reg |= SystemControl_VTOR_TBLOFF(mask);
659 	SystemControl_CRITICAL_SECTION_LEAVE();
660 }
661 
hri_systemcontrol_get_VTOR_TBLOFF_bf(const void * const hw,hri_systemcontrol_vtor_reg_t mask)662 static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_TBLOFF_bf(const void *const            hw,
663                                                                                 hri_systemcontrol_vtor_reg_t mask)
664 {
665 	uint32_t tmp;
666 	tmp = ((Systemcontrol *)hw)->VTOR.reg;
667 	tmp = (tmp & SystemControl_VTOR_TBLOFF(mask)) >> 7;
668 	return tmp;
669 }
670 
hri_systemcontrol_write_VTOR_TBLOFF_bf(const void * const hw,hri_systemcontrol_vtor_reg_t data)671 static inline void hri_systemcontrol_write_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t data)
672 {
673 	uint32_t tmp;
674 	SystemControl_CRITICAL_SECTION_ENTER();
675 	tmp = ((Systemcontrol *)hw)->VTOR.reg;
676 	tmp &= ~SystemControl_VTOR_TBLOFF_Msk;
677 	tmp |= SystemControl_VTOR_TBLOFF(data);
678 	((Systemcontrol *)hw)->VTOR.reg = tmp;
679 	SystemControl_CRITICAL_SECTION_LEAVE();
680 }
681 
hri_systemcontrol_clear_VTOR_TBLOFF_bf(const void * const hw,hri_systemcontrol_vtor_reg_t mask)682 static inline void hri_systemcontrol_clear_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
683 {
684 	SystemControl_CRITICAL_SECTION_ENTER();
685 	((Systemcontrol *)hw)->VTOR.reg &= ~SystemControl_VTOR_TBLOFF(mask);
686 	SystemControl_CRITICAL_SECTION_LEAVE();
687 }
688 
hri_systemcontrol_toggle_VTOR_TBLOFF_bf(const void * const hw,hri_systemcontrol_vtor_reg_t mask)689 static inline void hri_systemcontrol_toggle_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
690 {
691 	SystemControl_CRITICAL_SECTION_ENTER();
692 	((Systemcontrol *)hw)->VTOR.reg ^= SystemControl_VTOR_TBLOFF(mask);
693 	SystemControl_CRITICAL_SECTION_LEAVE();
694 }
695 
hri_systemcontrol_read_VTOR_TBLOFF_bf(const void * const hw)696 static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_TBLOFF_bf(const void *const hw)
697 {
698 	uint32_t tmp;
699 	tmp = ((Systemcontrol *)hw)->VTOR.reg;
700 	tmp = (tmp & SystemControl_VTOR_TBLOFF_Msk) >> 7;
701 	return tmp;
702 }
703 
hri_systemcontrol_set_VTOR_reg(const void * const hw,hri_systemcontrol_vtor_reg_t mask)704 static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
705 {
706 	SystemControl_CRITICAL_SECTION_ENTER();
707 	((Systemcontrol *)hw)->VTOR.reg |= mask;
708 	SystemControl_CRITICAL_SECTION_LEAVE();
709 }
710 
hri_systemcontrol_get_VTOR_reg(const void * const hw,hri_systemcontrol_vtor_reg_t mask)711 static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const            hw,
712                                                                           hri_systemcontrol_vtor_reg_t mask)
713 {
714 	uint32_t tmp;
715 	tmp = ((Systemcontrol *)hw)->VTOR.reg;
716 	tmp &= mask;
717 	return tmp;
718 }
719 
hri_systemcontrol_write_VTOR_reg(const void * const hw,hri_systemcontrol_vtor_reg_t data)720 static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data)
721 {
722 	SystemControl_CRITICAL_SECTION_ENTER();
723 	((Systemcontrol *)hw)->VTOR.reg = data;
724 	SystemControl_CRITICAL_SECTION_LEAVE();
725 }
726 
hri_systemcontrol_clear_VTOR_reg(const void * const hw,hri_systemcontrol_vtor_reg_t mask)727 static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
728 {
729 	SystemControl_CRITICAL_SECTION_ENTER();
730 	((Systemcontrol *)hw)->VTOR.reg &= ~mask;
731 	SystemControl_CRITICAL_SECTION_LEAVE();
732 }
733 
hri_systemcontrol_toggle_VTOR_reg(const void * const hw,hri_systemcontrol_vtor_reg_t mask)734 static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask)
735 {
736 	SystemControl_CRITICAL_SECTION_ENTER();
737 	((Systemcontrol *)hw)->VTOR.reg ^= mask;
738 	SystemControl_CRITICAL_SECTION_LEAVE();
739 }
740 
hri_systemcontrol_read_VTOR_reg(const void * const hw)741 static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw)
742 {
743 	return ((Systemcontrol *)hw)->VTOR.reg;
744 }
745 
hri_systemcontrol_set_AIRCR_VECTCLRACTIVE_bit(const void * const hw)746 static inline void hri_systemcontrol_set_AIRCR_VECTCLRACTIVE_bit(const void *const hw)
747 {
748 	SystemControl_CRITICAL_SECTION_ENTER();
749 	((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_VECTCLRACTIVE;
750 	SystemControl_CRITICAL_SECTION_LEAVE();
751 }
752 
hri_systemcontrol_get_AIRCR_VECTCLRACTIVE_bit(const void * const hw)753 static inline bool hri_systemcontrol_get_AIRCR_VECTCLRACTIVE_bit(const void *const hw)
754 {
755 	uint32_t tmp;
756 	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
757 	tmp = (tmp & SystemControl_AIRCR_VECTCLRACTIVE) >> 1;
758 	return (bool)tmp;
759 }
760 
hri_systemcontrol_write_AIRCR_VECTCLRACTIVE_bit(const void * const hw,bool value)761 static inline void hri_systemcontrol_write_AIRCR_VECTCLRACTIVE_bit(const void *const hw, bool value)
762 {
763 	uint32_t tmp;
764 	SystemControl_CRITICAL_SECTION_ENTER();
765 	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
766 	tmp &= ~SystemControl_AIRCR_VECTCLRACTIVE;
767 	tmp |= value << 1;
768 	((Systemcontrol *)hw)->AIRCR.reg = tmp;
769 	SystemControl_CRITICAL_SECTION_LEAVE();
770 }
771 
hri_systemcontrol_clear_AIRCR_VECTCLRACTIVE_bit(const void * const hw)772 static inline void hri_systemcontrol_clear_AIRCR_VECTCLRACTIVE_bit(const void *const hw)
773 {
774 	SystemControl_CRITICAL_SECTION_ENTER();
775 	((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_VECTCLRACTIVE;
776 	SystemControl_CRITICAL_SECTION_LEAVE();
777 }
778 
hri_systemcontrol_toggle_AIRCR_VECTCLRACTIVE_bit(const void * const hw)779 static inline void hri_systemcontrol_toggle_AIRCR_VECTCLRACTIVE_bit(const void *const hw)
780 {
781 	SystemControl_CRITICAL_SECTION_ENTER();
782 	((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_VECTCLRACTIVE;
783 	SystemControl_CRITICAL_SECTION_LEAVE();
784 }
785 
hri_systemcontrol_set_AIRCR_SYSRESETREQ_bit(const void * const hw)786 static inline void hri_systemcontrol_set_AIRCR_SYSRESETREQ_bit(const void *const hw)
787 {
788 	SystemControl_CRITICAL_SECTION_ENTER();
789 	((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_SYSRESETREQ;
790 	SystemControl_CRITICAL_SECTION_LEAVE();
791 }
792 
hri_systemcontrol_get_AIRCR_SYSRESETREQ_bit(const void * const hw)793 static inline bool hri_systemcontrol_get_AIRCR_SYSRESETREQ_bit(const void *const hw)
794 {
795 	uint32_t tmp;
796 	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
797 	tmp = (tmp & SystemControl_AIRCR_SYSRESETREQ) >> 2;
798 	return (bool)tmp;
799 }
800 
hri_systemcontrol_write_AIRCR_SYSRESETREQ_bit(const void * const hw,bool value)801 static inline void hri_systemcontrol_write_AIRCR_SYSRESETREQ_bit(const void *const hw, bool value)
802 {
803 	uint32_t tmp;
804 	SystemControl_CRITICAL_SECTION_ENTER();
805 	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
806 	tmp &= ~SystemControl_AIRCR_SYSRESETREQ;
807 	tmp |= value << 2;
808 	((Systemcontrol *)hw)->AIRCR.reg = tmp;
809 	SystemControl_CRITICAL_SECTION_LEAVE();
810 }
811 
hri_systemcontrol_clear_AIRCR_SYSRESETREQ_bit(const void * const hw)812 static inline void hri_systemcontrol_clear_AIRCR_SYSRESETREQ_bit(const void *const hw)
813 {
814 	SystemControl_CRITICAL_SECTION_ENTER();
815 	((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_SYSRESETREQ;
816 	SystemControl_CRITICAL_SECTION_LEAVE();
817 }
818 
hri_systemcontrol_toggle_AIRCR_SYSRESETREQ_bit(const void * const hw)819 static inline void hri_systemcontrol_toggle_AIRCR_SYSRESETREQ_bit(const void *const hw)
820 {
821 	SystemControl_CRITICAL_SECTION_ENTER();
822 	((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_SYSRESETREQ;
823 	SystemControl_CRITICAL_SECTION_LEAVE();
824 }
825 
hri_systemcontrol_set_AIRCR_ENDIANNESS_bit(const void * const hw)826 static inline void hri_systemcontrol_set_AIRCR_ENDIANNESS_bit(const void *const hw)
827 {
828 	SystemControl_CRITICAL_SECTION_ENTER();
829 	((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_ENDIANNESS;
830 	SystemControl_CRITICAL_SECTION_LEAVE();
831 }
832 
hri_systemcontrol_get_AIRCR_ENDIANNESS_bit(const void * const hw)833 static inline bool hri_systemcontrol_get_AIRCR_ENDIANNESS_bit(const void *const hw)
834 {
835 	uint32_t tmp;
836 	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
837 	tmp = (tmp & SystemControl_AIRCR_ENDIANNESS) >> 15;
838 	return (bool)tmp;
839 }
840 
hri_systemcontrol_write_AIRCR_ENDIANNESS_bit(const void * const hw,bool value)841 static inline void hri_systemcontrol_write_AIRCR_ENDIANNESS_bit(const void *const hw, bool value)
842 {
843 	uint32_t tmp;
844 	SystemControl_CRITICAL_SECTION_ENTER();
845 	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
846 	tmp &= ~SystemControl_AIRCR_ENDIANNESS;
847 	tmp |= value << 15;
848 	((Systemcontrol *)hw)->AIRCR.reg = tmp;
849 	SystemControl_CRITICAL_SECTION_LEAVE();
850 }
851 
hri_systemcontrol_clear_AIRCR_ENDIANNESS_bit(const void * const hw)852 static inline void hri_systemcontrol_clear_AIRCR_ENDIANNESS_bit(const void *const hw)
853 {
854 	SystemControl_CRITICAL_SECTION_ENTER();
855 	((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_ENDIANNESS;
856 	SystemControl_CRITICAL_SECTION_LEAVE();
857 }
858 
hri_systemcontrol_toggle_AIRCR_ENDIANNESS_bit(const void * const hw)859 static inline void hri_systemcontrol_toggle_AIRCR_ENDIANNESS_bit(const void *const hw)
860 {
861 	SystemControl_CRITICAL_SECTION_ENTER();
862 	((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_ENDIANNESS;
863 	SystemControl_CRITICAL_SECTION_LEAVE();
864 }
865 
hri_systemcontrol_set_AIRCR_VECTKEY_bf(const void * const hw,hri_systemcontrol_aircr_reg_t mask)866 static inline void hri_systemcontrol_set_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
867 {
868 	SystemControl_CRITICAL_SECTION_ENTER();
869 	((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_VECTKEY(mask);
870 	SystemControl_CRITICAL_SECTION_LEAVE();
871 }
872 
hri_systemcontrol_get_AIRCR_VECTKEY_bf(const void * const hw,hri_systemcontrol_aircr_reg_t mask)873 static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_VECTKEY_bf(const void *const             hw,
874                                                                                    hri_systemcontrol_aircr_reg_t mask)
875 {
876 	uint32_t tmp;
877 	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
878 	tmp = (tmp & SystemControl_AIRCR_VECTKEY(mask)) >> 16;
879 	return tmp;
880 }
881 
hri_systemcontrol_write_AIRCR_VECTKEY_bf(const void * const hw,hri_systemcontrol_aircr_reg_t data)882 static inline void hri_systemcontrol_write_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t data)
883 {
884 	uint32_t tmp;
885 	SystemControl_CRITICAL_SECTION_ENTER();
886 	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
887 	tmp &= ~SystemControl_AIRCR_VECTKEY_Msk;
888 	tmp |= SystemControl_AIRCR_VECTKEY(data);
889 	((Systemcontrol *)hw)->AIRCR.reg = tmp;
890 	SystemControl_CRITICAL_SECTION_LEAVE();
891 }
892 
hri_systemcontrol_clear_AIRCR_VECTKEY_bf(const void * const hw,hri_systemcontrol_aircr_reg_t mask)893 static inline void hri_systemcontrol_clear_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
894 {
895 	SystemControl_CRITICAL_SECTION_ENTER();
896 	((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_VECTKEY(mask);
897 	SystemControl_CRITICAL_SECTION_LEAVE();
898 }
899 
hri_systemcontrol_toggle_AIRCR_VECTKEY_bf(const void * const hw,hri_systemcontrol_aircr_reg_t mask)900 static inline void hri_systemcontrol_toggle_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
901 {
902 	SystemControl_CRITICAL_SECTION_ENTER();
903 	((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_VECTKEY(mask);
904 	SystemControl_CRITICAL_SECTION_LEAVE();
905 }
906 
hri_systemcontrol_read_AIRCR_VECTKEY_bf(const void * const hw)907 static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_VECTKEY_bf(const void *const hw)
908 {
909 	uint32_t tmp;
910 	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
911 	tmp = (tmp & SystemControl_AIRCR_VECTKEY_Msk) >> 16;
912 	return tmp;
913 }
914 
hri_systemcontrol_set_AIRCR_reg(const void * const hw,hri_systemcontrol_aircr_reg_t mask)915 static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
916 {
917 	SystemControl_CRITICAL_SECTION_ENTER();
918 	((Systemcontrol *)hw)->AIRCR.reg |= mask;
919 	SystemControl_CRITICAL_SECTION_LEAVE();
920 }
921 
hri_systemcontrol_get_AIRCR_reg(const void * const hw,hri_systemcontrol_aircr_reg_t mask)922 static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const             hw,
923                                                                             hri_systemcontrol_aircr_reg_t mask)
924 {
925 	uint32_t tmp;
926 	tmp = ((Systemcontrol *)hw)->AIRCR.reg;
927 	tmp &= mask;
928 	return tmp;
929 }
930 
hri_systemcontrol_write_AIRCR_reg(const void * const hw,hri_systemcontrol_aircr_reg_t data)931 static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data)
932 {
933 	SystemControl_CRITICAL_SECTION_ENTER();
934 	((Systemcontrol *)hw)->AIRCR.reg = data;
935 	SystemControl_CRITICAL_SECTION_LEAVE();
936 }
937 
hri_systemcontrol_clear_AIRCR_reg(const void * const hw,hri_systemcontrol_aircr_reg_t mask)938 static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
939 {
940 	SystemControl_CRITICAL_SECTION_ENTER();
941 	((Systemcontrol *)hw)->AIRCR.reg &= ~mask;
942 	SystemControl_CRITICAL_SECTION_LEAVE();
943 }
944 
hri_systemcontrol_toggle_AIRCR_reg(const void * const hw,hri_systemcontrol_aircr_reg_t mask)945 static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask)
946 {
947 	SystemControl_CRITICAL_SECTION_ENTER();
948 	((Systemcontrol *)hw)->AIRCR.reg ^= mask;
949 	SystemControl_CRITICAL_SECTION_LEAVE();
950 }
951 
hri_systemcontrol_read_AIRCR_reg(const void * const hw)952 static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw)
953 {
954 	return ((Systemcontrol *)hw)->AIRCR.reg;
955 }
956 
hri_systemcontrol_set_SCR_SLEEPONEXIT_bit(const void * const hw)957 static inline void hri_systemcontrol_set_SCR_SLEEPONEXIT_bit(const void *const hw)
958 {
959 	SystemControl_CRITICAL_SECTION_ENTER();
960 	((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPONEXIT;
961 	SystemControl_CRITICAL_SECTION_LEAVE();
962 }
963 
hri_systemcontrol_get_SCR_SLEEPONEXIT_bit(const void * const hw)964 static inline bool hri_systemcontrol_get_SCR_SLEEPONEXIT_bit(const void *const hw)
965 {
966 	uint32_t tmp;
967 	tmp = ((Systemcontrol *)hw)->SCR.reg;
968 	tmp = (tmp & SystemControl_SCR_SLEEPONEXIT) >> 1;
969 	return (bool)tmp;
970 }
971 
hri_systemcontrol_write_SCR_SLEEPONEXIT_bit(const void * const hw,bool value)972 static inline void hri_systemcontrol_write_SCR_SLEEPONEXIT_bit(const void *const hw, bool value)
973 {
974 	uint32_t tmp;
975 	SystemControl_CRITICAL_SECTION_ENTER();
976 	tmp = ((Systemcontrol *)hw)->SCR.reg;
977 	tmp &= ~SystemControl_SCR_SLEEPONEXIT;
978 	tmp |= value << 1;
979 	((Systemcontrol *)hw)->SCR.reg = tmp;
980 	SystemControl_CRITICAL_SECTION_LEAVE();
981 }
982 
hri_systemcontrol_clear_SCR_SLEEPONEXIT_bit(const void * const hw)983 static inline void hri_systemcontrol_clear_SCR_SLEEPONEXIT_bit(const void *const hw)
984 {
985 	SystemControl_CRITICAL_SECTION_ENTER();
986 	((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SLEEPONEXIT;
987 	SystemControl_CRITICAL_SECTION_LEAVE();
988 }
989 
hri_systemcontrol_toggle_SCR_SLEEPONEXIT_bit(const void * const hw)990 static inline void hri_systemcontrol_toggle_SCR_SLEEPONEXIT_bit(const void *const hw)
991 {
992 	SystemControl_CRITICAL_SECTION_ENTER();
993 	((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SLEEPONEXIT;
994 	SystemControl_CRITICAL_SECTION_LEAVE();
995 }
996 
hri_systemcontrol_set_SCR_SLEEPDEEP_bit(const void * const hw)997 static inline void hri_systemcontrol_set_SCR_SLEEPDEEP_bit(const void *const hw)
998 {
999 	SystemControl_CRITICAL_SECTION_ENTER();
1000 	((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPDEEP;
1001 	SystemControl_CRITICAL_SECTION_LEAVE();
1002 }
1003 
hri_systemcontrol_get_SCR_SLEEPDEEP_bit(const void * const hw)1004 static inline bool hri_systemcontrol_get_SCR_SLEEPDEEP_bit(const void *const hw)
1005 {
1006 	uint32_t tmp;
1007 	tmp = ((Systemcontrol *)hw)->SCR.reg;
1008 	tmp = (tmp & SystemControl_SCR_SLEEPDEEP) >> 2;
1009 	return (bool)tmp;
1010 }
1011 
hri_systemcontrol_write_SCR_SLEEPDEEP_bit(const void * const hw,bool value)1012 static inline void hri_systemcontrol_write_SCR_SLEEPDEEP_bit(const void *const hw, bool value)
1013 {
1014 	uint32_t tmp;
1015 	SystemControl_CRITICAL_SECTION_ENTER();
1016 	tmp = ((Systemcontrol *)hw)->SCR.reg;
1017 	tmp &= ~SystemControl_SCR_SLEEPDEEP;
1018 	tmp |= value << 2;
1019 	((Systemcontrol *)hw)->SCR.reg = tmp;
1020 	SystemControl_CRITICAL_SECTION_LEAVE();
1021 }
1022 
hri_systemcontrol_clear_SCR_SLEEPDEEP_bit(const void * const hw)1023 static inline void hri_systemcontrol_clear_SCR_SLEEPDEEP_bit(const void *const hw)
1024 {
1025 	SystemControl_CRITICAL_SECTION_ENTER();
1026 	((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SLEEPDEEP;
1027 	SystemControl_CRITICAL_SECTION_LEAVE();
1028 }
1029 
hri_systemcontrol_toggle_SCR_SLEEPDEEP_bit(const void * const hw)1030 static inline void hri_systemcontrol_toggle_SCR_SLEEPDEEP_bit(const void *const hw)
1031 {
1032 	SystemControl_CRITICAL_SECTION_ENTER();
1033 	((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SLEEPDEEP;
1034 	SystemControl_CRITICAL_SECTION_LEAVE();
1035 }
1036 
hri_systemcontrol_set_SCR_SEVONPEND_bit(const void * const hw)1037 static inline void hri_systemcontrol_set_SCR_SEVONPEND_bit(const void *const hw)
1038 {
1039 	SystemControl_CRITICAL_SECTION_ENTER();
1040 	((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SEVONPEND;
1041 	SystemControl_CRITICAL_SECTION_LEAVE();
1042 }
1043 
hri_systemcontrol_get_SCR_SEVONPEND_bit(const void * const hw)1044 static inline bool hri_systemcontrol_get_SCR_SEVONPEND_bit(const void *const hw)
1045 {
1046 	uint32_t tmp;
1047 	tmp = ((Systemcontrol *)hw)->SCR.reg;
1048 	tmp = (tmp & SystemControl_SCR_SEVONPEND) >> 4;
1049 	return (bool)tmp;
1050 }
1051 
hri_systemcontrol_write_SCR_SEVONPEND_bit(const void * const hw,bool value)1052 static inline void hri_systemcontrol_write_SCR_SEVONPEND_bit(const void *const hw, bool value)
1053 {
1054 	uint32_t tmp;
1055 	SystemControl_CRITICAL_SECTION_ENTER();
1056 	tmp = ((Systemcontrol *)hw)->SCR.reg;
1057 	tmp &= ~SystemControl_SCR_SEVONPEND;
1058 	tmp |= value << 4;
1059 	((Systemcontrol *)hw)->SCR.reg = tmp;
1060 	SystemControl_CRITICAL_SECTION_LEAVE();
1061 }
1062 
hri_systemcontrol_clear_SCR_SEVONPEND_bit(const void * const hw)1063 static inline void hri_systemcontrol_clear_SCR_SEVONPEND_bit(const void *const hw)
1064 {
1065 	SystemControl_CRITICAL_SECTION_ENTER();
1066 	((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SEVONPEND;
1067 	SystemControl_CRITICAL_SECTION_LEAVE();
1068 }
1069 
hri_systemcontrol_toggle_SCR_SEVONPEND_bit(const void * const hw)1070 static inline void hri_systemcontrol_toggle_SCR_SEVONPEND_bit(const void *const hw)
1071 {
1072 	SystemControl_CRITICAL_SECTION_ENTER();
1073 	((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SEVONPEND;
1074 	SystemControl_CRITICAL_SECTION_LEAVE();
1075 }
1076 
hri_systemcontrol_set_SCR_reg(const void * const hw,hri_systemcontrol_scr_reg_t mask)1077 static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
1078 {
1079 	SystemControl_CRITICAL_SECTION_ENTER();
1080 	((Systemcontrol *)hw)->SCR.reg |= mask;
1081 	SystemControl_CRITICAL_SECTION_LEAVE();
1082 }
1083 
hri_systemcontrol_get_SCR_reg(const void * const hw,hri_systemcontrol_scr_reg_t mask)1084 static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const           hw,
1085                                                                         hri_systemcontrol_scr_reg_t mask)
1086 {
1087 	uint32_t tmp;
1088 	tmp = ((Systemcontrol *)hw)->SCR.reg;
1089 	tmp &= mask;
1090 	return tmp;
1091 }
1092 
hri_systemcontrol_write_SCR_reg(const void * const hw,hri_systemcontrol_scr_reg_t data)1093 static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data)
1094 {
1095 	SystemControl_CRITICAL_SECTION_ENTER();
1096 	((Systemcontrol *)hw)->SCR.reg = data;
1097 	SystemControl_CRITICAL_SECTION_LEAVE();
1098 }
1099 
hri_systemcontrol_clear_SCR_reg(const void * const hw,hri_systemcontrol_scr_reg_t mask)1100 static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
1101 {
1102 	SystemControl_CRITICAL_SECTION_ENTER();
1103 	((Systemcontrol *)hw)->SCR.reg &= ~mask;
1104 	SystemControl_CRITICAL_SECTION_LEAVE();
1105 }
1106 
hri_systemcontrol_toggle_SCR_reg(const void * const hw,hri_systemcontrol_scr_reg_t mask)1107 static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask)
1108 {
1109 	SystemControl_CRITICAL_SECTION_ENTER();
1110 	((Systemcontrol *)hw)->SCR.reg ^= mask;
1111 	SystemControl_CRITICAL_SECTION_LEAVE();
1112 }
1113 
hri_systemcontrol_read_SCR_reg(const void * const hw)1114 static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw)
1115 {
1116 	return ((Systemcontrol *)hw)->SCR.reg;
1117 }
1118 
hri_systemcontrol_set_CCR_UNALIGN_TRP_bit(const void * const hw)1119 static inline void hri_systemcontrol_set_CCR_UNALIGN_TRP_bit(const void *const hw)
1120 {
1121 	SystemControl_CRITICAL_SECTION_ENTER();
1122 	((Systemcontrol *)hw)->CCR.reg |= SystemControl_CCR_UNALIGN_TRP;
1123 	SystemControl_CRITICAL_SECTION_LEAVE();
1124 }
1125 
hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void * const hw)1126 static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw)
1127 {
1128 	uint32_t tmp;
1129 	tmp = ((Systemcontrol *)hw)->CCR.reg;
1130 	tmp = (tmp & SystemControl_CCR_UNALIGN_TRP) >> 3;
1131 	return (bool)tmp;
1132 }
1133 
hri_systemcontrol_write_CCR_UNALIGN_TRP_bit(const void * const hw,bool value)1134 static inline void hri_systemcontrol_write_CCR_UNALIGN_TRP_bit(const void *const hw, bool value)
1135 {
1136 	uint32_t tmp;
1137 	SystemControl_CRITICAL_SECTION_ENTER();
1138 	tmp = ((Systemcontrol *)hw)->CCR.reg;
1139 	tmp &= ~SystemControl_CCR_UNALIGN_TRP;
1140 	tmp |= value << 3;
1141 	((Systemcontrol *)hw)->CCR.reg = tmp;
1142 	SystemControl_CRITICAL_SECTION_LEAVE();
1143 }
1144 
hri_systemcontrol_clear_CCR_UNALIGN_TRP_bit(const void * const hw)1145 static inline void hri_systemcontrol_clear_CCR_UNALIGN_TRP_bit(const void *const hw)
1146 {
1147 	SystemControl_CRITICAL_SECTION_ENTER();
1148 	((Systemcontrol *)hw)->CCR.reg &= ~SystemControl_CCR_UNALIGN_TRP;
1149 	SystemControl_CRITICAL_SECTION_LEAVE();
1150 }
1151 
hri_systemcontrol_toggle_CCR_UNALIGN_TRP_bit(const void * const hw)1152 static inline void hri_systemcontrol_toggle_CCR_UNALIGN_TRP_bit(const void *const hw)
1153 {
1154 	SystemControl_CRITICAL_SECTION_ENTER();
1155 	((Systemcontrol *)hw)->CCR.reg ^= SystemControl_CCR_UNALIGN_TRP;
1156 	SystemControl_CRITICAL_SECTION_LEAVE();
1157 }
1158 
hri_systemcontrol_set_CCR_STKALIGN_bit(const void * const hw)1159 static inline void hri_systemcontrol_set_CCR_STKALIGN_bit(const void *const hw)
1160 {
1161 	SystemControl_CRITICAL_SECTION_ENTER();
1162 	((Systemcontrol *)hw)->CCR.reg |= SystemControl_CCR_STKALIGN;
1163 	SystemControl_CRITICAL_SECTION_LEAVE();
1164 }
1165 
hri_systemcontrol_get_CCR_STKALIGN_bit(const void * const hw)1166 static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw)
1167 {
1168 	uint32_t tmp;
1169 	tmp = ((Systemcontrol *)hw)->CCR.reg;
1170 	tmp = (tmp & SystemControl_CCR_STKALIGN) >> 9;
1171 	return (bool)tmp;
1172 }
1173 
hri_systemcontrol_write_CCR_STKALIGN_bit(const void * const hw,bool value)1174 static inline void hri_systemcontrol_write_CCR_STKALIGN_bit(const void *const hw, bool value)
1175 {
1176 	uint32_t tmp;
1177 	SystemControl_CRITICAL_SECTION_ENTER();
1178 	tmp = ((Systemcontrol *)hw)->CCR.reg;
1179 	tmp &= ~SystemControl_CCR_STKALIGN;
1180 	tmp |= value << 9;
1181 	((Systemcontrol *)hw)->CCR.reg = tmp;
1182 	SystemControl_CRITICAL_SECTION_LEAVE();
1183 }
1184 
hri_systemcontrol_clear_CCR_STKALIGN_bit(const void * const hw)1185 static inline void hri_systemcontrol_clear_CCR_STKALIGN_bit(const void *const hw)
1186 {
1187 	SystemControl_CRITICAL_SECTION_ENTER();
1188 	((Systemcontrol *)hw)->CCR.reg &= ~SystemControl_CCR_STKALIGN;
1189 	SystemControl_CRITICAL_SECTION_LEAVE();
1190 }
1191 
hri_systemcontrol_toggle_CCR_STKALIGN_bit(const void * const hw)1192 static inline void hri_systemcontrol_toggle_CCR_STKALIGN_bit(const void *const hw)
1193 {
1194 	SystemControl_CRITICAL_SECTION_ENTER();
1195 	((Systemcontrol *)hw)->CCR.reg ^= SystemControl_CCR_STKALIGN;
1196 	SystemControl_CRITICAL_SECTION_LEAVE();
1197 }
1198 
hri_systemcontrol_set_CCR_reg(const void * const hw,hri_systemcontrol_ccr_reg_t mask)1199 static inline void hri_systemcontrol_set_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
1200 {
1201 	SystemControl_CRITICAL_SECTION_ENTER();
1202 	((Systemcontrol *)hw)->CCR.reg |= mask;
1203 	SystemControl_CRITICAL_SECTION_LEAVE();
1204 }
1205 
hri_systemcontrol_get_CCR_reg(const void * const hw,hri_systemcontrol_ccr_reg_t mask)1206 static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const           hw,
1207                                                                         hri_systemcontrol_ccr_reg_t mask)
1208 {
1209 	uint32_t tmp;
1210 	tmp = ((Systemcontrol *)hw)->CCR.reg;
1211 	tmp &= mask;
1212 	return tmp;
1213 }
1214 
hri_systemcontrol_write_CCR_reg(const void * const hw,hri_systemcontrol_ccr_reg_t data)1215 static inline void hri_systemcontrol_write_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t data)
1216 {
1217 	SystemControl_CRITICAL_SECTION_ENTER();
1218 	((Systemcontrol *)hw)->CCR.reg = data;
1219 	SystemControl_CRITICAL_SECTION_LEAVE();
1220 }
1221 
hri_systemcontrol_clear_CCR_reg(const void * const hw,hri_systemcontrol_ccr_reg_t mask)1222 static inline void hri_systemcontrol_clear_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
1223 {
1224 	SystemControl_CRITICAL_SECTION_ENTER();
1225 	((Systemcontrol *)hw)->CCR.reg &= ~mask;
1226 	SystemControl_CRITICAL_SECTION_LEAVE();
1227 }
1228 
hri_systemcontrol_toggle_CCR_reg(const void * const hw,hri_systemcontrol_ccr_reg_t mask)1229 static inline void hri_systemcontrol_toggle_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask)
1230 {
1231 	SystemControl_CRITICAL_SECTION_ENTER();
1232 	((Systemcontrol *)hw)->CCR.reg ^= mask;
1233 	SystemControl_CRITICAL_SECTION_LEAVE();
1234 }
1235 
hri_systemcontrol_read_CCR_reg(const void * const hw)1236 static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw)
1237 {
1238 	return ((Systemcontrol *)hw)->CCR.reg;
1239 }
1240 
hri_systemcontrol_set_SHPR2_PRI_11_bf(const void * const hw,hri_systemcontrol_shpr2_reg_t mask)1241 static inline void hri_systemcontrol_set_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
1242 {
1243 	SystemControl_CRITICAL_SECTION_ENTER();
1244 	((Systemcontrol *)hw)->SHPR2.reg |= SystemControl_SHPR2_PRI_11(mask);
1245 	SystemControl_CRITICAL_SECTION_LEAVE();
1246 }
1247 
hri_systemcontrol_get_SHPR2_PRI_11_bf(const void * const hw,hri_systemcontrol_shpr2_reg_t mask)1248 static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_PRI_11_bf(const void *const             hw,
1249                                                                                   hri_systemcontrol_shpr2_reg_t mask)
1250 {
1251 	uint32_t tmp;
1252 	tmp = ((Systemcontrol *)hw)->SHPR2.reg;
1253 	tmp = (tmp & SystemControl_SHPR2_PRI_11(mask)) >> 24;
1254 	return tmp;
1255 }
1256 
hri_systemcontrol_write_SHPR2_PRI_11_bf(const void * const hw,hri_systemcontrol_shpr2_reg_t data)1257 static inline void hri_systemcontrol_write_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t data)
1258 {
1259 	uint32_t tmp;
1260 	SystemControl_CRITICAL_SECTION_ENTER();
1261 	tmp = ((Systemcontrol *)hw)->SHPR2.reg;
1262 	tmp &= ~SystemControl_SHPR2_PRI_11_Msk;
1263 	tmp |= SystemControl_SHPR2_PRI_11(data);
1264 	((Systemcontrol *)hw)->SHPR2.reg = tmp;
1265 	SystemControl_CRITICAL_SECTION_LEAVE();
1266 }
1267 
hri_systemcontrol_clear_SHPR2_PRI_11_bf(const void * const hw,hri_systemcontrol_shpr2_reg_t mask)1268 static inline void hri_systemcontrol_clear_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
1269 {
1270 	SystemControl_CRITICAL_SECTION_ENTER();
1271 	((Systemcontrol *)hw)->SHPR2.reg &= ~SystemControl_SHPR2_PRI_11(mask);
1272 	SystemControl_CRITICAL_SECTION_LEAVE();
1273 }
1274 
hri_systemcontrol_toggle_SHPR2_PRI_11_bf(const void * const hw,hri_systemcontrol_shpr2_reg_t mask)1275 static inline void hri_systemcontrol_toggle_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
1276 {
1277 	SystemControl_CRITICAL_SECTION_ENTER();
1278 	((Systemcontrol *)hw)->SHPR2.reg ^= SystemControl_SHPR2_PRI_11(mask);
1279 	SystemControl_CRITICAL_SECTION_LEAVE();
1280 }
1281 
hri_systemcontrol_read_SHPR2_PRI_11_bf(const void * const hw)1282 static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_PRI_11_bf(const void *const hw)
1283 {
1284 	uint32_t tmp;
1285 	tmp = ((Systemcontrol *)hw)->SHPR2.reg;
1286 	tmp = (tmp & SystemControl_SHPR2_PRI_11_Msk) >> 24;
1287 	return tmp;
1288 }
1289 
hri_systemcontrol_set_SHPR2_reg(const void * const hw,hri_systemcontrol_shpr2_reg_t mask)1290 static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
1291 {
1292 	SystemControl_CRITICAL_SECTION_ENTER();
1293 	((Systemcontrol *)hw)->SHPR2.reg |= mask;
1294 	SystemControl_CRITICAL_SECTION_LEAVE();
1295 }
1296 
hri_systemcontrol_get_SHPR2_reg(const void * const hw,hri_systemcontrol_shpr2_reg_t mask)1297 static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const             hw,
1298                                                                             hri_systemcontrol_shpr2_reg_t mask)
1299 {
1300 	uint32_t tmp;
1301 	tmp = ((Systemcontrol *)hw)->SHPR2.reg;
1302 	tmp &= mask;
1303 	return tmp;
1304 }
1305 
hri_systemcontrol_write_SHPR2_reg(const void * const hw,hri_systemcontrol_shpr2_reg_t data)1306 static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data)
1307 {
1308 	SystemControl_CRITICAL_SECTION_ENTER();
1309 	((Systemcontrol *)hw)->SHPR2.reg = data;
1310 	SystemControl_CRITICAL_SECTION_LEAVE();
1311 }
1312 
hri_systemcontrol_clear_SHPR2_reg(const void * const hw,hri_systemcontrol_shpr2_reg_t mask)1313 static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
1314 {
1315 	SystemControl_CRITICAL_SECTION_ENTER();
1316 	((Systemcontrol *)hw)->SHPR2.reg &= ~mask;
1317 	SystemControl_CRITICAL_SECTION_LEAVE();
1318 }
1319 
hri_systemcontrol_toggle_SHPR2_reg(const void * const hw,hri_systemcontrol_shpr2_reg_t mask)1320 static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask)
1321 {
1322 	SystemControl_CRITICAL_SECTION_ENTER();
1323 	((Systemcontrol *)hw)->SHPR2.reg ^= mask;
1324 	SystemControl_CRITICAL_SECTION_LEAVE();
1325 }
1326 
hri_systemcontrol_read_SHPR2_reg(const void * const hw)1327 static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw)
1328 {
1329 	return ((Systemcontrol *)hw)->SHPR2.reg;
1330 }
1331 
hri_systemcontrol_set_SHPR3_PRI_14_bf(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1332 static inline void hri_systemcontrol_set_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
1333 {
1334 	SystemControl_CRITICAL_SECTION_ENTER();
1335 	((Systemcontrol *)hw)->SHPR3.reg |= SystemControl_SHPR3_PRI_14(mask);
1336 	SystemControl_CRITICAL_SECTION_LEAVE();
1337 }
1338 
hri_systemcontrol_get_SHPR3_PRI_14_bf(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1339 static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_PRI_14_bf(const void *const             hw,
1340                                                                                   hri_systemcontrol_shpr3_reg_t mask)
1341 {
1342 	uint32_t tmp;
1343 	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
1344 	tmp = (tmp & SystemControl_SHPR3_PRI_14(mask)) >> 16;
1345 	return tmp;
1346 }
1347 
hri_systemcontrol_write_SHPR3_PRI_14_bf(const void * const hw,hri_systemcontrol_shpr3_reg_t data)1348 static inline void hri_systemcontrol_write_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
1349 {
1350 	uint32_t tmp;
1351 	SystemControl_CRITICAL_SECTION_ENTER();
1352 	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
1353 	tmp &= ~SystemControl_SHPR3_PRI_14_Msk;
1354 	tmp |= SystemControl_SHPR3_PRI_14(data);
1355 	((Systemcontrol *)hw)->SHPR3.reg = tmp;
1356 	SystemControl_CRITICAL_SECTION_LEAVE();
1357 }
1358 
hri_systemcontrol_clear_SHPR3_PRI_14_bf(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1359 static inline void hri_systemcontrol_clear_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
1360 {
1361 	SystemControl_CRITICAL_SECTION_ENTER();
1362 	((Systemcontrol *)hw)->SHPR3.reg &= ~SystemControl_SHPR3_PRI_14(mask);
1363 	SystemControl_CRITICAL_SECTION_LEAVE();
1364 }
1365 
hri_systemcontrol_toggle_SHPR3_PRI_14_bf(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1366 static inline void hri_systemcontrol_toggle_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
1367 {
1368 	SystemControl_CRITICAL_SECTION_ENTER();
1369 	((Systemcontrol *)hw)->SHPR3.reg ^= SystemControl_SHPR3_PRI_14(mask);
1370 	SystemControl_CRITICAL_SECTION_LEAVE();
1371 }
1372 
hri_systemcontrol_read_SHPR3_PRI_14_bf(const void * const hw)1373 static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_PRI_14_bf(const void *const hw)
1374 {
1375 	uint32_t tmp;
1376 	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
1377 	tmp = (tmp & SystemControl_SHPR3_PRI_14_Msk) >> 16;
1378 	return tmp;
1379 }
1380 
hri_systemcontrol_set_SHPR3_PRI_15_bf(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1381 static inline void hri_systemcontrol_set_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
1382 {
1383 	SystemControl_CRITICAL_SECTION_ENTER();
1384 	((Systemcontrol *)hw)->SHPR3.reg |= SystemControl_SHPR3_PRI_15(mask);
1385 	SystemControl_CRITICAL_SECTION_LEAVE();
1386 }
1387 
hri_systemcontrol_get_SHPR3_PRI_15_bf(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1388 static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_PRI_15_bf(const void *const             hw,
1389                                                                                   hri_systemcontrol_shpr3_reg_t mask)
1390 {
1391 	uint32_t tmp;
1392 	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
1393 	tmp = (tmp & SystemControl_SHPR3_PRI_15(mask)) >> 24;
1394 	return tmp;
1395 }
1396 
hri_systemcontrol_write_SHPR3_PRI_15_bf(const void * const hw,hri_systemcontrol_shpr3_reg_t data)1397 static inline void hri_systemcontrol_write_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
1398 {
1399 	uint32_t tmp;
1400 	SystemControl_CRITICAL_SECTION_ENTER();
1401 	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
1402 	tmp &= ~SystemControl_SHPR3_PRI_15_Msk;
1403 	tmp |= SystemControl_SHPR3_PRI_15(data);
1404 	((Systemcontrol *)hw)->SHPR3.reg = tmp;
1405 	SystemControl_CRITICAL_SECTION_LEAVE();
1406 }
1407 
hri_systemcontrol_clear_SHPR3_PRI_15_bf(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1408 static inline void hri_systemcontrol_clear_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
1409 {
1410 	SystemControl_CRITICAL_SECTION_ENTER();
1411 	((Systemcontrol *)hw)->SHPR3.reg &= ~SystemControl_SHPR3_PRI_15(mask);
1412 	SystemControl_CRITICAL_SECTION_LEAVE();
1413 }
1414 
hri_systemcontrol_toggle_SHPR3_PRI_15_bf(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1415 static inline void hri_systemcontrol_toggle_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
1416 {
1417 	SystemControl_CRITICAL_SECTION_ENTER();
1418 	((Systemcontrol *)hw)->SHPR3.reg ^= SystemControl_SHPR3_PRI_15(mask);
1419 	SystemControl_CRITICAL_SECTION_LEAVE();
1420 }
1421 
hri_systemcontrol_read_SHPR3_PRI_15_bf(const void * const hw)1422 static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_PRI_15_bf(const void *const hw)
1423 {
1424 	uint32_t tmp;
1425 	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
1426 	tmp = (tmp & SystemControl_SHPR3_PRI_15_Msk) >> 24;
1427 	return tmp;
1428 }
1429 
hri_systemcontrol_set_SHPR3_reg(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1430 static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
1431 {
1432 	SystemControl_CRITICAL_SECTION_ENTER();
1433 	((Systemcontrol *)hw)->SHPR3.reg |= mask;
1434 	SystemControl_CRITICAL_SECTION_LEAVE();
1435 }
1436 
hri_systemcontrol_get_SHPR3_reg(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1437 static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const             hw,
1438                                                                             hri_systemcontrol_shpr3_reg_t mask)
1439 {
1440 	uint32_t tmp;
1441 	tmp = ((Systemcontrol *)hw)->SHPR3.reg;
1442 	tmp &= mask;
1443 	return tmp;
1444 }
1445 
hri_systemcontrol_write_SHPR3_reg(const void * const hw,hri_systemcontrol_shpr3_reg_t data)1446 static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data)
1447 {
1448 	SystemControl_CRITICAL_SECTION_ENTER();
1449 	((Systemcontrol *)hw)->SHPR3.reg = data;
1450 	SystemControl_CRITICAL_SECTION_LEAVE();
1451 }
1452 
hri_systemcontrol_clear_SHPR3_reg(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1453 static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
1454 {
1455 	SystemControl_CRITICAL_SECTION_ENTER();
1456 	((Systemcontrol *)hw)->SHPR3.reg &= ~mask;
1457 	SystemControl_CRITICAL_SECTION_LEAVE();
1458 }
1459 
hri_systemcontrol_toggle_SHPR3_reg(const void * const hw,hri_systemcontrol_shpr3_reg_t mask)1460 static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask)
1461 {
1462 	SystemControl_CRITICAL_SECTION_ENTER();
1463 	((Systemcontrol *)hw)->SHPR3.reg ^= mask;
1464 	SystemControl_CRITICAL_SECTION_LEAVE();
1465 }
1466 
hri_systemcontrol_read_SHPR3_reg(const void * const hw)1467 static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw)
1468 {
1469 	return ((Systemcontrol *)hw)->SHPR3.reg;
1470 }
1471 
1472 #ifdef __cplusplus
1473 }
1474 #endif
1475 
1476 #endif /* _HRI_SystemControl_L21_H_INCLUDED */
1477 #endif /* _SAML21_SystemControl_COMPONENT_ */
1478