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Searched refs:__IO (Results 1 – 25 of 255) sorted by relevance

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/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Src/
Dstm32l4xx_hal_nand.c320 __IO uint32_t data = 0; in HAL_NAND_Read_ID()
321 __IO uint32_t data1 = 0; in HAL_NAND_Read_ID()
340 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID; in HAL_NAND_Read_ID()
342 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; in HAL_NAND_Read_ID()
348 data = *(__IO uint32_t *)deviceAddress; in HAL_NAND_Read_ID()
358 data = *(__IO uint32_t *)deviceAddress; in HAL_NAND_Read_ID()
359 data1 = *((__IO uint32_t *)deviceAddress + 4); in HAL_NAND_Read_ID()
403 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF; in HAL_NAND_Reset()
447 __IO uint32_t index = 0; in HAL_NAND_Read_Page_8b()
476 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; in HAL_NAND_Read_Page_8b()
[all …]
Dstm32l4xx_hal_crc.c452 __IO uint16_t *pReg; in CRC_Handle_8()
469 …*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation Misra… in CRC_Handle_8()
474 …pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation Misra… in CRC_Handle_8()
480 …pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation Misra… in CRC_Handle_8()
483 …*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation Misra… in CRC_Handle_8()
502 __IO uint16_t *pReg; in CRC_Handle_16()
513 …pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC20… in CRC_Handle_16()
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Inc/
Dstm32l1xx_hal_sd.h88 …__IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode…
90 …__IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode …
92 …__IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag …
94 …__IO uint32_t SdOperation; /*!< SD transfer operation (read/write) …
110 __IO uint8_t CSDStruct; /*!< CSD structure */
111 __IO uint8_t SysSpecVersion; /*!< System specification version */
112 __IO uint8_t Reserved1; /*!< Reserved */
113 __IO uint8_t TAAC; /*!< Data read access time 1 */
114 __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
115 __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
[all …]
Dstm32l1xx_ll_sdmmc.h548 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
554 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
560 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
566 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
752 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
758 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
764 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
770 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
776 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
782 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
[all …]
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L4xx_HAL_Driver/Inc/
Dstm32l4xx_hal_sd.h152 __IO uint32_t Context; /*!< SD transfer context */
154 __IO HAL_SD_StateTypeDef State; /*!< SD card State */
156 __IO uint32_t ErrorCode; /*!< SD Card Error codes */
199 __IO uint8_t CSDStruct; /*!< CSD structure */
200 __IO uint8_t SysSpecVersion; /*!< System specification version */
201 __IO uint8_t Reserved1; /*!< Reserved */
202 __IO uint8_t TAAC; /*!< Data read access time 1 */
203 __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
204 __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
205 __IO uint16_t CardComdClasses; /*!< Card command classes */
[all …]
/loramac-node-3.4.0/src/boards/mcu/saml21/cmsis/
Dcore_cm3.h203 #define __IO volatile /*!< Defines 'read / write' permissions */ macro
318 …__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register …
320 …__IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register …
322 …__IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register …
324 …__IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
326 …__IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register …
328 …__IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
351 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
352 …__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register …
353 …__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
[all …]
Dcore_sc300.h203 #define __IO volatile /*!< Defines 'read / write' permissions */ macro
318 …__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register …
320 …__IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register …
322 …__IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register …
324 …__IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
326 …__IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register …
328 …__IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
351 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
352 …__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register …
353 …__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
[all …]
Dcore_cm4.h249 #define __IO volatile /*!< Defines 'read / write' permissions */ macro
365 …__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register …
367 …__IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register …
369 …__IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register …
371 …__IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
373 …__IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register …
375 …__IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
398 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
399 …__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register …
400 …__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
[all …]
Dcore_cm7.h264 #define __IO volatile /*!< Defines 'read / write' permissions */ macro
380 …__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register …
382 …__IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register …
384 …__IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register …
386 …__IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
388 …__IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register …
390 …__IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…
413 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
414 …__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register …
415 …__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
[all …]
Dcore_sc000.h203 #define __IO volatile /*!< Defines 'read / write' permissions */ macro
317 …__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register …
319 …__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register …
321 …__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register …
323 …__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
326 …__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register …
343 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
344 …__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register …
345 …__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
346 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register …
[all …]
Dcore_cm0plus.h208 #define __IO volatile /*!< Defines 'read / write' permissions */ macro
322 …__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register …
324 …__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register …
326 …__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register …
328 …__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
331 …__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register …
348 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
350 …__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register …
354 …__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
355 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register …
[all …]
Dcore_cm0.h198 #define __IO volatile /*!< Defines 'read / write' permissions */ macro
311 …__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register …
313 …__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register …
315 …__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register …
317 …__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …
320 …__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register …
337 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…
339 …__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…
340 …__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register …
341 …__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register …
[all …]
/loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/component/
Dtc.h747 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
748 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
749 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
750 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
751 …__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Cle…
752 …__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set…
753 …__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Statu…
754 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
755 …__IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation …
756 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
[all …]
Daes.h301 __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
302 __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
303 …__IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Cle…
304 …__IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set…
305 …__IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Statu…
306 …__IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer …
311 __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
314 __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
315 __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
317 __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
[all …]
Dsercom.h1345 __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
1346 __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
1348 __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
1350 …__IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enabl…
1352 …__IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enabl…
1354 …__IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag …
1356 __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
1359 __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
1360 __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
1362 …__IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
[all …]
/loramac-node-3.4.0/src/boards/mcu/stm32/STM32L1xx_HAL_Driver/Src/
Dstm32l1xx_hal_pwr_ex.c98 *(__IO uint32_t *) CR_FWU_BB = (uint32_t)ENABLE; in HAL_PWREx_EnableFastWakeUp()
108 *(__IO uint32_t *) CR_FWU_BB = (uint32_t)DISABLE; in HAL_PWREx_DisableFastWakeUp()
118 *(__IO uint32_t *) CR_ULP_BB = (uint32_t)ENABLE; in HAL_PWREx_EnableUltraLowPower()
128 *(__IO uint32_t *) CR_ULP_BB = (uint32_t)DISABLE; in HAL_PWREx_DisableUltraLowPower()
144 *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)ENABLE; in HAL_PWREx_EnableLowPowerRunMode()
145 *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)ENABLE; in HAL_PWREx_EnableLowPowerRunMode()
155 *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)DISABLE; in HAL_PWREx_DisableLowPowerRunMode()
156 *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)DISABLE; in HAL_PWREx_DisableLowPowerRunMode()
/loramac-node-3.4.0/src/boards/NucleoL073/cmsis/
Dstm32l073xx.h147 …__IO uint32_t ISR; /*!< ADC Interrupt and Status register, Addre…
148 …__IO uint32_t IER; /*!< ADC Interrupt Enable register, Addre…
149 …__IO uint32_t CR; /*!< ADC Control register, Addre…
150 …__IO uint32_t CFGR1; /*!< ADC Configuration register 1, Addre…
151 …__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Addre…
152 …__IO uint32_t SMPR; /*!< ADC Sampling time register, Addre…
155 …__IO uint32_t TR; /*!< ADC watchdog threshold register, Addre…
157 …__IO uint32_t CHSELR; /*!< ADC channel selection register, Addre…
159 …__IO uint32_t DR; /*!< ADC data register, Addre…
161 …__IO uint32_t CALFACT; /*!< ADC data register, Addre…
[all …]
/loramac-node-3.4.0/src/boards/B-L072Z-LRWAN1/cmsis/
Dstm32l072xx.h146 …__IO uint32_t ISR; /*!< ADC Interrupt and Status register, Addre…
147 …__IO uint32_t IER; /*!< ADC Interrupt Enable register, Addre…
148 …__IO uint32_t CR; /*!< ADC Control register, Addre…
149 …__IO uint32_t CFGR1; /*!< ADC Configuration register 1, Addre…
150 …__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Addre…
151 …__IO uint32_t SMPR; /*!< ADC Sampling time register, Addre…
154 …__IO uint32_t TR; /*!< ADC watchdog threshold register, Addre…
156 …__IO uint32_t CHSELR; /*!< ADC channel selection register, Addre…
158 …__IO uint32_t DR; /*!< ADC data register, Addre…
160 …__IO uint32_t CALFACT; /*!< ADC data register, Addre…
[all …]
/loramac-node-3.4.0/src/boards/SKiM881AXL/cmsis/
Dstm32l081xx.h144 …__IO uint32_t ISR; /*!< ADC Interrupt and Status register, Addre…
145 …__IO uint32_t IER; /*!< ADC Interrupt Enable register, Addre…
146 …__IO uint32_t CR; /*!< ADC Control register, Addre…
147 …__IO uint32_t CFGR1; /*!< ADC Configuration register 1, Addre…
148 …__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Addre…
149 …__IO uint32_t SMPR; /*!< ADC Sampling time register, Addre…
152 …__IO uint32_t TR; /*!< ADC watchdog threshold register, Addre…
154 …__IO uint32_t CHSELR; /*!< ADC channel selection register, Addre…
156 …__IO uint32_t DR; /*!< ADC data register, Addre…
158 …__IO uint32_t CALFACT; /*!< ADC data register, Addre…
[all …]
/loramac-node-3.4.0/src/boards/NAMote72/cmsis/
Dstm32l152xc.h172 …__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00…
173 …__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04…
174 …__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08…
175 …__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C…
176 …__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10…
177 …__IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14…
178 …__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18…
179 …__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C…
180 …__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20…
181 …__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24…
[all …]
/loramac-node-3.4.0/src/boards/NucleoL152/cmsis/
Dstm32l152xe.h174 …__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00…
175 …__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04…
176 …__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08…
177 …__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C…
178 …__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10…
179 …__IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14…
180 …__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18…
181 …__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C…
182 …__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20…
183 …__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24…
[all …]
/loramac-node-3.4.0/src/boards/NucleoL476/
DsysIrqHandlers.c93 if( ( *( __IO uint32_t* )address == 0x0 ) && ( *( __IO uint32_t* )( address + 4 ) == 0x0 ) ) in HardFault_Handler()
102 …*( __IO uint32_t* )( sram2address + ( element * 4 ) ) = *( __IO uint32_t* )( address + ( element *… in HardFault_Handler()
106 *( __IO uint32_t* )sram2address = ( uint32_t )data; in HardFault_Handler()
107 *( __IO uint32_t* )( sram2address + 4 ) = ( uint32_t )( data >> 32 ); in HardFault_Handler()
155 …*( __IO uint32_t* )( address + ( element * 4 ) ) = *( __IO uint32_t* )( sram2address + ( element *… in HardFault_Handler()
/loramac-node-3.4.0/src/boards/SKiM980A/cmsis/
Dstm32l151xba.h163 …__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00…
164 …__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04…
165 …__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08…
166 …__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C…
167 …__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10…
168 …__IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14…
169 …__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18…
170 …__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C…
171 …__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20…
172 …__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24…
[all …]
/loramac-node-3.4.0/src/boards/SKiM880B/cmsis/
Dstm32l151xba.h163 …__IO uint32_t SR; /*!< ADC status register, Address offset: 0x00…
164 …__IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04…
165 …__IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08…
166 …__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C…
167 …__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10…
168 …__IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14…
169 …__IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18…
170 …__IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C…
171 …__IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20…
172 …__IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24…
[all …]
/loramac-node-3.4.0/src/boards/NucleoL476/cmsis/
Dstm32l476xx.h196 …__IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x…
197 …__IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x…
198 …__IO uint32_t CR; /*!< ADC control register, Address offset: 0x…
199 …__IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x…
200 …__IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x…
201 …__IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x…
202 …__IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x…
204 …__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x…
205 …__IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x…
206 …__IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x…
[all …]

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